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Merge tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[deliverable/linux.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
47enum {
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 51 MLX5_MKEY_BSF_OCTO_SIZE = 4,
52 MLX5_MAX_PSVS = 4,
e126ba97
EC		 53};
54
55enum {
56 MLX5_EXTENDED_UD_AV = 0x80000000,
57};
58
59enum {
60 MLX5_CQ_STATE_ARMED = 9,
61 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
62 MLX5_CQ_STATE_FIRED = 0xa,
63};
64
65enum {
66 MLX5_STAT_RATE_OFFSET = 5,
67};
68
69enum {
70 MLX5_INLINE_SEG = 0x80000000,
71};
72
73enum {
74 MLX5_PERM_LOCAL_READ = 1 << 2,
75 MLX5_PERM_LOCAL_WRITE = 1 << 3,
76 MLX5_PERM_REMOTE_READ = 1 << 4,
77 MLX5_PERM_REMOTE_WRITE = 1 << 5,
78 MLX5_PERM_ATOMIC = 1 << 6,
79 MLX5_PERM_UMR_EN = 1 << 7,
80};
81
82enum {
83 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
84 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
85 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
86 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
87 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
88};
89
90enum {
91 MLX5_ACCESS_MODE_PA = 0,
92 MLX5_ACCESS_MODE_MTT = 1,
93 MLX5_ACCESS_MODE_KLM = 2
94};
95
96enum {
97 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
98 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
99 MLX5_MKEY_BSF_EN = 1 << 30,
100 MLX5_MKEY_LEN64 = 1 << 31,
101};
102
103enum {
104 MLX5_EN_RD = (u64)1,
105 MLX5_EN_WR = (u64)2
106};
107
108enum {
c1be5232
EC		 109 MLX5_BF_REGS_PER_PAGE = 4,
110 MLX5_MAX_UAR_PAGES = 1 << 8,
111 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
112 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 113};
114
115enum {
116 MLX5_MKEY_MASK_LEN = 1ull << 0,
117 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
118 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
119 MLX5_MKEY_MASK_PD = 1ull << 7,
120 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 121 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 122 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
123 MLX5_MKEY_MASK_KEY = 1ull << 13,
124 MLX5_MKEY_MASK_QPN = 1ull << 14,
125 MLX5_MKEY_MASK_LR = 1ull << 17,
126 MLX5_MKEY_MASK_LW = 1ull << 18,
127 MLX5_MKEY_MASK_RR = 1ull << 19,
128 MLX5_MKEY_MASK_RW = 1ull << 20,
129 MLX5_MKEY_MASK_A = 1ull << 21,
130 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
131 MLX5_MKEY_MASK_FREE = 1ull << 29,
132};
133
134enum mlx5_event {
135 MLX5_EVENT_TYPE_COMP = 0x0,
136
137 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
138 MLX5_EVENT_TYPE_COMM_EST = 0x02,
139 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
140 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
141 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
142
143 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
144 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
145 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
146 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
147 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
148 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
149
150 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
151 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
152 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
153 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
154
155 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
156 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
157
158 MLX5_EVENT_TYPE_CMD = 0x0a,
159 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
160};
161
162enum {
163 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
164 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
165 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
166 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
167 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
168 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
169 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
170};
171
172enum {
173 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
174 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
175 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
176 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
177 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
178 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
179 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
180 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
181 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
182 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 183 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 184 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
e126ba97
EC		 185 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
186 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
187 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
188 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
189 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
c1868b82 190 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 191};
192
193enum {
194 MLX5_OPCODE_NOP = 0x00,
195 MLX5_OPCODE_SEND_INVAL = 0x01,
196 MLX5_OPCODE_RDMA_WRITE = 0x08,
197 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
198 MLX5_OPCODE_SEND = 0x0a,
199 MLX5_OPCODE_SEND_IMM = 0x0b,
200 MLX5_OPCODE_RDMA_READ = 0x10,
201 MLX5_OPCODE_ATOMIC_CS = 0x11,
202 MLX5_OPCODE_ATOMIC_FA = 0x12,
203 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
204 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
205 MLX5_OPCODE_BIND_MW = 0x18,
206 MLX5_OPCODE_CONFIG_CMD = 0x1f,
207
208 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
209 MLX5_RECV_OPCODE_SEND = 0x01,
210 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
211 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
212
213 MLX5_CQE_OPCODE_ERROR = 0x1e,
214 MLX5_CQE_OPCODE_RESIZE = 0x16,
215
216 MLX5_OPCODE_SET_PSV = 0x20,
217 MLX5_OPCODE_GET_PSV = 0x21,
218 MLX5_OPCODE_CHECK_PSV = 0x22,
219 MLX5_OPCODE_RGET_PSV = 0x26,
220 MLX5_OPCODE_RCHECK_PSV = 0x27,
221
222 MLX5_OPCODE_UMR = 0x25,
223
224};
225
226enum {
227 MLX5_SET_PORT_RESET_QKEY = 0,
228 MLX5_SET_PORT_GUID0 = 16,
229 MLX5_SET_PORT_NODE_GUID = 17,
230 MLX5_SET_PORT_SYS_GUID = 18,
231 MLX5_SET_PORT_GID_TABLE = 19,
232 MLX5_SET_PORT_PKEY_TABLE = 20,
233};
234
235enum {
236 MLX5_MAX_PAGE_SHIFT = 31
237};
238
1b77d2bd 239enum {
05bdb2ab
EC		 240 MLX5_ADAPTER_PAGE_SHIFT = 12,
241 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 242};
243
87b8de49
EC		 244enum {
245 MLX5_CAP_OFF_DCT = 41,
246 MLX5_CAP_OFF_CMDIF_CSUM = 46,
247};
248
e126ba97
EC		 249struct mlx5_inbox_hdr {
250 __be16 opcode;
251 u8 rsvd[4];
252 __be16 opmod;
253};
254
255struct mlx5_outbox_hdr {
256 u8 status;
257 u8 rsvd[3];
258 __be32 syndrome;
259};
260
261struct mlx5_cmd_query_adapter_mbox_in {
262 struct mlx5_inbox_hdr hdr;
263 u8 rsvd[8];
264};
265
266struct mlx5_cmd_query_adapter_mbox_out {
267 struct mlx5_outbox_hdr hdr;
268 u8 rsvd0[24];
269 u8 intapin;
270 u8 rsvd1[13];
271 __be16 vsd_vendor_id;
272 u8 vsd[208];
273 u8 vsd_psid[16];
274};
275
276struct mlx5_hca_cap {
277 u8 rsvd1[16];
278 u8 log_max_srq_sz;
279 u8 log_max_qp_sz;
280 u8 rsvd2;
281 u8 log_max_qp;
282 u8 log_max_strq_sz;
283 u8 log_max_srqs;
284 u8 rsvd4[2];
285 u8 rsvd5;
286 u8 log_max_cq_sz;
287 u8 rsvd6;
288 u8 log_max_cq;
289 u8 log_max_eq_sz;
290 u8 log_max_mkey;
291 u8 rsvd7;
292 u8 log_max_eq;
293 u8 max_indirection;
294 u8 log_max_mrw_sz;
295 u8 log_max_bsf_list_sz;
296 u8 log_max_klm_list_sz;
297 u8 rsvd_8_0;
298 u8 log_max_ra_req_dc;
299 u8 rsvd_8_1;
300 u8 log_max_ra_res_dc;
301 u8 rsvd9;
302 u8 log_max_ra_req_qp;
303 u8 rsvd10;
304 u8 log_max_ra_res_qp;
305 u8 rsvd11[4];
306 __be16 max_qp_count;
307 __be16 rsvd12;
308 u8 rsvd13;
309 u8 local_ca_ack_delay;
310 u8 rsvd14;
311 u8 num_ports;
312 u8 log_max_msg;
313 u8 rsvd15[3];
314 __be16 stat_rate_support;
315 u8 rsvd16[2];
316 __be64 flags;
317 u8 rsvd17;
318 u8 uar_sz;
319 u8 rsvd18;
320 u8 log_pg_sz;
321 __be16 bf_log_bf_reg_size;
322 u8 rsvd19[4];
323 __be16 max_desc_sz_sq;
324 u8 rsvd20[2];
325 __be16 max_desc_sz_rq;
326 u8 rsvd21[2];
327 __be16 max_desc_sz_sq_dc;
0a324f31
ML		 328 __be32 max_qp_mcg;
329 u8 rsvd22[3];
e126ba97 330 u8 log_max_mcg;
0a324f31 331 u8 rsvd23;
e126ba97 332 u8 log_max_pd;
0a324f31 333 u8 rsvd24;
e126ba97 334 u8 log_max_xrcd;
0a324f31 335 u8 rsvd25[42];
288dde9f 336 __be16 log_uar_page_sz;
0a324f31 337 u8 rsvd26[28];
87b8de49 338 u8 log_max_atomic_size_qp;
0a324f31 339 u8 rsvd27[2];
87b8de49 340 u8 log_max_atomic_size_dc;
0a324f31 341 u8 rsvd28[76];
e126ba97
EC		 342};
343
344
345struct mlx5_cmd_query_hca_cap_mbox_in {
346 struct mlx5_inbox_hdr hdr;
347 u8 rsvd[8];
348};
349
350
351struct mlx5_cmd_query_hca_cap_mbox_out {
352 struct mlx5_outbox_hdr hdr;
353 u8 rsvd0[8];
354 struct mlx5_hca_cap hca_cap;
355};
356
357
358struct mlx5_cmd_set_hca_cap_mbox_in {
359 struct mlx5_inbox_hdr hdr;
360 u8 rsvd[8];
361 struct mlx5_hca_cap hca_cap;
362};
363
364
365struct mlx5_cmd_set_hca_cap_mbox_out {
366 struct mlx5_outbox_hdr hdr;
367 u8 rsvd0[8];
368};
369
370
371struct mlx5_cmd_init_hca_mbox_in {
372 struct mlx5_inbox_hdr hdr;
373 u8 rsvd0[2];
374 __be16 profile;
375 u8 rsvd1[4];
376};
377
378struct mlx5_cmd_init_hca_mbox_out {
379 struct mlx5_outbox_hdr hdr;
380 u8 rsvd[8];
381};
382
383struct mlx5_cmd_teardown_hca_mbox_in {
384 struct mlx5_inbox_hdr hdr;
385 u8 rsvd0[2];
386 __be16 profile;
387 u8 rsvd1[4];
388};
389
390struct mlx5_cmd_teardown_hca_mbox_out {
391 struct mlx5_outbox_hdr hdr;
392 u8 rsvd[8];
393};
394
395struct mlx5_cmd_layout {
396 u8 type;
397 u8 rsvd0[3];
398 __be32 inlen;
399 __be64 in_ptr;
400 __be32 in[4];
401 __be32 out[4];
402 __be64 out_ptr;
403 __be32 outlen;
404 u8 token;
405 u8 sig;
406 u8 rsvd1;
407 u8 status_own;
408};
409
410
411struct health_buffer {
412 __be32 assert_var[5];
413 __be32 rsvd0[3];
414 __be32 assert_exit_ptr;
415 __be32 assert_callra;
416 __be32 rsvd1[2];
417 __be32 fw_ver;
418 __be32 hw_id;
419 __be32 rsvd2;
420 u8 irisc_index;
421 u8 synd;
422 __be16 ext_sync;
423};
424
425struct mlx5_init_seg {
426 __be32 fw_rev;
427 __be32 cmdif_rev_fw_sub;
428 __be32 rsvd0[2];
429 __be32 cmdq_addr_h;
430 __be32 cmdq_addr_l_sz;
431 __be32 cmd_dbell;
432 __be32 rsvd1[121];
433 struct health_buffer health;
434 __be32 rsvd2[884];
435 __be32 health_counter;
2f6daec1 436 __be32 rsvd3[1019];
e126ba97
EC		 437 __be64 ieee1588_clk;
438 __be32 ieee1588_clk_type;
439 __be32 clr_intx;
440};
441
442struct mlx5_eqe_comp {
443 __be32 reserved[6];
444 __be32 cqn;
445};
446
447struct mlx5_eqe_qp_srq {
448 __be32 reserved[6];
449 __be32 qp_srq_n;
450};
451
452struct mlx5_eqe_cq_err {
453 __be32 cqn;
454 u8 reserved1[7];
455 u8 syndrome;
456};
457
458struct mlx5_eqe_dropped_packet {
459};
460
461struct mlx5_eqe_port_state {
462 u8 reserved0[8];
463 u8 port;
464};
465
466struct mlx5_eqe_gpio {
467 __be32 reserved0[2];
468 __be64 gpio_event;
469};
470
471struct mlx5_eqe_congestion {
472 u8 type;
473 u8 rsvd0;
474 u8 congestion_level;
475};
476
477struct mlx5_eqe_stall_vl {
478 u8 rsvd0[3];
479 u8 port_vl;
480};
481
482struct mlx5_eqe_cmd {
483 __be32 vector;
484 __be32 rsvd[6];
485};
486
487struct mlx5_eqe_page_req {
488 u8 rsvd0[2];
489 __be16 func_id;
0a324f31
ML		 490 __be32 num_pages;
491 __be32 rsvd1[5];
e126ba97
EC		 492};
493
494union ev_data {
495 __be32 raw[7];
496 struct mlx5_eqe_cmd cmd;
497 struct mlx5_eqe_comp comp;
498 struct mlx5_eqe_qp_srq qp_srq;
499 struct mlx5_eqe_cq_err cq_err;
500 struct mlx5_eqe_dropped_packet dp;
501 struct mlx5_eqe_port_state port;
502 struct mlx5_eqe_gpio gpio;
503 struct mlx5_eqe_congestion cong;
504 struct mlx5_eqe_stall_vl stall_vl;
505 struct mlx5_eqe_page_req req_pages;
506} __packed;
507
508struct mlx5_eqe {
509 u8 rsvd0;
510 u8 type;
511 u8 rsvd1;
512 u8 sub_type;
513 __be32 rsvd2[7];
514 union ev_data data;
515 __be16 rsvd3;
516 u8 signature;
517 u8 owner;
518} __packed;
519
520struct mlx5_cmd_prot_block {
521 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
522 u8 rsvd0[48];
523 __be64 next;
524 __be32 block_num;
525 u8 rsvd1;
526 u8 token;
527 u8 ctrl_sig;
528 u8 sig;
529};
530
531struct mlx5_err_cqe {
532 u8 rsvd0[32];
533 __be32 srqn;
534 u8 rsvd1[18];
535 u8 vendor_err_synd;
536 u8 syndrome;
537 __be32 s_wqe_opcode_qpn;
538 __be16 wqe_counter;
539 u8 signature;
540 u8 op_own;
541};
542
543struct mlx5_cqe64 {
544 u8 rsvd0[17];
545 u8 ml_path;
546 u8 rsvd20[4];
547 __be16 slid;
548 __be32 flags_rqpn;
549 u8 rsvd28[4];
550 __be32 srqn;
551 __be32 imm_inval_pkey;
552 u8 rsvd40[4];
553 __be32 byte_cnt;
554 __be64 timestamp;
555 __be32 sop_drop_qpn;
556 __be16 wqe_counter;
557 u8 signature;
558 u8 op_own;
559};
560
d5436ba0
SG		 561struct mlx5_sig_err_cqe {
562 u8 rsvd0[16];
563 __be32 expected_trans_sig;
564 __be32 actual_trans_sig;
565 __be32 expected_reftag;
566 __be32 actual_reftag;
567 __be16 syndrome;
568 u8 rsvd22[2];
569 __be32 mkey;
570 __be64 err_offset;
571 u8 rsvd30[8];
572 __be32 qpn;
573 u8 rsvd38[2];
574 u8 signature;
575 u8 op_own;
576};
577
e126ba97
EC		 578struct mlx5_wqe_srq_next_seg {
579 u8 rsvd0[2];
580 __be16 next_wqe_index;
581 u8 signature;
582 u8 rsvd1[11];
583};
584
585union mlx5_ext_cqe {
586 struct ib_grh grh;
587 u8 inl[64];
588};
589
590struct mlx5_cqe128 {
591 union mlx5_ext_cqe inl_grh;
592 struct mlx5_cqe64 cqe64;
593};
594
595struct mlx5_srq_ctx {
596 u8 state_log_sz;
597 u8 rsvd0[3];
598 __be32 flags_xrcd;
599 __be32 pgoff_cqn;
600 u8 rsvd1[4];
601 u8 log_pg_sz;
602 u8 rsvd2[7];
603 __be32 pd;
604 __be16 lwm;
605 __be16 wqe_cnt;
606 u8 rsvd3[8];
607 __be64 db_record;
608};
609
610struct mlx5_create_srq_mbox_in {
611 struct mlx5_inbox_hdr hdr;
612 __be32 input_srqn;
613 u8 rsvd0[4];
614 struct mlx5_srq_ctx ctx;
615 u8 rsvd1[208];
616 __be64 pas[0];
617};
618
619struct mlx5_create_srq_mbox_out {
620 struct mlx5_outbox_hdr hdr;
621 __be32 srqn;
622 u8 rsvd[4];
623};
624
625struct mlx5_destroy_srq_mbox_in {
626 struct mlx5_inbox_hdr hdr;
627 __be32 srqn;
628 u8 rsvd[4];
629};
630
631struct mlx5_destroy_srq_mbox_out {
632 struct mlx5_outbox_hdr hdr;
633 u8 rsvd[8];
634};
635
636struct mlx5_query_srq_mbox_in {
637 struct mlx5_inbox_hdr hdr;
638 __be32 srqn;
639 u8 rsvd0[4];
640};
641
642struct mlx5_query_srq_mbox_out {
643 struct mlx5_outbox_hdr hdr;
644 u8 rsvd0[8];
645 struct mlx5_srq_ctx ctx;
646 u8 rsvd1[32];
647 __be64 pas[0];
648};
649
650struct mlx5_arm_srq_mbox_in {
651 struct mlx5_inbox_hdr hdr;
652 __be32 srqn;
653 __be16 rsvd;
654 __be16 lwm;
655};
656
657struct mlx5_arm_srq_mbox_out {
658 struct mlx5_outbox_hdr hdr;
659 u8 rsvd[8];
660};
661
662struct mlx5_cq_context {
663 u8 status;
664 u8 cqe_sz_flags;
665 u8 st;
666 u8 rsvd3;
667 u8 rsvd4[6];
668 __be16 page_offset;
669 __be32 log_sz_usr_page;
670 __be16 cq_period;
671 __be16 cq_max_count;
672 __be16 rsvd20;
673 __be16 c_eqn;
674 u8 log_pg_sz;
675 u8 rsvd25[7];
676 __be32 last_notified_index;
677 __be32 solicit_producer_index;
678 __be32 consumer_counter;
679 __be32 producer_counter;
680 u8 rsvd48[8];
681 __be64 db_record_addr;
682};
683
684struct mlx5_create_cq_mbox_in {
685 struct mlx5_inbox_hdr hdr;
686 __be32 input_cqn;
687 u8 rsvdx[4];
688 struct mlx5_cq_context ctx;
689 u8 rsvd6[192];
690 __be64 pas[0];
691};
692
693struct mlx5_create_cq_mbox_out {
694 struct mlx5_outbox_hdr hdr;
695 __be32 cqn;
696 u8 rsvd0[4];
697};
698
699struct mlx5_destroy_cq_mbox_in {
700 struct mlx5_inbox_hdr hdr;
701 __be32 cqn;
702 u8 rsvd0[4];
703};
704
705struct mlx5_destroy_cq_mbox_out {
706 struct mlx5_outbox_hdr hdr;
707 u8 rsvd0[8];
708};
709
710struct mlx5_query_cq_mbox_in {
711 struct mlx5_inbox_hdr hdr;
712 __be32 cqn;
713 u8 rsvd0[4];
714};
715
716struct mlx5_query_cq_mbox_out {
717 struct mlx5_outbox_hdr hdr;
718 u8 rsvd0[8];
719 struct mlx5_cq_context ctx;
720 u8 rsvd6[16];
721 __be64 pas[0];
722};
723
3bdb31f6
EC		 724struct mlx5_modify_cq_mbox_in {
725 struct mlx5_inbox_hdr hdr;
726 __be32 cqn;
727 __be32 field_select;
728 struct mlx5_cq_context ctx;
729 u8 rsvd[192];
730 __be64 pas[0];
731};
732
733struct mlx5_modify_cq_mbox_out {
734 struct mlx5_outbox_hdr hdr;
bde51583 735 u8 rsvd[8];
3bdb31f6
EC		 736};
737
cd23b14b
EC		 738struct mlx5_enable_hca_mbox_in {
739 struct mlx5_inbox_hdr hdr;
740 u8 rsvd[8];
741};
742
743struct mlx5_enable_hca_mbox_out {
744 struct mlx5_outbox_hdr hdr;
745 u8 rsvd[8];
746};
747
748struct mlx5_disable_hca_mbox_in {
749 struct mlx5_inbox_hdr hdr;
750 u8 rsvd[8];
751};
752
753struct mlx5_disable_hca_mbox_out {
754 struct mlx5_outbox_hdr hdr;
755 u8 rsvd[8];
756};
757
e126ba97
EC		 758struct mlx5_eq_context {
759 u8 status;
760 u8 ec_oi;
761 u8 st;
762 u8 rsvd2[7];
763 __be16 page_pffset;
764 __be32 log_sz_usr_page;
765 u8 rsvd3[7];
766 u8 intr;
767 u8 log_page_size;
768 u8 rsvd4[15];
769 __be32 consumer_counter;
770 __be32 produser_counter;
771 u8 rsvd5[16];
772};
773
774struct mlx5_create_eq_mbox_in {
775 struct mlx5_inbox_hdr hdr;
776 u8 rsvd0[3];
777 u8 input_eqn;
778 u8 rsvd1[4];
779 struct mlx5_eq_context ctx;
780 u8 rsvd2[8];
781 __be64 events_mask;
782 u8 rsvd3[176];
783 __be64 pas[0];
784};
785
786struct mlx5_create_eq_mbox_out {
787 struct mlx5_outbox_hdr hdr;
788 u8 rsvd0[3];
789 u8 eq_number;
790 u8 rsvd1[4];
791};
792
793struct mlx5_destroy_eq_mbox_in {
794 struct mlx5_inbox_hdr hdr;
795 u8 rsvd0[3];
796 u8 eqn;
797 u8 rsvd1[4];
798};
799
800struct mlx5_destroy_eq_mbox_out {
801 struct mlx5_outbox_hdr hdr;
802 u8 rsvd[8];
803};
804
805struct mlx5_map_eq_mbox_in {
806 struct mlx5_inbox_hdr hdr;
807 __be64 mask;
808 u8 mu;
809 u8 rsvd0[2];
810 u8 eqn;
811 u8 rsvd1[24];
812};
813
814struct mlx5_map_eq_mbox_out {
815 struct mlx5_outbox_hdr hdr;
816 u8 rsvd[8];
817};
818
819struct mlx5_query_eq_mbox_in {
820 struct mlx5_inbox_hdr hdr;
821 u8 rsvd0[3];
822 u8 eqn;
823 u8 rsvd1[4];
824};
825
826struct mlx5_query_eq_mbox_out {
827 struct mlx5_outbox_hdr hdr;
828 u8 rsvd[8];
829 struct mlx5_eq_context ctx;
830};
831
832struct mlx5_mkey_seg {
833 /* This is a two bit field occupying bits 31-30.
834 * bit 31 is always 0,
835 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
836 */
837 u8 status;
838 u8 pcie_control;
839 u8 flags;
840 u8 version;
841 __be32 qpn_mkey7_0;
842 u8 rsvd1[4];
843 __be32 flags_pd;
844 __be64 start_addr;
845 __be64 len;
846 __be32 bsfs_octo_size;
847 u8 rsvd2[16];
848 __be32 xlt_oct_size;
849 u8 rsvd3[3];
850 u8 log2_page_size;
851 u8 rsvd4[4];
852};
853
854struct mlx5_query_special_ctxs_mbox_in {
855 struct mlx5_inbox_hdr hdr;
856 u8 rsvd[8];
857};
858
859struct mlx5_query_special_ctxs_mbox_out {
860 struct mlx5_outbox_hdr hdr;
861 __be32 dump_fill_mkey;
862 __be32 reserved_lkey;
863};
864
865struct mlx5_create_mkey_mbox_in {
866 struct mlx5_inbox_hdr hdr;
867 __be32 input_mkey_index;
868 u8 rsvd0[4];
869 struct mlx5_mkey_seg seg;
870 u8 rsvd1[16];
871 __be32 xlat_oct_act_size;
8c8a4914
EC		 872 __be32 rsvd2;
873 u8 rsvd3[168];
e126ba97
EC		 874 __be64 pas[0];
875};
876
877struct mlx5_create_mkey_mbox_out {
878 struct mlx5_outbox_hdr hdr;
879 __be32 mkey;
880 u8 rsvd[4];
881};
882
883struct mlx5_destroy_mkey_mbox_in {
884 struct mlx5_inbox_hdr hdr;
885 __be32 mkey;
886 u8 rsvd[4];
887};
888
889struct mlx5_destroy_mkey_mbox_out {
890 struct mlx5_outbox_hdr hdr;
891 u8 rsvd[8];
892};
893
894struct mlx5_query_mkey_mbox_in {
895 struct mlx5_inbox_hdr hdr;
896 __be32 mkey;
897};
898
899struct mlx5_query_mkey_mbox_out {
900 struct mlx5_outbox_hdr hdr;
901 __be64 pas[0];
902};
903
904struct mlx5_modify_mkey_mbox_in {
905 struct mlx5_inbox_hdr hdr;
906 __be32 mkey;
907 __be64 pas[0];
908};
909
910struct mlx5_modify_mkey_mbox_out {
911 struct mlx5_outbox_hdr hdr;
3bdb31f6 912 u8 rsvd[8];
e126ba97
EC		 913};
914
915struct mlx5_dump_mkey_mbox_in {
916 struct mlx5_inbox_hdr hdr;
917};
918
919struct mlx5_dump_mkey_mbox_out {
920 struct mlx5_outbox_hdr hdr;
921 __be32 mkey;
922};
923
924struct mlx5_mad_ifc_mbox_in {
925 struct mlx5_inbox_hdr hdr;
926 __be16 remote_lid;
927 u8 rsvd0;
928 u8 port;
929 u8 rsvd1[4];
930 u8 data[256];
931};
932
933struct mlx5_mad_ifc_mbox_out {
934 struct mlx5_outbox_hdr hdr;
935 u8 rsvd[8];
936 u8 data[256];
937};
938
939struct mlx5_access_reg_mbox_in {
940 struct mlx5_inbox_hdr hdr;
941 u8 rsvd0[2];
942 __be16 register_id;
943 __be32 arg;
944 __be32 data[0];
945};
946
947struct mlx5_access_reg_mbox_out {
948 struct mlx5_outbox_hdr hdr;
949 u8 rsvd[8];
950 __be32 data[0];
951};
952
953#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
954
955enum {
956 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
957};
958
3121e3c4
SG		 959struct mlx5_allocate_psv_in {
960 struct mlx5_inbox_hdr hdr;
961 __be32 npsv_pd;
962 __be32 rsvd_psv0;
963};
964
965struct mlx5_allocate_psv_out {
966 struct mlx5_outbox_hdr hdr;
967 u8 rsvd[8];
968 __be32 psv_idx[4];
969};
970
971struct mlx5_destroy_psv_in {
972 struct mlx5_inbox_hdr hdr;
973 __be32 psv_number;
974 u8 rsvd[4];
975};
976
977struct mlx5_destroy_psv_out {
978 struct mlx5_outbox_hdr hdr;
979 u8 rsvd[8];
980};
981
e126ba97 982#endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
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