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IB/mlx5: Implement the ODP capability query verb
[deliverable/linux.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
d29b796a
EC		 47/* helper macros */
48#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
49#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
50#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
51#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
52#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
53#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
54#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
55#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
56#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
57
58#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
59#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
60#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
61#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
62#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
63
64/* insert a value to a struct */
65#define MLX5_SET(typ, p, fld, v) do { \
66 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
67 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
68 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
69 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
70 << __mlx5_dw_bit_off(typ, fld))); \
71} while (0)
72
73#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
74__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
75__mlx5_mask(typ, fld))
76
77#define MLX5_GET_PR(typ, p, fld) ({ \
78 u32 ___t = MLX5_GET(typ, p, fld); \
79 pr_debug(#fld " = 0x%x\n", ___t); \
80 ___t; \
81})
82
83#define MLX5_SET64(typ, p, fld, v) do { \
84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
85 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
86 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
87} while (0)
88
89#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
90
e126ba97
EC		 91enum {
92 MLX5_MAX_COMMANDS = 32,
93 MLX5_CMD_DATA_BLOCK_SIZE = 512,
94 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 95 MLX5_MKEY_BSF_OCTO_SIZE = 4,
96 MLX5_MAX_PSVS = 4,
e126ba97
EC		 97};
98
99enum {
100 MLX5_EXTENDED_UD_AV = 0x80000000,
101};
102
103enum {
104 MLX5_CQ_STATE_ARMED = 9,
105 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
106 MLX5_CQ_STATE_FIRED = 0xa,
107};
108
109enum {
110 MLX5_STAT_RATE_OFFSET = 5,
111};
112
113enum {
114 MLX5_INLINE_SEG = 0x80000000,
115};
116
c7a08ac7
EC		 117enum {
118 MLX5_MIN_PKEY_TABLE_SIZE = 128,
119 MLX5_MAX_LOG_PKEY_TABLE = 5,
120};
121
e420f0c0
HE		 122enum {
123 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
124};
125
126enum {
127 MLX5_PFAULT_SUBTYPE_WQE = 0,
128 MLX5_PFAULT_SUBTYPE_RDMA = 1,
129};
130
e126ba97
EC		 131enum {
132 MLX5_PERM_LOCAL_READ = 1 << 2,
133 MLX5_PERM_LOCAL_WRITE = 1 << 3,
134 MLX5_PERM_REMOTE_READ = 1 << 4,
135 MLX5_PERM_REMOTE_WRITE = 1 << 5,
136 MLX5_PERM_ATOMIC = 1 << 6,
137 MLX5_PERM_UMR_EN = 1 << 7,
138};
139
140enum {
141 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
142 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
143 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
144 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
145 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
146};
147
148enum {
149 MLX5_ACCESS_MODE_PA = 0,
150 MLX5_ACCESS_MODE_MTT = 1,
151 MLX5_ACCESS_MODE_KLM = 2
152};
153
154enum {
155 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
156 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
157 MLX5_MKEY_BSF_EN = 1 << 30,
158 MLX5_MKEY_LEN64 = 1 << 31,
159};
160
161enum {
162 MLX5_EN_RD = (u64)1,
163 MLX5_EN_WR = (u64)2
164};
165
166enum {
c1be5232
EC		 167 MLX5_BF_REGS_PER_PAGE = 4,
168 MLX5_MAX_UAR_PAGES = 1 << 8,
169 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
170 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 171};
172
173enum {
174 MLX5_MKEY_MASK_LEN = 1ull << 0,
175 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
176 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
177 MLX5_MKEY_MASK_PD = 1ull << 7,
178 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 179 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 180 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
181 MLX5_MKEY_MASK_KEY = 1ull << 13,
182 MLX5_MKEY_MASK_QPN = 1ull << 14,
183 MLX5_MKEY_MASK_LR = 1ull << 17,
184 MLX5_MKEY_MASK_LW = 1ull << 18,
185 MLX5_MKEY_MASK_RR = 1ull << 19,
186 MLX5_MKEY_MASK_RW = 1ull << 20,
187 MLX5_MKEY_MASK_A = 1ull << 21,
188 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
189 MLX5_MKEY_MASK_FREE = 1ull << 29,
190};
191
968e78dd
HE		 192enum {
193 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
194
195 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
196 MLX5_UMR_CHECK_FREE = (2 << 5),
197
198 MLX5_UMR_INLINE = (1 << 7),
199};
200
e126ba97
EC		 201enum mlx5_event {
202 MLX5_EVENT_TYPE_COMP = 0x0,
203
204 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
205 MLX5_EVENT_TYPE_COMM_EST = 0x02,
206 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
207 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
208 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
209
210 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
211 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
212 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
213 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
214 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
215 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
216
217 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
218 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
219 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
220 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
221
222 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
223 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
224
225 MLX5_EVENT_TYPE_CMD = 0x0a,
226 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 227
228 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
e126ba97
EC		 229};
230
231enum {
232 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
233 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
234 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
235 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
236 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
237 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
238 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
239};
240
241enum {
e126ba97 242 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 243 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
244 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
245 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
246 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 247 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 248 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 249 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 250 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 251 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 252 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 253 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 254};
255
256enum {
257 MLX5_OPCODE_NOP = 0x00,
258 MLX5_OPCODE_SEND_INVAL = 0x01,
259 MLX5_OPCODE_RDMA_WRITE = 0x08,
260 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
261 MLX5_OPCODE_SEND = 0x0a,
262 MLX5_OPCODE_SEND_IMM = 0x0b,
263 MLX5_OPCODE_RDMA_READ = 0x10,
264 MLX5_OPCODE_ATOMIC_CS = 0x11,
265 MLX5_OPCODE_ATOMIC_FA = 0x12,
266 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
267 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
268 MLX5_OPCODE_BIND_MW = 0x18,
269 MLX5_OPCODE_CONFIG_CMD = 0x1f,
270
271 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
272 MLX5_RECV_OPCODE_SEND = 0x01,
273 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
274 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
275
276 MLX5_CQE_OPCODE_ERROR = 0x1e,
277 MLX5_CQE_OPCODE_RESIZE = 0x16,
278
279 MLX5_OPCODE_SET_PSV = 0x20,
280 MLX5_OPCODE_GET_PSV = 0x21,
281 MLX5_OPCODE_CHECK_PSV = 0x22,
282 MLX5_OPCODE_RGET_PSV = 0x26,
283 MLX5_OPCODE_RCHECK_PSV = 0x27,
284
285 MLX5_OPCODE_UMR = 0x25,
286
287};
288
289enum {
290 MLX5_SET_PORT_RESET_QKEY = 0,
291 MLX5_SET_PORT_GUID0 = 16,
292 MLX5_SET_PORT_NODE_GUID = 17,
293 MLX5_SET_PORT_SYS_GUID = 18,
294 MLX5_SET_PORT_GID_TABLE = 19,
295 MLX5_SET_PORT_PKEY_TABLE = 20,
296};
297
298enum {
299 MLX5_MAX_PAGE_SHIFT = 31
300};
301
1b77d2bd 302enum {
05bdb2ab
EC		 303 MLX5_ADAPTER_PAGE_SHIFT = 12,
304 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 305};
306
87b8de49 307enum {
87b8de49
EC		 308 MLX5_CAP_OFF_CMDIF_CSUM = 46,
309};
310
c7a08ac7
EC		 311enum {
312 HCA_CAP_OPMOD_GET_MAX = 0,
313 HCA_CAP_OPMOD_GET_CUR = 1,
e420f0c0
HE		 314 HCA_CAP_OPMOD_GET_ODP_MAX = 4,
315 HCA_CAP_OPMOD_GET_ODP_CUR = 5
c7a08ac7
EC		 316};
317
e126ba97
EC		 318struct mlx5_inbox_hdr {
319 __be16 opcode;
320 u8 rsvd[4];
321 __be16 opmod;
322};
323
324struct mlx5_outbox_hdr {
325 u8 status;
326 u8 rsvd[3];
327 __be32 syndrome;
328};
329
330struct mlx5_cmd_query_adapter_mbox_in {
331 struct mlx5_inbox_hdr hdr;
332 u8 rsvd[8];
333};
334
335struct mlx5_cmd_query_adapter_mbox_out {
336 struct mlx5_outbox_hdr hdr;
337 u8 rsvd0[24];
338 u8 intapin;
339 u8 rsvd1[13];
340 __be16 vsd_vendor_id;
341 u8 vsd[208];
342 u8 vsd_psid[16];
343};
344
e420f0c0
HE		 345enum mlx5_odp_transport_cap_bits {
346 MLX5_ODP_SUPPORT_SEND = 1 << 31,
347 MLX5_ODP_SUPPORT_RECV = 1 << 30,
348 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
349 MLX5_ODP_SUPPORT_READ = 1 << 28,
350};
351
352struct mlx5_odp_caps {
353 char reserved[0x10];
354 struct {
355 __be32 rc_odp_caps;
356 __be32 uc_odp_caps;
357 __be32 ud_odp_caps;
358 } per_transport_caps;
359 char reserved2[0xe4];
360};
361
e126ba97
EC		 362struct mlx5_cmd_init_hca_mbox_in {
363 struct mlx5_inbox_hdr hdr;
364 u8 rsvd0[2];
365 __be16 profile;
366 u8 rsvd1[4];
367};
368
369struct mlx5_cmd_init_hca_mbox_out {
370 struct mlx5_outbox_hdr hdr;
371 u8 rsvd[8];
372};
373
374struct mlx5_cmd_teardown_hca_mbox_in {
375 struct mlx5_inbox_hdr hdr;
376 u8 rsvd0[2];
377 __be16 profile;
378 u8 rsvd1[4];
379};
380
381struct mlx5_cmd_teardown_hca_mbox_out {
382 struct mlx5_outbox_hdr hdr;
383 u8 rsvd[8];
384};
385
386struct mlx5_cmd_layout {
387 u8 type;
388 u8 rsvd0[3];
389 __be32 inlen;
390 __be64 in_ptr;
391 __be32 in[4];
392 __be32 out[4];
393 __be64 out_ptr;
394 __be32 outlen;
395 u8 token;
396 u8 sig;
397 u8 rsvd1;
398 u8 status_own;
399};
400
401
402struct health_buffer {
403 __be32 assert_var[5];
404 __be32 rsvd0[3];
405 __be32 assert_exit_ptr;
406 __be32 assert_callra;
407 __be32 rsvd1[2];
408 __be32 fw_ver;
409 __be32 hw_id;
410 __be32 rsvd2;
411 u8 irisc_index;
412 u8 synd;
413 __be16 ext_sync;
414};
415
416struct mlx5_init_seg {
417 __be32 fw_rev;
418 __be32 cmdif_rev_fw_sub;
419 __be32 rsvd0[2];
420 __be32 cmdq_addr_h;
421 __be32 cmdq_addr_l_sz;
422 __be32 cmd_dbell;
423 __be32 rsvd1[121];
424 struct health_buffer health;
425 __be32 rsvd2[884];
426 __be32 health_counter;
2f6daec1 427 __be32 rsvd3[1019];
e126ba97
EC		 428 __be64 ieee1588_clk;
429 __be32 ieee1588_clk_type;
430 __be32 clr_intx;
431};
432
433struct mlx5_eqe_comp {
434 __be32 reserved[6];
435 __be32 cqn;
436};
437
438struct mlx5_eqe_qp_srq {
439 __be32 reserved[6];
440 __be32 qp_srq_n;
441};
442
443struct mlx5_eqe_cq_err {
444 __be32 cqn;
445 u8 reserved1[7];
446 u8 syndrome;
447};
448
e126ba97
EC		 449struct mlx5_eqe_port_state {
450 u8 reserved0[8];
451 u8 port;
452};
453
454struct mlx5_eqe_gpio {
455 __be32 reserved0[2];
456 __be64 gpio_event;
457};
458
459struct mlx5_eqe_congestion {
460 u8 type;
461 u8 rsvd0;
462 u8 congestion_level;
463};
464
465struct mlx5_eqe_stall_vl {
466 u8 rsvd0[3];
467 u8 port_vl;
468};
469
470struct mlx5_eqe_cmd {
471 __be32 vector;
472 __be32 rsvd[6];
473};
474
475struct mlx5_eqe_page_req {
476 u8 rsvd0[2];
477 __be16 func_id;
0a324f31
ML		 478 __be32 num_pages;
479 __be32 rsvd1[5];
e126ba97
EC		 480};
481
e420f0c0
HE		 482struct mlx5_eqe_page_fault {
483 __be32 bytes_committed;
484 union {
485 struct {
486 u16 reserved1;
487 __be16 wqe_index;
488 u16 reserved2;
489 __be16 packet_length;
490 u8 reserved3[12];
491 } __packed wqe;
492 struct {
493 __be32 r_key;
494 u16 reserved1;
495 __be16 packet_length;
496 __be32 rdma_op_len;
497 __be64 rdma_va;
498 } __packed rdma;
499 } __packed;
500 __be32 flags_qpn;
501} __packed;
502
e126ba97
EC		 503union ev_data {
504 __be32 raw[7];
505 struct mlx5_eqe_cmd cmd;
506 struct mlx5_eqe_comp comp;
507 struct mlx5_eqe_qp_srq qp_srq;
508 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 509 struct mlx5_eqe_port_state port;
510 struct mlx5_eqe_gpio gpio;
511 struct mlx5_eqe_congestion cong;
512 struct mlx5_eqe_stall_vl stall_vl;
513 struct mlx5_eqe_page_req req_pages;
e420f0c0 514 struct mlx5_eqe_page_fault page_fault;
e126ba97
EC		 515} __packed;
516
517struct mlx5_eqe {
518 u8 rsvd0;
519 u8 type;
520 u8 rsvd1;
521 u8 sub_type;
522 __be32 rsvd2[7];
523 union ev_data data;
524 __be16 rsvd3;
525 u8 signature;
526 u8 owner;
527} __packed;
528
529struct mlx5_cmd_prot_block {
530 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
531 u8 rsvd0[48];
532 __be64 next;
533 __be32 block_num;
534 u8 rsvd1;
535 u8 token;
536 u8 ctrl_sig;
537 u8 sig;
538};
539
540struct mlx5_err_cqe {
541 u8 rsvd0[32];
542 __be32 srqn;
543 u8 rsvd1[18];
544 u8 vendor_err_synd;
545 u8 syndrome;
546 __be32 s_wqe_opcode_qpn;
547 __be16 wqe_counter;
548 u8 signature;
549 u8 op_own;
550};
551
552struct mlx5_cqe64 {
553 u8 rsvd0[17];
554 u8 ml_path;
555 u8 rsvd20[4];
556 __be16 slid;
557 __be32 flags_rqpn;
558 u8 rsvd28[4];
559 __be32 srqn;
560 __be32 imm_inval_pkey;
561 u8 rsvd40[4];
562 __be32 byte_cnt;
563 __be64 timestamp;
564 __be32 sop_drop_qpn;
565 __be16 wqe_counter;
566 u8 signature;
567 u8 op_own;
568};
569
d5436ba0
SG		 570struct mlx5_sig_err_cqe {
571 u8 rsvd0[16];
572 __be32 expected_trans_sig;
573 __be32 actual_trans_sig;
574 __be32 expected_reftag;
575 __be32 actual_reftag;
576 __be16 syndrome;
577 u8 rsvd22[2];
578 __be32 mkey;
579 __be64 err_offset;
580 u8 rsvd30[8];
581 __be32 qpn;
582 u8 rsvd38[2];
583 u8 signature;
584 u8 op_own;
585};
586
e126ba97
EC		 587struct mlx5_wqe_srq_next_seg {
588 u8 rsvd0[2];
589 __be16 next_wqe_index;
590 u8 signature;
591 u8 rsvd1[11];
592};
593
594union mlx5_ext_cqe {
595 struct ib_grh grh;
596 u8 inl[64];
597};
598
599struct mlx5_cqe128 {
600 union mlx5_ext_cqe inl_grh;
601 struct mlx5_cqe64 cqe64;
602};
603
604struct mlx5_srq_ctx {
605 u8 state_log_sz;
606 u8 rsvd0[3];
607 __be32 flags_xrcd;
608 __be32 pgoff_cqn;
609 u8 rsvd1[4];
610 u8 log_pg_sz;
611 u8 rsvd2[7];
612 __be32 pd;
613 __be16 lwm;
614 __be16 wqe_cnt;
615 u8 rsvd3[8];
616 __be64 db_record;
617};
618
619struct mlx5_create_srq_mbox_in {
620 struct mlx5_inbox_hdr hdr;
621 __be32 input_srqn;
622 u8 rsvd0[4];
623 struct mlx5_srq_ctx ctx;
624 u8 rsvd1[208];
625 __be64 pas[0];
626};
627
628struct mlx5_create_srq_mbox_out {
629 struct mlx5_outbox_hdr hdr;
630 __be32 srqn;
631 u8 rsvd[4];
632};
633
634struct mlx5_destroy_srq_mbox_in {
635 struct mlx5_inbox_hdr hdr;
636 __be32 srqn;
637 u8 rsvd[4];
638};
639
640struct mlx5_destroy_srq_mbox_out {
641 struct mlx5_outbox_hdr hdr;
642 u8 rsvd[8];
643};
644
645struct mlx5_query_srq_mbox_in {
646 struct mlx5_inbox_hdr hdr;
647 __be32 srqn;
648 u8 rsvd0[4];
649};
650
651struct mlx5_query_srq_mbox_out {
652 struct mlx5_outbox_hdr hdr;
653 u8 rsvd0[8];
654 struct mlx5_srq_ctx ctx;
655 u8 rsvd1[32];
656 __be64 pas[0];
657};
658
659struct mlx5_arm_srq_mbox_in {
660 struct mlx5_inbox_hdr hdr;
661 __be32 srqn;
662 __be16 rsvd;
663 __be16 lwm;
664};
665
666struct mlx5_arm_srq_mbox_out {
667 struct mlx5_outbox_hdr hdr;
668 u8 rsvd[8];
669};
670
671struct mlx5_cq_context {
672 u8 status;
673 u8 cqe_sz_flags;
674 u8 st;
675 u8 rsvd3;
676 u8 rsvd4[6];
677 __be16 page_offset;
678 __be32 log_sz_usr_page;
679 __be16 cq_period;
680 __be16 cq_max_count;
681 __be16 rsvd20;
682 __be16 c_eqn;
683 u8 log_pg_sz;
684 u8 rsvd25[7];
685 __be32 last_notified_index;
686 __be32 solicit_producer_index;
687 __be32 consumer_counter;
688 __be32 producer_counter;
689 u8 rsvd48[8];
690 __be64 db_record_addr;
691};
692
693struct mlx5_create_cq_mbox_in {
694 struct mlx5_inbox_hdr hdr;
695 __be32 input_cqn;
696 u8 rsvdx[4];
697 struct mlx5_cq_context ctx;
698 u8 rsvd6[192];
699 __be64 pas[0];
700};
701
702struct mlx5_create_cq_mbox_out {
703 struct mlx5_outbox_hdr hdr;
704 __be32 cqn;
705 u8 rsvd0[4];
706};
707
708struct mlx5_destroy_cq_mbox_in {
709 struct mlx5_inbox_hdr hdr;
710 __be32 cqn;
711 u8 rsvd0[4];
712};
713
714struct mlx5_destroy_cq_mbox_out {
715 struct mlx5_outbox_hdr hdr;
716 u8 rsvd0[8];
717};
718
719struct mlx5_query_cq_mbox_in {
720 struct mlx5_inbox_hdr hdr;
721 __be32 cqn;
722 u8 rsvd0[4];
723};
724
725struct mlx5_query_cq_mbox_out {
726 struct mlx5_outbox_hdr hdr;
727 u8 rsvd0[8];
728 struct mlx5_cq_context ctx;
729 u8 rsvd6[16];
730 __be64 pas[0];
731};
732
3bdb31f6
EC		 733struct mlx5_modify_cq_mbox_in {
734 struct mlx5_inbox_hdr hdr;
735 __be32 cqn;
736 __be32 field_select;
737 struct mlx5_cq_context ctx;
738 u8 rsvd[192];
739 __be64 pas[0];
740};
741
742struct mlx5_modify_cq_mbox_out {
743 struct mlx5_outbox_hdr hdr;
bde51583 744 u8 rsvd[8];
3bdb31f6
EC		 745};
746
cd23b14b
EC		 747struct mlx5_enable_hca_mbox_in {
748 struct mlx5_inbox_hdr hdr;
749 u8 rsvd[8];
750};
751
752struct mlx5_enable_hca_mbox_out {
753 struct mlx5_outbox_hdr hdr;
754 u8 rsvd[8];
755};
756
757struct mlx5_disable_hca_mbox_in {
758 struct mlx5_inbox_hdr hdr;
759 u8 rsvd[8];
760};
761
762struct mlx5_disable_hca_mbox_out {
763 struct mlx5_outbox_hdr hdr;
764 u8 rsvd[8];
765};
766
e126ba97
EC		 767struct mlx5_eq_context {
768 u8 status;
769 u8 ec_oi;
770 u8 st;
771 u8 rsvd2[7];
772 __be16 page_pffset;
773 __be32 log_sz_usr_page;
774 u8 rsvd3[7];
775 u8 intr;
776 u8 log_page_size;
777 u8 rsvd4[15];
778 __be32 consumer_counter;
779 __be32 produser_counter;
780 u8 rsvd5[16];
781};
782
783struct mlx5_create_eq_mbox_in {
784 struct mlx5_inbox_hdr hdr;
785 u8 rsvd0[3];
786 u8 input_eqn;
787 u8 rsvd1[4];
788 struct mlx5_eq_context ctx;
789 u8 rsvd2[8];
790 __be64 events_mask;
791 u8 rsvd3[176];
792 __be64 pas[0];
793};
794
795struct mlx5_create_eq_mbox_out {
796 struct mlx5_outbox_hdr hdr;
797 u8 rsvd0[3];
798 u8 eq_number;
799 u8 rsvd1[4];
800};
801
802struct mlx5_destroy_eq_mbox_in {
803 struct mlx5_inbox_hdr hdr;
804 u8 rsvd0[3];
805 u8 eqn;
806 u8 rsvd1[4];
807};
808
809struct mlx5_destroy_eq_mbox_out {
810 struct mlx5_outbox_hdr hdr;
811 u8 rsvd[8];
812};
813
814struct mlx5_map_eq_mbox_in {
815 struct mlx5_inbox_hdr hdr;
816 __be64 mask;
817 u8 mu;
818 u8 rsvd0[2];
819 u8 eqn;
820 u8 rsvd1[24];
821};
822
823struct mlx5_map_eq_mbox_out {
824 struct mlx5_outbox_hdr hdr;
825 u8 rsvd[8];
826};
827
828struct mlx5_query_eq_mbox_in {
829 struct mlx5_inbox_hdr hdr;
830 u8 rsvd0[3];
831 u8 eqn;
832 u8 rsvd1[4];
833};
834
835struct mlx5_query_eq_mbox_out {
836 struct mlx5_outbox_hdr hdr;
837 u8 rsvd[8];
838 struct mlx5_eq_context ctx;
839};
840
968e78dd
HE		 841enum {
842 MLX5_MKEY_STATUS_FREE = 1 << 6,
843};
844
e126ba97
EC		 845struct mlx5_mkey_seg {
846 /* This is a two bit field occupying bits 31-30.
847 * bit 31 is always 0,
848 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
849 */
850 u8 status;
851 u8 pcie_control;
852 u8 flags;
853 u8 version;
854 __be32 qpn_mkey7_0;
855 u8 rsvd1[4];
856 __be32 flags_pd;
857 __be64 start_addr;
858 __be64 len;
859 __be32 bsfs_octo_size;
860 u8 rsvd2[16];
861 __be32 xlt_oct_size;
862 u8 rsvd3[3];
863 u8 log2_page_size;
864 u8 rsvd4[4];
865};
866
867struct mlx5_query_special_ctxs_mbox_in {
868 struct mlx5_inbox_hdr hdr;
869 u8 rsvd[8];
870};
871
872struct mlx5_query_special_ctxs_mbox_out {
873 struct mlx5_outbox_hdr hdr;
874 __be32 dump_fill_mkey;
875 __be32 reserved_lkey;
876};
877
878struct mlx5_create_mkey_mbox_in {
879 struct mlx5_inbox_hdr hdr;
880 __be32 input_mkey_index;
e420f0c0 881 __be32 flags;
e126ba97
EC		 882 struct mlx5_mkey_seg seg;
883 u8 rsvd1[16];
884 __be32 xlat_oct_act_size;
8c8a4914
EC		 885 __be32 rsvd2;
886 u8 rsvd3[168];
e126ba97
EC		 887 __be64 pas[0];
888};
889
890struct mlx5_create_mkey_mbox_out {
891 struct mlx5_outbox_hdr hdr;
892 __be32 mkey;
893 u8 rsvd[4];
894};
895
896struct mlx5_destroy_mkey_mbox_in {
897 struct mlx5_inbox_hdr hdr;
898 __be32 mkey;
899 u8 rsvd[4];
900};
901
902struct mlx5_destroy_mkey_mbox_out {
903 struct mlx5_outbox_hdr hdr;
904 u8 rsvd[8];
905};
906
907struct mlx5_query_mkey_mbox_in {
908 struct mlx5_inbox_hdr hdr;
909 __be32 mkey;
910};
911
912struct mlx5_query_mkey_mbox_out {
913 struct mlx5_outbox_hdr hdr;
914 __be64 pas[0];
915};
916
917struct mlx5_modify_mkey_mbox_in {
918 struct mlx5_inbox_hdr hdr;
919 __be32 mkey;
920 __be64 pas[0];
921};
922
923struct mlx5_modify_mkey_mbox_out {
924 struct mlx5_outbox_hdr hdr;
3bdb31f6 925 u8 rsvd[8];
e126ba97
EC		 926};
927
928struct mlx5_dump_mkey_mbox_in {
929 struct mlx5_inbox_hdr hdr;
930};
931
932struct mlx5_dump_mkey_mbox_out {
933 struct mlx5_outbox_hdr hdr;
934 __be32 mkey;
935};
936
937struct mlx5_mad_ifc_mbox_in {
938 struct mlx5_inbox_hdr hdr;
939 __be16 remote_lid;
940 u8 rsvd0;
941 u8 port;
942 u8 rsvd1[4];
943 u8 data[256];
944};
945
946struct mlx5_mad_ifc_mbox_out {
947 struct mlx5_outbox_hdr hdr;
948 u8 rsvd[8];
949 u8 data[256];
950};
951
952struct mlx5_access_reg_mbox_in {
953 struct mlx5_inbox_hdr hdr;
954 u8 rsvd0[2];
955 __be16 register_id;
956 __be32 arg;
957 __be32 data[0];
958};
959
960struct mlx5_access_reg_mbox_out {
961 struct mlx5_outbox_hdr hdr;
962 u8 rsvd[8];
963 __be32 data[0];
964};
965
966#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
967
968enum {
969 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
970};
971
3121e3c4
SG		 972struct mlx5_allocate_psv_in {
973 struct mlx5_inbox_hdr hdr;
974 __be32 npsv_pd;
975 __be32 rsvd_psv0;
976};
977
978struct mlx5_allocate_psv_out {
979 struct mlx5_outbox_hdr hdr;
980 u8 rsvd[8];
981 __be32 psv_idx[4];
982};
983
984struct mlx5_destroy_psv_in {
985 struct mlx5_inbox_hdr hdr;
986 __be32 psv_number;
987 u8 rsvd[4];
988};
989
990struct mlx5_destroy_psv_out {
991 struct mlx5_outbox_hdr hdr;
992 u8 rsvd[8];
993};
994
e126ba97 995#endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
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