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IB/mlx5: Make sure doorbell record is visible before doorbell
[deliverable/linux.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
47enum {
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
51};
52
53enum {
54 MLX5_EXTENDED_UD_AV = 0x80000000,
55};
56
57enum {
58 MLX5_CQ_STATE_ARMED = 9,
59 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
60 MLX5_CQ_STATE_FIRED = 0xa,
61};
62
63enum {
64 MLX5_STAT_RATE_OFFSET = 5,
65};
66
67enum {
68 MLX5_INLINE_SEG = 0x80000000,
69};
70
71enum {
72 MLX5_PERM_LOCAL_READ = 1 << 2,
73 MLX5_PERM_LOCAL_WRITE = 1 << 3,
74 MLX5_PERM_REMOTE_READ = 1 << 4,
75 MLX5_PERM_REMOTE_WRITE = 1 << 5,
76 MLX5_PERM_ATOMIC = 1 << 6,
77 MLX5_PERM_UMR_EN = 1 << 7,
78};
79
80enum {
81 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
82 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
83 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
84 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
85 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
86};
87
88enum {
89 MLX5_ACCESS_MODE_PA = 0,
90 MLX5_ACCESS_MODE_MTT = 1,
91 MLX5_ACCESS_MODE_KLM = 2
92};
93
94enum {
95 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
96 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
97 MLX5_MKEY_BSF_EN = 1 << 30,
98 MLX5_MKEY_LEN64 = 1 << 31,
99};
100
101enum {
102 MLX5_EN_RD = (u64)1,
103 MLX5_EN_WR = (u64)2
104};
105
106enum {
c1be5232
EC		 107 MLX5_BF_REGS_PER_PAGE = 4,
108 MLX5_MAX_UAR_PAGES = 1 << 8,
109 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
110 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 111};
112
113enum {
114 MLX5_MKEY_MASK_LEN = 1ull << 0,
115 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
116 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
117 MLX5_MKEY_MASK_PD = 1ull << 7,
118 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
119 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
120 MLX5_MKEY_MASK_KEY = 1ull << 13,
121 MLX5_MKEY_MASK_QPN = 1ull << 14,
122 MLX5_MKEY_MASK_LR = 1ull << 17,
123 MLX5_MKEY_MASK_LW = 1ull << 18,
124 MLX5_MKEY_MASK_RR = 1ull << 19,
125 MLX5_MKEY_MASK_RW = 1ull << 20,
126 MLX5_MKEY_MASK_A = 1ull << 21,
127 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
128 MLX5_MKEY_MASK_FREE = 1ull << 29,
129};
130
131enum mlx5_event {
132 MLX5_EVENT_TYPE_COMP = 0x0,
133
134 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
135 MLX5_EVENT_TYPE_COMM_EST = 0x02,
136 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
137 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
138 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
139
140 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
141 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
142 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
143 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
144 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
145 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
146
147 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
148 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
149 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
150 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
151
152 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
153 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
154
155 MLX5_EVENT_TYPE_CMD = 0x0a,
156 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
157};
158
159enum {
160 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
161 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
162 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
163 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
164 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
165 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
166 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
167};
168
169enum {
170 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
171 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
172 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
173 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
174 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
175 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
176 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
177 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
178 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
179 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
180 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
181 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
182 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
183 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
184 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
c1868b82 185 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 186};
187
188enum {
189 MLX5_OPCODE_NOP = 0x00,
190 MLX5_OPCODE_SEND_INVAL = 0x01,
191 MLX5_OPCODE_RDMA_WRITE = 0x08,
192 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
193 MLX5_OPCODE_SEND = 0x0a,
194 MLX5_OPCODE_SEND_IMM = 0x0b,
195 MLX5_OPCODE_RDMA_READ = 0x10,
196 MLX5_OPCODE_ATOMIC_CS = 0x11,
197 MLX5_OPCODE_ATOMIC_FA = 0x12,
198 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
199 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
200 MLX5_OPCODE_BIND_MW = 0x18,
201 MLX5_OPCODE_CONFIG_CMD = 0x1f,
202
203 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
204 MLX5_RECV_OPCODE_SEND = 0x01,
205 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
206 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
207
208 MLX5_CQE_OPCODE_ERROR = 0x1e,
209 MLX5_CQE_OPCODE_RESIZE = 0x16,
210
211 MLX5_OPCODE_SET_PSV = 0x20,
212 MLX5_OPCODE_GET_PSV = 0x21,
213 MLX5_OPCODE_CHECK_PSV = 0x22,
214 MLX5_OPCODE_RGET_PSV = 0x26,
215 MLX5_OPCODE_RCHECK_PSV = 0x27,
216
217 MLX5_OPCODE_UMR = 0x25,
218
219};
220
221enum {
222 MLX5_SET_PORT_RESET_QKEY = 0,
223 MLX5_SET_PORT_GUID0 = 16,
224 MLX5_SET_PORT_NODE_GUID = 17,
225 MLX5_SET_PORT_SYS_GUID = 18,
226 MLX5_SET_PORT_GID_TABLE = 19,
227 MLX5_SET_PORT_PKEY_TABLE = 20,
228};
229
230enum {
231 MLX5_MAX_PAGE_SHIFT = 31
232};
233
1b77d2bd
EC		 234enum {
235 MLX5_ADAPTER_PAGE_SHIFT = 12
236};
237
87b8de49
EC		 238enum {
239 MLX5_CAP_OFF_DCT = 41,
240 MLX5_CAP_OFF_CMDIF_CSUM = 46,
241};
242
e126ba97
EC		 243struct mlx5_inbox_hdr {
244 __be16 opcode;
245 u8 rsvd[4];
246 __be16 opmod;
247};
248
249struct mlx5_outbox_hdr {
250 u8 status;
251 u8 rsvd[3];
252 __be32 syndrome;
253};
254
255struct mlx5_cmd_query_adapter_mbox_in {
256 struct mlx5_inbox_hdr hdr;
257 u8 rsvd[8];
258};
259
260struct mlx5_cmd_query_adapter_mbox_out {
261 struct mlx5_outbox_hdr hdr;
262 u8 rsvd0[24];
263 u8 intapin;
264 u8 rsvd1[13];
265 __be16 vsd_vendor_id;
266 u8 vsd[208];
267 u8 vsd_psid[16];
268};
269
270struct mlx5_hca_cap {
271 u8 rsvd1[16];
272 u8 log_max_srq_sz;
273 u8 log_max_qp_sz;
274 u8 rsvd2;
275 u8 log_max_qp;
276 u8 log_max_strq_sz;
277 u8 log_max_srqs;
278 u8 rsvd4[2];
279 u8 rsvd5;
280 u8 log_max_cq_sz;
281 u8 rsvd6;
282 u8 log_max_cq;
283 u8 log_max_eq_sz;
284 u8 log_max_mkey;
285 u8 rsvd7;
286 u8 log_max_eq;
287 u8 max_indirection;
288 u8 log_max_mrw_sz;
289 u8 log_max_bsf_list_sz;
290 u8 log_max_klm_list_sz;
291 u8 rsvd_8_0;
292 u8 log_max_ra_req_dc;
293 u8 rsvd_8_1;
294 u8 log_max_ra_res_dc;
295 u8 rsvd9;
296 u8 log_max_ra_req_qp;
297 u8 rsvd10;
298 u8 log_max_ra_res_qp;
299 u8 rsvd11[4];
300 __be16 max_qp_count;
301 __be16 rsvd12;
302 u8 rsvd13;
303 u8 local_ca_ack_delay;
304 u8 rsvd14;
305 u8 num_ports;
306 u8 log_max_msg;
307 u8 rsvd15[3];
308 __be16 stat_rate_support;
309 u8 rsvd16[2];
310 __be64 flags;
311 u8 rsvd17;
312 u8 uar_sz;
313 u8 rsvd18;
314 u8 log_pg_sz;
315 __be16 bf_log_bf_reg_size;
316 u8 rsvd19[4];
317 __be16 max_desc_sz_sq;
318 u8 rsvd20[2];
319 __be16 max_desc_sz_rq;
320 u8 rsvd21[2];
321 __be16 max_desc_sz_sq_dc;
0a324f31
ML		 322 __be32 max_qp_mcg;
323 u8 rsvd22[3];
e126ba97 324 u8 log_max_mcg;
0a324f31 325 u8 rsvd23;
e126ba97 326 u8 log_max_pd;
0a324f31 327 u8 rsvd24;
e126ba97 328 u8 log_max_xrcd;
0a324f31 329 u8 rsvd25[42];
288dde9f 330 __be16 log_uar_page_sz;
0a324f31 331 u8 rsvd26[28];
87b8de49 332 u8 log_max_atomic_size_qp;
0a324f31 333 u8 rsvd27[2];
87b8de49 334 u8 log_max_atomic_size_dc;
0a324f31 335 u8 rsvd28[76];
e126ba97
EC		 336};
337
338
339struct mlx5_cmd_query_hca_cap_mbox_in {
340 struct mlx5_inbox_hdr hdr;
341 u8 rsvd[8];
342};
343
344
345struct mlx5_cmd_query_hca_cap_mbox_out {
346 struct mlx5_outbox_hdr hdr;
347 u8 rsvd0[8];
348 struct mlx5_hca_cap hca_cap;
349};
350
351
352struct mlx5_cmd_set_hca_cap_mbox_in {
353 struct mlx5_inbox_hdr hdr;
354 u8 rsvd[8];
355 struct mlx5_hca_cap hca_cap;
356};
357
358
359struct mlx5_cmd_set_hca_cap_mbox_out {
360 struct mlx5_outbox_hdr hdr;
361 u8 rsvd0[8];
362};
363
364
365struct mlx5_cmd_init_hca_mbox_in {
366 struct mlx5_inbox_hdr hdr;
367 u8 rsvd0[2];
368 __be16 profile;
369 u8 rsvd1[4];
370};
371
372struct mlx5_cmd_init_hca_mbox_out {
373 struct mlx5_outbox_hdr hdr;
374 u8 rsvd[8];
375};
376
377struct mlx5_cmd_teardown_hca_mbox_in {
378 struct mlx5_inbox_hdr hdr;
379 u8 rsvd0[2];
380 __be16 profile;
381 u8 rsvd1[4];
382};
383
384struct mlx5_cmd_teardown_hca_mbox_out {
385 struct mlx5_outbox_hdr hdr;
386 u8 rsvd[8];
387};
388
389struct mlx5_cmd_layout {
390 u8 type;
391 u8 rsvd0[3];
392 __be32 inlen;
393 __be64 in_ptr;
394 __be32 in[4];
395 __be32 out[4];
396 __be64 out_ptr;
397 __be32 outlen;
398 u8 token;
399 u8 sig;
400 u8 rsvd1;
401 u8 status_own;
402};
403
404
405struct health_buffer {
406 __be32 assert_var[5];
407 __be32 rsvd0[3];
408 __be32 assert_exit_ptr;
409 __be32 assert_callra;
410 __be32 rsvd1[2];
411 __be32 fw_ver;
412 __be32 hw_id;
413 __be32 rsvd2;
414 u8 irisc_index;
415 u8 synd;
416 __be16 ext_sync;
417};
418
419struct mlx5_init_seg {
420 __be32 fw_rev;
421 __be32 cmdif_rev_fw_sub;
422 __be32 rsvd0[2];
423 __be32 cmdq_addr_h;
424 __be32 cmdq_addr_l_sz;
425 __be32 cmd_dbell;
426 __be32 rsvd1[121];
427 struct health_buffer health;
428 __be32 rsvd2[884];
429 __be32 health_counter;
2f6daec1 430 __be32 rsvd3[1019];
e126ba97
EC		 431 __be64 ieee1588_clk;
432 __be32 ieee1588_clk_type;
433 __be32 clr_intx;
434};
435
436struct mlx5_eqe_comp {
437 __be32 reserved[6];
438 __be32 cqn;
439};
440
441struct mlx5_eqe_qp_srq {
442 __be32 reserved[6];
443 __be32 qp_srq_n;
444};
445
446struct mlx5_eqe_cq_err {
447 __be32 cqn;
448 u8 reserved1[7];
449 u8 syndrome;
450};
451
452struct mlx5_eqe_dropped_packet {
453};
454
455struct mlx5_eqe_port_state {
456 u8 reserved0[8];
457 u8 port;
458};
459
460struct mlx5_eqe_gpio {
461 __be32 reserved0[2];
462 __be64 gpio_event;
463};
464
465struct mlx5_eqe_congestion {
466 u8 type;
467 u8 rsvd0;
468 u8 congestion_level;
469};
470
471struct mlx5_eqe_stall_vl {
472 u8 rsvd0[3];
473 u8 port_vl;
474};
475
476struct mlx5_eqe_cmd {
477 __be32 vector;
478 __be32 rsvd[6];
479};
480
481struct mlx5_eqe_page_req {
482 u8 rsvd0[2];
483 __be16 func_id;
0a324f31
ML		 484 __be32 num_pages;
485 __be32 rsvd1[5];
e126ba97
EC		 486};
487
488union ev_data {
489 __be32 raw[7];
490 struct mlx5_eqe_cmd cmd;
491 struct mlx5_eqe_comp comp;
492 struct mlx5_eqe_qp_srq qp_srq;
493 struct mlx5_eqe_cq_err cq_err;
494 struct mlx5_eqe_dropped_packet dp;
495 struct mlx5_eqe_port_state port;
496 struct mlx5_eqe_gpio gpio;
497 struct mlx5_eqe_congestion cong;
498 struct mlx5_eqe_stall_vl stall_vl;
499 struct mlx5_eqe_page_req req_pages;
500} __packed;
501
502struct mlx5_eqe {
503 u8 rsvd0;
504 u8 type;
505 u8 rsvd1;
506 u8 sub_type;
507 __be32 rsvd2[7];
508 union ev_data data;
509 __be16 rsvd3;
510 u8 signature;
511 u8 owner;
512} __packed;
513
514struct mlx5_cmd_prot_block {
515 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
516 u8 rsvd0[48];
517 __be64 next;
518 __be32 block_num;
519 u8 rsvd1;
520 u8 token;
521 u8 ctrl_sig;
522 u8 sig;
523};
524
525struct mlx5_err_cqe {
526 u8 rsvd0[32];
527 __be32 srqn;
528 u8 rsvd1[18];
529 u8 vendor_err_synd;
530 u8 syndrome;
531 __be32 s_wqe_opcode_qpn;
532 __be16 wqe_counter;
533 u8 signature;
534 u8 op_own;
535};
536
537struct mlx5_cqe64 {
538 u8 rsvd0[17];
539 u8 ml_path;
540 u8 rsvd20[4];
541 __be16 slid;
542 __be32 flags_rqpn;
543 u8 rsvd28[4];
544 __be32 srqn;
545 __be32 imm_inval_pkey;
546 u8 rsvd40[4];
547 __be32 byte_cnt;
548 __be64 timestamp;
549 __be32 sop_drop_qpn;
550 __be16 wqe_counter;
551 u8 signature;
552 u8 op_own;
553};
554
555struct mlx5_wqe_srq_next_seg {
556 u8 rsvd0[2];
557 __be16 next_wqe_index;
558 u8 signature;
559 u8 rsvd1[11];
560};
561
562union mlx5_ext_cqe {
563 struct ib_grh grh;
564 u8 inl[64];
565};
566
567struct mlx5_cqe128 {
568 union mlx5_ext_cqe inl_grh;
569 struct mlx5_cqe64 cqe64;
570};
571
572struct mlx5_srq_ctx {
573 u8 state_log_sz;
574 u8 rsvd0[3];
575 __be32 flags_xrcd;
576 __be32 pgoff_cqn;
577 u8 rsvd1[4];
578 u8 log_pg_sz;
579 u8 rsvd2[7];
580 __be32 pd;
581 __be16 lwm;
582 __be16 wqe_cnt;
583 u8 rsvd3[8];
584 __be64 db_record;
585};
586
587struct mlx5_create_srq_mbox_in {
588 struct mlx5_inbox_hdr hdr;
589 __be32 input_srqn;
590 u8 rsvd0[4];
591 struct mlx5_srq_ctx ctx;
592 u8 rsvd1[208];
593 __be64 pas[0];
594};
595
596struct mlx5_create_srq_mbox_out {
597 struct mlx5_outbox_hdr hdr;
598 __be32 srqn;
599 u8 rsvd[4];
600};
601
602struct mlx5_destroy_srq_mbox_in {
603 struct mlx5_inbox_hdr hdr;
604 __be32 srqn;
605 u8 rsvd[4];
606};
607
608struct mlx5_destroy_srq_mbox_out {
609 struct mlx5_outbox_hdr hdr;
610 u8 rsvd[8];
611};
612
613struct mlx5_query_srq_mbox_in {
614 struct mlx5_inbox_hdr hdr;
615 __be32 srqn;
616 u8 rsvd0[4];
617};
618
619struct mlx5_query_srq_mbox_out {
620 struct mlx5_outbox_hdr hdr;
621 u8 rsvd0[8];
622 struct mlx5_srq_ctx ctx;
623 u8 rsvd1[32];
624 __be64 pas[0];
625};
626
627struct mlx5_arm_srq_mbox_in {
628 struct mlx5_inbox_hdr hdr;
629 __be32 srqn;
630 __be16 rsvd;
631 __be16 lwm;
632};
633
634struct mlx5_arm_srq_mbox_out {
635 struct mlx5_outbox_hdr hdr;
636 u8 rsvd[8];
637};
638
639struct mlx5_cq_context {
640 u8 status;
641 u8 cqe_sz_flags;
642 u8 st;
643 u8 rsvd3;
644 u8 rsvd4[6];
645 __be16 page_offset;
646 __be32 log_sz_usr_page;
647 __be16 cq_period;
648 __be16 cq_max_count;
649 __be16 rsvd20;
650 __be16 c_eqn;
651 u8 log_pg_sz;
652 u8 rsvd25[7];
653 __be32 last_notified_index;
654 __be32 solicit_producer_index;
655 __be32 consumer_counter;
656 __be32 producer_counter;
657 u8 rsvd48[8];
658 __be64 db_record_addr;
659};
660
661struct mlx5_create_cq_mbox_in {
662 struct mlx5_inbox_hdr hdr;
663 __be32 input_cqn;
664 u8 rsvdx[4];
665 struct mlx5_cq_context ctx;
666 u8 rsvd6[192];
667 __be64 pas[0];
668};
669
670struct mlx5_create_cq_mbox_out {
671 struct mlx5_outbox_hdr hdr;
672 __be32 cqn;
673 u8 rsvd0[4];
674};
675
676struct mlx5_destroy_cq_mbox_in {
677 struct mlx5_inbox_hdr hdr;
678 __be32 cqn;
679 u8 rsvd0[4];
680};
681
682struct mlx5_destroy_cq_mbox_out {
683 struct mlx5_outbox_hdr hdr;
684 u8 rsvd0[8];
685};
686
687struct mlx5_query_cq_mbox_in {
688 struct mlx5_inbox_hdr hdr;
689 __be32 cqn;
690 u8 rsvd0[4];
691};
692
693struct mlx5_query_cq_mbox_out {
694 struct mlx5_outbox_hdr hdr;
695 u8 rsvd0[8];
696 struct mlx5_cq_context ctx;
697 u8 rsvd6[16];
698 __be64 pas[0];
699};
700
cd23b14b
EC		 701struct mlx5_enable_hca_mbox_in {
702 struct mlx5_inbox_hdr hdr;
703 u8 rsvd[8];
704};
705
706struct mlx5_enable_hca_mbox_out {
707 struct mlx5_outbox_hdr hdr;
708 u8 rsvd[8];
709};
710
711struct mlx5_disable_hca_mbox_in {
712 struct mlx5_inbox_hdr hdr;
713 u8 rsvd[8];
714};
715
716struct mlx5_disable_hca_mbox_out {
717 struct mlx5_outbox_hdr hdr;
718 u8 rsvd[8];
719};
720
e126ba97
EC		 721struct mlx5_eq_context {
722 u8 status;
723 u8 ec_oi;
724 u8 st;
725 u8 rsvd2[7];
726 __be16 page_pffset;
727 __be32 log_sz_usr_page;
728 u8 rsvd3[7];
729 u8 intr;
730 u8 log_page_size;
731 u8 rsvd4[15];
732 __be32 consumer_counter;
733 __be32 produser_counter;
734 u8 rsvd5[16];
735};
736
737struct mlx5_create_eq_mbox_in {
738 struct mlx5_inbox_hdr hdr;
739 u8 rsvd0[3];
740 u8 input_eqn;
741 u8 rsvd1[4];
742 struct mlx5_eq_context ctx;
743 u8 rsvd2[8];
744 __be64 events_mask;
745 u8 rsvd3[176];
746 __be64 pas[0];
747};
748
749struct mlx5_create_eq_mbox_out {
750 struct mlx5_outbox_hdr hdr;
751 u8 rsvd0[3];
752 u8 eq_number;
753 u8 rsvd1[4];
754};
755
756struct mlx5_destroy_eq_mbox_in {
757 struct mlx5_inbox_hdr hdr;
758 u8 rsvd0[3];
759 u8 eqn;
760 u8 rsvd1[4];
761};
762
763struct mlx5_destroy_eq_mbox_out {
764 struct mlx5_outbox_hdr hdr;
765 u8 rsvd[8];
766};
767
768struct mlx5_map_eq_mbox_in {
769 struct mlx5_inbox_hdr hdr;
770 __be64 mask;
771 u8 mu;
772 u8 rsvd0[2];
773 u8 eqn;
774 u8 rsvd1[24];
775};
776
777struct mlx5_map_eq_mbox_out {
778 struct mlx5_outbox_hdr hdr;
779 u8 rsvd[8];
780};
781
782struct mlx5_query_eq_mbox_in {
783 struct mlx5_inbox_hdr hdr;
784 u8 rsvd0[3];
785 u8 eqn;
786 u8 rsvd1[4];
787};
788
789struct mlx5_query_eq_mbox_out {
790 struct mlx5_outbox_hdr hdr;
791 u8 rsvd[8];
792 struct mlx5_eq_context ctx;
793};
794
795struct mlx5_mkey_seg {
796 /* This is a two bit field occupying bits 31-30.
797 * bit 31 is always 0,
798 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
799 */
800 u8 status;
801 u8 pcie_control;
802 u8 flags;
803 u8 version;
804 __be32 qpn_mkey7_0;
805 u8 rsvd1[4];
806 __be32 flags_pd;
807 __be64 start_addr;
808 __be64 len;
809 __be32 bsfs_octo_size;
810 u8 rsvd2[16];
811 __be32 xlt_oct_size;
812 u8 rsvd3[3];
813 u8 log2_page_size;
814 u8 rsvd4[4];
815};
816
817struct mlx5_query_special_ctxs_mbox_in {
818 struct mlx5_inbox_hdr hdr;
819 u8 rsvd[8];
820};
821
822struct mlx5_query_special_ctxs_mbox_out {
823 struct mlx5_outbox_hdr hdr;
824 __be32 dump_fill_mkey;
825 __be32 reserved_lkey;
826};
827
828struct mlx5_create_mkey_mbox_in {
829 struct mlx5_inbox_hdr hdr;
830 __be32 input_mkey_index;
831 u8 rsvd0[4];
832 struct mlx5_mkey_seg seg;
833 u8 rsvd1[16];
834 __be32 xlat_oct_act_size;
835 __be32 bsf_coto_act_size;
836 u8 rsvd2[168];
837 __be64 pas[0];
838};
839
840struct mlx5_create_mkey_mbox_out {
841 struct mlx5_outbox_hdr hdr;
842 __be32 mkey;
843 u8 rsvd[4];
844};
845
846struct mlx5_destroy_mkey_mbox_in {
847 struct mlx5_inbox_hdr hdr;
848 __be32 mkey;
849 u8 rsvd[4];
850};
851
852struct mlx5_destroy_mkey_mbox_out {
853 struct mlx5_outbox_hdr hdr;
854 u8 rsvd[8];
855};
856
857struct mlx5_query_mkey_mbox_in {
858 struct mlx5_inbox_hdr hdr;
859 __be32 mkey;
860};
861
862struct mlx5_query_mkey_mbox_out {
863 struct mlx5_outbox_hdr hdr;
864 __be64 pas[0];
865};
866
867struct mlx5_modify_mkey_mbox_in {
868 struct mlx5_inbox_hdr hdr;
869 __be32 mkey;
870 __be64 pas[0];
871};
872
873struct mlx5_modify_mkey_mbox_out {
874 struct mlx5_outbox_hdr hdr;
875};
876
877struct mlx5_dump_mkey_mbox_in {
878 struct mlx5_inbox_hdr hdr;
879};
880
881struct mlx5_dump_mkey_mbox_out {
882 struct mlx5_outbox_hdr hdr;
883 __be32 mkey;
884};
885
886struct mlx5_mad_ifc_mbox_in {
887 struct mlx5_inbox_hdr hdr;
888 __be16 remote_lid;
889 u8 rsvd0;
890 u8 port;
891 u8 rsvd1[4];
892 u8 data[256];
893};
894
895struct mlx5_mad_ifc_mbox_out {
896 struct mlx5_outbox_hdr hdr;
897 u8 rsvd[8];
898 u8 data[256];
899};
900
901struct mlx5_access_reg_mbox_in {
902 struct mlx5_inbox_hdr hdr;
903 u8 rsvd0[2];
904 __be16 register_id;
905 __be32 arg;
906 __be32 data[0];
907};
908
909struct mlx5_access_reg_mbox_out {
910 struct mlx5_outbox_hdr hdr;
911 u8 rsvd[8];
912 __be32 data[0];
913};
914
915#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
916
917enum {
918 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
919};
920
921#endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
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