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e126ba97 EC |
1 | /* |
2 | * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DEVICE_H | |
34 | #define MLX5_DEVICE_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <rdma/ib_verbs.h> | |
38 | ||
39 | #if defined(__LITTLE_ENDIAN) | |
40 | #define MLX5_SET_HOST_ENDIANNESS 0 | |
41 | #elif defined(__BIG_ENDIAN) | |
42 | #define MLX5_SET_HOST_ENDIANNESS 0x80 | |
43 | #else | |
44 | #error Host endianness not defined | |
45 | #endif | |
46 | ||
d29b796a EC |
47 | /* helper macros */ |
48 | #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) | |
49 | #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) | |
50 | #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) | |
51 | #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) | |
52 | #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) | |
53 | #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) | |
54 | #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) | |
55 | #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) | |
56 | #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) | |
57 | ||
58 | #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) | |
59 | #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) | |
60 | #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) | |
61 | #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) | |
62 | #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) | |
63 | ||
64 | /* insert a value to a struct */ | |
65 | #define MLX5_SET(typ, p, fld, v) do { \ | |
66 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ | |
67 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ | |
68 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ | |
69 | (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ | |
70 | << __mlx5_dw_bit_off(typ, fld))); \ | |
71 | } while (0) | |
72 | ||
73 | #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ | |
74 | __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ | |
75 | __mlx5_mask(typ, fld)) | |
76 | ||
77 | #define MLX5_GET_PR(typ, p, fld) ({ \ | |
78 | u32 ___t = MLX5_GET(typ, p, fld); \ | |
79 | pr_debug(#fld " = 0x%x\n", ___t); \ | |
80 | ___t; \ | |
81 | }) | |
82 | ||
83 | #define MLX5_SET64(typ, p, fld, v) do { \ | |
84 | BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ | |
85 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ | |
86 | *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ | |
87 | } while (0) | |
88 | ||
89 | #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) | |
90 | ||
e126ba97 EC |
91 | enum { |
92 | MLX5_MAX_COMMANDS = 32, | |
93 | MLX5_CMD_DATA_BLOCK_SIZE = 512, | |
94 | MLX5_PCI_CMD_XPORT = 7, | |
3121e3c4 SG |
95 | MLX5_MKEY_BSF_OCTO_SIZE = 4, |
96 | MLX5_MAX_PSVS = 4, | |
e126ba97 EC |
97 | }; |
98 | ||
99 | enum { | |
100 | MLX5_EXTENDED_UD_AV = 0x80000000, | |
101 | }; | |
102 | ||
103 | enum { | |
104 | MLX5_CQ_STATE_ARMED = 9, | |
105 | MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, | |
106 | MLX5_CQ_STATE_FIRED = 0xa, | |
107 | }; | |
108 | ||
109 | enum { | |
110 | MLX5_STAT_RATE_OFFSET = 5, | |
111 | }; | |
112 | ||
113 | enum { | |
114 | MLX5_INLINE_SEG = 0x80000000, | |
115 | }; | |
116 | ||
c7a08ac7 EC |
117 | enum { |
118 | MLX5_MIN_PKEY_TABLE_SIZE = 128, | |
119 | MLX5_MAX_LOG_PKEY_TABLE = 5, | |
120 | }; | |
121 | ||
e420f0c0 HE |
122 | enum { |
123 | MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 | |
124 | }; | |
125 | ||
126 | enum { | |
127 | MLX5_PFAULT_SUBTYPE_WQE = 0, | |
128 | MLX5_PFAULT_SUBTYPE_RDMA = 1, | |
129 | }; | |
130 | ||
e126ba97 EC |
131 | enum { |
132 | MLX5_PERM_LOCAL_READ = 1 << 2, | |
133 | MLX5_PERM_LOCAL_WRITE = 1 << 3, | |
134 | MLX5_PERM_REMOTE_READ = 1 << 4, | |
135 | MLX5_PERM_REMOTE_WRITE = 1 << 5, | |
136 | MLX5_PERM_ATOMIC = 1 << 6, | |
137 | MLX5_PERM_UMR_EN = 1 << 7, | |
138 | }; | |
139 | ||
140 | enum { | |
141 | MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, | |
142 | MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, | |
143 | MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, | |
144 | MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, | |
145 | MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, | |
146 | }; | |
147 | ||
148 | enum { | |
149 | MLX5_ACCESS_MODE_PA = 0, | |
150 | MLX5_ACCESS_MODE_MTT = 1, | |
151 | MLX5_ACCESS_MODE_KLM = 2 | |
152 | }; | |
153 | ||
154 | enum { | |
155 | MLX5_MKEY_REMOTE_INVAL = 1 << 24, | |
156 | MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, | |
157 | MLX5_MKEY_BSF_EN = 1 << 30, | |
158 | MLX5_MKEY_LEN64 = 1 << 31, | |
159 | }; | |
160 | ||
161 | enum { | |
162 | MLX5_EN_RD = (u64)1, | |
163 | MLX5_EN_WR = (u64)2 | |
164 | }; | |
165 | ||
166 | enum { | |
c1be5232 EC |
167 | MLX5_BF_REGS_PER_PAGE = 4, |
168 | MLX5_MAX_UAR_PAGES = 1 << 8, | |
169 | MLX5_NON_FP_BF_REGS_PER_PAGE = 2, | |
170 | MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, | |
e126ba97 EC |
171 | }; |
172 | ||
173 | enum { | |
174 | MLX5_MKEY_MASK_LEN = 1ull << 0, | |
175 | MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, | |
176 | MLX5_MKEY_MASK_START_ADDR = 1ull << 6, | |
177 | MLX5_MKEY_MASK_PD = 1ull << 7, | |
178 | MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, | |
d5436ba0 | 179 | MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, |
e126ba97 EC |
180 | MLX5_MKEY_MASK_BSF_EN = 1ull << 12, |
181 | MLX5_MKEY_MASK_KEY = 1ull << 13, | |
182 | MLX5_MKEY_MASK_QPN = 1ull << 14, | |
183 | MLX5_MKEY_MASK_LR = 1ull << 17, | |
184 | MLX5_MKEY_MASK_LW = 1ull << 18, | |
185 | MLX5_MKEY_MASK_RR = 1ull << 19, | |
186 | MLX5_MKEY_MASK_RW = 1ull << 20, | |
187 | MLX5_MKEY_MASK_A = 1ull << 21, | |
188 | MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, | |
189 | MLX5_MKEY_MASK_FREE = 1ull << 29, | |
190 | }; | |
191 | ||
968e78dd HE |
192 | enum { |
193 | MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), | |
194 | ||
195 | MLX5_UMR_CHECK_NOT_FREE = (1 << 5), | |
196 | MLX5_UMR_CHECK_FREE = (2 << 5), | |
197 | ||
198 | MLX5_UMR_INLINE = (1 << 7), | |
199 | }; | |
200 | ||
cc149f75 HE |
201 | #define MLX5_UMR_MTT_ALIGNMENT 0x40 |
202 | #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) | |
203 | ||
e126ba97 EC |
204 | enum mlx5_event { |
205 | MLX5_EVENT_TYPE_COMP = 0x0, | |
206 | ||
207 | MLX5_EVENT_TYPE_PATH_MIG = 0x01, | |
208 | MLX5_EVENT_TYPE_COMM_EST = 0x02, | |
209 | MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, | |
210 | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | |
211 | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | |
212 | ||
213 | MLX5_EVENT_TYPE_CQ_ERROR = 0x04, | |
214 | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
215 | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
216 | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
217 | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
218 | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
219 | ||
220 | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, | |
221 | MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, | |
222 | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | |
223 | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, | |
224 | ||
225 | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | |
226 | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | |
227 | ||
228 | MLX5_EVENT_TYPE_CMD = 0x0a, | |
229 | MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, | |
e420f0c0 HE |
230 | |
231 | MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, | |
e126ba97 EC |
232 | }; |
233 | ||
234 | enum { | |
235 | MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
236 | MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, | |
237 | MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, | |
238 | MLX5_PORT_CHANGE_SUBTYPE_LID = 6, | |
239 | MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, | |
240 | MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, | |
241 | MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, | |
242 | }; | |
243 | ||
244 | enum { | |
e126ba97 | 245 | MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, |
e126ba97 EC |
246 | MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, |
247 | MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
248 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, | |
249 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
f360d88a | 250 | MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, |
6cb7ff3d | 251 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, |
3bdb31f6 | 252 | MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, |
bde51583 | 253 | MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, |
c7a08ac7 | 254 | MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, |
e126ba97 | 255 | MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, |
c1868b82 | 256 | MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, |
e126ba97 EC |
257 | }; |
258 | ||
259 | enum { | |
260 | MLX5_OPCODE_NOP = 0x00, | |
261 | MLX5_OPCODE_SEND_INVAL = 0x01, | |
262 | MLX5_OPCODE_RDMA_WRITE = 0x08, | |
263 | MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, | |
264 | MLX5_OPCODE_SEND = 0x0a, | |
265 | MLX5_OPCODE_SEND_IMM = 0x0b, | |
266 | MLX5_OPCODE_RDMA_READ = 0x10, | |
267 | MLX5_OPCODE_ATOMIC_CS = 0x11, | |
268 | MLX5_OPCODE_ATOMIC_FA = 0x12, | |
269 | MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, | |
270 | MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, | |
271 | MLX5_OPCODE_BIND_MW = 0x18, | |
272 | MLX5_OPCODE_CONFIG_CMD = 0x1f, | |
273 | ||
274 | MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
275 | MLX5_RECV_OPCODE_SEND = 0x01, | |
276 | MLX5_RECV_OPCODE_SEND_IMM = 0x02, | |
277 | MLX5_RECV_OPCODE_SEND_INVAL = 0x03, | |
278 | ||
279 | MLX5_CQE_OPCODE_ERROR = 0x1e, | |
280 | MLX5_CQE_OPCODE_RESIZE = 0x16, | |
281 | ||
282 | MLX5_OPCODE_SET_PSV = 0x20, | |
283 | MLX5_OPCODE_GET_PSV = 0x21, | |
284 | MLX5_OPCODE_CHECK_PSV = 0x22, | |
285 | MLX5_OPCODE_RGET_PSV = 0x26, | |
286 | MLX5_OPCODE_RCHECK_PSV = 0x27, | |
287 | ||
288 | MLX5_OPCODE_UMR = 0x25, | |
289 | ||
290 | }; | |
291 | ||
292 | enum { | |
293 | MLX5_SET_PORT_RESET_QKEY = 0, | |
294 | MLX5_SET_PORT_GUID0 = 16, | |
295 | MLX5_SET_PORT_NODE_GUID = 17, | |
296 | MLX5_SET_PORT_SYS_GUID = 18, | |
297 | MLX5_SET_PORT_GID_TABLE = 19, | |
298 | MLX5_SET_PORT_PKEY_TABLE = 20, | |
299 | }; | |
300 | ||
301 | enum { | |
302 | MLX5_MAX_PAGE_SHIFT = 31 | |
303 | }; | |
304 | ||
1b77d2bd | 305 | enum { |
05bdb2ab EC |
306 | MLX5_ADAPTER_PAGE_SHIFT = 12, |
307 | MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, | |
1b77d2bd EC |
308 | }; |
309 | ||
87b8de49 | 310 | enum { |
87b8de49 EC |
311 | MLX5_CAP_OFF_CMDIF_CSUM = 46, |
312 | }; | |
313 | ||
c7a08ac7 EC |
314 | enum { |
315 | HCA_CAP_OPMOD_GET_MAX = 0, | |
316 | HCA_CAP_OPMOD_GET_CUR = 1, | |
e420f0c0 HE |
317 | HCA_CAP_OPMOD_GET_ODP_MAX = 4, |
318 | HCA_CAP_OPMOD_GET_ODP_CUR = 5 | |
c7a08ac7 EC |
319 | }; |
320 | ||
e126ba97 EC |
321 | struct mlx5_inbox_hdr { |
322 | __be16 opcode; | |
323 | u8 rsvd[4]; | |
324 | __be16 opmod; | |
325 | }; | |
326 | ||
327 | struct mlx5_outbox_hdr { | |
328 | u8 status; | |
329 | u8 rsvd[3]; | |
330 | __be32 syndrome; | |
331 | }; | |
332 | ||
333 | struct mlx5_cmd_query_adapter_mbox_in { | |
334 | struct mlx5_inbox_hdr hdr; | |
335 | u8 rsvd[8]; | |
336 | }; | |
337 | ||
338 | struct mlx5_cmd_query_adapter_mbox_out { | |
339 | struct mlx5_outbox_hdr hdr; | |
340 | u8 rsvd0[24]; | |
341 | u8 intapin; | |
342 | u8 rsvd1[13]; | |
343 | __be16 vsd_vendor_id; | |
344 | u8 vsd[208]; | |
345 | u8 vsd_psid[16]; | |
346 | }; | |
347 | ||
e420f0c0 HE |
348 | enum mlx5_odp_transport_cap_bits { |
349 | MLX5_ODP_SUPPORT_SEND = 1 << 31, | |
350 | MLX5_ODP_SUPPORT_RECV = 1 << 30, | |
351 | MLX5_ODP_SUPPORT_WRITE = 1 << 29, | |
352 | MLX5_ODP_SUPPORT_READ = 1 << 28, | |
353 | }; | |
354 | ||
355 | struct mlx5_odp_caps { | |
356 | char reserved[0x10]; | |
357 | struct { | |
358 | __be32 rc_odp_caps; | |
359 | __be32 uc_odp_caps; | |
360 | __be32 ud_odp_caps; | |
361 | } per_transport_caps; | |
362 | char reserved2[0xe4]; | |
363 | }; | |
364 | ||
e126ba97 EC |
365 | struct mlx5_cmd_init_hca_mbox_in { |
366 | struct mlx5_inbox_hdr hdr; | |
367 | u8 rsvd0[2]; | |
368 | __be16 profile; | |
369 | u8 rsvd1[4]; | |
370 | }; | |
371 | ||
372 | struct mlx5_cmd_init_hca_mbox_out { | |
373 | struct mlx5_outbox_hdr hdr; | |
374 | u8 rsvd[8]; | |
375 | }; | |
376 | ||
377 | struct mlx5_cmd_teardown_hca_mbox_in { | |
378 | struct mlx5_inbox_hdr hdr; | |
379 | u8 rsvd0[2]; | |
380 | __be16 profile; | |
381 | u8 rsvd1[4]; | |
382 | }; | |
383 | ||
384 | struct mlx5_cmd_teardown_hca_mbox_out { | |
385 | struct mlx5_outbox_hdr hdr; | |
386 | u8 rsvd[8]; | |
387 | }; | |
388 | ||
389 | struct mlx5_cmd_layout { | |
390 | u8 type; | |
391 | u8 rsvd0[3]; | |
392 | __be32 inlen; | |
393 | __be64 in_ptr; | |
394 | __be32 in[4]; | |
395 | __be32 out[4]; | |
396 | __be64 out_ptr; | |
397 | __be32 outlen; | |
398 | u8 token; | |
399 | u8 sig; | |
400 | u8 rsvd1; | |
401 | u8 status_own; | |
402 | }; | |
403 | ||
404 | ||
405 | struct health_buffer { | |
406 | __be32 assert_var[5]; | |
407 | __be32 rsvd0[3]; | |
408 | __be32 assert_exit_ptr; | |
409 | __be32 assert_callra; | |
410 | __be32 rsvd1[2]; | |
411 | __be32 fw_ver; | |
412 | __be32 hw_id; | |
413 | __be32 rsvd2; | |
414 | u8 irisc_index; | |
415 | u8 synd; | |
416 | __be16 ext_sync; | |
417 | }; | |
418 | ||
419 | struct mlx5_init_seg { | |
420 | __be32 fw_rev; | |
421 | __be32 cmdif_rev_fw_sub; | |
422 | __be32 rsvd0[2]; | |
423 | __be32 cmdq_addr_h; | |
424 | __be32 cmdq_addr_l_sz; | |
425 | __be32 cmd_dbell; | |
426 | __be32 rsvd1[121]; | |
427 | struct health_buffer health; | |
428 | __be32 rsvd2[884]; | |
429 | __be32 health_counter; | |
2f6daec1 | 430 | __be32 rsvd3[1019]; |
e126ba97 EC |
431 | __be64 ieee1588_clk; |
432 | __be32 ieee1588_clk_type; | |
433 | __be32 clr_intx; | |
434 | }; | |
435 | ||
436 | struct mlx5_eqe_comp { | |
437 | __be32 reserved[6]; | |
438 | __be32 cqn; | |
439 | }; | |
440 | ||
441 | struct mlx5_eqe_qp_srq { | |
442 | __be32 reserved[6]; | |
443 | __be32 qp_srq_n; | |
444 | }; | |
445 | ||
446 | struct mlx5_eqe_cq_err { | |
447 | __be32 cqn; | |
448 | u8 reserved1[7]; | |
449 | u8 syndrome; | |
450 | }; | |
451 | ||
e126ba97 EC |
452 | struct mlx5_eqe_port_state { |
453 | u8 reserved0[8]; | |
454 | u8 port; | |
455 | }; | |
456 | ||
457 | struct mlx5_eqe_gpio { | |
458 | __be32 reserved0[2]; | |
459 | __be64 gpio_event; | |
460 | }; | |
461 | ||
462 | struct mlx5_eqe_congestion { | |
463 | u8 type; | |
464 | u8 rsvd0; | |
465 | u8 congestion_level; | |
466 | }; | |
467 | ||
468 | struct mlx5_eqe_stall_vl { | |
469 | u8 rsvd0[3]; | |
470 | u8 port_vl; | |
471 | }; | |
472 | ||
473 | struct mlx5_eqe_cmd { | |
474 | __be32 vector; | |
475 | __be32 rsvd[6]; | |
476 | }; | |
477 | ||
478 | struct mlx5_eqe_page_req { | |
479 | u8 rsvd0[2]; | |
480 | __be16 func_id; | |
0a324f31 ML |
481 | __be32 num_pages; |
482 | __be32 rsvd1[5]; | |
e126ba97 EC |
483 | }; |
484 | ||
e420f0c0 HE |
485 | struct mlx5_eqe_page_fault { |
486 | __be32 bytes_committed; | |
487 | union { | |
488 | struct { | |
489 | u16 reserved1; | |
490 | __be16 wqe_index; | |
491 | u16 reserved2; | |
492 | __be16 packet_length; | |
493 | u8 reserved3[12]; | |
494 | } __packed wqe; | |
495 | struct { | |
496 | __be32 r_key; | |
497 | u16 reserved1; | |
498 | __be16 packet_length; | |
499 | __be32 rdma_op_len; | |
500 | __be64 rdma_va; | |
501 | } __packed rdma; | |
502 | } __packed; | |
503 | __be32 flags_qpn; | |
504 | } __packed; | |
505 | ||
e126ba97 EC |
506 | union ev_data { |
507 | __be32 raw[7]; | |
508 | struct mlx5_eqe_cmd cmd; | |
509 | struct mlx5_eqe_comp comp; | |
510 | struct mlx5_eqe_qp_srq qp_srq; | |
511 | struct mlx5_eqe_cq_err cq_err; | |
e126ba97 EC |
512 | struct mlx5_eqe_port_state port; |
513 | struct mlx5_eqe_gpio gpio; | |
514 | struct mlx5_eqe_congestion cong; | |
515 | struct mlx5_eqe_stall_vl stall_vl; | |
516 | struct mlx5_eqe_page_req req_pages; | |
e420f0c0 | 517 | struct mlx5_eqe_page_fault page_fault; |
e126ba97 EC |
518 | } __packed; |
519 | ||
520 | struct mlx5_eqe { | |
521 | u8 rsvd0; | |
522 | u8 type; | |
523 | u8 rsvd1; | |
524 | u8 sub_type; | |
525 | __be32 rsvd2[7]; | |
526 | union ev_data data; | |
527 | __be16 rsvd3; | |
528 | u8 signature; | |
529 | u8 owner; | |
530 | } __packed; | |
531 | ||
532 | struct mlx5_cmd_prot_block { | |
533 | u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; | |
534 | u8 rsvd0[48]; | |
535 | __be64 next; | |
536 | __be32 block_num; | |
537 | u8 rsvd1; | |
538 | u8 token; | |
539 | u8 ctrl_sig; | |
540 | u8 sig; | |
541 | }; | |
542 | ||
543 | struct mlx5_err_cqe { | |
544 | u8 rsvd0[32]; | |
545 | __be32 srqn; | |
546 | u8 rsvd1[18]; | |
547 | u8 vendor_err_synd; | |
548 | u8 syndrome; | |
549 | __be32 s_wqe_opcode_qpn; | |
550 | __be16 wqe_counter; | |
551 | u8 signature; | |
552 | u8 op_own; | |
553 | }; | |
554 | ||
555 | struct mlx5_cqe64 { | |
556 | u8 rsvd0[17]; | |
557 | u8 ml_path; | |
558 | u8 rsvd20[4]; | |
559 | __be16 slid; | |
560 | __be32 flags_rqpn; | |
561 | u8 rsvd28[4]; | |
562 | __be32 srqn; | |
563 | __be32 imm_inval_pkey; | |
564 | u8 rsvd40[4]; | |
565 | __be32 byte_cnt; | |
566 | __be64 timestamp; | |
567 | __be32 sop_drop_qpn; | |
568 | __be16 wqe_counter; | |
569 | u8 signature; | |
570 | u8 op_own; | |
571 | }; | |
572 | ||
d5436ba0 SG |
573 | struct mlx5_sig_err_cqe { |
574 | u8 rsvd0[16]; | |
575 | __be32 expected_trans_sig; | |
576 | __be32 actual_trans_sig; | |
577 | __be32 expected_reftag; | |
578 | __be32 actual_reftag; | |
579 | __be16 syndrome; | |
580 | u8 rsvd22[2]; | |
581 | __be32 mkey; | |
582 | __be64 err_offset; | |
583 | u8 rsvd30[8]; | |
584 | __be32 qpn; | |
585 | u8 rsvd38[2]; | |
586 | u8 signature; | |
587 | u8 op_own; | |
588 | }; | |
589 | ||
e126ba97 EC |
590 | struct mlx5_wqe_srq_next_seg { |
591 | u8 rsvd0[2]; | |
592 | __be16 next_wqe_index; | |
593 | u8 signature; | |
594 | u8 rsvd1[11]; | |
595 | }; | |
596 | ||
597 | union mlx5_ext_cqe { | |
598 | struct ib_grh grh; | |
599 | u8 inl[64]; | |
600 | }; | |
601 | ||
602 | struct mlx5_cqe128 { | |
603 | union mlx5_ext_cqe inl_grh; | |
604 | struct mlx5_cqe64 cqe64; | |
605 | }; | |
606 | ||
607 | struct mlx5_srq_ctx { | |
608 | u8 state_log_sz; | |
609 | u8 rsvd0[3]; | |
610 | __be32 flags_xrcd; | |
611 | __be32 pgoff_cqn; | |
612 | u8 rsvd1[4]; | |
613 | u8 log_pg_sz; | |
614 | u8 rsvd2[7]; | |
615 | __be32 pd; | |
616 | __be16 lwm; | |
617 | __be16 wqe_cnt; | |
618 | u8 rsvd3[8]; | |
619 | __be64 db_record; | |
620 | }; | |
621 | ||
622 | struct mlx5_create_srq_mbox_in { | |
623 | struct mlx5_inbox_hdr hdr; | |
624 | __be32 input_srqn; | |
625 | u8 rsvd0[4]; | |
626 | struct mlx5_srq_ctx ctx; | |
627 | u8 rsvd1[208]; | |
628 | __be64 pas[0]; | |
629 | }; | |
630 | ||
631 | struct mlx5_create_srq_mbox_out { | |
632 | struct mlx5_outbox_hdr hdr; | |
633 | __be32 srqn; | |
634 | u8 rsvd[4]; | |
635 | }; | |
636 | ||
637 | struct mlx5_destroy_srq_mbox_in { | |
638 | struct mlx5_inbox_hdr hdr; | |
639 | __be32 srqn; | |
640 | u8 rsvd[4]; | |
641 | }; | |
642 | ||
643 | struct mlx5_destroy_srq_mbox_out { | |
644 | struct mlx5_outbox_hdr hdr; | |
645 | u8 rsvd[8]; | |
646 | }; | |
647 | ||
648 | struct mlx5_query_srq_mbox_in { | |
649 | struct mlx5_inbox_hdr hdr; | |
650 | __be32 srqn; | |
651 | u8 rsvd0[4]; | |
652 | }; | |
653 | ||
654 | struct mlx5_query_srq_mbox_out { | |
655 | struct mlx5_outbox_hdr hdr; | |
656 | u8 rsvd0[8]; | |
657 | struct mlx5_srq_ctx ctx; | |
658 | u8 rsvd1[32]; | |
659 | __be64 pas[0]; | |
660 | }; | |
661 | ||
662 | struct mlx5_arm_srq_mbox_in { | |
663 | struct mlx5_inbox_hdr hdr; | |
664 | __be32 srqn; | |
665 | __be16 rsvd; | |
666 | __be16 lwm; | |
667 | }; | |
668 | ||
669 | struct mlx5_arm_srq_mbox_out { | |
670 | struct mlx5_outbox_hdr hdr; | |
671 | u8 rsvd[8]; | |
672 | }; | |
673 | ||
674 | struct mlx5_cq_context { | |
675 | u8 status; | |
676 | u8 cqe_sz_flags; | |
677 | u8 st; | |
678 | u8 rsvd3; | |
679 | u8 rsvd4[6]; | |
680 | __be16 page_offset; | |
681 | __be32 log_sz_usr_page; | |
682 | __be16 cq_period; | |
683 | __be16 cq_max_count; | |
684 | __be16 rsvd20; | |
685 | __be16 c_eqn; | |
686 | u8 log_pg_sz; | |
687 | u8 rsvd25[7]; | |
688 | __be32 last_notified_index; | |
689 | __be32 solicit_producer_index; | |
690 | __be32 consumer_counter; | |
691 | __be32 producer_counter; | |
692 | u8 rsvd48[8]; | |
693 | __be64 db_record_addr; | |
694 | }; | |
695 | ||
696 | struct mlx5_create_cq_mbox_in { | |
697 | struct mlx5_inbox_hdr hdr; | |
698 | __be32 input_cqn; | |
699 | u8 rsvdx[4]; | |
700 | struct mlx5_cq_context ctx; | |
701 | u8 rsvd6[192]; | |
702 | __be64 pas[0]; | |
703 | }; | |
704 | ||
705 | struct mlx5_create_cq_mbox_out { | |
706 | struct mlx5_outbox_hdr hdr; | |
707 | __be32 cqn; | |
708 | u8 rsvd0[4]; | |
709 | }; | |
710 | ||
711 | struct mlx5_destroy_cq_mbox_in { | |
712 | struct mlx5_inbox_hdr hdr; | |
713 | __be32 cqn; | |
714 | u8 rsvd0[4]; | |
715 | }; | |
716 | ||
717 | struct mlx5_destroy_cq_mbox_out { | |
718 | struct mlx5_outbox_hdr hdr; | |
719 | u8 rsvd0[8]; | |
720 | }; | |
721 | ||
722 | struct mlx5_query_cq_mbox_in { | |
723 | struct mlx5_inbox_hdr hdr; | |
724 | __be32 cqn; | |
725 | u8 rsvd0[4]; | |
726 | }; | |
727 | ||
728 | struct mlx5_query_cq_mbox_out { | |
729 | struct mlx5_outbox_hdr hdr; | |
730 | u8 rsvd0[8]; | |
731 | struct mlx5_cq_context ctx; | |
732 | u8 rsvd6[16]; | |
733 | __be64 pas[0]; | |
734 | }; | |
735 | ||
3bdb31f6 EC |
736 | struct mlx5_modify_cq_mbox_in { |
737 | struct mlx5_inbox_hdr hdr; | |
738 | __be32 cqn; | |
739 | __be32 field_select; | |
740 | struct mlx5_cq_context ctx; | |
741 | u8 rsvd[192]; | |
742 | __be64 pas[0]; | |
743 | }; | |
744 | ||
745 | struct mlx5_modify_cq_mbox_out { | |
746 | struct mlx5_outbox_hdr hdr; | |
bde51583 | 747 | u8 rsvd[8]; |
3bdb31f6 EC |
748 | }; |
749 | ||
cd23b14b EC |
750 | struct mlx5_enable_hca_mbox_in { |
751 | struct mlx5_inbox_hdr hdr; | |
752 | u8 rsvd[8]; | |
753 | }; | |
754 | ||
755 | struct mlx5_enable_hca_mbox_out { | |
756 | struct mlx5_outbox_hdr hdr; | |
757 | u8 rsvd[8]; | |
758 | }; | |
759 | ||
760 | struct mlx5_disable_hca_mbox_in { | |
761 | struct mlx5_inbox_hdr hdr; | |
762 | u8 rsvd[8]; | |
763 | }; | |
764 | ||
765 | struct mlx5_disable_hca_mbox_out { | |
766 | struct mlx5_outbox_hdr hdr; | |
767 | u8 rsvd[8]; | |
768 | }; | |
769 | ||
e126ba97 EC |
770 | struct mlx5_eq_context { |
771 | u8 status; | |
772 | u8 ec_oi; | |
773 | u8 st; | |
774 | u8 rsvd2[7]; | |
775 | __be16 page_pffset; | |
776 | __be32 log_sz_usr_page; | |
777 | u8 rsvd3[7]; | |
778 | u8 intr; | |
779 | u8 log_page_size; | |
780 | u8 rsvd4[15]; | |
781 | __be32 consumer_counter; | |
782 | __be32 produser_counter; | |
783 | u8 rsvd5[16]; | |
784 | }; | |
785 | ||
786 | struct mlx5_create_eq_mbox_in { | |
787 | struct mlx5_inbox_hdr hdr; | |
788 | u8 rsvd0[3]; | |
789 | u8 input_eqn; | |
790 | u8 rsvd1[4]; | |
791 | struct mlx5_eq_context ctx; | |
792 | u8 rsvd2[8]; | |
793 | __be64 events_mask; | |
794 | u8 rsvd3[176]; | |
795 | __be64 pas[0]; | |
796 | }; | |
797 | ||
798 | struct mlx5_create_eq_mbox_out { | |
799 | struct mlx5_outbox_hdr hdr; | |
800 | u8 rsvd0[3]; | |
801 | u8 eq_number; | |
802 | u8 rsvd1[4]; | |
803 | }; | |
804 | ||
805 | struct mlx5_destroy_eq_mbox_in { | |
806 | struct mlx5_inbox_hdr hdr; | |
807 | u8 rsvd0[3]; | |
808 | u8 eqn; | |
809 | u8 rsvd1[4]; | |
810 | }; | |
811 | ||
812 | struct mlx5_destroy_eq_mbox_out { | |
813 | struct mlx5_outbox_hdr hdr; | |
814 | u8 rsvd[8]; | |
815 | }; | |
816 | ||
817 | struct mlx5_map_eq_mbox_in { | |
818 | struct mlx5_inbox_hdr hdr; | |
819 | __be64 mask; | |
820 | u8 mu; | |
821 | u8 rsvd0[2]; | |
822 | u8 eqn; | |
823 | u8 rsvd1[24]; | |
824 | }; | |
825 | ||
826 | struct mlx5_map_eq_mbox_out { | |
827 | struct mlx5_outbox_hdr hdr; | |
828 | u8 rsvd[8]; | |
829 | }; | |
830 | ||
831 | struct mlx5_query_eq_mbox_in { | |
832 | struct mlx5_inbox_hdr hdr; | |
833 | u8 rsvd0[3]; | |
834 | u8 eqn; | |
835 | u8 rsvd1[4]; | |
836 | }; | |
837 | ||
838 | struct mlx5_query_eq_mbox_out { | |
839 | struct mlx5_outbox_hdr hdr; | |
840 | u8 rsvd[8]; | |
841 | struct mlx5_eq_context ctx; | |
842 | }; | |
843 | ||
968e78dd HE |
844 | enum { |
845 | MLX5_MKEY_STATUS_FREE = 1 << 6, | |
846 | }; | |
847 | ||
e126ba97 EC |
848 | struct mlx5_mkey_seg { |
849 | /* This is a two bit field occupying bits 31-30. | |
850 | * bit 31 is always 0, | |
851 | * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation | |
852 | */ | |
853 | u8 status; | |
854 | u8 pcie_control; | |
855 | u8 flags; | |
856 | u8 version; | |
857 | __be32 qpn_mkey7_0; | |
858 | u8 rsvd1[4]; | |
859 | __be32 flags_pd; | |
860 | __be64 start_addr; | |
861 | __be64 len; | |
862 | __be32 bsfs_octo_size; | |
863 | u8 rsvd2[16]; | |
864 | __be32 xlt_oct_size; | |
865 | u8 rsvd3[3]; | |
866 | u8 log2_page_size; | |
867 | u8 rsvd4[4]; | |
868 | }; | |
869 | ||
870 | struct mlx5_query_special_ctxs_mbox_in { | |
871 | struct mlx5_inbox_hdr hdr; | |
872 | u8 rsvd[8]; | |
873 | }; | |
874 | ||
875 | struct mlx5_query_special_ctxs_mbox_out { | |
876 | struct mlx5_outbox_hdr hdr; | |
877 | __be32 dump_fill_mkey; | |
878 | __be32 reserved_lkey; | |
879 | }; | |
880 | ||
881 | struct mlx5_create_mkey_mbox_in { | |
882 | struct mlx5_inbox_hdr hdr; | |
883 | __be32 input_mkey_index; | |
e420f0c0 | 884 | __be32 flags; |
e126ba97 EC |
885 | struct mlx5_mkey_seg seg; |
886 | u8 rsvd1[16]; | |
887 | __be32 xlat_oct_act_size; | |
8c8a4914 EC |
888 | __be32 rsvd2; |
889 | u8 rsvd3[168]; | |
e126ba97 EC |
890 | __be64 pas[0]; |
891 | }; | |
892 | ||
893 | struct mlx5_create_mkey_mbox_out { | |
894 | struct mlx5_outbox_hdr hdr; | |
895 | __be32 mkey; | |
896 | u8 rsvd[4]; | |
897 | }; | |
898 | ||
899 | struct mlx5_destroy_mkey_mbox_in { | |
900 | struct mlx5_inbox_hdr hdr; | |
901 | __be32 mkey; | |
902 | u8 rsvd[4]; | |
903 | }; | |
904 | ||
905 | struct mlx5_destroy_mkey_mbox_out { | |
906 | struct mlx5_outbox_hdr hdr; | |
907 | u8 rsvd[8]; | |
908 | }; | |
909 | ||
910 | struct mlx5_query_mkey_mbox_in { | |
911 | struct mlx5_inbox_hdr hdr; | |
912 | __be32 mkey; | |
913 | }; | |
914 | ||
915 | struct mlx5_query_mkey_mbox_out { | |
916 | struct mlx5_outbox_hdr hdr; | |
917 | __be64 pas[0]; | |
918 | }; | |
919 | ||
920 | struct mlx5_modify_mkey_mbox_in { | |
921 | struct mlx5_inbox_hdr hdr; | |
922 | __be32 mkey; | |
923 | __be64 pas[0]; | |
924 | }; | |
925 | ||
926 | struct mlx5_modify_mkey_mbox_out { | |
927 | struct mlx5_outbox_hdr hdr; | |
3bdb31f6 | 928 | u8 rsvd[8]; |
e126ba97 EC |
929 | }; |
930 | ||
931 | struct mlx5_dump_mkey_mbox_in { | |
932 | struct mlx5_inbox_hdr hdr; | |
933 | }; | |
934 | ||
935 | struct mlx5_dump_mkey_mbox_out { | |
936 | struct mlx5_outbox_hdr hdr; | |
937 | __be32 mkey; | |
938 | }; | |
939 | ||
940 | struct mlx5_mad_ifc_mbox_in { | |
941 | struct mlx5_inbox_hdr hdr; | |
942 | __be16 remote_lid; | |
943 | u8 rsvd0; | |
944 | u8 port; | |
945 | u8 rsvd1[4]; | |
946 | u8 data[256]; | |
947 | }; | |
948 | ||
949 | struct mlx5_mad_ifc_mbox_out { | |
950 | struct mlx5_outbox_hdr hdr; | |
951 | u8 rsvd[8]; | |
952 | u8 data[256]; | |
953 | }; | |
954 | ||
955 | struct mlx5_access_reg_mbox_in { | |
956 | struct mlx5_inbox_hdr hdr; | |
957 | u8 rsvd0[2]; | |
958 | __be16 register_id; | |
959 | __be32 arg; | |
960 | __be32 data[0]; | |
961 | }; | |
962 | ||
963 | struct mlx5_access_reg_mbox_out { | |
964 | struct mlx5_outbox_hdr hdr; | |
965 | u8 rsvd[8]; | |
966 | __be32 data[0]; | |
967 | }; | |
968 | ||
969 | #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) | |
970 | ||
971 | enum { | |
972 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
973 | }; | |
974 | ||
3121e3c4 SG |
975 | struct mlx5_allocate_psv_in { |
976 | struct mlx5_inbox_hdr hdr; | |
977 | __be32 npsv_pd; | |
978 | __be32 rsvd_psv0; | |
979 | }; | |
980 | ||
981 | struct mlx5_allocate_psv_out { | |
982 | struct mlx5_outbox_hdr hdr; | |
983 | u8 rsvd[8]; | |
984 | __be32 psv_idx[4]; | |
985 | }; | |
986 | ||
987 | struct mlx5_destroy_psv_in { | |
988 | struct mlx5_inbox_hdr hdr; | |
989 | __be32 psv_number; | |
990 | u8 rsvd[4]; | |
991 | }; | |
992 | ||
993 | struct mlx5_destroy_psv_out { | |
994 | struct mlx5_outbox_hdr hdr; | |
995 | u8 rsvd[8]; | |
996 | }; | |
997 | ||
e126ba97 | 998 | #endif /* MLX5_DEVICE_H */ |