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net/mlx5e: Add per priority group to PPort counters
[deliverable/linux.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
9218b44d 62#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
938fe83c
SM		 63#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 65#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68/* insert a value to a struct */
69#define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
75} while (0)
76
e281682b
SM		 77#define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83} while (0)
84
d29b796a
EC		 85#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87__mlx5_mask(typ, fld))
88
89#define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93})
94
95#define MLX5_SET64(typ, p, fld, v) do { \
96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
99} while (0)
100
101#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
102
707c4602
MD		 103#define MLX5_GET64_PR(typ, p, fld) ({ \
104 u64 ___t = MLX5_GET64(typ, p, fld); \
105 pr_debug(#fld " = 0x%llx\n", ___t); \
106 ___t; \
107})
108
3efd9a11
MY		 109/* Big endian getters */
110#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
111 __mlx5_64_off(typ, fld)))
112
113#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
114 type_t tmp; \
115 switch (sizeof(tmp)) { \
116 case sizeof(u8): \
117 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
118 break; \
119 case sizeof(u16): \
120 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
121 break; \
122 case sizeof(u32): \
123 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
124 break; \
125 case sizeof(u64): \
126 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
127 break; \
128 } \
129 tmp; \
130 })
131
e126ba97
EC		 132enum {
133 MLX5_MAX_COMMANDS = 32,
134 MLX5_CMD_DATA_BLOCK_SIZE = 512,
135 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 136 MLX5_MKEY_BSF_OCTO_SIZE = 4,
137 MLX5_MAX_PSVS = 4,
e126ba97
EC		 138};
139
140enum {
141 MLX5_EXTENDED_UD_AV = 0x80000000,
142};
143
144enum {
145 MLX5_CQ_STATE_ARMED = 9,
146 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
147 MLX5_CQ_STATE_FIRED = 0xa,
148};
149
150enum {
151 MLX5_STAT_RATE_OFFSET = 5,
152};
153
154enum {
155 MLX5_INLINE_SEG = 0x80000000,
156};
157
fc11fbf9
SM		 158enum {
159 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
160};
161
c7a08ac7
EC		 162enum {
163 MLX5_MIN_PKEY_TABLE_SIZE = 128,
164 MLX5_MAX_LOG_PKEY_TABLE = 5,
165};
166
e420f0c0
HE		 167enum {
168 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
169};
170
171enum {
172 MLX5_PFAULT_SUBTYPE_WQE = 0,
173 MLX5_PFAULT_SUBTYPE_RDMA = 1,
174};
175
e126ba97
EC		 176enum {
177 MLX5_PERM_LOCAL_READ = 1 << 2,
178 MLX5_PERM_LOCAL_WRITE = 1 << 3,
179 MLX5_PERM_REMOTE_READ = 1 << 4,
180 MLX5_PERM_REMOTE_WRITE = 1 << 5,
181 MLX5_PERM_ATOMIC = 1 << 6,
182 MLX5_PERM_UMR_EN = 1 << 7,
183};
184
185enum {
186 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
187 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
188 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
189 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
190 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
191};
192
193enum {
194 MLX5_ACCESS_MODE_PA = 0,
195 MLX5_ACCESS_MODE_MTT = 1,
196 MLX5_ACCESS_MODE_KLM = 2
197};
198
199enum {
200 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
201 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
202 MLX5_MKEY_BSF_EN = 1 << 30,
203 MLX5_MKEY_LEN64 = 1 << 31,
204};
205
206enum {
207 MLX5_EN_RD = (u64)1,
208 MLX5_EN_WR = (u64)2
209};
210
211enum {
c1be5232
EC		 212 MLX5_BF_REGS_PER_PAGE = 4,
213 MLX5_MAX_UAR_PAGES = 1 << 8,
214 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
215 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 216};
217
218enum {
219 MLX5_MKEY_MASK_LEN = 1ull << 0,
220 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
221 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
222 MLX5_MKEY_MASK_PD = 1ull << 7,
223 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 224 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 225 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
226 MLX5_MKEY_MASK_KEY = 1ull << 13,
227 MLX5_MKEY_MASK_QPN = 1ull << 14,
228 MLX5_MKEY_MASK_LR = 1ull << 17,
229 MLX5_MKEY_MASK_LW = 1ull << 18,
230 MLX5_MKEY_MASK_RR = 1ull << 19,
231 MLX5_MKEY_MASK_RW = 1ull << 20,
232 MLX5_MKEY_MASK_A = 1ull << 21,
233 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
234 MLX5_MKEY_MASK_FREE = 1ull << 29,
235};
236
968e78dd
HE		 237enum {
238 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
239
240 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
241 MLX5_UMR_CHECK_FREE = (2 << 5),
242
243 MLX5_UMR_INLINE = (1 << 7),
244};
245
cc149f75
HE		 246#define MLX5_UMR_MTT_ALIGNMENT 0x40
247#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 248#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 249
e2013b21 250#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
251
252enum {
253 MLX5_EVENT_QUEUE_TYPE_QP = 0,
254 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
255 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
256};
257
e126ba97
EC		 258enum mlx5_event {
259 MLX5_EVENT_TYPE_COMP = 0x0,
260
261 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
262 MLX5_EVENT_TYPE_COMM_EST = 0x02,
263 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
264 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
265 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
266
267 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
268 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
269 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
270 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
271 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
272 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
273
274 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
275 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
276 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
277 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
278
279 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
280 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
281
282 MLX5_EVENT_TYPE_CMD = 0x0a,
283 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 284
285 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 286 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e126ba97
EC		 287};
288
289enum {
290 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
291 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
292 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
293 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
294 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
295 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
296 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
297};
298
299enum {
e126ba97 300 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 301 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
302 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
303 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
304 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 305 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 306 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 307 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 308 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 309 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 310 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 311 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 312};
313
3cca2606
AS		 314enum {
315 MLX5_ROCE_VERSION_1 = 0,
316 MLX5_ROCE_VERSION_2 = 2,
317};
318
319enum {
320 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
321 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
322};
323
324enum {
325 MLX5_ROCE_L3_TYPE_IPV4 = 0,
326 MLX5_ROCE_L3_TYPE_IPV6 = 1,
327};
328
329enum {
330 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
331 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
332};
333
e126ba97
EC		 334enum {
335 MLX5_OPCODE_NOP = 0x00,
336 MLX5_OPCODE_SEND_INVAL = 0x01,
337 MLX5_OPCODE_RDMA_WRITE = 0x08,
338 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
339 MLX5_OPCODE_SEND = 0x0a,
340 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 341 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 342 MLX5_OPCODE_RDMA_READ = 0x10,
343 MLX5_OPCODE_ATOMIC_CS = 0x11,
344 MLX5_OPCODE_ATOMIC_FA = 0x12,
345 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
346 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
347 MLX5_OPCODE_BIND_MW = 0x18,
348 MLX5_OPCODE_CONFIG_CMD = 0x1f,
349
350 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
351 MLX5_RECV_OPCODE_SEND = 0x01,
352 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
353 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
354
355 MLX5_CQE_OPCODE_ERROR = 0x1e,
356 MLX5_CQE_OPCODE_RESIZE = 0x16,
357
358 MLX5_OPCODE_SET_PSV = 0x20,
359 MLX5_OPCODE_GET_PSV = 0x21,
360 MLX5_OPCODE_CHECK_PSV = 0x22,
361 MLX5_OPCODE_RGET_PSV = 0x26,
362 MLX5_OPCODE_RCHECK_PSV = 0x27,
363
364 MLX5_OPCODE_UMR = 0x25,
365
366};
367
368enum {
369 MLX5_SET_PORT_RESET_QKEY = 0,
370 MLX5_SET_PORT_GUID0 = 16,
371 MLX5_SET_PORT_NODE_GUID = 17,
372 MLX5_SET_PORT_SYS_GUID = 18,
373 MLX5_SET_PORT_GID_TABLE = 19,
374 MLX5_SET_PORT_PKEY_TABLE = 20,
375};
376
d8880795
TT		 377enum {
378 MLX5_BW_NO_LIMIT = 0,
379 MLX5_100_MBPS_UNIT = 3,
380 MLX5_GBPS_UNIT = 4,
381};
382
e126ba97
EC		 383enum {
384 MLX5_MAX_PAGE_SHIFT = 31
385};
386
1b77d2bd 387enum {
05bdb2ab
EC		 388 MLX5_ADAPTER_PAGE_SHIFT = 12,
389 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 390};
391
87b8de49 392enum {
87b8de49
EC		 393 MLX5_CAP_OFF_CMDIF_CSUM = 46,
394};
395
e126ba97
EC		 396struct mlx5_inbox_hdr {
397 __be16 opcode;
398 u8 rsvd[4];
399 __be16 opmod;
400};
401
402struct mlx5_outbox_hdr {
403 u8 status;
404 u8 rsvd[3];
405 __be32 syndrome;
406};
407
408struct mlx5_cmd_query_adapter_mbox_in {
409 struct mlx5_inbox_hdr hdr;
410 u8 rsvd[8];
411};
412
413struct mlx5_cmd_query_adapter_mbox_out {
414 struct mlx5_outbox_hdr hdr;
415 u8 rsvd0[24];
416 u8 intapin;
417 u8 rsvd1[13];
418 __be16 vsd_vendor_id;
419 u8 vsd[208];
420 u8 vsd_psid[16];
421};
422
e420f0c0
HE		 423enum mlx5_odp_transport_cap_bits {
424 MLX5_ODP_SUPPORT_SEND = 1 << 31,
425 MLX5_ODP_SUPPORT_RECV = 1 << 30,
426 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
427 MLX5_ODP_SUPPORT_READ = 1 << 28,
428};
429
430struct mlx5_odp_caps {
431 char reserved[0x10];
432 struct {
433 __be32 rc_odp_caps;
434 __be32 uc_odp_caps;
435 __be32 ud_odp_caps;
436 } per_transport_caps;
437 char reserved2[0xe4];
438};
439
e126ba97
EC		 440struct mlx5_cmd_init_hca_mbox_in {
441 struct mlx5_inbox_hdr hdr;
442 u8 rsvd0[2];
443 __be16 profile;
444 u8 rsvd1[4];
445};
446
447struct mlx5_cmd_init_hca_mbox_out {
448 struct mlx5_outbox_hdr hdr;
449 u8 rsvd[8];
450};
451
452struct mlx5_cmd_teardown_hca_mbox_in {
453 struct mlx5_inbox_hdr hdr;
454 u8 rsvd0[2];
455 __be16 profile;
456 u8 rsvd1[4];
457};
458
459struct mlx5_cmd_teardown_hca_mbox_out {
460 struct mlx5_outbox_hdr hdr;
461 u8 rsvd[8];
462};
463
464struct mlx5_cmd_layout {
465 u8 type;
466 u8 rsvd0[3];
467 __be32 inlen;
468 __be64 in_ptr;
469 __be32 in[4];
470 __be32 out[4];
471 __be64 out_ptr;
472 __be32 outlen;
473 u8 token;
474 u8 sig;
475 u8 rsvd1;
476 u8 status_own;
477};
478
479
480struct health_buffer {
481 __be32 assert_var[5];
482 __be32 rsvd0[3];
483 __be32 assert_exit_ptr;
484 __be32 assert_callra;
485 __be32 rsvd1[2];
486 __be32 fw_ver;
487 __be32 hw_id;
488 __be32 rsvd2;
489 u8 irisc_index;
490 u8 synd;
78ccb258 491 __be16 ext_synd;
e126ba97
EC		 492};
493
494struct mlx5_init_seg {
495 __be32 fw_rev;
496 __be32 cmdif_rev_fw_sub;
497 __be32 rsvd0[2];
498 __be32 cmdq_addr_h;
499 __be32 cmdq_addr_l_sz;
500 __be32 cmd_dbell;
e3297246
EC		 501 __be32 rsvd1[120];
502 __be32 initializing;
e126ba97 503 struct health_buffer health;
b0844444
EBE		 504 __be32 rsvd2[880];
505 __be32 internal_timer_h;
506 __be32 internal_timer_l;
b368d7cb 507 __be32 rsvd3[2];
e126ba97 508 __be32 health_counter;
b0844444 509 __be32 rsvd4[1019];
e126ba97
EC		 510 __be64 ieee1588_clk;
511 __be32 ieee1588_clk_type;
512 __be32 clr_intx;
513};
514
515struct mlx5_eqe_comp {
516 __be32 reserved[6];
517 __be32 cqn;
518};
519
520struct mlx5_eqe_qp_srq {
e2013b21 521 __be32 reserved1[5];
522 u8 type;
523 u8 reserved2[3];
e126ba97
EC		 524 __be32 qp_srq_n;
525};
526
527struct mlx5_eqe_cq_err {
528 __be32 cqn;
529 u8 reserved1[7];
530 u8 syndrome;
531};
532
e126ba97
EC		 533struct mlx5_eqe_port_state {
534 u8 reserved0[8];
535 u8 port;
536};
537
538struct mlx5_eqe_gpio {
539 __be32 reserved0[2];
540 __be64 gpio_event;
541};
542
543struct mlx5_eqe_congestion {
544 u8 type;
545 u8 rsvd0;
546 u8 congestion_level;
547};
548
549struct mlx5_eqe_stall_vl {
550 u8 rsvd0[3];
551 u8 port_vl;
552};
553
554struct mlx5_eqe_cmd {
555 __be32 vector;
556 __be32 rsvd[6];
557};
558
559struct mlx5_eqe_page_req {
560 u8 rsvd0[2];
561 __be16 func_id;
0a324f31
ML		 562 __be32 num_pages;
563 __be32 rsvd1[5];
e126ba97
EC		 564};
565
e420f0c0
HE		 566struct mlx5_eqe_page_fault {
567 __be32 bytes_committed;
568 union {
569 struct {
570 u16 reserved1;
571 __be16 wqe_index;
572 u16 reserved2;
573 __be16 packet_length;
574 u8 reserved3[12];
575 } __packed wqe;
576 struct {
577 __be32 r_key;
578 u16 reserved1;
579 __be16 packet_length;
580 __be32 rdma_op_len;
581 __be64 rdma_va;
582 } __packed rdma;
583 } __packed;
584 __be32 flags_qpn;
585} __packed;
586
073bb189
SM		 587struct mlx5_eqe_vport_change {
588 u8 rsvd0[2];
589 __be16 vport_num;
590 __be32 rsvd1[6];
591} __packed;
592
e126ba97
EC		 593union ev_data {
594 __be32 raw[7];
595 struct mlx5_eqe_cmd cmd;
596 struct mlx5_eqe_comp comp;
597 struct mlx5_eqe_qp_srq qp_srq;
598 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 599 struct mlx5_eqe_port_state port;
600 struct mlx5_eqe_gpio gpio;
601 struct mlx5_eqe_congestion cong;
602 struct mlx5_eqe_stall_vl stall_vl;
603 struct mlx5_eqe_page_req req_pages;
e420f0c0 604 struct mlx5_eqe_page_fault page_fault;
073bb189 605 struct mlx5_eqe_vport_change vport_change;
e126ba97
EC		 606} __packed;
607
608struct mlx5_eqe {
609 u8 rsvd0;
610 u8 type;
611 u8 rsvd1;
612 u8 sub_type;
613 __be32 rsvd2[7];
614 union ev_data data;
615 __be16 rsvd3;
616 u8 signature;
617 u8 owner;
618} __packed;
619
620struct mlx5_cmd_prot_block {
621 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
622 u8 rsvd0[48];
623 __be64 next;
624 __be32 block_num;
625 u8 rsvd1;
626 u8 token;
627 u8 ctrl_sig;
628 u8 sig;
629};
630
e281682b
SM		 631enum {
632 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
633};
634
e126ba97
EC		 635struct mlx5_err_cqe {
636 u8 rsvd0[32];
637 __be32 srqn;
638 u8 rsvd1[18];
639 u8 vendor_err_synd;
640 u8 syndrome;
641 __be32 s_wqe_opcode_qpn;
642 __be16 wqe_counter;
643 u8 signature;
644 u8 op_own;
645};
646
647struct mlx5_cqe64 {
461017cb
TT		 648 u8 rsvd0[2];
649 __be16 wqe_id;
e281682b
SM		 650 u8 lro_tcppsh_abort_dupack;
651 u8 lro_min_ttl;
652 __be16 lro_tcp_win;
653 __be32 lro_ack_seq_num;
654 __be32 rss_hash_result;
655 u8 rss_hash_type;
e126ba97 656 u8 ml_path;
e281682b
SM		 657 u8 rsvd20[2];
658 __be16 check_sum;
e126ba97
EC		 659 __be16 slid;
660 __be32 flags_rqpn;
e281682b
SM		 661 u8 hds_ip_ext;
662 u8 l4_hdr_type_etc;
663 __be16 vlan_info;
664 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 665 __be32 imm_inval_pkey;
666 u8 rsvd40[4];
667 __be32 byte_cnt;
b0844444
EBE		 668 __be32 timestamp_h;
669 __be32 timestamp_l;
e126ba97
EC		 670 __be32 sop_drop_qpn;
671 __be16 wqe_counter;
672 u8 signature;
673 u8 op_own;
674};
675
e281682b
SM		 676static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
677{
678 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
679}
680
681static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
682{
683 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
684}
685
686static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
687{
688 return !!(cqe->l4_hdr_type_etc & 0x1);
689}
690
b0844444
EBE		 691static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
692{
693 u32 hi, lo;
694
695 hi = be32_to_cpu(cqe->timestamp_h);
696 lo = be32_to_cpu(cqe->timestamp_l);
697
698 return (u64)lo | ((u64)hi << 32);
699}
700
461017cb
TT		 701struct mpwrq_cqe_bc {
702 __be16 filler_consumed_strides;
703 __be16 byte_cnt;
704};
705
706static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
707{
708 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
709
710 return be16_to_cpu(bc->byte_cnt);
711}
712
713static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
714{
715 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
716}
717
718static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
719{
720 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
721
722 return mpwrq_get_cqe_bc_consumed_strides(bc);
723}
724
725static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
726{
727 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
728
729 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
730}
731
732static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
733{
734 return be16_to_cpu(cqe->wqe_counter);
735}
736
e281682b
SM		 737enum {
738 CQE_L4_HDR_TYPE_NONE = 0x0,
739 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
740 CQE_L4_HDR_TYPE_UDP = 0x2,
741 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
742 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
743};
744
745enum {
746 CQE_RSS_HTYPE_IP = 0x3 << 6,
747 CQE_RSS_HTYPE_L4 = 0x3 << 2,
748};
749
cb34be6d
AS		 750enum {
751 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
752 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
753 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
754};
755
e281682b
SM		 756enum {
757 CQE_L2_OK = 1 << 0,
758 CQE_L3_OK = 1 << 1,
759 CQE_L4_OK = 1 << 2,
760};
761
d5436ba0
SG		 762struct mlx5_sig_err_cqe {
763 u8 rsvd0[16];
764 __be32 expected_trans_sig;
765 __be32 actual_trans_sig;
766 __be32 expected_reftag;
767 __be32 actual_reftag;
768 __be16 syndrome;
769 u8 rsvd22[2];
770 __be32 mkey;
771 __be64 err_offset;
772 u8 rsvd30[8];
773 __be32 qpn;
774 u8 rsvd38[2];
775 u8 signature;
776 u8 op_own;
777};
778
e126ba97
EC		 779struct mlx5_wqe_srq_next_seg {
780 u8 rsvd0[2];
781 __be16 next_wqe_index;
782 u8 signature;
783 u8 rsvd1[11];
784};
785
786union mlx5_ext_cqe {
787 struct ib_grh grh;
788 u8 inl[64];
789};
790
791struct mlx5_cqe128 {
792 union mlx5_ext_cqe inl_grh;
793 struct mlx5_cqe64 cqe64;
794};
795
796struct mlx5_srq_ctx {
797 u8 state_log_sz;
798 u8 rsvd0[3];
799 __be32 flags_xrcd;
800 __be32 pgoff_cqn;
801 u8 rsvd1[4];
802 u8 log_pg_sz;
803 u8 rsvd2[7];
804 __be32 pd;
805 __be16 lwm;
806 __be16 wqe_cnt;
807 u8 rsvd3[8];
808 __be64 db_record;
809};
810
811struct mlx5_create_srq_mbox_in {
812 struct mlx5_inbox_hdr hdr;
813 __be32 input_srqn;
814 u8 rsvd0[4];
815 struct mlx5_srq_ctx ctx;
816 u8 rsvd1[208];
817 __be64 pas[0];
818};
819
820struct mlx5_create_srq_mbox_out {
821 struct mlx5_outbox_hdr hdr;
822 __be32 srqn;
823 u8 rsvd[4];
824};
825
826struct mlx5_destroy_srq_mbox_in {
827 struct mlx5_inbox_hdr hdr;
828 __be32 srqn;
829 u8 rsvd[4];
830};
831
832struct mlx5_destroy_srq_mbox_out {
833 struct mlx5_outbox_hdr hdr;
834 u8 rsvd[8];
835};
836
837struct mlx5_query_srq_mbox_in {
838 struct mlx5_inbox_hdr hdr;
839 __be32 srqn;
840 u8 rsvd0[4];
841};
842
843struct mlx5_query_srq_mbox_out {
844 struct mlx5_outbox_hdr hdr;
845 u8 rsvd0[8];
846 struct mlx5_srq_ctx ctx;
847 u8 rsvd1[32];
848 __be64 pas[0];
849};
850
851struct mlx5_arm_srq_mbox_in {
852 struct mlx5_inbox_hdr hdr;
853 __be32 srqn;
854 __be16 rsvd;
855 __be16 lwm;
856};
857
858struct mlx5_arm_srq_mbox_out {
859 struct mlx5_outbox_hdr hdr;
860 u8 rsvd[8];
861};
862
863struct mlx5_cq_context {
864 u8 status;
865 u8 cqe_sz_flags;
866 u8 st;
867 u8 rsvd3;
868 u8 rsvd4[6];
869 __be16 page_offset;
870 __be32 log_sz_usr_page;
871 __be16 cq_period;
872 __be16 cq_max_count;
873 __be16 rsvd20;
874 __be16 c_eqn;
875 u8 log_pg_sz;
876 u8 rsvd25[7];
877 __be32 last_notified_index;
878 __be32 solicit_producer_index;
879 __be32 consumer_counter;
880 __be32 producer_counter;
881 u8 rsvd48[8];
882 __be64 db_record_addr;
883};
884
885struct mlx5_create_cq_mbox_in {
886 struct mlx5_inbox_hdr hdr;
887 __be32 input_cqn;
888 u8 rsvdx[4];
889 struct mlx5_cq_context ctx;
890 u8 rsvd6[192];
891 __be64 pas[0];
892};
893
894struct mlx5_create_cq_mbox_out {
895 struct mlx5_outbox_hdr hdr;
896 __be32 cqn;
897 u8 rsvd0[4];
898};
899
900struct mlx5_destroy_cq_mbox_in {
901 struct mlx5_inbox_hdr hdr;
902 __be32 cqn;
903 u8 rsvd0[4];
904};
905
906struct mlx5_destroy_cq_mbox_out {
907 struct mlx5_outbox_hdr hdr;
908 u8 rsvd0[8];
909};
910
911struct mlx5_query_cq_mbox_in {
912 struct mlx5_inbox_hdr hdr;
913 __be32 cqn;
914 u8 rsvd0[4];
915};
916
917struct mlx5_query_cq_mbox_out {
918 struct mlx5_outbox_hdr hdr;
919 u8 rsvd0[8];
920 struct mlx5_cq_context ctx;
921 u8 rsvd6[16];
922 __be64 pas[0];
923};
924
3bdb31f6
EC		 925struct mlx5_modify_cq_mbox_in {
926 struct mlx5_inbox_hdr hdr;
927 __be32 cqn;
928 __be32 field_select;
929 struct mlx5_cq_context ctx;
930 u8 rsvd[192];
931 __be64 pas[0];
932};
933
934struct mlx5_modify_cq_mbox_out {
935 struct mlx5_outbox_hdr hdr;
bde51583 936 u8 rsvd[8];
3bdb31f6
EC		 937};
938
cd23b14b
EC		 939struct mlx5_enable_hca_mbox_in {
940 struct mlx5_inbox_hdr hdr;
941 u8 rsvd[8];
942};
943
944struct mlx5_enable_hca_mbox_out {
945 struct mlx5_outbox_hdr hdr;
946 u8 rsvd[8];
947};
948
949struct mlx5_disable_hca_mbox_in {
950 struct mlx5_inbox_hdr hdr;
951 u8 rsvd[8];
952};
953
954struct mlx5_disable_hca_mbox_out {
955 struct mlx5_outbox_hdr hdr;
956 u8 rsvd[8];
957};
958
e126ba97
EC		 959struct mlx5_eq_context {
960 u8 status;
961 u8 ec_oi;
962 u8 st;
963 u8 rsvd2[7];
964 __be16 page_pffset;
965 __be32 log_sz_usr_page;
966 u8 rsvd3[7];
967 u8 intr;
968 u8 log_page_size;
969 u8 rsvd4[15];
970 __be32 consumer_counter;
971 __be32 produser_counter;
972 u8 rsvd5[16];
973};
974
975struct mlx5_create_eq_mbox_in {
976 struct mlx5_inbox_hdr hdr;
977 u8 rsvd0[3];
978 u8 input_eqn;
979 u8 rsvd1[4];
980 struct mlx5_eq_context ctx;
981 u8 rsvd2[8];
982 __be64 events_mask;
983 u8 rsvd3[176];
984 __be64 pas[0];
985};
986
987struct mlx5_create_eq_mbox_out {
988 struct mlx5_outbox_hdr hdr;
989 u8 rsvd0[3];
990 u8 eq_number;
991 u8 rsvd1[4];
992};
993
994struct mlx5_destroy_eq_mbox_in {
995 struct mlx5_inbox_hdr hdr;
996 u8 rsvd0[3];
997 u8 eqn;
998 u8 rsvd1[4];
999};
1000
1001struct mlx5_destroy_eq_mbox_out {
1002 struct mlx5_outbox_hdr hdr;
1003 u8 rsvd[8];
1004};
1005
1006struct mlx5_map_eq_mbox_in {
1007 struct mlx5_inbox_hdr hdr;
1008 __be64 mask;
1009 u8 mu;
1010 u8 rsvd0[2];
1011 u8 eqn;
1012 u8 rsvd1[24];
1013};
1014
1015struct mlx5_map_eq_mbox_out {
1016 struct mlx5_outbox_hdr hdr;
1017 u8 rsvd[8];
1018};
1019
1020struct mlx5_query_eq_mbox_in {
1021 struct mlx5_inbox_hdr hdr;
1022 u8 rsvd0[3];
1023 u8 eqn;
1024 u8 rsvd1[4];
1025};
1026
1027struct mlx5_query_eq_mbox_out {
1028 struct mlx5_outbox_hdr hdr;
1029 u8 rsvd[8];
1030 struct mlx5_eq_context ctx;
1031};
1032
968e78dd
HE		 1033enum {
1034 MLX5_MKEY_STATUS_FREE = 1 << 6,
1035};
1036
e126ba97
EC		 1037struct mlx5_mkey_seg {
1038 /* This is a two bit field occupying bits 31-30.
1039 * bit 31 is always 0,
1040 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
1041 */
1042 u8 status;
1043 u8 pcie_control;
1044 u8 flags;
1045 u8 version;
1046 __be32 qpn_mkey7_0;
1047 u8 rsvd1[4];
1048 __be32 flags_pd;
1049 __be64 start_addr;
1050 __be64 len;
1051 __be32 bsfs_octo_size;
1052 u8 rsvd2[16];
1053 __be32 xlt_oct_size;
1054 u8 rsvd3[3];
1055 u8 log2_page_size;
1056 u8 rsvd4[4];
1057};
1058
1059struct mlx5_query_special_ctxs_mbox_in {
1060 struct mlx5_inbox_hdr hdr;
1061 u8 rsvd[8];
1062};
1063
1064struct mlx5_query_special_ctxs_mbox_out {
1065 struct mlx5_outbox_hdr hdr;
1066 __be32 dump_fill_mkey;
1067 __be32 reserved_lkey;
1068};
1069
1070struct mlx5_create_mkey_mbox_in {
1071 struct mlx5_inbox_hdr hdr;
1072 __be32 input_mkey_index;
e420f0c0 1073 __be32 flags;
e126ba97
EC		 1074 struct mlx5_mkey_seg seg;
1075 u8 rsvd1[16];
1076 __be32 xlat_oct_act_size;
8c8a4914
EC		 1077 __be32 rsvd2;
1078 u8 rsvd3[168];
e126ba97
EC		 1079 __be64 pas[0];
1080};
1081
1082struct mlx5_create_mkey_mbox_out {
1083 struct mlx5_outbox_hdr hdr;
1084 __be32 mkey;
1085 u8 rsvd[4];
1086};
1087
1088struct mlx5_destroy_mkey_mbox_in {
1089 struct mlx5_inbox_hdr hdr;
1090 __be32 mkey;
1091 u8 rsvd[4];
1092};
1093
1094struct mlx5_destroy_mkey_mbox_out {
1095 struct mlx5_outbox_hdr hdr;
1096 u8 rsvd[8];
1097};
1098
1099struct mlx5_query_mkey_mbox_in {
1100 struct mlx5_inbox_hdr hdr;
1101 __be32 mkey;
1102};
1103
1104struct mlx5_query_mkey_mbox_out {
1105 struct mlx5_outbox_hdr hdr;
1106 __be64 pas[0];
1107};
1108
1109struct mlx5_modify_mkey_mbox_in {
1110 struct mlx5_inbox_hdr hdr;
1111 __be32 mkey;
1112 __be64 pas[0];
1113};
1114
1115struct mlx5_modify_mkey_mbox_out {
1116 struct mlx5_outbox_hdr hdr;
3bdb31f6 1117 u8 rsvd[8];
e126ba97
EC		 1118};
1119
1120struct mlx5_dump_mkey_mbox_in {
1121 struct mlx5_inbox_hdr hdr;
1122};
1123
1124struct mlx5_dump_mkey_mbox_out {
1125 struct mlx5_outbox_hdr hdr;
1126 __be32 mkey;
1127};
1128
1129struct mlx5_mad_ifc_mbox_in {
1130 struct mlx5_inbox_hdr hdr;
1131 __be16 remote_lid;
1132 u8 rsvd0;
1133 u8 port;
1134 u8 rsvd1[4];
1135 u8 data[256];
1136};
1137
1138struct mlx5_mad_ifc_mbox_out {
1139 struct mlx5_outbox_hdr hdr;
1140 u8 rsvd[8];
1141 u8 data[256];
1142};
1143
1144struct mlx5_access_reg_mbox_in {
1145 struct mlx5_inbox_hdr hdr;
1146 u8 rsvd0[2];
1147 __be16 register_id;
1148 __be32 arg;
1149 __be32 data[0];
1150};
1151
1152struct mlx5_access_reg_mbox_out {
1153 struct mlx5_outbox_hdr hdr;
1154 u8 rsvd[8];
1155 __be32 data[0];
1156};
1157
1158#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1159
1160enum {
1161 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1162};
1163
3121e3c4
SG		 1164struct mlx5_allocate_psv_in {
1165 struct mlx5_inbox_hdr hdr;
1166 __be32 npsv_pd;
1167 __be32 rsvd_psv0;
1168};
1169
1170struct mlx5_allocate_psv_out {
1171 struct mlx5_outbox_hdr hdr;
1172 u8 rsvd[8];
1173 __be32 psv_idx[4];
1174};
1175
1176struct mlx5_destroy_psv_in {
1177 struct mlx5_inbox_hdr hdr;
1178 __be32 psv_number;
1179 u8 rsvd[4];
1180};
1181
1182struct mlx5_destroy_psv_out {
1183 struct mlx5_outbox_hdr hdr;
1184 u8 rsvd[8];
1185};
1186
e281682b
SM		 1187#define MLX5_CMD_OP_MAX 0x920
1188
1189enum {
1190 VPORT_STATE_DOWN = 0x0,
1191 VPORT_STATE_UP = 0x1,
1192};
1193
81848731
SM		 1194enum {
1195 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1196 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1197 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1198};
1199
e281682b
SM		 1200enum {
1201 MLX5_L3_PROT_TYPE_IPV4 = 0,
1202 MLX5_L3_PROT_TYPE_IPV6 = 1,
1203};
1204
1205enum {
1206 MLX5_L4_PROT_TYPE_TCP = 0,
1207 MLX5_L4_PROT_TYPE_UDP = 1,
1208};
1209
1210enum {
1211 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1212 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1213 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1214 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1215 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1216};
1217
1218enum {
1219 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1220 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1221 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1222
1223};
1224
1225enum {
1226 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1227 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1228};
1229
1230enum {
1231 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1232 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1233 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1234};
1235
e16aea27
SM		 1236enum mlx5_list_type {
1237 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1238 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1239 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1240};
1241
e281682b
SM		 1242enum {
1243 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1244 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1245};
1246
928cfe87
TT		 1247enum mlx5_wol_mode {
1248 MLX5_WOL_DISABLE = 0,
1249 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1250 MLX5_WOL_MAGIC = 1 << 2,
1251 MLX5_WOL_ARP = 1 << 3,
1252 MLX5_WOL_BROADCAST = 1 << 4,
1253 MLX5_WOL_MULTICAST = 1 << 5,
1254 MLX5_WOL_UNICAST = 1 << 6,
1255 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1256};
1257
938fe83c
SM		 1258/* MLX5 DEV CAPs */
1259
1260/* TODO: EAT.ME */
1261enum mlx5_cap_mode {
1262 HCA_CAP_OPMOD_GET_MAX = 0,
1263 HCA_CAP_OPMOD_GET_CUR = 1,
1264};
1265
1266enum mlx5_cap_type {
1267 MLX5_CAP_GENERAL = 0,
1268 MLX5_CAP_ETHERNET_OFFLOADS,
1269 MLX5_CAP_ODP,
1270 MLX5_CAP_ATOMIC,
1271 MLX5_CAP_ROCE,
1272 MLX5_CAP_IPOIB_OFFLOADS,
1273 MLX5_CAP_EOIB_OFFLOADS,
1274 MLX5_CAP_FLOW_TABLE,
495716b1 1275 MLX5_CAP_ESWITCH_FLOW_TABLE,
d6666753 1276 MLX5_CAP_ESWITCH,
3f0393a5
SG		 1277 MLX5_CAP_RESERVED,
1278 MLX5_CAP_VECTOR_CALC,
938fe83c
SM		 1279 /* NUM OF CAP Types */
1280 MLX5_CAP_NUM
1281};
1282
1283/* GET Dev Caps macros */
1284#define MLX5_CAP_GEN(mdev, cap) \
1285 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1286
1287#define MLX5_CAP_GEN_MAX(mdev, cap) \
1288 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1289
1290#define MLX5_CAP_ETH(mdev, cap) \
1291 MLX5_GET(per_protocol_networking_offload_caps,\
1292 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1293
1294#define MLX5_CAP_ETH_MAX(mdev, cap) \
1295 MLX5_GET(per_protocol_networking_offload_caps,\
1296 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1297
1298#define MLX5_CAP_ROCE(mdev, cap) \
1299 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1300
1301#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1302 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1303
1304#define MLX5_CAP_ATOMIC(mdev, cap) \
1305 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1306
1307#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1308 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1309
1310#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1311 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1312
1313#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1314 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1315
495716b1
SM		 1316#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1317 MLX5_GET(flow_table_eswitch_cap, \
1318 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1319
1320#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1321 MLX5_GET(flow_table_eswitch_cap, \
1322 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1323
1324#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1325 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1326
1327#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1328 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1329
d6666753
SM		 1330#define MLX5_CAP_ESW(mdev, cap) \
1331 MLX5_GET(e_switch_cap, \
1332 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1333
1334#define MLX5_CAP_ESW_MAX(mdev, cap) \
1335 MLX5_GET(e_switch_cap, \
1336 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1337
938fe83c
SM		 1338#define MLX5_CAP_ODP(mdev, cap)\
1339 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1340
3f0393a5
SG		 1341#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1342 MLX5_GET(vector_calc_cap, \
1343 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1344
f62b8bb8
AV		 1345enum {
1346 MLX5_CMD_STAT_OK = 0x0,
1347 MLX5_CMD_STAT_INT_ERR = 0x1,
1348 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1349 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1350 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1351 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1352 MLX5_CMD_STAT_RES_BUSY = 0x6,
1353 MLX5_CMD_STAT_LIM_ERR = 0x8,
1354 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1355 MLX5_CMD_STAT_IX_ERR = 0xa,
1356 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1357 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1358 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1359 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1360 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1361 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1362};
1363
efea389d
GP		 1364enum {
1365 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1366 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1367 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1368 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1369 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1370 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1c64bf6f
MY		 1371 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1372 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
efea389d
GP		 1373};
1374
707c4602
MD		 1375static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1376{
1377 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1378 return 0;
1379 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1380}
1381
35d19011
MG		 1382#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1383#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1384#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1385#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1386 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1387 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
4cbdd30e 1388
e126ba97 1389#endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
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