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d29b796a | 1 | /* |
e281682b | 2 | * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. |
d29b796a EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
e281682b | 31 | */ |
d29b796a EC |
32 | #ifndef MLX5_IFC_H |
33 | #define MLX5_IFC_H | |
34 | ||
e281682b SM |
35 | enum { |
36 | MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, | |
37 | MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, | |
38 | MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, | |
39 | MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, | |
40 | MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, | |
41 | MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, | |
42 | MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, | |
43 | MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, | |
44 | MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, | |
45 | MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, | |
46 | MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, | |
47 | MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, | |
48 | MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, | |
49 | MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, | |
50 | MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, | |
51 | MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, | |
52 | MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, | |
53 | MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, | |
54 | MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, | |
55 | MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, | |
56 | MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, | |
57 | MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, | |
58 | MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, | |
59 | MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb | |
60 | }; | |
61 | ||
62 | enum { | |
63 | MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, | |
64 | MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, | |
65 | MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, | |
66 | MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 | |
67 | }; | |
68 | ||
f91e6d89 EBE |
69 | enum { |
70 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, | |
71 | MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, | |
72 | }; | |
73 | ||
d29b796a EC |
74 | enum { |
75 | MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, | |
76 | MLX5_CMD_OP_QUERY_ADAPTER = 0x101, | |
77 | MLX5_CMD_OP_INIT_HCA = 0x102, | |
78 | MLX5_CMD_OP_TEARDOWN_HCA = 0x103, | |
79 | MLX5_CMD_OP_ENABLE_HCA = 0x104, | |
80 | MLX5_CMD_OP_DISABLE_HCA = 0x105, | |
81 | MLX5_CMD_OP_QUERY_PAGES = 0x107, | |
82 | MLX5_CMD_OP_MANAGE_PAGES = 0x108, | |
83 | MLX5_CMD_OP_SET_HCA_CAP = 0x109, | |
e281682b SM |
84 | MLX5_CMD_OP_QUERY_ISSI = 0x10a, |
85 | MLX5_CMD_OP_SET_ISSI = 0x10b, | |
d29b796a EC |
86 | MLX5_CMD_OP_CREATE_MKEY = 0x200, |
87 | MLX5_CMD_OP_QUERY_MKEY = 0x201, | |
88 | MLX5_CMD_OP_DESTROY_MKEY = 0x202, | |
89 | MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, | |
90 | MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, | |
91 | MLX5_CMD_OP_CREATE_EQ = 0x301, | |
92 | MLX5_CMD_OP_DESTROY_EQ = 0x302, | |
93 | MLX5_CMD_OP_QUERY_EQ = 0x303, | |
94 | MLX5_CMD_OP_GEN_EQE = 0x304, | |
95 | MLX5_CMD_OP_CREATE_CQ = 0x400, | |
96 | MLX5_CMD_OP_DESTROY_CQ = 0x401, | |
97 | MLX5_CMD_OP_QUERY_CQ = 0x402, | |
98 | MLX5_CMD_OP_MODIFY_CQ = 0x403, | |
99 | MLX5_CMD_OP_CREATE_QP = 0x500, | |
100 | MLX5_CMD_OP_DESTROY_QP = 0x501, | |
101 | MLX5_CMD_OP_RST2INIT_QP = 0x502, | |
102 | MLX5_CMD_OP_INIT2RTR_QP = 0x503, | |
103 | MLX5_CMD_OP_RTR2RTS_QP = 0x504, | |
104 | MLX5_CMD_OP_RTS2RTS_QP = 0x505, | |
105 | MLX5_CMD_OP_SQERR2RTS_QP = 0x506, | |
106 | MLX5_CMD_OP_2ERR_QP = 0x507, | |
107 | MLX5_CMD_OP_2RST_QP = 0x50a, | |
108 | MLX5_CMD_OP_QUERY_QP = 0x50b, | |
e281682b | 109 | MLX5_CMD_OP_SQD_RTS_QP = 0x50c, |
d29b796a EC |
110 | MLX5_CMD_OP_INIT2INIT_QP = 0x50e, |
111 | MLX5_CMD_OP_CREATE_PSV = 0x600, | |
112 | MLX5_CMD_OP_DESTROY_PSV = 0x601, | |
113 | MLX5_CMD_OP_CREATE_SRQ = 0x700, | |
114 | MLX5_CMD_OP_DESTROY_SRQ = 0x701, | |
115 | MLX5_CMD_OP_QUERY_SRQ = 0x702, | |
116 | MLX5_CMD_OP_ARM_RQ = 0x703, | |
e281682b SM |
117 | MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, |
118 | MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, | |
119 | MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, | |
120 | MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, | |
d29b796a EC |
121 | MLX5_CMD_OP_CREATE_DCT = 0x710, |
122 | MLX5_CMD_OP_DESTROY_DCT = 0x711, | |
123 | MLX5_CMD_OP_DRAIN_DCT = 0x712, | |
124 | MLX5_CMD_OP_QUERY_DCT = 0x713, | |
125 | MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, | |
126 | MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, | |
127 | MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, | |
128 | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, | |
129 | MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, | |
130 | MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, | |
131 | MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, | |
e281682b | 132 | MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, |
d29b796a | 133 | MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, |
e281682b SM |
134 | MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, |
135 | MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, | |
136 | MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, | |
137 | MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, | |
d29b796a EC |
138 | MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, |
139 | MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, | |
140 | MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, | |
141 | MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, | |
142 | MLX5_CMD_OP_ALLOC_PD = 0x800, | |
143 | MLX5_CMD_OP_DEALLOC_PD = 0x801, | |
144 | MLX5_CMD_OP_ALLOC_UAR = 0x802, | |
145 | MLX5_CMD_OP_DEALLOC_UAR = 0x803, | |
146 | MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, | |
147 | MLX5_CMD_OP_ACCESS_REG = 0x805, | |
148 | MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, | |
e281682b | 149 | MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807, |
d29b796a EC |
150 | MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, |
151 | MLX5_CMD_OP_MAD_IFC = 0x50d, | |
152 | MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, | |
153 | MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, | |
154 | MLX5_CMD_OP_NOP = 0x80d, | |
155 | MLX5_CMD_OP_ALLOC_XRCD = 0x80e, | |
156 | MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, | |
e281682b SM |
157 | MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, |
158 | MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, | |
159 | MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, | |
160 | MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, | |
161 | MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, | |
162 | MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, | |
163 | MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, | |
164 | MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, | |
165 | MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, | |
166 | MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, | |
167 | MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, | |
168 | MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, | |
d29b796a EC |
169 | MLX5_CMD_OP_CREATE_TIR = 0x900, |
170 | MLX5_CMD_OP_MODIFY_TIR = 0x901, | |
171 | MLX5_CMD_OP_DESTROY_TIR = 0x902, | |
172 | MLX5_CMD_OP_QUERY_TIR = 0x903, | |
d29b796a EC |
173 | MLX5_CMD_OP_CREATE_SQ = 0x904, |
174 | MLX5_CMD_OP_MODIFY_SQ = 0x905, | |
175 | MLX5_CMD_OP_DESTROY_SQ = 0x906, | |
176 | MLX5_CMD_OP_QUERY_SQ = 0x907, | |
177 | MLX5_CMD_OP_CREATE_RQ = 0x908, | |
178 | MLX5_CMD_OP_MODIFY_RQ = 0x909, | |
179 | MLX5_CMD_OP_DESTROY_RQ = 0x90a, | |
180 | MLX5_CMD_OP_QUERY_RQ = 0x90b, | |
181 | MLX5_CMD_OP_CREATE_RMP = 0x90c, | |
182 | MLX5_CMD_OP_MODIFY_RMP = 0x90d, | |
183 | MLX5_CMD_OP_DESTROY_RMP = 0x90e, | |
184 | MLX5_CMD_OP_QUERY_RMP = 0x90f, | |
e281682b SM |
185 | MLX5_CMD_OP_CREATE_TIS = 0x912, |
186 | MLX5_CMD_OP_MODIFY_TIS = 0x913, | |
187 | MLX5_CMD_OP_DESTROY_TIS = 0x914, | |
188 | MLX5_CMD_OP_QUERY_TIS = 0x915, | |
189 | MLX5_CMD_OP_CREATE_RQT = 0x916, | |
190 | MLX5_CMD_OP_MODIFY_RQT = 0x917, | |
191 | MLX5_CMD_OP_DESTROY_RQT = 0x918, | |
192 | MLX5_CMD_OP_QUERY_RQT = 0x919, | |
2cc43b49 | 193 | MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, |
e281682b SM |
194 | MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, |
195 | MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, | |
196 | MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, | |
197 | MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, | |
198 | MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, | |
199 | MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, | |
200 | MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, | |
201 | MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, | |
34a40e68 MG |
202 | MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, |
203 | MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c | |
e281682b SM |
204 | }; |
205 | ||
206 | struct mlx5_ifc_flow_table_fields_supported_bits { | |
207 | u8 outer_dmac[0x1]; | |
208 | u8 outer_smac[0x1]; | |
209 | u8 outer_ether_type[0x1]; | |
b4ff3a36 | 210 | u8 reserved_at_3[0x1]; |
e281682b SM |
211 | u8 outer_first_prio[0x1]; |
212 | u8 outer_first_cfi[0x1]; | |
213 | u8 outer_first_vid[0x1]; | |
b4ff3a36 | 214 | u8 reserved_at_7[0x1]; |
e281682b SM |
215 | u8 outer_second_prio[0x1]; |
216 | u8 outer_second_cfi[0x1]; | |
217 | u8 outer_second_vid[0x1]; | |
b4ff3a36 | 218 | u8 reserved_at_b[0x1]; |
e281682b SM |
219 | u8 outer_sip[0x1]; |
220 | u8 outer_dip[0x1]; | |
221 | u8 outer_frag[0x1]; | |
222 | u8 outer_ip_protocol[0x1]; | |
223 | u8 outer_ip_ecn[0x1]; | |
224 | u8 outer_ip_dscp[0x1]; | |
225 | u8 outer_udp_sport[0x1]; | |
226 | u8 outer_udp_dport[0x1]; | |
227 | u8 outer_tcp_sport[0x1]; | |
228 | u8 outer_tcp_dport[0x1]; | |
229 | u8 outer_tcp_flags[0x1]; | |
230 | u8 outer_gre_protocol[0x1]; | |
231 | u8 outer_gre_key[0x1]; | |
232 | u8 outer_vxlan_vni[0x1]; | |
b4ff3a36 | 233 | u8 reserved_at_1a[0x5]; |
e281682b SM |
234 | u8 source_eswitch_port[0x1]; |
235 | ||
236 | u8 inner_dmac[0x1]; | |
237 | u8 inner_smac[0x1]; | |
238 | u8 inner_ether_type[0x1]; | |
b4ff3a36 | 239 | u8 reserved_at_23[0x1]; |
e281682b SM |
240 | u8 inner_first_prio[0x1]; |
241 | u8 inner_first_cfi[0x1]; | |
242 | u8 inner_first_vid[0x1]; | |
b4ff3a36 | 243 | u8 reserved_at_27[0x1]; |
e281682b SM |
244 | u8 inner_second_prio[0x1]; |
245 | u8 inner_second_cfi[0x1]; | |
246 | u8 inner_second_vid[0x1]; | |
b4ff3a36 | 247 | u8 reserved_at_2b[0x1]; |
e281682b SM |
248 | u8 inner_sip[0x1]; |
249 | u8 inner_dip[0x1]; | |
250 | u8 inner_frag[0x1]; | |
251 | u8 inner_ip_protocol[0x1]; | |
252 | u8 inner_ip_ecn[0x1]; | |
253 | u8 inner_ip_dscp[0x1]; | |
254 | u8 inner_udp_sport[0x1]; | |
255 | u8 inner_udp_dport[0x1]; | |
256 | u8 inner_tcp_sport[0x1]; | |
257 | u8 inner_tcp_dport[0x1]; | |
258 | u8 inner_tcp_flags[0x1]; | |
b4ff3a36 | 259 | u8 reserved_at_37[0x9]; |
e281682b | 260 | |
b4ff3a36 | 261 | u8 reserved_at_40[0x40]; |
e281682b SM |
262 | }; |
263 | ||
264 | struct mlx5_ifc_flow_table_prop_layout_bits { | |
265 | u8 ft_support[0x1]; | |
b4ff3a36 | 266 | u8 reserved_at_1[0x2]; |
26a81453 | 267 | u8 flow_modify_en[0x1]; |
2cc43b49 | 268 | u8 modify_root[0x1]; |
34a40e68 MG |
269 | u8 identified_miss_table_mode[0x1]; |
270 | u8 flow_table_modify[0x1]; | |
b4ff3a36 | 271 | u8 reserved_at_7[0x19]; |
e281682b | 272 | |
b4ff3a36 | 273 | u8 reserved_at_20[0x2]; |
e281682b | 274 | u8 log_max_ft_size[0x6]; |
b4ff3a36 | 275 | u8 reserved_at_28[0x10]; |
e281682b SM |
276 | u8 max_ft_level[0x8]; |
277 | ||
b4ff3a36 | 278 | u8 reserved_at_40[0x20]; |
e281682b | 279 | |
b4ff3a36 | 280 | u8 reserved_at_60[0x18]; |
e281682b SM |
281 | u8 log_max_ft_num[0x8]; |
282 | ||
b4ff3a36 | 283 | u8 reserved_at_80[0x18]; |
e281682b SM |
284 | u8 log_max_destination[0x8]; |
285 | ||
b4ff3a36 | 286 | u8 reserved_at_a0[0x18]; |
e281682b SM |
287 | u8 log_max_flow[0x8]; |
288 | ||
b4ff3a36 | 289 | u8 reserved_at_c0[0x40]; |
e281682b SM |
290 | |
291 | struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; | |
292 | ||
293 | struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; | |
294 | }; | |
295 | ||
296 | struct mlx5_ifc_odp_per_transport_service_cap_bits { | |
297 | u8 send[0x1]; | |
298 | u8 receive[0x1]; | |
299 | u8 write[0x1]; | |
300 | u8 read[0x1]; | |
b4ff3a36 | 301 | u8 reserved_at_4[0x1]; |
e281682b | 302 | u8 srq_receive[0x1]; |
b4ff3a36 | 303 | u8 reserved_at_6[0x1a]; |
e281682b SM |
304 | }; |
305 | ||
b4d1f032 | 306 | struct mlx5_ifc_ipv4_layout_bits { |
b4ff3a36 | 307 | u8 reserved_at_0[0x60]; |
b4d1f032 MG |
308 | |
309 | u8 ipv4[0x20]; | |
310 | }; | |
311 | ||
312 | struct mlx5_ifc_ipv6_layout_bits { | |
313 | u8 ipv6[16][0x8]; | |
314 | }; | |
315 | ||
316 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { | |
317 | struct mlx5_ifc_ipv6_layout_bits ipv6_layout; | |
318 | struct mlx5_ifc_ipv4_layout_bits ipv4_layout; | |
b4ff3a36 | 319 | u8 reserved_at_0[0x80]; |
b4d1f032 MG |
320 | }; |
321 | ||
e281682b SM |
322 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits { |
323 | u8 smac_47_16[0x20]; | |
324 | ||
325 | u8 smac_15_0[0x10]; | |
326 | u8 ethertype[0x10]; | |
327 | ||
328 | u8 dmac_47_16[0x20]; | |
329 | ||
330 | u8 dmac_15_0[0x10]; | |
331 | u8 first_prio[0x3]; | |
332 | u8 first_cfi[0x1]; | |
333 | u8 first_vid[0xc]; | |
334 | ||
335 | u8 ip_protocol[0x8]; | |
336 | u8 ip_dscp[0x6]; | |
337 | u8 ip_ecn[0x2]; | |
338 | u8 vlan_tag[0x1]; | |
b4ff3a36 | 339 | u8 reserved_at_91[0x1]; |
e281682b | 340 | u8 frag[0x1]; |
b4ff3a36 | 341 | u8 reserved_at_93[0x4]; |
e281682b SM |
342 | u8 tcp_flags[0x9]; |
343 | ||
344 | u8 tcp_sport[0x10]; | |
345 | u8 tcp_dport[0x10]; | |
346 | ||
b4ff3a36 | 347 | u8 reserved_at_c0[0x20]; |
e281682b SM |
348 | |
349 | u8 udp_sport[0x10]; | |
350 | u8 udp_dport[0x10]; | |
351 | ||
b4d1f032 | 352 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; |
e281682b | 353 | |
b4d1f032 | 354 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; |
e281682b SM |
355 | }; |
356 | ||
357 | struct mlx5_ifc_fte_match_set_misc_bits { | |
b4ff3a36 | 358 | u8 reserved_at_0[0x20]; |
e281682b | 359 | |
b4ff3a36 | 360 | u8 reserved_at_20[0x10]; |
e281682b SM |
361 | u8 source_port[0x10]; |
362 | ||
363 | u8 outer_second_prio[0x3]; | |
364 | u8 outer_second_cfi[0x1]; | |
365 | u8 outer_second_vid[0xc]; | |
366 | u8 inner_second_prio[0x3]; | |
367 | u8 inner_second_cfi[0x1]; | |
368 | u8 inner_second_vid[0xc]; | |
369 | ||
370 | u8 outer_second_vlan_tag[0x1]; | |
371 | u8 inner_second_vlan_tag[0x1]; | |
b4ff3a36 | 372 | u8 reserved_at_62[0xe]; |
e281682b SM |
373 | u8 gre_protocol[0x10]; |
374 | ||
375 | u8 gre_key_h[0x18]; | |
376 | u8 gre_key_l[0x8]; | |
377 | ||
378 | u8 vxlan_vni[0x18]; | |
b4ff3a36 | 379 | u8 reserved_at_b8[0x8]; |
e281682b | 380 | |
b4ff3a36 | 381 | u8 reserved_at_c0[0x20]; |
e281682b | 382 | |
b4ff3a36 | 383 | u8 reserved_at_e0[0xc]; |
e281682b SM |
384 | u8 outer_ipv6_flow_label[0x14]; |
385 | ||
b4ff3a36 | 386 | u8 reserved_at_100[0xc]; |
e281682b SM |
387 | u8 inner_ipv6_flow_label[0x14]; |
388 | ||
b4ff3a36 | 389 | u8 reserved_at_120[0xe0]; |
e281682b SM |
390 | }; |
391 | ||
392 | struct mlx5_ifc_cmd_pas_bits { | |
393 | u8 pa_h[0x20]; | |
394 | ||
395 | u8 pa_l[0x14]; | |
b4ff3a36 | 396 | u8 reserved_at_34[0xc]; |
e281682b SM |
397 | }; |
398 | ||
399 | struct mlx5_ifc_uint64_bits { | |
400 | u8 hi[0x20]; | |
401 | ||
402 | u8 lo[0x20]; | |
403 | }; | |
404 | ||
405 | enum { | |
406 | MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, | |
407 | MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, | |
408 | MLX5_ADS_STAT_RATE_10GBPS = 0x8, | |
409 | MLX5_ADS_STAT_RATE_30GBPS = 0x9, | |
410 | MLX5_ADS_STAT_RATE_5GBPS = 0xa, | |
411 | MLX5_ADS_STAT_RATE_20GBPS = 0xb, | |
412 | MLX5_ADS_STAT_RATE_40GBPS = 0xc, | |
413 | MLX5_ADS_STAT_RATE_60GBPS = 0xd, | |
414 | MLX5_ADS_STAT_RATE_80GBPS = 0xe, | |
415 | MLX5_ADS_STAT_RATE_120GBPS = 0xf, | |
416 | }; | |
417 | ||
418 | struct mlx5_ifc_ads_bits { | |
419 | u8 fl[0x1]; | |
420 | u8 free_ar[0x1]; | |
b4ff3a36 | 421 | u8 reserved_at_2[0xe]; |
e281682b SM |
422 | u8 pkey_index[0x10]; |
423 | ||
b4ff3a36 | 424 | u8 reserved_at_20[0x8]; |
e281682b SM |
425 | u8 grh[0x1]; |
426 | u8 mlid[0x7]; | |
427 | u8 rlid[0x10]; | |
428 | ||
429 | u8 ack_timeout[0x5]; | |
b4ff3a36 | 430 | u8 reserved_at_45[0x3]; |
e281682b | 431 | u8 src_addr_index[0x8]; |
b4ff3a36 | 432 | u8 reserved_at_50[0x4]; |
e281682b SM |
433 | u8 stat_rate[0x4]; |
434 | u8 hop_limit[0x8]; | |
435 | ||
b4ff3a36 | 436 | u8 reserved_at_60[0x4]; |
e281682b SM |
437 | u8 tclass[0x8]; |
438 | u8 flow_label[0x14]; | |
439 | ||
440 | u8 rgid_rip[16][0x8]; | |
441 | ||
b4ff3a36 | 442 | u8 reserved_at_100[0x4]; |
e281682b SM |
443 | u8 f_dscp[0x1]; |
444 | u8 f_ecn[0x1]; | |
b4ff3a36 | 445 | u8 reserved_at_106[0x1]; |
e281682b SM |
446 | u8 f_eth_prio[0x1]; |
447 | u8 ecn[0x2]; | |
448 | u8 dscp[0x6]; | |
449 | u8 udp_sport[0x10]; | |
450 | ||
451 | u8 dei_cfi[0x1]; | |
452 | u8 eth_prio[0x3]; | |
453 | u8 sl[0x4]; | |
454 | u8 port[0x8]; | |
455 | u8 rmac_47_32[0x10]; | |
456 | ||
457 | u8 rmac_31_0[0x20]; | |
458 | }; | |
459 | ||
460 | struct mlx5_ifc_flow_table_nic_cap_bits { | |
b4ff3a36 | 461 | u8 reserved_at_0[0x200]; |
e281682b SM |
462 | |
463 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; | |
464 | ||
b4ff3a36 | 465 | u8 reserved_at_400[0x200]; |
e281682b SM |
466 | |
467 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; | |
468 | ||
469 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; | |
470 | ||
b4ff3a36 | 471 | u8 reserved_at_a00[0x200]; |
e281682b SM |
472 | |
473 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; | |
474 | ||
b4ff3a36 | 475 | u8 reserved_at_e00[0x7200]; |
e281682b SM |
476 | }; |
477 | ||
495716b1 | 478 | struct mlx5_ifc_flow_table_eswitch_cap_bits { |
b4ff3a36 | 479 | u8 reserved_at_0[0x200]; |
495716b1 SM |
480 | |
481 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; | |
482 | ||
483 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; | |
484 | ||
485 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; | |
486 | ||
b4ff3a36 | 487 | u8 reserved_at_800[0x7800]; |
495716b1 SM |
488 | }; |
489 | ||
d6666753 SM |
490 | struct mlx5_ifc_e_switch_cap_bits { |
491 | u8 vport_svlan_strip[0x1]; | |
492 | u8 vport_cvlan_strip[0x1]; | |
493 | u8 vport_svlan_insert[0x1]; | |
494 | u8 vport_cvlan_insert_if_not_exist[0x1]; | |
495 | u8 vport_cvlan_insert_overwrite[0x1]; | |
b4ff3a36 | 496 | u8 reserved_at_5[0x1b]; |
d6666753 | 497 | |
b4ff3a36 | 498 | u8 reserved_at_20[0x7e0]; |
d6666753 SM |
499 | }; |
500 | ||
e281682b SM |
501 | struct mlx5_ifc_per_protocol_networking_offload_caps_bits { |
502 | u8 csum_cap[0x1]; | |
503 | u8 vlan_cap[0x1]; | |
504 | u8 lro_cap[0x1]; | |
505 | u8 lro_psh_flag[0x1]; | |
506 | u8 lro_time_stamp[0x1]; | |
b4ff3a36 | 507 | u8 reserved_at_5[0x3]; |
66189961 | 508 | u8 self_lb_en_modifiable[0x1]; |
b4ff3a36 | 509 | u8 reserved_at_9[0x2]; |
e281682b | 510 | u8 max_lso_cap[0x5]; |
b4ff3a36 | 511 | u8 reserved_at_10[0x4]; |
e281682b | 512 | u8 rss_ind_tbl_cap[0x4]; |
b4ff3a36 | 513 | u8 reserved_at_18[0x3]; |
e281682b | 514 | u8 tunnel_lso_const_out_ip_id[0x1]; |
b4ff3a36 | 515 | u8 reserved_at_1c[0x2]; |
e281682b SM |
516 | u8 tunnel_statless_gre[0x1]; |
517 | u8 tunnel_stateless_vxlan[0x1]; | |
518 | ||
b4ff3a36 | 519 | u8 reserved_at_20[0x20]; |
e281682b | 520 | |
b4ff3a36 | 521 | u8 reserved_at_40[0x10]; |
e281682b SM |
522 | u8 lro_min_mss_size[0x10]; |
523 | ||
b4ff3a36 | 524 | u8 reserved_at_60[0x120]; |
e281682b SM |
525 | |
526 | u8 lro_timer_supported_periods[4][0x20]; | |
527 | ||
b4ff3a36 | 528 | u8 reserved_at_200[0x600]; |
e281682b SM |
529 | }; |
530 | ||
531 | struct mlx5_ifc_roce_cap_bits { | |
532 | u8 roce_apm[0x1]; | |
b4ff3a36 | 533 | u8 reserved_at_1[0x1f]; |
e281682b | 534 | |
b4ff3a36 | 535 | u8 reserved_at_20[0x60]; |
e281682b | 536 | |
b4ff3a36 | 537 | u8 reserved_at_80[0xc]; |
e281682b | 538 | u8 l3_type[0x4]; |
b4ff3a36 | 539 | u8 reserved_at_90[0x8]; |
e281682b SM |
540 | u8 roce_version[0x8]; |
541 | ||
b4ff3a36 | 542 | u8 reserved_at_a0[0x10]; |
e281682b SM |
543 | u8 r_roce_dest_udp_port[0x10]; |
544 | ||
545 | u8 r_roce_max_src_udp_port[0x10]; | |
546 | u8 r_roce_min_src_udp_port[0x10]; | |
547 | ||
b4ff3a36 | 548 | u8 reserved_at_e0[0x10]; |
e281682b SM |
549 | u8 roce_address_table_size[0x10]; |
550 | ||
b4ff3a36 | 551 | u8 reserved_at_100[0x700]; |
e281682b SM |
552 | }; |
553 | ||
554 | enum { | |
555 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, | |
556 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, | |
557 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, | |
558 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, | |
559 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, | |
560 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, | |
561 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, | |
562 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, | |
563 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, | |
564 | }; | |
565 | ||
566 | enum { | |
567 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, | |
568 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, | |
569 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, | |
570 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, | |
571 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, | |
572 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, | |
573 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, | |
574 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, | |
575 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, | |
576 | }; | |
577 | ||
578 | struct mlx5_ifc_atomic_caps_bits { | |
b4ff3a36 | 579 | u8 reserved_at_0[0x40]; |
e281682b | 580 | |
f91e6d89 | 581 | u8 atomic_req_8B_endianess_mode[0x2]; |
b4ff3a36 | 582 | u8 reserved_at_42[0x4]; |
f91e6d89 | 583 | u8 supported_atomic_req_8B_endianess_mode_1[0x1]; |
e281682b | 584 | |
b4ff3a36 | 585 | u8 reserved_at_47[0x19]; |
e281682b | 586 | |
b4ff3a36 | 587 | u8 reserved_at_60[0x20]; |
e281682b | 588 | |
b4ff3a36 | 589 | u8 reserved_at_80[0x10]; |
f91e6d89 | 590 | u8 atomic_operations[0x10]; |
e281682b | 591 | |
b4ff3a36 | 592 | u8 reserved_at_a0[0x10]; |
f91e6d89 EBE |
593 | u8 atomic_size_qp[0x10]; |
594 | ||
b4ff3a36 | 595 | u8 reserved_at_c0[0x10]; |
e281682b SM |
596 | u8 atomic_size_dc[0x10]; |
597 | ||
b4ff3a36 | 598 | u8 reserved_at_e0[0x720]; |
e281682b SM |
599 | }; |
600 | ||
601 | struct mlx5_ifc_odp_cap_bits { | |
b4ff3a36 | 602 | u8 reserved_at_0[0x40]; |
e281682b SM |
603 | |
604 | u8 sig[0x1]; | |
b4ff3a36 | 605 | u8 reserved_at_41[0x1f]; |
e281682b | 606 | |
b4ff3a36 | 607 | u8 reserved_at_60[0x20]; |
e281682b SM |
608 | |
609 | struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; | |
610 | ||
611 | struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; | |
612 | ||
613 | struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; | |
614 | ||
b4ff3a36 | 615 | u8 reserved_at_e0[0x720]; |
e281682b SM |
616 | }; |
617 | ||
618 | enum { | |
619 | MLX5_WQ_TYPE_LINKED_LIST = 0x0, | |
620 | MLX5_WQ_TYPE_CYCLIC = 0x1, | |
621 | MLX5_WQ_TYPE_STRQ = 0x2, | |
622 | }; | |
623 | ||
624 | enum { | |
625 | MLX5_WQ_END_PAD_MODE_NONE = 0x0, | |
626 | MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, | |
627 | }; | |
628 | ||
629 | enum { | |
630 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, | |
631 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, | |
632 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, | |
633 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, | |
634 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, | |
635 | }; | |
636 | ||
637 | enum { | |
638 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, | |
639 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, | |
640 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, | |
641 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, | |
642 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, | |
643 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, | |
644 | }; | |
645 | ||
646 | enum { | |
647 | MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, | |
648 | MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, | |
649 | }; | |
650 | ||
651 | enum { | |
652 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, | |
653 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, | |
654 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, | |
655 | }; | |
656 | ||
657 | enum { | |
658 | MLX5_CAP_PORT_TYPE_IB = 0x0, | |
659 | MLX5_CAP_PORT_TYPE_ETH = 0x1, | |
d29b796a EC |
660 | }; |
661 | ||
b775516b | 662 | struct mlx5_ifc_cmd_hca_cap_bits { |
b4ff3a36 | 663 | u8 reserved_at_0[0x80]; |
b775516b EC |
664 | |
665 | u8 log_max_srq_sz[0x8]; | |
666 | u8 log_max_qp_sz[0x8]; | |
b4ff3a36 | 667 | u8 reserved_at_90[0xb]; |
b775516b EC |
668 | u8 log_max_qp[0x5]; |
669 | ||
b4ff3a36 | 670 | u8 reserved_at_a0[0xb]; |
e281682b | 671 | u8 log_max_srq[0x5]; |
b4ff3a36 | 672 | u8 reserved_at_b0[0x10]; |
b775516b | 673 | |
b4ff3a36 | 674 | u8 reserved_at_c0[0x8]; |
b775516b | 675 | u8 log_max_cq_sz[0x8]; |
b4ff3a36 | 676 | u8 reserved_at_d0[0xb]; |
b775516b EC |
677 | u8 log_max_cq[0x5]; |
678 | ||
679 | u8 log_max_eq_sz[0x8]; | |
b4ff3a36 | 680 | u8 reserved_at_e8[0x2]; |
b775516b | 681 | u8 log_max_mkey[0x6]; |
b4ff3a36 | 682 | u8 reserved_at_f0[0xc]; |
b775516b EC |
683 | u8 log_max_eq[0x4]; |
684 | ||
685 | u8 max_indirection[0x8]; | |
b4ff3a36 | 686 | u8 reserved_at_108[0x1]; |
b775516b | 687 | u8 log_max_mrw_sz[0x7]; |
b4ff3a36 | 688 | u8 reserved_at_110[0x2]; |
b775516b | 689 | u8 log_max_bsf_list_size[0x6]; |
b4ff3a36 | 690 | u8 reserved_at_118[0x2]; |
b775516b EC |
691 | u8 log_max_klm_list_size[0x6]; |
692 | ||
b4ff3a36 | 693 | u8 reserved_at_120[0xa]; |
b775516b | 694 | u8 log_max_ra_req_dc[0x6]; |
b4ff3a36 | 695 | u8 reserved_at_130[0xa]; |
b775516b EC |
696 | u8 log_max_ra_res_dc[0x6]; |
697 | ||
b4ff3a36 | 698 | u8 reserved_at_140[0xa]; |
b775516b | 699 | u8 log_max_ra_req_qp[0x6]; |
b4ff3a36 | 700 | u8 reserved_at_150[0xa]; |
b775516b EC |
701 | u8 log_max_ra_res_qp[0x6]; |
702 | ||
703 | u8 pad_cap[0x1]; | |
704 | u8 cc_query_allowed[0x1]; | |
705 | u8 cc_modify_allowed[0x1]; | |
b4ff3a36 | 706 | u8 reserved_at_163[0xd]; |
e281682b | 707 | u8 gid_table_size[0x10]; |
b775516b | 708 | |
e281682b SM |
709 | u8 out_of_seq_cnt[0x1]; |
710 | u8 vport_counters[0x1]; | |
b4ff3a36 | 711 | u8 reserved_at_182[0x4]; |
b775516b EC |
712 | u8 max_qp_cnt[0xa]; |
713 | u8 pkey_table_size[0x10]; | |
714 | ||
e281682b SM |
715 | u8 vport_group_manager[0x1]; |
716 | u8 vhca_group_manager[0x1]; | |
717 | u8 ib_virt[0x1]; | |
718 | u8 eth_virt[0x1]; | |
b4ff3a36 | 719 | u8 reserved_at_1a4[0x1]; |
e281682b SM |
720 | u8 ets[0x1]; |
721 | u8 nic_flow_table[0x1]; | |
54f0a411 | 722 | u8 eswitch_flow_table[0x1]; |
fc50db98 | 723 | u8 early_vf_enable; |
b4ff3a36 | 724 | u8 reserved_at_1a8[0x2]; |
b775516b | 725 | u8 local_ca_ack_delay[0x5]; |
b4ff3a36 | 726 | u8 reserved_at_1af[0x6]; |
e281682b | 727 | u8 port_type[0x2]; |
b775516b EC |
728 | u8 num_ports[0x8]; |
729 | ||
b4ff3a36 | 730 | u8 reserved_at_1bf[0x3]; |
b775516b | 731 | u8 log_max_msg[0x5]; |
b4ff3a36 | 732 | u8 reserved_at_1c7[0x18]; |
b775516b EC |
733 | |
734 | u8 stat_rate_support[0x10]; | |
b4ff3a36 | 735 | u8 reserved_at_1ef[0xc]; |
e281682b | 736 | u8 cqe_version[0x4]; |
b775516b | 737 | |
e281682b | 738 | u8 compact_address_vector[0x1]; |
b4ff3a36 | 739 | u8 reserved_at_200[0xe]; |
e281682b | 740 | u8 drain_sigerr[0x1]; |
b775516b EC |
741 | u8 cmdif_checksum[0x2]; |
742 | u8 sigerr_cqe[0x1]; | |
b4ff3a36 | 743 | u8 reserved_at_212[0x1]; |
b775516b EC |
744 | u8 wq_signature[0x1]; |
745 | u8 sctr_data_cqe[0x1]; | |
b4ff3a36 | 746 | u8 reserved_at_215[0x1]; |
b775516b EC |
747 | u8 sho[0x1]; |
748 | u8 tph[0x1]; | |
749 | u8 rf[0x1]; | |
e281682b | 750 | u8 dct[0x1]; |
b4ff3a36 | 751 | u8 reserved_at_21a[0x1]; |
e281682b | 752 | u8 eth_net_offloads[0x1]; |
b775516b EC |
753 | u8 roce[0x1]; |
754 | u8 atomic[0x1]; | |
b4ff3a36 | 755 | u8 reserved_at_21e[0x1]; |
b775516b EC |
756 | |
757 | u8 cq_oi[0x1]; | |
758 | u8 cq_resize[0x1]; | |
759 | u8 cq_moderation[0x1]; | |
b4ff3a36 | 760 | u8 reserved_at_222[0x3]; |
e281682b | 761 | u8 cq_eq_remap[0x1]; |
b775516b EC |
762 | u8 pg[0x1]; |
763 | u8 block_lb_mc[0x1]; | |
b4ff3a36 | 764 | u8 reserved_at_228[0x1]; |
e281682b | 765 | u8 scqe_break_moderation[0x1]; |
b4ff3a36 | 766 | u8 reserved_at_22a[0x1]; |
b775516b | 767 | u8 cd[0x1]; |
b4ff3a36 | 768 | u8 reserved_at_22c[0x1]; |
b775516b | 769 | u8 apm[0x1]; |
b4ff3a36 | 770 | u8 reserved_at_22e[0x7]; |
b775516b EC |
771 | u8 qkv[0x1]; |
772 | u8 pkv[0x1]; | |
b4ff3a36 | 773 | u8 reserved_at_237[0x4]; |
b775516b EC |
774 | u8 xrc[0x1]; |
775 | u8 ud[0x1]; | |
776 | u8 uc[0x1]; | |
777 | u8 rc[0x1]; | |
778 | ||
b4ff3a36 | 779 | u8 reserved_at_23f[0xa]; |
b775516b | 780 | u8 uar_sz[0x6]; |
b4ff3a36 | 781 | u8 reserved_at_24f[0x8]; |
b775516b EC |
782 | u8 log_pg_sz[0x8]; |
783 | ||
784 | u8 bf[0x1]; | |
b4ff3a36 | 785 | u8 reserved_at_260[0x1]; |
e281682b | 786 | u8 pad_tx_eth_packet[0x1]; |
b4ff3a36 | 787 | u8 reserved_at_262[0x8]; |
b775516b | 788 | u8 log_bf_reg_size[0x5]; |
b4ff3a36 | 789 | u8 reserved_at_26f[0x10]; |
b775516b | 790 | |
b4ff3a36 | 791 | u8 reserved_at_27f[0x10]; |
b775516b EC |
792 | u8 max_wqe_sz_sq[0x10]; |
793 | ||
b4ff3a36 | 794 | u8 reserved_at_29f[0x10]; |
b775516b EC |
795 | u8 max_wqe_sz_rq[0x10]; |
796 | ||
b4ff3a36 | 797 | u8 reserved_at_2bf[0x10]; |
b775516b EC |
798 | u8 max_wqe_sz_sq_dc[0x10]; |
799 | ||
b4ff3a36 | 800 | u8 reserved_at_2df[0x7]; |
b775516b EC |
801 | u8 max_qp_mcg[0x19]; |
802 | ||
b4ff3a36 | 803 | u8 reserved_at_2ff[0x18]; |
b775516b EC |
804 | u8 log_max_mcg[0x8]; |
805 | ||
b4ff3a36 | 806 | u8 reserved_at_31f[0x3]; |
e281682b | 807 | u8 log_max_transport_domain[0x5]; |
b4ff3a36 | 808 | u8 reserved_at_327[0x3]; |
b775516b | 809 | u8 log_max_pd[0x5]; |
b4ff3a36 | 810 | u8 reserved_at_32f[0xb]; |
b775516b EC |
811 | u8 log_max_xrcd[0x5]; |
812 | ||
b4ff3a36 | 813 | u8 reserved_at_33f[0x20]; |
b775516b | 814 | |
b4ff3a36 | 815 | u8 reserved_at_35f[0x3]; |
b775516b | 816 | u8 log_max_rq[0x5]; |
b4ff3a36 | 817 | u8 reserved_at_367[0x3]; |
b775516b | 818 | u8 log_max_sq[0x5]; |
b4ff3a36 | 819 | u8 reserved_at_36f[0x3]; |
b775516b | 820 | u8 log_max_tir[0x5]; |
b4ff3a36 | 821 | u8 reserved_at_377[0x3]; |
b775516b EC |
822 | u8 log_max_tis[0x5]; |
823 | ||
e281682b | 824 | u8 basic_cyclic_rcv_wqe[0x1]; |
b4ff3a36 | 825 | u8 reserved_at_380[0x2]; |
e281682b | 826 | u8 log_max_rmp[0x5]; |
b4ff3a36 | 827 | u8 reserved_at_387[0x3]; |
e281682b | 828 | u8 log_max_rqt[0x5]; |
b4ff3a36 | 829 | u8 reserved_at_38f[0x3]; |
e281682b | 830 | u8 log_max_rqt_size[0x5]; |
b4ff3a36 | 831 | u8 reserved_at_397[0x3]; |
b775516b EC |
832 | u8 log_max_tis_per_sq[0x5]; |
833 | ||
b4ff3a36 | 834 | u8 reserved_at_39f[0x3]; |
e281682b | 835 | u8 log_max_stride_sz_rq[0x5]; |
b4ff3a36 | 836 | u8 reserved_at_3a7[0x3]; |
e281682b | 837 | u8 log_min_stride_sz_rq[0x5]; |
b4ff3a36 | 838 | u8 reserved_at_3af[0x3]; |
e281682b | 839 | u8 log_max_stride_sz_sq[0x5]; |
b4ff3a36 | 840 | u8 reserved_at_3b7[0x3]; |
e281682b SM |
841 | u8 log_min_stride_sz_sq[0x5]; |
842 | ||
b4ff3a36 | 843 | u8 reserved_at_3bf[0x1b]; |
e281682b SM |
844 | u8 log_max_wq_sz[0x5]; |
845 | ||
54f0a411 | 846 | u8 nic_vport_change_event[0x1]; |
b4ff3a36 | 847 | u8 reserved_at_3e0[0xa]; |
54f0a411 | 848 | u8 log_max_vlan_list[0x5]; |
b4ff3a36 | 849 | u8 reserved_at_3ef[0x3]; |
54f0a411 | 850 | u8 log_max_current_mc_list[0x5]; |
b4ff3a36 | 851 | u8 reserved_at_3f7[0x3]; |
54f0a411 SM |
852 | u8 log_max_current_uc_list[0x5]; |
853 | ||
b4ff3a36 | 854 | u8 reserved_at_3ff[0x80]; |
54f0a411 | 855 | |
b4ff3a36 | 856 | u8 reserved_at_47f[0x3]; |
e281682b | 857 | u8 log_max_l2_table[0x5]; |
b4ff3a36 | 858 | u8 reserved_at_487[0x8]; |
b775516b EC |
859 | u8 log_uar_page_sz[0x10]; |
860 | ||
b4ff3a36 | 861 | u8 reserved_at_49f[0x20]; |
048ccca8 | 862 | u8 device_frequency_mhz[0x20]; |
b0844444 | 863 | u8 device_frequency_khz[0x20]; |
b4ff3a36 | 864 | u8 reserved_at_4ff[0x5f]; |
b775516b EC |
865 | u8 cqe_zip[0x1]; |
866 | ||
867 | u8 cqe_zip_timeout[0x10]; | |
868 | u8 cqe_zip_max_num[0x10]; | |
869 | ||
b4ff3a36 | 870 | u8 reserved_at_57f[0x220]; |
b775516b EC |
871 | }; |
872 | ||
81848731 SM |
873 | enum mlx5_flow_destination_type { |
874 | MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, | |
875 | MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, | |
876 | MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, | |
e281682b | 877 | }; |
b775516b | 878 | |
e281682b SM |
879 | struct mlx5_ifc_dest_format_struct_bits { |
880 | u8 destination_type[0x8]; | |
881 | u8 destination_id[0x18]; | |
b775516b | 882 | |
b4ff3a36 | 883 | u8 reserved_at_20[0x20]; |
e281682b SM |
884 | }; |
885 | ||
886 | struct mlx5_ifc_fte_match_param_bits { | |
887 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; | |
888 | ||
889 | struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; | |
890 | ||
891 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; | |
b775516b | 892 | |
b4ff3a36 | 893 | u8 reserved_at_600[0xa00]; |
b775516b EC |
894 | }; |
895 | ||
e281682b SM |
896 | enum { |
897 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, | |
898 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, | |
899 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, | |
900 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, | |
901 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, | |
902 | }; | |
b775516b | 903 | |
e281682b SM |
904 | struct mlx5_ifc_rx_hash_field_select_bits { |
905 | u8 l3_prot_type[0x1]; | |
906 | u8 l4_prot_type[0x1]; | |
907 | u8 selected_fields[0x1e]; | |
908 | }; | |
b775516b | 909 | |
e281682b SM |
910 | enum { |
911 | MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, | |
912 | MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, | |
b775516b EC |
913 | }; |
914 | ||
e281682b SM |
915 | enum { |
916 | MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, | |
917 | MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, | |
918 | }; | |
919 | ||
920 | struct mlx5_ifc_wq_bits { | |
921 | u8 wq_type[0x4]; | |
922 | u8 wq_signature[0x1]; | |
923 | u8 end_padding_mode[0x2]; | |
924 | u8 cd_slave[0x1]; | |
b4ff3a36 | 925 | u8 reserved_at_8[0x18]; |
b775516b | 926 | |
e281682b SM |
927 | u8 hds_skip_first_sge[0x1]; |
928 | u8 log2_hds_buf_size[0x3]; | |
b4ff3a36 | 929 | u8 reserved_at_24[0x7]; |
e281682b SM |
930 | u8 page_offset[0x5]; |
931 | u8 lwm[0x10]; | |
b775516b | 932 | |
b4ff3a36 | 933 | u8 reserved_at_40[0x8]; |
e281682b SM |
934 | u8 pd[0x18]; |
935 | ||
b4ff3a36 | 936 | u8 reserved_at_60[0x8]; |
e281682b SM |
937 | u8 uar_page[0x18]; |
938 | ||
939 | u8 dbr_addr[0x40]; | |
940 | ||
941 | u8 hw_counter[0x20]; | |
942 | ||
943 | u8 sw_counter[0x20]; | |
944 | ||
b4ff3a36 | 945 | u8 reserved_at_100[0xc]; |
e281682b | 946 | u8 log_wq_stride[0x4]; |
b4ff3a36 | 947 | u8 reserved_at_110[0x3]; |
e281682b | 948 | u8 log_wq_pg_sz[0x5]; |
b4ff3a36 | 949 | u8 reserved_at_118[0x3]; |
e281682b SM |
950 | u8 log_wq_sz[0x5]; |
951 | ||
b4ff3a36 | 952 | u8 reserved_at_120[0x4e0]; |
b775516b | 953 | |
e281682b | 954 | struct mlx5_ifc_cmd_pas_bits pas[0]; |
b775516b EC |
955 | }; |
956 | ||
e281682b | 957 | struct mlx5_ifc_rq_num_bits { |
b4ff3a36 | 958 | u8 reserved_at_0[0x8]; |
e281682b SM |
959 | u8 rq_num[0x18]; |
960 | }; | |
b775516b | 961 | |
e281682b | 962 | struct mlx5_ifc_mac_address_layout_bits { |
b4ff3a36 | 963 | u8 reserved_at_0[0x10]; |
e281682b | 964 | u8 mac_addr_47_32[0x10]; |
b775516b | 965 | |
e281682b SM |
966 | u8 mac_addr_31_0[0x20]; |
967 | }; | |
968 | ||
c0046cf7 | 969 | struct mlx5_ifc_vlan_layout_bits { |
b4ff3a36 | 970 | u8 reserved_at_0[0x14]; |
c0046cf7 SM |
971 | u8 vlan[0x0c]; |
972 | ||
b4ff3a36 | 973 | u8 reserved_at_20[0x20]; |
c0046cf7 SM |
974 | }; |
975 | ||
e281682b | 976 | struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { |
b4ff3a36 | 977 | u8 reserved_at_0[0xa0]; |
e281682b SM |
978 | |
979 | u8 min_time_between_cnps[0x20]; | |
980 | ||
b4ff3a36 | 981 | u8 reserved_at_c0[0x12]; |
e281682b | 982 | u8 cnp_dscp[0x6]; |
b4ff3a36 | 983 | u8 reserved_at_d8[0x5]; |
e281682b SM |
984 | u8 cnp_802p_prio[0x3]; |
985 | ||
b4ff3a36 | 986 | u8 reserved_at_e0[0x720]; |
e281682b SM |
987 | }; |
988 | ||
989 | struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { | |
b4ff3a36 | 990 | u8 reserved_at_0[0x60]; |
e281682b | 991 | |
b4ff3a36 | 992 | u8 reserved_at_60[0x4]; |
e281682b | 993 | u8 clamp_tgt_rate[0x1]; |
b4ff3a36 | 994 | u8 reserved_at_65[0x3]; |
e281682b | 995 | u8 clamp_tgt_rate_after_time_inc[0x1]; |
b4ff3a36 | 996 | u8 reserved_at_69[0x17]; |
e281682b | 997 | |
b4ff3a36 | 998 | u8 reserved_at_80[0x20]; |
e281682b SM |
999 | |
1000 | u8 rpg_time_reset[0x20]; | |
1001 | ||
1002 | u8 rpg_byte_reset[0x20]; | |
1003 | ||
1004 | u8 rpg_threshold[0x20]; | |
1005 | ||
1006 | u8 rpg_max_rate[0x20]; | |
1007 | ||
1008 | u8 rpg_ai_rate[0x20]; | |
1009 | ||
1010 | u8 rpg_hai_rate[0x20]; | |
1011 | ||
1012 | u8 rpg_gd[0x20]; | |
1013 | ||
1014 | u8 rpg_min_dec_fac[0x20]; | |
1015 | ||
1016 | u8 rpg_min_rate[0x20]; | |
1017 | ||
b4ff3a36 | 1018 | u8 reserved_at_1c0[0xe0]; |
e281682b SM |
1019 | |
1020 | u8 rate_to_set_on_first_cnp[0x20]; | |
1021 | ||
1022 | u8 dce_tcp_g[0x20]; | |
1023 | ||
1024 | u8 dce_tcp_rtt[0x20]; | |
1025 | ||
1026 | u8 rate_reduce_monitor_period[0x20]; | |
1027 | ||
b4ff3a36 | 1028 | u8 reserved_at_320[0x20]; |
e281682b SM |
1029 | |
1030 | u8 initial_alpha_value[0x20]; | |
1031 | ||
b4ff3a36 | 1032 | u8 reserved_at_360[0x4a0]; |
e281682b SM |
1033 | }; |
1034 | ||
1035 | struct mlx5_ifc_cong_control_802_1qau_rp_bits { | |
b4ff3a36 | 1036 | u8 reserved_at_0[0x80]; |
e281682b SM |
1037 | |
1038 | u8 rppp_max_rps[0x20]; | |
1039 | ||
1040 | u8 rpg_time_reset[0x20]; | |
1041 | ||
1042 | u8 rpg_byte_reset[0x20]; | |
1043 | ||
1044 | u8 rpg_threshold[0x20]; | |
1045 | ||
1046 | u8 rpg_max_rate[0x20]; | |
1047 | ||
1048 | u8 rpg_ai_rate[0x20]; | |
1049 | ||
1050 | u8 rpg_hai_rate[0x20]; | |
1051 | ||
1052 | u8 rpg_gd[0x20]; | |
1053 | ||
1054 | u8 rpg_min_dec_fac[0x20]; | |
1055 | ||
1056 | u8 rpg_min_rate[0x20]; | |
1057 | ||
b4ff3a36 | 1058 | u8 reserved_at_1c0[0x640]; |
e281682b SM |
1059 | }; |
1060 | ||
1061 | enum { | |
1062 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, | |
1063 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, | |
1064 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, | |
1065 | }; | |
1066 | ||
1067 | struct mlx5_ifc_resize_field_select_bits { | |
1068 | u8 resize_field_select[0x20]; | |
1069 | }; | |
1070 | ||
1071 | enum { | |
1072 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, | |
1073 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, | |
1074 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, | |
1075 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, | |
1076 | }; | |
1077 | ||
1078 | struct mlx5_ifc_modify_field_select_bits { | |
1079 | u8 modify_field_select[0x20]; | |
1080 | }; | |
1081 | ||
1082 | struct mlx5_ifc_field_select_r_roce_np_bits { | |
1083 | u8 field_select_r_roce_np[0x20]; | |
1084 | }; | |
1085 | ||
1086 | struct mlx5_ifc_field_select_r_roce_rp_bits { | |
1087 | u8 field_select_r_roce_rp[0x20]; | |
1088 | }; | |
1089 | ||
1090 | enum { | |
1091 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, | |
1092 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, | |
1093 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, | |
1094 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, | |
1095 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, | |
1096 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, | |
1097 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, | |
1098 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, | |
1099 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, | |
1100 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, | |
1101 | }; | |
1102 | ||
1103 | struct mlx5_ifc_field_select_802_1qau_rp_bits { | |
1104 | u8 field_select_8021qaurp[0x20]; | |
1105 | }; | |
1106 | ||
1107 | struct mlx5_ifc_phys_layer_cntrs_bits { | |
1108 | u8 time_since_last_clear_high[0x20]; | |
1109 | ||
1110 | u8 time_since_last_clear_low[0x20]; | |
1111 | ||
1112 | u8 symbol_errors_high[0x20]; | |
1113 | ||
1114 | u8 symbol_errors_low[0x20]; | |
1115 | ||
1116 | u8 sync_headers_errors_high[0x20]; | |
1117 | ||
1118 | u8 sync_headers_errors_low[0x20]; | |
1119 | ||
1120 | u8 edpl_bip_errors_lane0_high[0x20]; | |
1121 | ||
1122 | u8 edpl_bip_errors_lane0_low[0x20]; | |
1123 | ||
1124 | u8 edpl_bip_errors_lane1_high[0x20]; | |
1125 | ||
1126 | u8 edpl_bip_errors_lane1_low[0x20]; | |
1127 | ||
1128 | u8 edpl_bip_errors_lane2_high[0x20]; | |
1129 | ||
1130 | u8 edpl_bip_errors_lane2_low[0x20]; | |
1131 | ||
1132 | u8 edpl_bip_errors_lane3_high[0x20]; | |
1133 | ||
1134 | u8 edpl_bip_errors_lane3_low[0x20]; | |
1135 | ||
1136 | u8 fc_fec_corrected_blocks_lane0_high[0x20]; | |
1137 | ||
1138 | u8 fc_fec_corrected_blocks_lane0_low[0x20]; | |
1139 | ||
1140 | u8 fc_fec_corrected_blocks_lane1_high[0x20]; | |
1141 | ||
1142 | u8 fc_fec_corrected_blocks_lane1_low[0x20]; | |
1143 | ||
1144 | u8 fc_fec_corrected_blocks_lane2_high[0x20]; | |
1145 | ||
1146 | u8 fc_fec_corrected_blocks_lane2_low[0x20]; | |
1147 | ||
1148 | u8 fc_fec_corrected_blocks_lane3_high[0x20]; | |
1149 | ||
1150 | u8 fc_fec_corrected_blocks_lane3_low[0x20]; | |
1151 | ||
1152 | u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; | |
1153 | ||
1154 | u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; | |
1155 | ||
1156 | u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; | |
1157 | ||
1158 | u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; | |
1159 | ||
1160 | u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; | |
1161 | ||
1162 | u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; | |
1163 | ||
1164 | u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; | |
1165 | ||
1166 | u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; | |
1167 | ||
1168 | u8 rs_fec_corrected_blocks_high[0x20]; | |
1169 | ||
1170 | u8 rs_fec_corrected_blocks_low[0x20]; | |
1171 | ||
1172 | u8 rs_fec_uncorrectable_blocks_high[0x20]; | |
1173 | ||
1174 | u8 rs_fec_uncorrectable_blocks_low[0x20]; | |
1175 | ||
1176 | u8 rs_fec_no_errors_blocks_high[0x20]; | |
1177 | ||
1178 | u8 rs_fec_no_errors_blocks_low[0x20]; | |
1179 | ||
1180 | u8 rs_fec_single_error_blocks_high[0x20]; | |
1181 | ||
1182 | u8 rs_fec_single_error_blocks_low[0x20]; | |
1183 | ||
1184 | u8 rs_fec_corrected_symbols_total_high[0x20]; | |
1185 | ||
1186 | u8 rs_fec_corrected_symbols_total_low[0x20]; | |
1187 | ||
1188 | u8 rs_fec_corrected_symbols_lane0_high[0x20]; | |
1189 | ||
1190 | u8 rs_fec_corrected_symbols_lane0_low[0x20]; | |
1191 | ||
1192 | u8 rs_fec_corrected_symbols_lane1_high[0x20]; | |
1193 | ||
1194 | u8 rs_fec_corrected_symbols_lane1_low[0x20]; | |
1195 | ||
1196 | u8 rs_fec_corrected_symbols_lane2_high[0x20]; | |
1197 | ||
1198 | u8 rs_fec_corrected_symbols_lane2_low[0x20]; | |
1199 | ||
1200 | u8 rs_fec_corrected_symbols_lane3_high[0x20]; | |
1201 | ||
1202 | u8 rs_fec_corrected_symbols_lane3_low[0x20]; | |
1203 | ||
1204 | u8 link_down_events[0x20]; | |
1205 | ||
1206 | u8 successful_recovery_events[0x20]; | |
1207 | ||
b4ff3a36 | 1208 | u8 reserved_at_640[0x180]; |
e281682b SM |
1209 | }; |
1210 | ||
1211 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { | |
1212 | u8 transmit_queue_high[0x20]; | |
1213 | ||
1214 | u8 transmit_queue_low[0x20]; | |
1215 | ||
b4ff3a36 | 1216 | u8 reserved_at_40[0x780]; |
e281682b SM |
1217 | }; |
1218 | ||
1219 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { | |
1220 | u8 rx_octets_high[0x20]; | |
1221 | ||
1222 | u8 rx_octets_low[0x20]; | |
1223 | ||
b4ff3a36 | 1224 | u8 reserved_at_40[0xc0]; |
e281682b SM |
1225 | |
1226 | u8 rx_frames_high[0x20]; | |
1227 | ||
1228 | u8 rx_frames_low[0x20]; | |
1229 | ||
1230 | u8 tx_octets_high[0x20]; | |
1231 | ||
1232 | u8 tx_octets_low[0x20]; | |
1233 | ||
b4ff3a36 | 1234 | u8 reserved_at_180[0xc0]; |
e281682b SM |
1235 | |
1236 | u8 tx_frames_high[0x20]; | |
1237 | ||
1238 | u8 tx_frames_low[0x20]; | |
1239 | ||
1240 | u8 rx_pause_high[0x20]; | |
1241 | ||
1242 | u8 rx_pause_low[0x20]; | |
1243 | ||
1244 | u8 rx_pause_duration_high[0x20]; | |
1245 | ||
1246 | u8 rx_pause_duration_low[0x20]; | |
1247 | ||
1248 | u8 tx_pause_high[0x20]; | |
1249 | ||
1250 | u8 tx_pause_low[0x20]; | |
1251 | ||
1252 | u8 tx_pause_duration_high[0x20]; | |
1253 | ||
1254 | u8 tx_pause_duration_low[0x20]; | |
1255 | ||
1256 | u8 rx_pause_transition_high[0x20]; | |
1257 | ||
1258 | u8 rx_pause_transition_low[0x20]; | |
1259 | ||
b4ff3a36 | 1260 | u8 reserved_at_3c0[0x400]; |
e281682b SM |
1261 | }; |
1262 | ||
1263 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { | |
1264 | u8 port_transmit_wait_high[0x20]; | |
1265 | ||
1266 | u8 port_transmit_wait_low[0x20]; | |
1267 | ||
b4ff3a36 | 1268 | u8 reserved_at_40[0x780]; |
e281682b SM |
1269 | }; |
1270 | ||
1271 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { | |
1272 | u8 dot3stats_alignment_errors_high[0x20]; | |
1273 | ||
1274 | u8 dot3stats_alignment_errors_low[0x20]; | |
1275 | ||
1276 | u8 dot3stats_fcs_errors_high[0x20]; | |
1277 | ||
1278 | u8 dot3stats_fcs_errors_low[0x20]; | |
1279 | ||
1280 | u8 dot3stats_single_collision_frames_high[0x20]; | |
1281 | ||
1282 | u8 dot3stats_single_collision_frames_low[0x20]; | |
1283 | ||
1284 | u8 dot3stats_multiple_collision_frames_high[0x20]; | |
1285 | ||
1286 | u8 dot3stats_multiple_collision_frames_low[0x20]; | |
1287 | ||
1288 | u8 dot3stats_sqe_test_errors_high[0x20]; | |
1289 | ||
1290 | u8 dot3stats_sqe_test_errors_low[0x20]; | |
1291 | ||
1292 | u8 dot3stats_deferred_transmissions_high[0x20]; | |
1293 | ||
1294 | u8 dot3stats_deferred_transmissions_low[0x20]; | |
1295 | ||
1296 | u8 dot3stats_late_collisions_high[0x20]; | |
1297 | ||
1298 | u8 dot3stats_late_collisions_low[0x20]; | |
1299 | ||
1300 | u8 dot3stats_excessive_collisions_high[0x20]; | |
1301 | ||
1302 | u8 dot3stats_excessive_collisions_low[0x20]; | |
1303 | ||
1304 | u8 dot3stats_internal_mac_transmit_errors_high[0x20]; | |
1305 | ||
1306 | u8 dot3stats_internal_mac_transmit_errors_low[0x20]; | |
1307 | ||
1308 | u8 dot3stats_carrier_sense_errors_high[0x20]; | |
1309 | ||
1310 | u8 dot3stats_carrier_sense_errors_low[0x20]; | |
1311 | ||
1312 | u8 dot3stats_frame_too_longs_high[0x20]; | |
1313 | ||
1314 | u8 dot3stats_frame_too_longs_low[0x20]; | |
1315 | ||
1316 | u8 dot3stats_internal_mac_receive_errors_high[0x20]; | |
1317 | ||
1318 | u8 dot3stats_internal_mac_receive_errors_low[0x20]; | |
1319 | ||
1320 | u8 dot3stats_symbol_errors_high[0x20]; | |
1321 | ||
1322 | u8 dot3stats_symbol_errors_low[0x20]; | |
1323 | ||
1324 | u8 dot3control_in_unknown_opcodes_high[0x20]; | |
1325 | ||
1326 | u8 dot3control_in_unknown_opcodes_low[0x20]; | |
1327 | ||
1328 | u8 dot3in_pause_frames_high[0x20]; | |
1329 | ||
1330 | u8 dot3in_pause_frames_low[0x20]; | |
1331 | ||
1332 | u8 dot3out_pause_frames_high[0x20]; | |
1333 | ||
1334 | u8 dot3out_pause_frames_low[0x20]; | |
1335 | ||
b4ff3a36 | 1336 | u8 reserved_at_400[0x3c0]; |
e281682b SM |
1337 | }; |
1338 | ||
1339 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { | |
1340 | u8 ether_stats_drop_events_high[0x20]; | |
1341 | ||
1342 | u8 ether_stats_drop_events_low[0x20]; | |
1343 | ||
1344 | u8 ether_stats_octets_high[0x20]; | |
1345 | ||
1346 | u8 ether_stats_octets_low[0x20]; | |
1347 | ||
1348 | u8 ether_stats_pkts_high[0x20]; | |
1349 | ||
1350 | u8 ether_stats_pkts_low[0x20]; | |
1351 | ||
1352 | u8 ether_stats_broadcast_pkts_high[0x20]; | |
1353 | ||
1354 | u8 ether_stats_broadcast_pkts_low[0x20]; | |
1355 | ||
1356 | u8 ether_stats_multicast_pkts_high[0x20]; | |
1357 | ||
1358 | u8 ether_stats_multicast_pkts_low[0x20]; | |
1359 | ||
1360 | u8 ether_stats_crc_align_errors_high[0x20]; | |
1361 | ||
1362 | u8 ether_stats_crc_align_errors_low[0x20]; | |
1363 | ||
1364 | u8 ether_stats_undersize_pkts_high[0x20]; | |
1365 | ||
1366 | u8 ether_stats_undersize_pkts_low[0x20]; | |
1367 | ||
1368 | u8 ether_stats_oversize_pkts_high[0x20]; | |
1369 | ||
1370 | u8 ether_stats_oversize_pkts_low[0x20]; | |
1371 | ||
1372 | u8 ether_stats_fragments_high[0x20]; | |
1373 | ||
1374 | u8 ether_stats_fragments_low[0x20]; | |
1375 | ||
1376 | u8 ether_stats_jabbers_high[0x20]; | |
1377 | ||
1378 | u8 ether_stats_jabbers_low[0x20]; | |
1379 | ||
1380 | u8 ether_stats_collisions_high[0x20]; | |
1381 | ||
1382 | u8 ether_stats_collisions_low[0x20]; | |
1383 | ||
1384 | u8 ether_stats_pkts64octets_high[0x20]; | |
1385 | ||
1386 | u8 ether_stats_pkts64octets_low[0x20]; | |
1387 | ||
1388 | u8 ether_stats_pkts65to127octets_high[0x20]; | |
1389 | ||
1390 | u8 ether_stats_pkts65to127octets_low[0x20]; | |
1391 | ||
1392 | u8 ether_stats_pkts128to255octets_high[0x20]; | |
1393 | ||
1394 | u8 ether_stats_pkts128to255octets_low[0x20]; | |
1395 | ||
1396 | u8 ether_stats_pkts256to511octets_high[0x20]; | |
1397 | ||
1398 | u8 ether_stats_pkts256to511octets_low[0x20]; | |
1399 | ||
1400 | u8 ether_stats_pkts512to1023octets_high[0x20]; | |
1401 | ||
1402 | u8 ether_stats_pkts512to1023octets_low[0x20]; | |
1403 | ||
1404 | u8 ether_stats_pkts1024to1518octets_high[0x20]; | |
1405 | ||
1406 | u8 ether_stats_pkts1024to1518octets_low[0x20]; | |
1407 | ||
1408 | u8 ether_stats_pkts1519to2047octets_high[0x20]; | |
1409 | ||
1410 | u8 ether_stats_pkts1519to2047octets_low[0x20]; | |
1411 | ||
1412 | u8 ether_stats_pkts2048to4095octets_high[0x20]; | |
1413 | ||
1414 | u8 ether_stats_pkts2048to4095octets_low[0x20]; | |
1415 | ||
1416 | u8 ether_stats_pkts4096to8191octets_high[0x20]; | |
1417 | ||
1418 | u8 ether_stats_pkts4096to8191octets_low[0x20]; | |
1419 | ||
1420 | u8 ether_stats_pkts8192to10239octets_high[0x20]; | |
1421 | ||
1422 | u8 ether_stats_pkts8192to10239octets_low[0x20]; | |
1423 | ||
b4ff3a36 | 1424 | u8 reserved_at_540[0x280]; |
e281682b SM |
1425 | }; |
1426 | ||
1427 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { | |
1428 | u8 if_in_octets_high[0x20]; | |
1429 | ||
1430 | u8 if_in_octets_low[0x20]; | |
1431 | ||
1432 | u8 if_in_ucast_pkts_high[0x20]; | |
1433 | ||
1434 | u8 if_in_ucast_pkts_low[0x20]; | |
1435 | ||
1436 | u8 if_in_discards_high[0x20]; | |
1437 | ||
1438 | u8 if_in_discards_low[0x20]; | |
1439 | ||
1440 | u8 if_in_errors_high[0x20]; | |
1441 | ||
1442 | u8 if_in_errors_low[0x20]; | |
1443 | ||
1444 | u8 if_in_unknown_protos_high[0x20]; | |
1445 | ||
1446 | u8 if_in_unknown_protos_low[0x20]; | |
1447 | ||
1448 | u8 if_out_octets_high[0x20]; | |
1449 | ||
1450 | u8 if_out_octets_low[0x20]; | |
1451 | ||
1452 | u8 if_out_ucast_pkts_high[0x20]; | |
1453 | ||
1454 | u8 if_out_ucast_pkts_low[0x20]; | |
1455 | ||
1456 | u8 if_out_discards_high[0x20]; | |
1457 | ||
1458 | u8 if_out_discards_low[0x20]; | |
1459 | ||
1460 | u8 if_out_errors_high[0x20]; | |
1461 | ||
1462 | u8 if_out_errors_low[0x20]; | |
1463 | ||
1464 | u8 if_in_multicast_pkts_high[0x20]; | |
1465 | ||
1466 | u8 if_in_multicast_pkts_low[0x20]; | |
1467 | ||
1468 | u8 if_in_broadcast_pkts_high[0x20]; | |
1469 | ||
1470 | u8 if_in_broadcast_pkts_low[0x20]; | |
1471 | ||
1472 | u8 if_out_multicast_pkts_high[0x20]; | |
1473 | ||
1474 | u8 if_out_multicast_pkts_low[0x20]; | |
1475 | ||
1476 | u8 if_out_broadcast_pkts_high[0x20]; | |
1477 | ||
1478 | u8 if_out_broadcast_pkts_low[0x20]; | |
1479 | ||
b4ff3a36 | 1480 | u8 reserved_at_340[0x480]; |
e281682b SM |
1481 | }; |
1482 | ||
1483 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { | |
1484 | u8 a_frames_transmitted_ok_high[0x20]; | |
1485 | ||
1486 | u8 a_frames_transmitted_ok_low[0x20]; | |
1487 | ||
1488 | u8 a_frames_received_ok_high[0x20]; | |
1489 | ||
1490 | u8 a_frames_received_ok_low[0x20]; | |
1491 | ||
1492 | u8 a_frame_check_sequence_errors_high[0x20]; | |
1493 | ||
1494 | u8 a_frame_check_sequence_errors_low[0x20]; | |
1495 | ||
1496 | u8 a_alignment_errors_high[0x20]; | |
1497 | ||
1498 | u8 a_alignment_errors_low[0x20]; | |
1499 | ||
1500 | u8 a_octets_transmitted_ok_high[0x20]; | |
1501 | ||
1502 | u8 a_octets_transmitted_ok_low[0x20]; | |
1503 | ||
1504 | u8 a_octets_received_ok_high[0x20]; | |
1505 | ||
1506 | u8 a_octets_received_ok_low[0x20]; | |
1507 | ||
1508 | u8 a_multicast_frames_xmitted_ok_high[0x20]; | |
1509 | ||
1510 | u8 a_multicast_frames_xmitted_ok_low[0x20]; | |
1511 | ||
1512 | u8 a_broadcast_frames_xmitted_ok_high[0x20]; | |
1513 | ||
1514 | u8 a_broadcast_frames_xmitted_ok_low[0x20]; | |
1515 | ||
1516 | u8 a_multicast_frames_received_ok_high[0x20]; | |
1517 | ||
1518 | u8 a_multicast_frames_received_ok_low[0x20]; | |
1519 | ||
1520 | u8 a_broadcast_frames_received_ok_high[0x20]; | |
1521 | ||
1522 | u8 a_broadcast_frames_received_ok_low[0x20]; | |
1523 | ||
1524 | u8 a_in_range_length_errors_high[0x20]; | |
1525 | ||
1526 | u8 a_in_range_length_errors_low[0x20]; | |
1527 | ||
1528 | u8 a_out_of_range_length_field_high[0x20]; | |
1529 | ||
1530 | u8 a_out_of_range_length_field_low[0x20]; | |
1531 | ||
1532 | u8 a_frame_too_long_errors_high[0x20]; | |
1533 | ||
1534 | u8 a_frame_too_long_errors_low[0x20]; | |
1535 | ||
1536 | u8 a_symbol_error_during_carrier_high[0x20]; | |
1537 | ||
1538 | u8 a_symbol_error_during_carrier_low[0x20]; | |
1539 | ||
1540 | u8 a_mac_control_frames_transmitted_high[0x20]; | |
1541 | ||
1542 | u8 a_mac_control_frames_transmitted_low[0x20]; | |
1543 | ||
1544 | u8 a_mac_control_frames_received_high[0x20]; | |
1545 | ||
1546 | u8 a_mac_control_frames_received_low[0x20]; | |
1547 | ||
1548 | u8 a_unsupported_opcodes_received_high[0x20]; | |
1549 | ||
1550 | u8 a_unsupported_opcodes_received_low[0x20]; | |
1551 | ||
1552 | u8 a_pause_mac_ctrl_frames_received_high[0x20]; | |
1553 | ||
1554 | u8 a_pause_mac_ctrl_frames_received_low[0x20]; | |
1555 | ||
1556 | u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; | |
1557 | ||
1558 | u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; | |
1559 | ||
b4ff3a36 | 1560 | u8 reserved_at_4c0[0x300]; |
e281682b SM |
1561 | }; |
1562 | ||
1563 | struct mlx5_ifc_cmd_inter_comp_event_bits { | |
1564 | u8 command_completion_vector[0x20]; | |
1565 | ||
b4ff3a36 | 1566 | u8 reserved_at_20[0xc0]; |
e281682b SM |
1567 | }; |
1568 | ||
1569 | struct mlx5_ifc_stall_vl_event_bits { | |
b4ff3a36 | 1570 | u8 reserved_at_0[0x18]; |
e281682b | 1571 | u8 port_num[0x1]; |
b4ff3a36 | 1572 | u8 reserved_at_19[0x3]; |
e281682b SM |
1573 | u8 vl[0x4]; |
1574 | ||
b4ff3a36 | 1575 | u8 reserved_at_20[0xa0]; |
e281682b SM |
1576 | }; |
1577 | ||
1578 | struct mlx5_ifc_db_bf_congestion_event_bits { | |
1579 | u8 event_subtype[0x8]; | |
b4ff3a36 | 1580 | u8 reserved_at_8[0x8]; |
e281682b | 1581 | u8 congestion_level[0x8]; |
b4ff3a36 | 1582 | u8 reserved_at_18[0x8]; |
e281682b | 1583 | |
b4ff3a36 | 1584 | u8 reserved_at_20[0xa0]; |
e281682b SM |
1585 | }; |
1586 | ||
1587 | struct mlx5_ifc_gpio_event_bits { | |
b4ff3a36 | 1588 | u8 reserved_at_0[0x60]; |
e281682b SM |
1589 | |
1590 | u8 gpio_event_hi[0x20]; | |
1591 | ||
1592 | u8 gpio_event_lo[0x20]; | |
1593 | ||
b4ff3a36 | 1594 | u8 reserved_at_a0[0x40]; |
e281682b SM |
1595 | }; |
1596 | ||
1597 | struct mlx5_ifc_port_state_change_event_bits { | |
b4ff3a36 | 1598 | u8 reserved_at_0[0x40]; |
e281682b SM |
1599 | |
1600 | u8 port_num[0x4]; | |
b4ff3a36 | 1601 | u8 reserved_at_44[0x1c]; |
e281682b | 1602 | |
b4ff3a36 | 1603 | u8 reserved_at_60[0x80]; |
e281682b SM |
1604 | }; |
1605 | ||
1606 | struct mlx5_ifc_dropped_packet_logged_bits { | |
b4ff3a36 | 1607 | u8 reserved_at_0[0xe0]; |
e281682b SM |
1608 | }; |
1609 | ||
1610 | enum { | |
1611 | MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, | |
1612 | MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, | |
1613 | }; | |
1614 | ||
1615 | struct mlx5_ifc_cq_error_bits { | |
b4ff3a36 | 1616 | u8 reserved_at_0[0x8]; |
e281682b SM |
1617 | u8 cqn[0x18]; |
1618 | ||
b4ff3a36 | 1619 | u8 reserved_at_20[0x20]; |
e281682b | 1620 | |
b4ff3a36 | 1621 | u8 reserved_at_40[0x18]; |
e281682b SM |
1622 | u8 syndrome[0x8]; |
1623 | ||
b4ff3a36 | 1624 | u8 reserved_at_60[0x80]; |
e281682b SM |
1625 | }; |
1626 | ||
1627 | struct mlx5_ifc_rdma_page_fault_event_bits { | |
1628 | u8 bytes_committed[0x20]; | |
1629 | ||
1630 | u8 r_key[0x20]; | |
1631 | ||
b4ff3a36 | 1632 | u8 reserved_at_40[0x10]; |
e281682b SM |
1633 | u8 packet_len[0x10]; |
1634 | ||
1635 | u8 rdma_op_len[0x20]; | |
1636 | ||
1637 | u8 rdma_va[0x40]; | |
1638 | ||
b4ff3a36 | 1639 | u8 reserved_at_c0[0x5]; |
e281682b SM |
1640 | u8 rdma[0x1]; |
1641 | u8 write[0x1]; | |
1642 | u8 requestor[0x1]; | |
1643 | u8 qp_number[0x18]; | |
1644 | }; | |
1645 | ||
1646 | struct mlx5_ifc_wqe_associated_page_fault_event_bits { | |
1647 | u8 bytes_committed[0x20]; | |
1648 | ||
b4ff3a36 | 1649 | u8 reserved_at_20[0x10]; |
e281682b SM |
1650 | u8 wqe_index[0x10]; |
1651 | ||
b4ff3a36 | 1652 | u8 reserved_at_40[0x10]; |
e281682b SM |
1653 | u8 len[0x10]; |
1654 | ||
b4ff3a36 | 1655 | u8 reserved_at_60[0x60]; |
e281682b | 1656 | |
b4ff3a36 | 1657 | u8 reserved_at_c0[0x5]; |
e281682b SM |
1658 | u8 rdma[0x1]; |
1659 | u8 write_read[0x1]; | |
1660 | u8 requestor[0x1]; | |
1661 | u8 qpn[0x18]; | |
1662 | }; | |
1663 | ||
1664 | struct mlx5_ifc_qp_events_bits { | |
b4ff3a36 | 1665 | u8 reserved_at_0[0xa0]; |
e281682b SM |
1666 | |
1667 | u8 type[0x8]; | |
b4ff3a36 | 1668 | u8 reserved_at_a8[0x18]; |
e281682b | 1669 | |
b4ff3a36 | 1670 | u8 reserved_at_c0[0x8]; |
e281682b SM |
1671 | u8 qpn_rqn_sqn[0x18]; |
1672 | }; | |
1673 | ||
1674 | struct mlx5_ifc_dct_events_bits { | |
b4ff3a36 | 1675 | u8 reserved_at_0[0xc0]; |
e281682b | 1676 | |
b4ff3a36 | 1677 | u8 reserved_at_c0[0x8]; |
e281682b SM |
1678 | u8 dct_number[0x18]; |
1679 | }; | |
1680 | ||
1681 | struct mlx5_ifc_comp_event_bits { | |
b4ff3a36 | 1682 | u8 reserved_at_0[0xc0]; |
e281682b | 1683 | |
b4ff3a36 | 1684 | u8 reserved_at_c0[0x8]; |
e281682b SM |
1685 | u8 cq_number[0x18]; |
1686 | }; | |
1687 | ||
1688 | enum { | |
1689 | MLX5_QPC_STATE_RST = 0x0, | |
1690 | MLX5_QPC_STATE_INIT = 0x1, | |
1691 | MLX5_QPC_STATE_RTR = 0x2, | |
1692 | MLX5_QPC_STATE_RTS = 0x3, | |
1693 | MLX5_QPC_STATE_SQER = 0x4, | |
1694 | MLX5_QPC_STATE_ERR = 0x6, | |
1695 | MLX5_QPC_STATE_SQD = 0x7, | |
1696 | MLX5_QPC_STATE_SUSPENDED = 0x9, | |
1697 | }; | |
1698 | ||
1699 | enum { | |
1700 | MLX5_QPC_ST_RC = 0x0, | |
1701 | MLX5_QPC_ST_UC = 0x1, | |
1702 | MLX5_QPC_ST_UD = 0x2, | |
1703 | MLX5_QPC_ST_XRC = 0x3, | |
1704 | MLX5_QPC_ST_DCI = 0x5, | |
1705 | MLX5_QPC_ST_QP0 = 0x7, | |
1706 | MLX5_QPC_ST_QP1 = 0x8, | |
1707 | MLX5_QPC_ST_RAW_DATAGRAM = 0x9, | |
1708 | MLX5_QPC_ST_REG_UMR = 0xc, | |
1709 | }; | |
1710 | ||
1711 | enum { | |
1712 | MLX5_QPC_PM_STATE_ARMED = 0x0, | |
1713 | MLX5_QPC_PM_STATE_REARM = 0x1, | |
1714 | MLX5_QPC_PM_STATE_RESERVED = 0x2, | |
1715 | MLX5_QPC_PM_STATE_MIGRATED = 0x3, | |
1716 | }; | |
1717 | ||
1718 | enum { | |
1719 | MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, | |
1720 | MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, | |
1721 | }; | |
1722 | ||
1723 | enum { | |
1724 | MLX5_QPC_MTU_256_BYTES = 0x1, | |
1725 | MLX5_QPC_MTU_512_BYTES = 0x2, | |
1726 | MLX5_QPC_MTU_1K_BYTES = 0x3, | |
1727 | MLX5_QPC_MTU_2K_BYTES = 0x4, | |
1728 | MLX5_QPC_MTU_4K_BYTES = 0x5, | |
1729 | MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, | |
1730 | }; | |
1731 | ||
1732 | enum { | |
1733 | MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, | |
1734 | MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, | |
1735 | MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, | |
1736 | MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, | |
1737 | MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, | |
1738 | MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, | |
1739 | MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, | |
1740 | MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, | |
1741 | }; | |
1742 | ||
1743 | enum { | |
1744 | MLX5_QPC_CS_REQ_DISABLE = 0x0, | |
1745 | MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, | |
1746 | MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, | |
1747 | }; | |
1748 | ||
1749 | enum { | |
1750 | MLX5_QPC_CS_RES_DISABLE = 0x0, | |
1751 | MLX5_QPC_CS_RES_UP_TO_32B = 0x1, | |
1752 | MLX5_QPC_CS_RES_UP_TO_64B = 0x2, | |
1753 | }; | |
1754 | ||
1755 | struct mlx5_ifc_qpc_bits { | |
1756 | u8 state[0x4]; | |
b4ff3a36 | 1757 | u8 reserved_at_4[0x4]; |
e281682b | 1758 | u8 st[0x8]; |
b4ff3a36 | 1759 | u8 reserved_at_10[0x3]; |
e281682b | 1760 | u8 pm_state[0x2]; |
b4ff3a36 | 1761 | u8 reserved_at_15[0x7]; |
e281682b | 1762 | u8 end_padding_mode[0x2]; |
b4ff3a36 | 1763 | u8 reserved_at_1e[0x2]; |
e281682b SM |
1764 | |
1765 | u8 wq_signature[0x1]; | |
1766 | u8 block_lb_mc[0x1]; | |
1767 | u8 atomic_like_write_en[0x1]; | |
1768 | u8 latency_sensitive[0x1]; | |
b4ff3a36 | 1769 | u8 reserved_at_24[0x1]; |
e281682b | 1770 | u8 drain_sigerr[0x1]; |
b4ff3a36 | 1771 | u8 reserved_at_26[0x2]; |
e281682b SM |
1772 | u8 pd[0x18]; |
1773 | ||
1774 | u8 mtu[0x3]; | |
1775 | u8 log_msg_max[0x5]; | |
b4ff3a36 | 1776 | u8 reserved_at_48[0x1]; |
e281682b SM |
1777 | u8 log_rq_size[0x4]; |
1778 | u8 log_rq_stride[0x3]; | |
1779 | u8 no_sq[0x1]; | |
1780 | u8 log_sq_size[0x4]; | |
b4ff3a36 | 1781 | u8 reserved_at_55[0x6]; |
e281682b | 1782 | u8 rlky[0x1]; |
b4ff3a36 | 1783 | u8 reserved_at_5c[0x4]; |
e281682b SM |
1784 | |
1785 | u8 counter_set_id[0x8]; | |
1786 | u8 uar_page[0x18]; | |
1787 | ||
b4ff3a36 | 1788 | u8 reserved_at_80[0x8]; |
e281682b SM |
1789 | u8 user_index[0x18]; |
1790 | ||
b4ff3a36 | 1791 | u8 reserved_at_a0[0x3]; |
e281682b SM |
1792 | u8 log_page_size[0x5]; |
1793 | u8 remote_qpn[0x18]; | |
1794 | ||
1795 | struct mlx5_ifc_ads_bits primary_address_path; | |
1796 | ||
1797 | struct mlx5_ifc_ads_bits secondary_address_path; | |
1798 | ||
1799 | u8 log_ack_req_freq[0x4]; | |
b4ff3a36 | 1800 | u8 reserved_at_384[0x4]; |
e281682b | 1801 | u8 log_sra_max[0x3]; |
b4ff3a36 | 1802 | u8 reserved_at_38b[0x2]; |
e281682b SM |
1803 | u8 retry_count[0x3]; |
1804 | u8 rnr_retry[0x3]; | |
b4ff3a36 | 1805 | u8 reserved_at_393[0x1]; |
e281682b SM |
1806 | u8 fre[0x1]; |
1807 | u8 cur_rnr_retry[0x3]; | |
1808 | u8 cur_retry_count[0x3]; | |
b4ff3a36 | 1809 | u8 reserved_at_39b[0x5]; |
e281682b | 1810 | |
b4ff3a36 | 1811 | u8 reserved_at_3a0[0x20]; |
e281682b | 1812 | |
b4ff3a36 | 1813 | u8 reserved_at_3c0[0x8]; |
e281682b SM |
1814 | u8 next_send_psn[0x18]; |
1815 | ||
b4ff3a36 | 1816 | u8 reserved_at_3e0[0x8]; |
e281682b SM |
1817 | u8 cqn_snd[0x18]; |
1818 | ||
b4ff3a36 | 1819 | u8 reserved_at_400[0x40]; |
e281682b | 1820 | |
b4ff3a36 | 1821 | u8 reserved_at_440[0x8]; |
e281682b SM |
1822 | u8 last_acked_psn[0x18]; |
1823 | ||
b4ff3a36 | 1824 | u8 reserved_at_460[0x8]; |
e281682b SM |
1825 | u8 ssn[0x18]; |
1826 | ||
b4ff3a36 | 1827 | u8 reserved_at_480[0x8]; |
e281682b | 1828 | u8 log_rra_max[0x3]; |
b4ff3a36 | 1829 | u8 reserved_at_48b[0x1]; |
e281682b SM |
1830 | u8 atomic_mode[0x4]; |
1831 | u8 rre[0x1]; | |
1832 | u8 rwe[0x1]; | |
1833 | u8 rae[0x1]; | |
b4ff3a36 | 1834 | u8 reserved_at_493[0x1]; |
e281682b | 1835 | u8 page_offset[0x6]; |
b4ff3a36 | 1836 | u8 reserved_at_49a[0x3]; |
e281682b SM |
1837 | u8 cd_slave_receive[0x1]; |
1838 | u8 cd_slave_send[0x1]; | |
1839 | u8 cd_master[0x1]; | |
1840 | ||
b4ff3a36 | 1841 | u8 reserved_at_4a0[0x3]; |
e281682b SM |
1842 | u8 min_rnr_nak[0x5]; |
1843 | u8 next_rcv_psn[0x18]; | |
1844 | ||
b4ff3a36 | 1845 | u8 reserved_at_4c0[0x8]; |
e281682b SM |
1846 | u8 xrcd[0x18]; |
1847 | ||
b4ff3a36 | 1848 | u8 reserved_at_4e0[0x8]; |
e281682b SM |
1849 | u8 cqn_rcv[0x18]; |
1850 | ||
1851 | u8 dbr_addr[0x40]; | |
1852 | ||
1853 | u8 q_key[0x20]; | |
1854 | ||
b4ff3a36 | 1855 | u8 reserved_at_560[0x5]; |
e281682b SM |
1856 | u8 rq_type[0x3]; |
1857 | u8 srqn_rmpn[0x18]; | |
1858 | ||
b4ff3a36 | 1859 | u8 reserved_at_580[0x8]; |
e281682b SM |
1860 | u8 rmsn[0x18]; |
1861 | ||
1862 | u8 hw_sq_wqebb_counter[0x10]; | |
1863 | u8 sw_sq_wqebb_counter[0x10]; | |
1864 | ||
1865 | u8 hw_rq_counter[0x20]; | |
1866 | ||
1867 | u8 sw_rq_counter[0x20]; | |
1868 | ||
b4ff3a36 | 1869 | u8 reserved_at_600[0x20]; |
e281682b | 1870 | |
b4ff3a36 | 1871 | u8 reserved_at_620[0xf]; |
e281682b SM |
1872 | u8 cgs[0x1]; |
1873 | u8 cs_req[0x8]; | |
1874 | u8 cs_res[0x8]; | |
1875 | ||
1876 | u8 dc_access_key[0x40]; | |
1877 | ||
b4ff3a36 | 1878 | u8 reserved_at_680[0xc0]; |
e281682b SM |
1879 | }; |
1880 | ||
1881 | struct mlx5_ifc_roce_addr_layout_bits { | |
1882 | u8 source_l3_address[16][0x8]; | |
1883 | ||
b4ff3a36 | 1884 | u8 reserved_at_80[0x3]; |
e281682b SM |
1885 | u8 vlan_valid[0x1]; |
1886 | u8 vlan_id[0xc]; | |
1887 | u8 source_mac_47_32[0x10]; | |
1888 | ||
1889 | u8 source_mac_31_0[0x20]; | |
1890 | ||
b4ff3a36 | 1891 | u8 reserved_at_c0[0x14]; |
e281682b SM |
1892 | u8 roce_l3_type[0x4]; |
1893 | u8 roce_version[0x8]; | |
1894 | ||
b4ff3a36 | 1895 | u8 reserved_at_e0[0x20]; |
e281682b SM |
1896 | }; |
1897 | ||
1898 | union mlx5_ifc_hca_cap_union_bits { | |
1899 | struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; | |
1900 | struct mlx5_ifc_odp_cap_bits odp_cap; | |
1901 | struct mlx5_ifc_atomic_caps_bits atomic_caps; | |
1902 | struct mlx5_ifc_roce_cap_bits roce_cap; | |
1903 | struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; | |
1904 | struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; | |
495716b1 | 1905 | struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; |
d6666753 | 1906 | struct mlx5_ifc_e_switch_cap_bits e_switch_cap; |
b4ff3a36 | 1907 | u8 reserved_at_0[0x8000]; |
e281682b SM |
1908 | }; |
1909 | ||
1910 | enum { | |
1911 | MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, | |
1912 | MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, | |
1913 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, | |
1914 | }; | |
1915 | ||
1916 | struct mlx5_ifc_flow_context_bits { | |
b4ff3a36 | 1917 | u8 reserved_at_0[0x20]; |
e281682b SM |
1918 | |
1919 | u8 group_id[0x20]; | |
1920 | ||
b4ff3a36 | 1921 | u8 reserved_at_40[0x8]; |
e281682b SM |
1922 | u8 flow_tag[0x18]; |
1923 | ||
b4ff3a36 | 1924 | u8 reserved_at_60[0x10]; |
e281682b SM |
1925 | u8 action[0x10]; |
1926 | ||
b4ff3a36 | 1927 | u8 reserved_at_80[0x8]; |
e281682b SM |
1928 | u8 destination_list_size[0x18]; |
1929 | ||
b4ff3a36 | 1930 | u8 reserved_at_a0[0x160]; |
e281682b SM |
1931 | |
1932 | struct mlx5_ifc_fte_match_param_bits match_value; | |
1933 | ||
b4ff3a36 | 1934 | u8 reserved_at_1200[0x600]; |
e281682b SM |
1935 | |
1936 | struct mlx5_ifc_dest_format_struct_bits destination[0]; | |
1937 | }; | |
1938 | ||
1939 | enum { | |
1940 | MLX5_XRC_SRQC_STATE_GOOD = 0x0, | |
1941 | MLX5_XRC_SRQC_STATE_ERROR = 0x1, | |
1942 | }; | |
1943 | ||
1944 | struct mlx5_ifc_xrc_srqc_bits { | |
1945 | u8 state[0x4]; | |
1946 | u8 log_xrc_srq_size[0x4]; | |
b4ff3a36 | 1947 | u8 reserved_at_8[0x18]; |
e281682b SM |
1948 | |
1949 | u8 wq_signature[0x1]; | |
1950 | u8 cont_srq[0x1]; | |
b4ff3a36 | 1951 | u8 reserved_at_22[0x1]; |
e281682b SM |
1952 | u8 rlky[0x1]; |
1953 | u8 basic_cyclic_rcv_wqe[0x1]; | |
1954 | u8 log_rq_stride[0x3]; | |
1955 | u8 xrcd[0x18]; | |
1956 | ||
1957 | u8 page_offset[0x6]; | |
b4ff3a36 | 1958 | u8 reserved_at_46[0x2]; |
e281682b SM |
1959 | u8 cqn[0x18]; |
1960 | ||
b4ff3a36 | 1961 | u8 reserved_at_60[0x20]; |
e281682b SM |
1962 | |
1963 | u8 user_index_equal_xrc_srqn[0x1]; | |
b4ff3a36 | 1964 | u8 reserved_at_81[0x1]; |
e281682b SM |
1965 | u8 log_page_size[0x6]; |
1966 | u8 user_index[0x18]; | |
1967 | ||
b4ff3a36 | 1968 | u8 reserved_at_a0[0x20]; |
e281682b | 1969 | |
b4ff3a36 | 1970 | u8 reserved_at_c0[0x8]; |
e281682b SM |
1971 | u8 pd[0x18]; |
1972 | ||
1973 | u8 lwm[0x10]; | |
1974 | u8 wqe_cnt[0x10]; | |
1975 | ||
b4ff3a36 | 1976 | u8 reserved_at_100[0x40]; |
e281682b SM |
1977 | |
1978 | u8 db_record_addr_h[0x20]; | |
1979 | ||
1980 | u8 db_record_addr_l[0x1e]; | |
b4ff3a36 | 1981 | u8 reserved_at_17e[0x2]; |
e281682b | 1982 | |
b4ff3a36 | 1983 | u8 reserved_at_180[0x80]; |
e281682b SM |
1984 | }; |
1985 | ||
1986 | struct mlx5_ifc_traffic_counter_bits { | |
1987 | u8 packets[0x40]; | |
1988 | ||
1989 | u8 octets[0x40]; | |
1990 | }; | |
1991 | ||
1992 | struct mlx5_ifc_tisc_bits { | |
b4ff3a36 | 1993 | u8 reserved_at_0[0xc]; |
e281682b | 1994 | u8 prio[0x4]; |
b4ff3a36 | 1995 | u8 reserved_at_10[0x10]; |
e281682b | 1996 | |
b4ff3a36 | 1997 | u8 reserved_at_20[0x100]; |
e281682b | 1998 | |
b4ff3a36 | 1999 | u8 reserved_at_120[0x8]; |
e281682b SM |
2000 | u8 transport_domain[0x18]; |
2001 | ||
b4ff3a36 | 2002 | u8 reserved_at_140[0x3c0]; |
e281682b SM |
2003 | }; |
2004 | ||
2005 | enum { | |
2006 | MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, | |
2007 | MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, | |
2008 | }; | |
2009 | ||
2010 | enum { | |
2011 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, | |
2012 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, | |
2013 | }; | |
2014 | ||
2015 | enum { | |
2be6967c SM |
2016 | MLX5_RX_HASH_FN_NONE = 0x0, |
2017 | MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, | |
2018 | MLX5_RX_HASH_FN_TOEPLITZ = 0x2, | |
e281682b SM |
2019 | }; |
2020 | ||
2021 | enum { | |
2022 | MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, | |
2023 | MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, | |
2024 | }; | |
2025 | ||
2026 | struct mlx5_ifc_tirc_bits { | |
b4ff3a36 | 2027 | u8 reserved_at_0[0x20]; |
e281682b SM |
2028 | |
2029 | u8 disp_type[0x4]; | |
b4ff3a36 | 2030 | u8 reserved_at_24[0x1c]; |
e281682b | 2031 | |
b4ff3a36 | 2032 | u8 reserved_at_40[0x40]; |
e281682b | 2033 | |
b4ff3a36 | 2034 | u8 reserved_at_80[0x4]; |
e281682b SM |
2035 | u8 lro_timeout_period_usecs[0x10]; |
2036 | u8 lro_enable_mask[0x4]; | |
2037 | u8 lro_max_ip_payload_size[0x8]; | |
2038 | ||
b4ff3a36 | 2039 | u8 reserved_at_a0[0x40]; |
e281682b | 2040 | |
b4ff3a36 | 2041 | u8 reserved_at_e0[0x8]; |
e281682b SM |
2042 | u8 inline_rqn[0x18]; |
2043 | ||
2044 | u8 rx_hash_symmetric[0x1]; | |
b4ff3a36 | 2045 | u8 reserved_at_101[0x1]; |
e281682b | 2046 | u8 tunneled_offload_en[0x1]; |
b4ff3a36 | 2047 | u8 reserved_at_103[0x5]; |
e281682b SM |
2048 | u8 indirect_table[0x18]; |
2049 | ||
2050 | u8 rx_hash_fn[0x4]; | |
b4ff3a36 | 2051 | u8 reserved_at_124[0x2]; |
e281682b SM |
2052 | u8 self_lb_block[0x2]; |
2053 | u8 transport_domain[0x18]; | |
2054 | ||
2055 | u8 rx_hash_toeplitz_key[10][0x20]; | |
2056 | ||
2057 | struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; | |
2058 | ||
2059 | struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; | |
2060 | ||
b4ff3a36 | 2061 | u8 reserved_at_2c0[0x4c0]; |
e281682b SM |
2062 | }; |
2063 | ||
2064 | enum { | |
2065 | MLX5_SRQC_STATE_GOOD = 0x0, | |
2066 | MLX5_SRQC_STATE_ERROR = 0x1, | |
2067 | }; | |
2068 | ||
2069 | struct mlx5_ifc_srqc_bits { | |
2070 | u8 state[0x4]; | |
2071 | u8 log_srq_size[0x4]; | |
b4ff3a36 | 2072 | u8 reserved_at_8[0x18]; |
e281682b SM |
2073 | |
2074 | u8 wq_signature[0x1]; | |
2075 | u8 cont_srq[0x1]; | |
b4ff3a36 | 2076 | u8 reserved_at_22[0x1]; |
e281682b | 2077 | u8 rlky[0x1]; |
b4ff3a36 | 2078 | u8 reserved_at_24[0x1]; |
e281682b SM |
2079 | u8 log_rq_stride[0x3]; |
2080 | u8 xrcd[0x18]; | |
2081 | ||
2082 | u8 page_offset[0x6]; | |
b4ff3a36 | 2083 | u8 reserved_at_46[0x2]; |
e281682b SM |
2084 | u8 cqn[0x18]; |
2085 | ||
b4ff3a36 | 2086 | u8 reserved_at_60[0x20]; |
e281682b | 2087 | |
b4ff3a36 | 2088 | u8 reserved_at_80[0x2]; |
e281682b | 2089 | u8 log_page_size[0x6]; |
b4ff3a36 | 2090 | u8 reserved_at_88[0x18]; |
e281682b | 2091 | |
b4ff3a36 | 2092 | u8 reserved_at_a0[0x20]; |
e281682b | 2093 | |
b4ff3a36 | 2094 | u8 reserved_at_c0[0x8]; |
e281682b SM |
2095 | u8 pd[0x18]; |
2096 | ||
2097 | u8 lwm[0x10]; | |
2098 | u8 wqe_cnt[0x10]; | |
2099 | ||
b4ff3a36 | 2100 | u8 reserved_at_100[0x40]; |
e281682b | 2101 | |
01949d01 | 2102 | u8 dbr_addr[0x40]; |
e281682b | 2103 | |
b4ff3a36 | 2104 | u8 reserved_at_180[0x80]; |
e281682b SM |
2105 | }; |
2106 | ||
2107 | enum { | |
2108 | MLX5_SQC_STATE_RST = 0x0, | |
2109 | MLX5_SQC_STATE_RDY = 0x1, | |
2110 | MLX5_SQC_STATE_ERR = 0x3, | |
2111 | }; | |
2112 | ||
2113 | struct mlx5_ifc_sqc_bits { | |
2114 | u8 rlky[0x1]; | |
2115 | u8 cd_master[0x1]; | |
2116 | u8 fre[0x1]; | |
2117 | u8 flush_in_error_en[0x1]; | |
b4ff3a36 | 2118 | u8 reserved_at_4[0x4]; |
e281682b | 2119 | u8 state[0x4]; |
b4ff3a36 | 2120 | u8 reserved_at_c[0x14]; |
e281682b | 2121 | |
b4ff3a36 | 2122 | u8 reserved_at_20[0x8]; |
e281682b SM |
2123 | u8 user_index[0x18]; |
2124 | ||
b4ff3a36 | 2125 | u8 reserved_at_40[0x8]; |
e281682b SM |
2126 | u8 cqn[0x18]; |
2127 | ||
b4ff3a36 | 2128 | u8 reserved_at_60[0xa0]; |
e281682b SM |
2129 | |
2130 | u8 tis_lst_sz[0x10]; | |
b4ff3a36 | 2131 | u8 reserved_at_110[0x10]; |
e281682b | 2132 | |
b4ff3a36 | 2133 | u8 reserved_at_120[0x40]; |
e281682b | 2134 | |
b4ff3a36 | 2135 | u8 reserved_at_160[0x8]; |
e281682b SM |
2136 | u8 tis_num_0[0x18]; |
2137 | ||
2138 | struct mlx5_ifc_wq_bits wq; | |
2139 | }; | |
2140 | ||
2141 | struct mlx5_ifc_rqtc_bits { | |
b4ff3a36 | 2142 | u8 reserved_at_0[0xa0]; |
e281682b | 2143 | |
b4ff3a36 | 2144 | u8 reserved_at_a0[0x10]; |
e281682b SM |
2145 | u8 rqt_max_size[0x10]; |
2146 | ||
b4ff3a36 | 2147 | u8 reserved_at_c0[0x10]; |
e281682b SM |
2148 | u8 rqt_actual_size[0x10]; |
2149 | ||
b4ff3a36 | 2150 | u8 reserved_at_e0[0x6a0]; |
e281682b SM |
2151 | |
2152 | struct mlx5_ifc_rq_num_bits rq_num[0]; | |
2153 | }; | |
2154 | ||
2155 | enum { | |
2156 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, | |
2157 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, | |
2158 | }; | |
2159 | ||
2160 | enum { | |
2161 | MLX5_RQC_STATE_RST = 0x0, | |
2162 | MLX5_RQC_STATE_RDY = 0x1, | |
2163 | MLX5_RQC_STATE_ERR = 0x3, | |
2164 | }; | |
2165 | ||
2166 | struct mlx5_ifc_rqc_bits { | |
2167 | u8 rlky[0x1]; | |
b4ff3a36 | 2168 | u8 reserved_at_1[0x2]; |
e281682b SM |
2169 | u8 vsd[0x1]; |
2170 | u8 mem_rq_type[0x4]; | |
2171 | u8 state[0x4]; | |
b4ff3a36 | 2172 | u8 reserved_at_c[0x1]; |
e281682b | 2173 | u8 flush_in_error_en[0x1]; |
b4ff3a36 | 2174 | u8 reserved_at_e[0x12]; |
e281682b | 2175 | |
b4ff3a36 | 2176 | u8 reserved_at_20[0x8]; |
e281682b SM |
2177 | u8 user_index[0x18]; |
2178 | ||
b4ff3a36 | 2179 | u8 reserved_at_40[0x8]; |
e281682b SM |
2180 | u8 cqn[0x18]; |
2181 | ||
2182 | u8 counter_set_id[0x8]; | |
b4ff3a36 | 2183 | u8 reserved_at_68[0x18]; |
e281682b | 2184 | |
b4ff3a36 | 2185 | u8 reserved_at_80[0x8]; |
e281682b SM |
2186 | u8 rmpn[0x18]; |
2187 | ||
b4ff3a36 | 2188 | u8 reserved_at_a0[0xe0]; |
e281682b SM |
2189 | |
2190 | struct mlx5_ifc_wq_bits wq; | |
2191 | }; | |
2192 | ||
2193 | enum { | |
2194 | MLX5_RMPC_STATE_RDY = 0x1, | |
2195 | MLX5_RMPC_STATE_ERR = 0x3, | |
2196 | }; | |
2197 | ||
2198 | struct mlx5_ifc_rmpc_bits { | |
b4ff3a36 | 2199 | u8 reserved_at_0[0x8]; |
e281682b | 2200 | u8 state[0x4]; |
b4ff3a36 | 2201 | u8 reserved_at_c[0x14]; |
e281682b SM |
2202 | |
2203 | u8 basic_cyclic_rcv_wqe[0x1]; | |
b4ff3a36 | 2204 | u8 reserved_at_21[0x1f]; |
e281682b | 2205 | |
b4ff3a36 | 2206 | u8 reserved_at_40[0x140]; |
e281682b SM |
2207 | |
2208 | struct mlx5_ifc_wq_bits wq; | |
2209 | }; | |
2210 | ||
e281682b | 2211 | struct mlx5_ifc_nic_vport_context_bits { |
b4ff3a36 | 2212 | u8 reserved_at_0[0x1f]; |
e281682b SM |
2213 | u8 roce_en[0x1]; |
2214 | ||
d82b7318 | 2215 | u8 arm_change_event[0x1]; |
b4ff3a36 | 2216 | u8 reserved_at_21[0x1a]; |
d82b7318 SM |
2217 | u8 event_on_mtu[0x1]; |
2218 | u8 event_on_promisc_change[0x1]; | |
2219 | u8 event_on_vlan_change[0x1]; | |
2220 | u8 event_on_mc_address_change[0x1]; | |
2221 | u8 event_on_uc_address_change[0x1]; | |
e281682b | 2222 | |
b4ff3a36 | 2223 | u8 reserved_at_40[0xf0]; |
d82b7318 SM |
2224 | |
2225 | u8 mtu[0x10]; | |
2226 | ||
9efa7525 AS |
2227 | u8 system_image_guid[0x40]; |
2228 | u8 port_guid[0x40]; | |
2229 | u8 node_guid[0x40]; | |
2230 | ||
b4ff3a36 | 2231 | u8 reserved_at_200[0x140]; |
9efa7525 | 2232 | u8 qkey_violation_counter[0x10]; |
b4ff3a36 | 2233 | u8 reserved_at_350[0x430]; |
d82b7318 SM |
2234 | |
2235 | u8 promisc_uc[0x1]; | |
2236 | u8 promisc_mc[0x1]; | |
2237 | u8 promisc_all[0x1]; | |
b4ff3a36 | 2238 | u8 reserved_at_783[0x2]; |
e281682b | 2239 | u8 allowed_list_type[0x3]; |
b4ff3a36 | 2240 | u8 reserved_at_788[0xc]; |
e281682b SM |
2241 | u8 allowed_list_size[0xc]; |
2242 | ||
2243 | struct mlx5_ifc_mac_address_layout_bits permanent_address; | |
2244 | ||
b4ff3a36 | 2245 | u8 reserved_at_7e0[0x20]; |
e281682b SM |
2246 | |
2247 | u8 current_uc_mac_address[0][0x40]; | |
2248 | }; | |
2249 | ||
2250 | enum { | |
2251 | MLX5_MKC_ACCESS_MODE_PA = 0x0, | |
2252 | MLX5_MKC_ACCESS_MODE_MTT = 0x1, | |
2253 | MLX5_MKC_ACCESS_MODE_KLMS = 0x2, | |
2254 | }; | |
2255 | ||
2256 | struct mlx5_ifc_mkc_bits { | |
b4ff3a36 | 2257 | u8 reserved_at_0[0x1]; |
e281682b | 2258 | u8 free[0x1]; |
b4ff3a36 | 2259 | u8 reserved_at_2[0xd]; |
e281682b SM |
2260 | u8 small_fence_on_rdma_read_response[0x1]; |
2261 | u8 umr_en[0x1]; | |
2262 | u8 a[0x1]; | |
2263 | u8 rw[0x1]; | |
2264 | u8 rr[0x1]; | |
2265 | u8 lw[0x1]; | |
2266 | u8 lr[0x1]; | |
2267 | u8 access_mode[0x2]; | |
b4ff3a36 | 2268 | u8 reserved_at_18[0x8]; |
e281682b SM |
2269 | |
2270 | u8 qpn[0x18]; | |
2271 | u8 mkey_7_0[0x8]; | |
2272 | ||
b4ff3a36 | 2273 | u8 reserved_at_40[0x20]; |
e281682b SM |
2274 | |
2275 | u8 length64[0x1]; | |
2276 | u8 bsf_en[0x1]; | |
2277 | u8 sync_umr[0x1]; | |
b4ff3a36 | 2278 | u8 reserved_at_63[0x2]; |
e281682b | 2279 | u8 expected_sigerr_count[0x1]; |
b4ff3a36 | 2280 | u8 reserved_at_66[0x1]; |
e281682b SM |
2281 | u8 en_rinval[0x1]; |
2282 | u8 pd[0x18]; | |
2283 | ||
2284 | u8 start_addr[0x40]; | |
2285 | ||
2286 | u8 len[0x40]; | |
2287 | ||
2288 | u8 bsf_octword_size[0x20]; | |
2289 | ||
b4ff3a36 | 2290 | u8 reserved_at_120[0x80]; |
e281682b SM |
2291 | |
2292 | u8 translations_octword_size[0x20]; | |
2293 | ||
b4ff3a36 | 2294 | u8 reserved_at_1c0[0x1b]; |
e281682b SM |
2295 | u8 log_page_size[0x5]; |
2296 | ||
b4ff3a36 | 2297 | u8 reserved_at_1e0[0x20]; |
e281682b SM |
2298 | }; |
2299 | ||
2300 | struct mlx5_ifc_pkey_bits { | |
b4ff3a36 | 2301 | u8 reserved_at_0[0x10]; |
e281682b SM |
2302 | u8 pkey[0x10]; |
2303 | }; | |
2304 | ||
2305 | struct mlx5_ifc_array128_auto_bits { | |
2306 | u8 array128_auto[16][0x8]; | |
2307 | }; | |
2308 | ||
2309 | struct mlx5_ifc_hca_vport_context_bits { | |
2310 | u8 field_select[0x20]; | |
2311 | ||
b4ff3a36 | 2312 | u8 reserved_at_20[0xe0]; |
e281682b SM |
2313 | |
2314 | u8 sm_virt_aware[0x1]; | |
2315 | u8 has_smi[0x1]; | |
2316 | u8 has_raw[0x1]; | |
2317 | u8 grh_required[0x1]; | |
b4ff3a36 | 2318 | u8 reserved_at_104[0xc]; |
707c4602 MD |
2319 | u8 port_physical_state[0x4]; |
2320 | u8 vport_state_policy[0x4]; | |
2321 | u8 port_state[0x4]; | |
e281682b SM |
2322 | u8 vport_state[0x4]; |
2323 | ||
b4ff3a36 | 2324 | u8 reserved_at_120[0x20]; |
707c4602 MD |
2325 | |
2326 | u8 system_image_guid[0x40]; | |
e281682b SM |
2327 | |
2328 | u8 port_guid[0x40]; | |
2329 | ||
2330 | u8 node_guid[0x40]; | |
2331 | ||
2332 | u8 cap_mask1[0x20]; | |
2333 | ||
2334 | u8 cap_mask1_field_select[0x20]; | |
2335 | ||
2336 | u8 cap_mask2[0x20]; | |
2337 | ||
2338 | u8 cap_mask2_field_select[0x20]; | |
2339 | ||
b4ff3a36 | 2340 | u8 reserved_at_280[0x80]; |
e281682b SM |
2341 | |
2342 | u8 lid[0x10]; | |
b4ff3a36 | 2343 | u8 reserved_at_310[0x4]; |
e281682b SM |
2344 | u8 init_type_reply[0x4]; |
2345 | u8 lmc[0x3]; | |
2346 | u8 subnet_timeout[0x5]; | |
2347 | ||
2348 | u8 sm_lid[0x10]; | |
2349 | u8 sm_sl[0x4]; | |
b4ff3a36 | 2350 | u8 reserved_at_334[0xc]; |
e281682b SM |
2351 | |
2352 | u8 qkey_violation_counter[0x10]; | |
2353 | u8 pkey_violation_counter[0x10]; | |
2354 | ||
b4ff3a36 | 2355 | u8 reserved_at_360[0xca0]; |
e281682b SM |
2356 | }; |
2357 | ||
d6666753 | 2358 | struct mlx5_ifc_esw_vport_context_bits { |
b4ff3a36 | 2359 | u8 reserved_at_0[0x3]; |
d6666753 SM |
2360 | u8 vport_svlan_strip[0x1]; |
2361 | u8 vport_cvlan_strip[0x1]; | |
2362 | u8 vport_svlan_insert[0x1]; | |
2363 | u8 vport_cvlan_insert[0x2]; | |
b4ff3a36 | 2364 | u8 reserved_at_8[0x18]; |
d6666753 | 2365 | |
b4ff3a36 | 2366 | u8 reserved_at_20[0x20]; |
d6666753 SM |
2367 | |
2368 | u8 svlan_cfi[0x1]; | |
2369 | u8 svlan_pcp[0x3]; | |
2370 | u8 svlan_id[0xc]; | |
2371 | u8 cvlan_cfi[0x1]; | |
2372 | u8 cvlan_pcp[0x3]; | |
2373 | u8 cvlan_id[0xc]; | |
2374 | ||
b4ff3a36 | 2375 | u8 reserved_at_60[0x7a0]; |
d6666753 SM |
2376 | }; |
2377 | ||
e281682b SM |
2378 | enum { |
2379 | MLX5_EQC_STATUS_OK = 0x0, | |
2380 | MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, | |
2381 | }; | |
2382 | ||
2383 | enum { | |
2384 | MLX5_EQC_ST_ARMED = 0x9, | |
2385 | MLX5_EQC_ST_FIRED = 0xa, | |
2386 | }; | |
2387 | ||
2388 | struct mlx5_ifc_eqc_bits { | |
2389 | u8 status[0x4]; | |
b4ff3a36 | 2390 | u8 reserved_at_4[0x9]; |
e281682b SM |
2391 | u8 ec[0x1]; |
2392 | u8 oi[0x1]; | |
b4ff3a36 | 2393 | u8 reserved_at_f[0x5]; |
e281682b | 2394 | u8 st[0x4]; |
b4ff3a36 | 2395 | u8 reserved_at_18[0x8]; |
e281682b | 2396 | |
b4ff3a36 | 2397 | u8 reserved_at_20[0x20]; |
e281682b | 2398 | |
b4ff3a36 | 2399 | u8 reserved_at_40[0x14]; |
e281682b | 2400 | u8 page_offset[0x6]; |
b4ff3a36 | 2401 | u8 reserved_at_5a[0x6]; |
e281682b | 2402 | |
b4ff3a36 | 2403 | u8 reserved_at_60[0x3]; |
e281682b SM |
2404 | u8 log_eq_size[0x5]; |
2405 | u8 uar_page[0x18]; | |
2406 | ||
b4ff3a36 | 2407 | u8 reserved_at_80[0x20]; |
e281682b | 2408 | |
b4ff3a36 | 2409 | u8 reserved_at_a0[0x18]; |
e281682b SM |
2410 | u8 intr[0x8]; |
2411 | ||
b4ff3a36 | 2412 | u8 reserved_at_c0[0x3]; |
e281682b | 2413 | u8 log_page_size[0x5]; |
b4ff3a36 | 2414 | u8 reserved_at_c8[0x18]; |
e281682b | 2415 | |
b4ff3a36 | 2416 | u8 reserved_at_e0[0x60]; |
e281682b | 2417 | |
b4ff3a36 | 2418 | u8 reserved_at_140[0x8]; |
e281682b SM |
2419 | u8 consumer_counter[0x18]; |
2420 | ||
b4ff3a36 | 2421 | u8 reserved_at_160[0x8]; |
e281682b SM |
2422 | u8 producer_counter[0x18]; |
2423 | ||
b4ff3a36 | 2424 | u8 reserved_at_180[0x80]; |
e281682b SM |
2425 | }; |
2426 | ||
2427 | enum { | |
2428 | MLX5_DCTC_STATE_ACTIVE = 0x0, | |
2429 | MLX5_DCTC_STATE_DRAINING = 0x1, | |
2430 | MLX5_DCTC_STATE_DRAINED = 0x2, | |
2431 | }; | |
2432 | ||
2433 | enum { | |
2434 | MLX5_DCTC_CS_RES_DISABLE = 0x0, | |
2435 | MLX5_DCTC_CS_RES_NA = 0x1, | |
2436 | MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, | |
2437 | }; | |
2438 | ||
2439 | enum { | |
2440 | MLX5_DCTC_MTU_256_BYTES = 0x1, | |
2441 | MLX5_DCTC_MTU_512_BYTES = 0x2, | |
2442 | MLX5_DCTC_MTU_1K_BYTES = 0x3, | |
2443 | MLX5_DCTC_MTU_2K_BYTES = 0x4, | |
2444 | MLX5_DCTC_MTU_4K_BYTES = 0x5, | |
2445 | }; | |
2446 | ||
2447 | struct mlx5_ifc_dctc_bits { | |
b4ff3a36 | 2448 | u8 reserved_at_0[0x4]; |
e281682b | 2449 | u8 state[0x4]; |
b4ff3a36 | 2450 | u8 reserved_at_8[0x18]; |
e281682b | 2451 | |
b4ff3a36 | 2452 | u8 reserved_at_20[0x8]; |
e281682b SM |
2453 | u8 user_index[0x18]; |
2454 | ||
b4ff3a36 | 2455 | u8 reserved_at_40[0x8]; |
e281682b SM |
2456 | u8 cqn[0x18]; |
2457 | ||
2458 | u8 counter_set_id[0x8]; | |
2459 | u8 atomic_mode[0x4]; | |
2460 | u8 rre[0x1]; | |
2461 | u8 rwe[0x1]; | |
2462 | u8 rae[0x1]; | |
2463 | u8 atomic_like_write_en[0x1]; | |
2464 | u8 latency_sensitive[0x1]; | |
2465 | u8 rlky[0x1]; | |
2466 | u8 free_ar[0x1]; | |
b4ff3a36 | 2467 | u8 reserved_at_73[0xd]; |
e281682b | 2468 | |
b4ff3a36 | 2469 | u8 reserved_at_80[0x8]; |
e281682b | 2470 | u8 cs_res[0x8]; |
b4ff3a36 | 2471 | u8 reserved_at_90[0x3]; |
e281682b | 2472 | u8 min_rnr_nak[0x5]; |
b4ff3a36 | 2473 | u8 reserved_at_98[0x8]; |
e281682b | 2474 | |
b4ff3a36 | 2475 | u8 reserved_at_a0[0x8]; |
e281682b SM |
2476 | u8 srqn[0x18]; |
2477 | ||
b4ff3a36 | 2478 | u8 reserved_at_c0[0x8]; |
e281682b SM |
2479 | u8 pd[0x18]; |
2480 | ||
2481 | u8 tclass[0x8]; | |
b4ff3a36 | 2482 | u8 reserved_at_e8[0x4]; |
e281682b SM |
2483 | u8 flow_label[0x14]; |
2484 | ||
2485 | u8 dc_access_key[0x40]; | |
2486 | ||
b4ff3a36 | 2487 | u8 reserved_at_140[0x5]; |
e281682b SM |
2488 | u8 mtu[0x3]; |
2489 | u8 port[0x8]; | |
2490 | u8 pkey_index[0x10]; | |
2491 | ||
b4ff3a36 | 2492 | u8 reserved_at_160[0x8]; |
e281682b | 2493 | u8 my_addr_index[0x8]; |
b4ff3a36 | 2494 | u8 reserved_at_170[0x8]; |
e281682b SM |
2495 | u8 hop_limit[0x8]; |
2496 | ||
2497 | u8 dc_access_key_violation_count[0x20]; | |
2498 | ||
b4ff3a36 | 2499 | u8 reserved_at_1a0[0x14]; |
e281682b SM |
2500 | u8 dei_cfi[0x1]; |
2501 | u8 eth_prio[0x3]; | |
2502 | u8 ecn[0x2]; | |
2503 | u8 dscp[0x6]; | |
2504 | ||
b4ff3a36 | 2505 | u8 reserved_at_1c0[0x40]; |
e281682b SM |
2506 | }; |
2507 | ||
2508 | enum { | |
2509 | MLX5_CQC_STATUS_OK = 0x0, | |
2510 | MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, | |
2511 | MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, | |
2512 | }; | |
2513 | ||
2514 | enum { | |
2515 | MLX5_CQC_CQE_SZ_64_BYTES = 0x0, | |
2516 | MLX5_CQC_CQE_SZ_128_BYTES = 0x1, | |
2517 | }; | |
2518 | ||
2519 | enum { | |
2520 | MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, | |
2521 | MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, | |
2522 | MLX5_CQC_ST_FIRED = 0xa, | |
2523 | }; | |
2524 | ||
2525 | struct mlx5_ifc_cqc_bits { | |
2526 | u8 status[0x4]; | |
b4ff3a36 | 2527 | u8 reserved_at_4[0x4]; |
e281682b SM |
2528 | u8 cqe_sz[0x3]; |
2529 | u8 cc[0x1]; | |
b4ff3a36 | 2530 | u8 reserved_at_c[0x1]; |
e281682b SM |
2531 | u8 scqe_break_moderation_en[0x1]; |
2532 | u8 oi[0x1]; | |
b4ff3a36 | 2533 | u8 reserved_at_f[0x2]; |
e281682b SM |
2534 | u8 cqe_zip_en[0x1]; |
2535 | u8 mini_cqe_res_format[0x2]; | |
2536 | u8 st[0x4]; | |
b4ff3a36 | 2537 | u8 reserved_at_18[0x8]; |
e281682b | 2538 | |
b4ff3a36 | 2539 | u8 reserved_at_20[0x20]; |
e281682b | 2540 | |
b4ff3a36 | 2541 | u8 reserved_at_40[0x14]; |
e281682b | 2542 | u8 page_offset[0x6]; |
b4ff3a36 | 2543 | u8 reserved_at_5a[0x6]; |
e281682b | 2544 | |
b4ff3a36 | 2545 | u8 reserved_at_60[0x3]; |
e281682b SM |
2546 | u8 log_cq_size[0x5]; |
2547 | u8 uar_page[0x18]; | |
2548 | ||
b4ff3a36 | 2549 | u8 reserved_at_80[0x4]; |
e281682b SM |
2550 | u8 cq_period[0xc]; |
2551 | u8 cq_max_count[0x10]; | |
2552 | ||
b4ff3a36 | 2553 | u8 reserved_at_a0[0x18]; |
e281682b SM |
2554 | u8 c_eqn[0x8]; |
2555 | ||
b4ff3a36 | 2556 | u8 reserved_at_c0[0x3]; |
e281682b | 2557 | u8 log_page_size[0x5]; |
b4ff3a36 | 2558 | u8 reserved_at_c8[0x18]; |
e281682b | 2559 | |
b4ff3a36 | 2560 | u8 reserved_at_e0[0x20]; |
e281682b | 2561 | |
b4ff3a36 | 2562 | u8 reserved_at_100[0x8]; |
e281682b SM |
2563 | u8 last_notified_index[0x18]; |
2564 | ||
b4ff3a36 | 2565 | u8 reserved_at_120[0x8]; |
e281682b SM |
2566 | u8 last_solicit_index[0x18]; |
2567 | ||
b4ff3a36 | 2568 | u8 reserved_at_140[0x8]; |
e281682b SM |
2569 | u8 consumer_counter[0x18]; |
2570 | ||
b4ff3a36 | 2571 | u8 reserved_at_160[0x8]; |
e281682b SM |
2572 | u8 producer_counter[0x18]; |
2573 | ||
b4ff3a36 | 2574 | u8 reserved_at_180[0x40]; |
e281682b SM |
2575 | |
2576 | u8 dbr_addr[0x40]; | |
2577 | }; | |
2578 | ||
2579 | union mlx5_ifc_cong_control_roce_ecn_auto_bits { | |
2580 | struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; | |
2581 | struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; | |
2582 | struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; | |
b4ff3a36 | 2583 | u8 reserved_at_0[0x800]; |
e281682b SM |
2584 | }; |
2585 | ||
2586 | struct mlx5_ifc_query_adapter_param_block_bits { | |
b4ff3a36 | 2587 | u8 reserved_at_0[0xc0]; |
e281682b | 2588 | |
b4ff3a36 | 2589 | u8 reserved_at_c0[0x8]; |
211e6c80 MD |
2590 | u8 ieee_vendor_id[0x18]; |
2591 | ||
b4ff3a36 | 2592 | u8 reserved_at_e0[0x10]; |
e281682b SM |
2593 | u8 vsd_vendor_id[0x10]; |
2594 | ||
2595 | u8 vsd[208][0x8]; | |
2596 | ||
2597 | u8 vsd_contd_psid[16][0x8]; | |
2598 | }; | |
2599 | ||
2600 | union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { | |
2601 | struct mlx5_ifc_modify_field_select_bits modify_field_select; | |
2602 | struct mlx5_ifc_resize_field_select_bits resize_field_select; | |
b4ff3a36 | 2603 | u8 reserved_at_0[0x20]; |
e281682b SM |
2604 | }; |
2605 | ||
2606 | union mlx5_ifc_field_select_802_1_r_roce_auto_bits { | |
2607 | struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; | |
2608 | struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; | |
2609 | struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; | |
b4ff3a36 | 2610 | u8 reserved_at_0[0x20]; |
e281682b SM |
2611 | }; |
2612 | ||
2613 | union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { | |
2614 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; | |
2615 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; | |
2616 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; | |
2617 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; | |
2618 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; | |
2619 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; | |
2620 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; | |
2621 | struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; | |
b4ff3a36 | 2622 | u8 reserved_at_0[0x7c0]; |
e281682b SM |
2623 | }; |
2624 | ||
2625 | union mlx5_ifc_event_auto_bits { | |
2626 | struct mlx5_ifc_comp_event_bits comp_event; | |
2627 | struct mlx5_ifc_dct_events_bits dct_events; | |
2628 | struct mlx5_ifc_qp_events_bits qp_events; | |
2629 | struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; | |
2630 | struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; | |
2631 | struct mlx5_ifc_cq_error_bits cq_error; | |
2632 | struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; | |
2633 | struct mlx5_ifc_port_state_change_event_bits port_state_change_event; | |
2634 | struct mlx5_ifc_gpio_event_bits gpio_event; | |
2635 | struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; | |
2636 | struct mlx5_ifc_stall_vl_event_bits stall_vl_event; | |
2637 | struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; | |
b4ff3a36 | 2638 | u8 reserved_at_0[0xe0]; |
e281682b SM |
2639 | }; |
2640 | ||
2641 | struct mlx5_ifc_health_buffer_bits { | |
b4ff3a36 | 2642 | u8 reserved_at_0[0x100]; |
e281682b SM |
2643 | |
2644 | u8 assert_existptr[0x20]; | |
2645 | ||
2646 | u8 assert_callra[0x20]; | |
2647 | ||
b4ff3a36 | 2648 | u8 reserved_at_140[0x40]; |
e281682b SM |
2649 | |
2650 | u8 fw_version[0x20]; | |
2651 | ||
2652 | u8 hw_id[0x20]; | |
2653 | ||
b4ff3a36 | 2654 | u8 reserved_at_1c0[0x20]; |
e281682b SM |
2655 | |
2656 | u8 irisc_index[0x8]; | |
2657 | u8 synd[0x8]; | |
2658 | u8 ext_synd[0x10]; | |
2659 | }; | |
2660 | ||
2661 | struct mlx5_ifc_register_loopback_control_bits { | |
2662 | u8 no_lb[0x1]; | |
b4ff3a36 | 2663 | u8 reserved_at_1[0x7]; |
e281682b | 2664 | u8 port[0x8]; |
b4ff3a36 | 2665 | u8 reserved_at_10[0x10]; |
e281682b | 2666 | |
b4ff3a36 | 2667 | u8 reserved_at_20[0x60]; |
e281682b SM |
2668 | }; |
2669 | ||
2670 | struct mlx5_ifc_teardown_hca_out_bits { | |
2671 | u8 status[0x8]; | |
b4ff3a36 | 2672 | u8 reserved_at_8[0x18]; |
e281682b SM |
2673 | |
2674 | u8 syndrome[0x20]; | |
2675 | ||
b4ff3a36 | 2676 | u8 reserved_at_40[0x40]; |
e281682b SM |
2677 | }; |
2678 | ||
2679 | enum { | |
2680 | MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, | |
2681 | MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, | |
2682 | }; | |
2683 | ||
2684 | struct mlx5_ifc_teardown_hca_in_bits { | |
2685 | u8 opcode[0x10]; | |
b4ff3a36 | 2686 | u8 reserved_at_10[0x10]; |
e281682b | 2687 | |
b4ff3a36 | 2688 | u8 reserved_at_20[0x10]; |
e281682b SM |
2689 | u8 op_mod[0x10]; |
2690 | ||
b4ff3a36 | 2691 | u8 reserved_at_40[0x10]; |
e281682b SM |
2692 | u8 profile[0x10]; |
2693 | ||
b4ff3a36 | 2694 | u8 reserved_at_60[0x20]; |
e281682b SM |
2695 | }; |
2696 | ||
2697 | struct mlx5_ifc_sqerr2rts_qp_out_bits { | |
2698 | u8 status[0x8]; | |
b4ff3a36 | 2699 | u8 reserved_at_8[0x18]; |
e281682b SM |
2700 | |
2701 | u8 syndrome[0x20]; | |
2702 | ||
b4ff3a36 | 2703 | u8 reserved_at_40[0x40]; |
e281682b SM |
2704 | }; |
2705 | ||
2706 | struct mlx5_ifc_sqerr2rts_qp_in_bits { | |
2707 | u8 opcode[0x10]; | |
b4ff3a36 | 2708 | u8 reserved_at_10[0x10]; |
e281682b | 2709 | |
b4ff3a36 | 2710 | u8 reserved_at_20[0x10]; |
e281682b SM |
2711 | u8 op_mod[0x10]; |
2712 | ||
b4ff3a36 | 2713 | u8 reserved_at_40[0x8]; |
e281682b SM |
2714 | u8 qpn[0x18]; |
2715 | ||
b4ff3a36 | 2716 | u8 reserved_at_60[0x20]; |
e281682b SM |
2717 | |
2718 | u8 opt_param_mask[0x20]; | |
2719 | ||
b4ff3a36 | 2720 | u8 reserved_at_a0[0x20]; |
e281682b SM |
2721 | |
2722 | struct mlx5_ifc_qpc_bits qpc; | |
2723 | ||
b4ff3a36 | 2724 | u8 reserved_at_800[0x80]; |
e281682b SM |
2725 | }; |
2726 | ||
2727 | struct mlx5_ifc_sqd2rts_qp_out_bits { | |
2728 | u8 status[0x8]; | |
b4ff3a36 | 2729 | u8 reserved_at_8[0x18]; |
e281682b SM |
2730 | |
2731 | u8 syndrome[0x20]; | |
2732 | ||
b4ff3a36 | 2733 | u8 reserved_at_40[0x40]; |
e281682b SM |
2734 | }; |
2735 | ||
2736 | struct mlx5_ifc_sqd2rts_qp_in_bits { | |
2737 | u8 opcode[0x10]; | |
b4ff3a36 | 2738 | u8 reserved_at_10[0x10]; |
e281682b | 2739 | |
b4ff3a36 | 2740 | u8 reserved_at_20[0x10]; |
e281682b SM |
2741 | u8 op_mod[0x10]; |
2742 | ||
b4ff3a36 | 2743 | u8 reserved_at_40[0x8]; |
e281682b SM |
2744 | u8 qpn[0x18]; |
2745 | ||
b4ff3a36 | 2746 | u8 reserved_at_60[0x20]; |
e281682b SM |
2747 | |
2748 | u8 opt_param_mask[0x20]; | |
2749 | ||
b4ff3a36 | 2750 | u8 reserved_at_a0[0x20]; |
e281682b SM |
2751 | |
2752 | struct mlx5_ifc_qpc_bits qpc; | |
2753 | ||
b4ff3a36 | 2754 | u8 reserved_at_800[0x80]; |
e281682b SM |
2755 | }; |
2756 | ||
2757 | struct mlx5_ifc_set_roce_address_out_bits { | |
2758 | u8 status[0x8]; | |
b4ff3a36 | 2759 | u8 reserved_at_8[0x18]; |
e281682b SM |
2760 | |
2761 | u8 syndrome[0x20]; | |
2762 | ||
b4ff3a36 | 2763 | u8 reserved_at_40[0x40]; |
e281682b SM |
2764 | }; |
2765 | ||
2766 | struct mlx5_ifc_set_roce_address_in_bits { | |
2767 | u8 opcode[0x10]; | |
b4ff3a36 | 2768 | u8 reserved_at_10[0x10]; |
e281682b | 2769 | |
b4ff3a36 | 2770 | u8 reserved_at_20[0x10]; |
e281682b SM |
2771 | u8 op_mod[0x10]; |
2772 | ||
2773 | u8 roce_address_index[0x10]; | |
b4ff3a36 | 2774 | u8 reserved_at_50[0x10]; |
e281682b | 2775 | |
b4ff3a36 | 2776 | u8 reserved_at_60[0x20]; |
e281682b SM |
2777 | |
2778 | struct mlx5_ifc_roce_addr_layout_bits roce_address; | |
2779 | }; | |
2780 | ||
2781 | struct mlx5_ifc_set_mad_demux_out_bits { | |
2782 | u8 status[0x8]; | |
b4ff3a36 | 2783 | u8 reserved_at_8[0x18]; |
e281682b SM |
2784 | |
2785 | u8 syndrome[0x20]; | |
2786 | ||
b4ff3a36 | 2787 | u8 reserved_at_40[0x40]; |
e281682b SM |
2788 | }; |
2789 | ||
2790 | enum { | |
2791 | MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, | |
2792 | MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, | |
2793 | }; | |
2794 | ||
2795 | struct mlx5_ifc_set_mad_demux_in_bits { | |
2796 | u8 opcode[0x10]; | |
b4ff3a36 | 2797 | u8 reserved_at_10[0x10]; |
e281682b | 2798 | |
b4ff3a36 | 2799 | u8 reserved_at_20[0x10]; |
e281682b SM |
2800 | u8 op_mod[0x10]; |
2801 | ||
b4ff3a36 | 2802 | u8 reserved_at_40[0x20]; |
e281682b | 2803 | |
b4ff3a36 | 2804 | u8 reserved_at_60[0x6]; |
e281682b | 2805 | u8 demux_mode[0x2]; |
b4ff3a36 | 2806 | u8 reserved_at_68[0x18]; |
e281682b SM |
2807 | }; |
2808 | ||
2809 | struct mlx5_ifc_set_l2_table_entry_out_bits { | |
2810 | u8 status[0x8]; | |
b4ff3a36 | 2811 | u8 reserved_at_8[0x18]; |
e281682b SM |
2812 | |
2813 | u8 syndrome[0x20]; | |
2814 | ||
b4ff3a36 | 2815 | u8 reserved_at_40[0x40]; |
e281682b SM |
2816 | }; |
2817 | ||
2818 | struct mlx5_ifc_set_l2_table_entry_in_bits { | |
2819 | u8 opcode[0x10]; | |
b4ff3a36 | 2820 | u8 reserved_at_10[0x10]; |
e281682b | 2821 | |
b4ff3a36 | 2822 | u8 reserved_at_20[0x10]; |
e281682b SM |
2823 | u8 op_mod[0x10]; |
2824 | ||
b4ff3a36 | 2825 | u8 reserved_at_40[0x60]; |
e281682b | 2826 | |
b4ff3a36 | 2827 | u8 reserved_at_a0[0x8]; |
e281682b SM |
2828 | u8 table_index[0x18]; |
2829 | ||
b4ff3a36 | 2830 | u8 reserved_at_c0[0x20]; |
e281682b | 2831 | |
b4ff3a36 | 2832 | u8 reserved_at_e0[0x13]; |
e281682b SM |
2833 | u8 vlan_valid[0x1]; |
2834 | u8 vlan[0xc]; | |
2835 | ||
2836 | struct mlx5_ifc_mac_address_layout_bits mac_address; | |
2837 | ||
b4ff3a36 | 2838 | u8 reserved_at_140[0xc0]; |
e281682b SM |
2839 | }; |
2840 | ||
2841 | struct mlx5_ifc_set_issi_out_bits { | |
2842 | u8 status[0x8]; | |
b4ff3a36 | 2843 | u8 reserved_at_8[0x18]; |
e281682b SM |
2844 | |
2845 | u8 syndrome[0x20]; | |
2846 | ||
b4ff3a36 | 2847 | u8 reserved_at_40[0x40]; |
e281682b SM |
2848 | }; |
2849 | ||
2850 | struct mlx5_ifc_set_issi_in_bits { | |
2851 | u8 opcode[0x10]; | |
b4ff3a36 | 2852 | u8 reserved_at_10[0x10]; |
e281682b | 2853 | |
b4ff3a36 | 2854 | u8 reserved_at_20[0x10]; |
e281682b SM |
2855 | u8 op_mod[0x10]; |
2856 | ||
b4ff3a36 | 2857 | u8 reserved_at_40[0x10]; |
e281682b SM |
2858 | u8 current_issi[0x10]; |
2859 | ||
b4ff3a36 | 2860 | u8 reserved_at_60[0x20]; |
e281682b SM |
2861 | }; |
2862 | ||
2863 | struct mlx5_ifc_set_hca_cap_out_bits { | |
2864 | u8 status[0x8]; | |
b4ff3a36 | 2865 | u8 reserved_at_8[0x18]; |
e281682b SM |
2866 | |
2867 | u8 syndrome[0x20]; | |
2868 | ||
b4ff3a36 | 2869 | u8 reserved_at_40[0x40]; |
e281682b SM |
2870 | }; |
2871 | ||
2872 | struct mlx5_ifc_set_hca_cap_in_bits { | |
2873 | u8 opcode[0x10]; | |
b4ff3a36 | 2874 | u8 reserved_at_10[0x10]; |
e281682b | 2875 | |
b4ff3a36 | 2876 | u8 reserved_at_20[0x10]; |
e281682b SM |
2877 | u8 op_mod[0x10]; |
2878 | ||
b4ff3a36 | 2879 | u8 reserved_at_40[0x40]; |
e281682b SM |
2880 | |
2881 | union mlx5_ifc_hca_cap_union_bits capability; | |
2882 | }; | |
2883 | ||
26a81453 MG |
2884 | enum { |
2885 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, | |
2886 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, | |
2887 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, | |
2888 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 | |
2889 | }; | |
2890 | ||
e281682b SM |
2891 | struct mlx5_ifc_set_fte_out_bits { |
2892 | u8 status[0x8]; | |
b4ff3a36 | 2893 | u8 reserved_at_8[0x18]; |
e281682b SM |
2894 | |
2895 | u8 syndrome[0x20]; | |
2896 | ||
b4ff3a36 | 2897 | u8 reserved_at_40[0x40]; |
e281682b SM |
2898 | }; |
2899 | ||
2900 | struct mlx5_ifc_set_fte_in_bits { | |
2901 | u8 opcode[0x10]; | |
b4ff3a36 | 2902 | u8 reserved_at_10[0x10]; |
e281682b | 2903 | |
b4ff3a36 | 2904 | u8 reserved_at_20[0x10]; |
e281682b SM |
2905 | u8 op_mod[0x10]; |
2906 | ||
b4ff3a36 | 2907 | u8 reserved_at_40[0x40]; |
e281682b SM |
2908 | |
2909 | u8 table_type[0x8]; | |
b4ff3a36 | 2910 | u8 reserved_at_88[0x18]; |
e281682b | 2911 | |
b4ff3a36 | 2912 | u8 reserved_at_a0[0x8]; |
e281682b SM |
2913 | u8 table_id[0x18]; |
2914 | ||
b4ff3a36 | 2915 | u8 reserved_at_c0[0x18]; |
26a81453 MG |
2916 | u8 modify_enable_mask[0x8]; |
2917 | ||
b4ff3a36 | 2918 | u8 reserved_at_e0[0x20]; |
e281682b SM |
2919 | |
2920 | u8 flow_index[0x20]; | |
2921 | ||
b4ff3a36 | 2922 | u8 reserved_at_120[0xe0]; |
e281682b SM |
2923 | |
2924 | struct mlx5_ifc_flow_context_bits flow_context; | |
2925 | }; | |
2926 | ||
2927 | struct mlx5_ifc_rts2rts_qp_out_bits { | |
2928 | u8 status[0x8]; | |
b4ff3a36 | 2929 | u8 reserved_at_8[0x18]; |
e281682b SM |
2930 | |
2931 | u8 syndrome[0x20]; | |
2932 | ||
b4ff3a36 | 2933 | u8 reserved_at_40[0x40]; |
e281682b SM |
2934 | }; |
2935 | ||
2936 | struct mlx5_ifc_rts2rts_qp_in_bits { | |
2937 | u8 opcode[0x10]; | |
b4ff3a36 | 2938 | u8 reserved_at_10[0x10]; |
e281682b | 2939 | |
b4ff3a36 | 2940 | u8 reserved_at_20[0x10]; |
e281682b SM |
2941 | u8 op_mod[0x10]; |
2942 | ||
b4ff3a36 | 2943 | u8 reserved_at_40[0x8]; |
e281682b SM |
2944 | u8 qpn[0x18]; |
2945 | ||
b4ff3a36 | 2946 | u8 reserved_at_60[0x20]; |
e281682b SM |
2947 | |
2948 | u8 opt_param_mask[0x20]; | |
2949 | ||
b4ff3a36 | 2950 | u8 reserved_at_a0[0x20]; |
e281682b SM |
2951 | |
2952 | struct mlx5_ifc_qpc_bits qpc; | |
2953 | ||
b4ff3a36 | 2954 | u8 reserved_at_800[0x80]; |
e281682b SM |
2955 | }; |
2956 | ||
2957 | struct mlx5_ifc_rtr2rts_qp_out_bits { | |
2958 | u8 status[0x8]; | |
b4ff3a36 | 2959 | u8 reserved_at_8[0x18]; |
e281682b SM |
2960 | |
2961 | u8 syndrome[0x20]; | |
2962 | ||
b4ff3a36 | 2963 | u8 reserved_at_40[0x40]; |
e281682b SM |
2964 | }; |
2965 | ||
2966 | struct mlx5_ifc_rtr2rts_qp_in_bits { | |
2967 | u8 opcode[0x10]; | |
b4ff3a36 | 2968 | u8 reserved_at_10[0x10]; |
e281682b | 2969 | |
b4ff3a36 | 2970 | u8 reserved_at_20[0x10]; |
e281682b SM |
2971 | u8 op_mod[0x10]; |
2972 | ||
b4ff3a36 | 2973 | u8 reserved_at_40[0x8]; |
e281682b SM |
2974 | u8 qpn[0x18]; |
2975 | ||
b4ff3a36 | 2976 | u8 reserved_at_60[0x20]; |
e281682b SM |
2977 | |
2978 | u8 opt_param_mask[0x20]; | |
2979 | ||
b4ff3a36 | 2980 | u8 reserved_at_a0[0x20]; |
e281682b SM |
2981 | |
2982 | struct mlx5_ifc_qpc_bits qpc; | |
2983 | ||
b4ff3a36 | 2984 | u8 reserved_at_800[0x80]; |
e281682b SM |
2985 | }; |
2986 | ||
2987 | struct mlx5_ifc_rst2init_qp_out_bits { | |
2988 | u8 status[0x8]; | |
b4ff3a36 | 2989 | u8 reserved_at_8[0x18]; |
e281682b SM |
2990 | |
2991 | u8 syndrome[0x20]; | |
2992 | ||
b4ff3a36 | 2993 | u8 reserved_at_40[0x40]; |
e281682b SM |
2994 | }; |
2995 | ||
2996 | struct mlx5_ifc_rst2init_qp_in_bits { | |
2997 | u8 opcode[0x10]; | |
b4ff3a36 | 2998 | u8 reserved_at_10[0x10]; |
e281682b | 2999 | |
b4ff3a36 | 3000 | u8 reserved_at_20[0x10]; |
e281682b SM |
3001 | u8 op_mod[0x10]; |
3002 | ||
b4ff3a36 | 3003 | u8 reserved_at_40[0x8]; |
e281682b SM |
3004 | u8 qpn[0x18]; |
3005 | ||
b4ff3a36 | 3006 | u8 reserved_at_60[0x20]; |
e281682b SM |
3007 | |
3008 | u8 opt_param_mask[0x20]; | |
3009 | ||
b4ff3a36 | 3010 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3011 | |
3012 | struct mlx5_ifc_qpc_bits qpc; | |
3013 | ||
b4ff3a36 | 3014 | u8 reserved_at_800[0x80]; |
e281682b SM |
3015 | }; |
3016 | ||
3017 | struct mlx5_ifc_query_xrc_srq_out_bits { | |
3018 | u8 status[0x8]; | |
b4ff3a36 | 3019 | u8 reserved_at_8[0x18]; |
e281682b SM |
3020 | |
3021 | u8 syndrome[0x20]; | |
3022 | ||
b4ff3a36 | 3023 | u8 reserved_at_40[0x40]; |
e281682b SM |
3024 | |
3025 | struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | |
3026 | ||
b4ff3a36 | 3027 | u8 reserved_at_280[0x600]; |
e281682b SM |
3028 | |
3029 | u8 pas[0][0x40]; | |
3030 | }; | |
3031 | ||
3032 | struct mlx5_ifc_query_xrc_srq_in_bits { | |
3033 | u8 opcode[0x10]; | |
b4ff3a36 | 3034 | u8 reserved_at_10[0x10]; |
e281682b | 3035 | |
b4ff3a36 | 3036 | u8 reserved_at_20[0x10]; |
e281682b SM |
3037 | u8 op_mod[0x10]; |
3038 | ||
b4ff3a36 | 3039 | u8 reserved_at_40[0x8]; |
e281682b SM |
3040 | u8 xrc_srqn[0x18]; |
3041 | ||
b4ff3a36 | 3042 | u8 reserved_at_60[0x20]; |
e281682b SM |
3043 | }; |
3044 | ||
3045 | enum { | |
3046 | MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, | |
3047 | MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, | |
3048 | }; | |
3049 | ||
3050 | struct mlx5_ifc_query_vport_state_out_bits { | |
3051 | u8 status[0x8]; | |
b4ff3a36 | 3052 | u8 reserved_at_8[0x18]; |
e281682b SM |
3053 | |
3054 | u8 syndrome[0x20]; | |
3055 | ||
b4ff3a36 | 3056 | u8 reserved_at_40[0x20]; |
e281682b | 3057 | |
b4ff3a36 | 3058 | u8 reserved_at_60[0x18]; |
e281682b SM |
3059 | u8 admin_state[0x4]; |
3060 | u8 state[0x4]; | |
3061 | }; | |
3062 | ||
3063 | enum { | |
3064 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, | |
e7546514 | 3065 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, |
e281682b SM |
3066 | }; |
3067 | ||
3068 | struct mlx5_ifc_query_vport_state_in_bits { | |
3069 | u8 opcode[0x10]; | |
b4ff3a36 | 3070 | u8 reserved_at_10[0x10]; |
e281682b | 3071 | |
b4ff3a36 | 3072 | u8 reserved_at_20[0x10]; |
e281682b SM |
3073 | u8 op_mod[0x10]; |
3074 | ||
3075 | u8 other_vport[0x1]; | |
b4ff3a36 | 3076 | u8 reserved_at_41[0xf]; |
e281682b SM |
3077 | u8 vport_number[0x10]; |
3078 | ||
b4ff3a36 | 3079 | u8 reserved_at_60[0x20]; |
e281682b SM |
3080 | }; |
3081 | ||
3082 | struct mlx5_ifc_query_vport_counter_out_bits { | |
3083 | u8 status[0x8]; | |
b4ff3a36 | 3084 | u8 reserved_at_8[0x18]; |
e281682b SM |
3085 | |
3086 | u8 syndrome[0x20]; | |
3087 | ||
b4ff3a36 | 3088 | u8 reserved_at_40[0x40]; |
e281682b SM |
3089 | |
3090 | struct mlx5_ifc_traffic_counter_bits received_errors; | |
3091 | ||
3092 | struct mlx5_ifc_traffic_counter_bits transmit_errors; | |
3093 | ||
3094 | struct mlx5_ifc_traffic_counter_bits received_ib_unicast; | |
3095 | ||
3096 | struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; | |
3097 | ||
3098 | struct mlx5_ifc_traffic_counter_bits received_ib_multicast; | |
3099 | ||
3100 | struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; | |
3101 | ||
3102 | struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; | |
3103 | ||
3104 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; | |
3105 | ||
3106 | struct mlx5_ifc_traffic_counter_bits received_eth_unicast; | |
3107 | ||
3108 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; | |
3109 | ||
3110 | struct mlx5_ifc_traffic_counter_bits received_eth_multicast; | |
3111 | ||
3112 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; | |
3113 | ||
b4ff3a36 | 3114 | u8 reserved_at_680[0xa00]; |
e281682b SM |
3115 | }; |
3116 | ||
3117 | enum { | |
3118 | MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, | |
3119 | }; | |
3120 | ||
3121 | struct mlx5_ifc_query_vport_counter_in_bits { | |
3122 | u8 opcode[0x10]; | |
b4ff3a36 | 3123 | u8 reserved_at_10[0x10]; |
e281682b | 3124 | |
b4ff3a36 | 3125 | u8 reserved_at_20[0x10]; |
e281682b SM |
3126 | u8 op_mod[0x10]; |
3127 | ||
3128 | u8 other_vport[0x1]; | |
b4ff3a36 | 3129 | u8 reserved_at_41[0xf]; |
e281682b SM |
3130 | u8 vport_number[0x10]; |
3131 | ||
b4ff3a36 | 3132 | u8 reserved_at_60[0x60]; |
e281682b SM |
3133 | |
3134 | u8 clear[0x1]; | |
b4ff3a36 | 3135 | u8 reserved_at_c1[0x1f]; |
e281682b | 3136 | |
b4ff3a36 | 3137 | u8 reserved_at_e0[0x20]; |
e281682b SM |
3138 | }; |
3139 | ||
3140 | struct mlx5_ifc_query_tis_out_bits { | |
3141 | u8 status[0x8]; | |
b4ff3a36 | 3142 | u8 reserved_at_8[0x18]; |
e281682b SM |
3143 | |
3144 | u8 syndrome[0x20]; | |
3145 | ||
b4ff3a36 | 3146 | u8 reserved_at_40[0x40]; |
e281682b SM |
3147 | |
3148 | struct mlx5_ifc_tisc_bits tis_context; | |
3149 | }; | |
3150 | ||
3151 | struct mlx5_ifc_query_tis_in_bits { | |
3152 | u8 opcode[0x10]; | |
b4ff3a36 | 3153 | u8 reserved_at_10[0x10]; |
e281682b | 3154 | |
b4ff3a36 | 3155 | u8 reserved_at_20[0x10]; |
e281682b SM |
3156 | u8 op_mod[0x10]; |
3157 | ||
b4ff3a36 | 3158 | u8 reserved_at_40[0x8]; |
e281682b SM |
3159 | u8 tisn[0x18]; |
3160 | ||
b4ff3a36 | 3161 | u8 reserved_at_60[0x20]; |
e281682b SM |
3162 | }; |
3163 | ||
3164 | struct mlx5_ifc_query_tir_out_bits { | |
3165 | u8 status[0x8]; | |
b4ff3a36 | 3166 | u8 reserved_at_8[0x18]; |
e281682b SM |
3167 | |
3168 | u8 syndrome[0x20]; | |
3169 | ||
b4ff3a36 | 3170 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3171 | |
3172 | struct mlx5_ifc_tirc_bits tir_context; | |
3173 | }; | |
3174 | ||
3175 | struct mlx5_ifc_query_tir_in_bits { | |
3176 | u8 opcode[0x10]; | |
b4ff3a36 | 3177 | u8 reserved_at_10[0x10]; |
e281682b | 3178 | |
b4ff3a36 | 3179 | u8 reserved_at_20[0x10]; |
e281682b SM |
3180 | u8 op_mod[0x10]; |
3181 | ||
b4ff3a36 | 3182 | u8 reserved_at_40[0x8]; |
e281682b SM |
3183 | u8 tirn[0x18]; |
3184 | ||
b4ff3a36 | 3185 | u8 reserved_at_60[0x20]; |
e281682b SM |
3186 | }; |
3187 | ||
3188 | struct mlx5_ifc_query_srq_out_bits { | |
3189 | u8 status[0x8]; | |
b4ff3a36 | 3190 | u8 reserved_at_8[0x18]; |
e281682b SM |
3191 | |
3192 | u8 syndrome[0x20]; | |
3193 | ||
b4ff3a36 | 3194 | u8 reserved_at_40[0x40]; |
e281682b SM |
3195 | |
3196 | struct mlx5_ifc_srqc_bits srq_context_entry; | |
3197 | ||
b4ff3a36 | 3198 | u8 reserved_at_280[0x600]; |
e281682b SM |
3199 | |
3200 | u8 pas[0][0x40]; | |
3201 | }; | |
3202 | ||
3203 | struct mlx5_ifc_query_srq_in_bits { | |
3204 | u8 opcode[0x10]; | |
b4ff3a36 | 3205 | u8 reserved_at_10[0x10]; |
e281682b | 3206 | |
b4ff3a36 | 3207 | u8 reserved_at_20[0x10]; |
e281682b SM |
3208 | u8 op_mod[0x10]; |
3209 | ||
b4ff3a36 | 3210 | u8 reserved_at_40[0x8]; |
e281682b SM |
3211 | u8 srqn[0x18]; |
3212 | ||
b4ff3a36 | 3213 | u8 reserved_at_60[0x20]; |
e281682b SM |
3214 | }; |
3215 | ||
3216 | struct mlx5_ifc_query_sq_out_bits { | |
3217 | u8 status[0x8]; | |
b4ff3a36 | 3218 | u8 reserved_at_8[0x18]; |
e281682b SM |
3219 | |
3220 | u8 syndrome[0x20]; | |
3221 | ||
b4ff3a36 | 3222 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3223 | |
3224 | struct mlx5_ifc_sqc_bits sq_context; | |
3225 | }; | |
3226 | ||
3227 | struct mlx5_ifc_query_sq_in_bits { | |
3228 | u8 opcode[0x10]; | |
b4ff3a36 | 3229 | u8 reserved_at_10[0x10]; |
e281682b | 3230 | |
b4ff3a36 | 3231 | u8 reserved_at_20[0x10]; |
e281682b SM |
3232 | u8 op_mod[0x10]; |
3233 | ||
b4ff3a36 | 3234 | u8 reserved_at_40[0x8]; |
e281682b SM |
3235 | u8 sqn[0x18]; |
3236 | ||
b4ff3a36 | 3237 | u8 reserved_at_60[0x20]; |
e281682b SM |
3238 | }; |
3239 | ||
3240 | struct mlx5_ifc_query_special_contexts_out_bits { | |
3241 | u8 status[0x8]; | |
b4ff3a36 | 3242 | u8 reserved_at_8[0x18]; |
e281682b SM |
3243 | |
3244 | u8 syndrome[0x20]; | |
3245 | ||
b4ff3a36 | 3246 | u8 reserved_at_40[0x20]; |
e281682b SM |
3247 | |
3248 | u8 resd_lkey[0x20]; | |
3249 | }; | |
3250 | ||
3251 | struct mlx5_ifc_query_special_contexts_in_bits { | |
3252 | u8 opcode[0x10]; | |
b4ff3a36 | 3253 | u8 reserved_at_10[0x10]; |
e281682b | 3254 | |
b4ff3a36 | 3255 | u8 reserved_at_20[0x10]; |
e281682b SM |
3256 | u8 op_mod[0x10]; |
3257 | ||
b4ff3a36 | 3258 | u8 reserved_at_40[0x40]; |
e281682b SM |
3259 | }; |
3260 | ||
3261 | struct mlx5_ifc_query_rqt_out_bits { | |
3262 | u8 status[0x8]; | |
b4ff3a36 | 3263 | u8 reserved_at_8[0x18]; |
e281682b SM |
3264 | |
3265 | u8 syndrome[0x20]; | |
3266 | ||
b4ff3a36 | 3267 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3268 | |
3269 | struct mlx5_ifc_rqtc_bits rqt_context; | |
3270 | }; | |
3271 | ||
3272 | struct mlx5_ifc_query_rqt_in_bits { | |
3273 | u8 opcode[0x10]; | |
b4ff3a36 | 3274 | u8 reserved_at_10[0x10]; |
e281682b | 3275 | |
b4ff3a36 | 3276 | u8 reserved_at_20[0x10]; |
e281682b SM |
3277 | u8 op_mod[0x10]; |
3278 | ||
b4ff3a36 | 3279 | u8 reserved_at_40[0x8]; |
e281682b SM |
3280 | u8 rqtn[0x18]; |
3281 | ||
b4ff3a36 | 3282 | u8 reserved_at_60[0x20]; |
e281682b SM |
3283 | }; |
3284 | ||
3285 | struct mlx5_ifc_query_rq_out_bits { | |
3286 | u8 status[0x8]; | |
b4ff3a36 | 3287 | u8 reserved_at_8[0x18]; |
e281682b SM |
3288 | |
3289 | u8 syndrome[0x20]; | |
3290 | ||
b4ff3a36 | 3291 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3292 | |
3293 | struct mlx5_ifc_rqc_bits rq_context; | |
3294 | }; | |
3295 | ||
3296 | struct mlx5_ifc_query_rq_in_bits { | |
3297 | u8 opcode[0x10]; | |
b4ff3a36 | 3298 | u8 reserved_at_10[0x10]; |
e281682b | 3299 | |
b4ff3a36 | 3300 | u8 reserved_at_20[0x10]; |
e281682b SM |
3301 | u8 op_mod[0x10]; |
3302 | ||
b4ff3a36 | 3303 | u8 reserved_at_40[0x8]; |
e281682b SM |
3304 | u8 rqn[0x18]; |
3305 | ||
b4ff3a36 | 3306 | u8 reserved_at_60[0x20]; |
e281682b SM |
3307 | }; |
3308 | ||
3309 | struct mlx5_ifc_query_roce_address_out_bits { | |
3310 | u8 status[0x8]; | |
b4ff3a36 | 3311 | u8 reserved_at_8[0x18]; |
e281682b SM |
3312 | |
3313 | u8 syndrome[0x20]; | |
3314 | ||
b4ff3a36 | 3315 | u8 reserved_at_40[0x40]; |
e281682b SM |
3316 | |
3317 | struct mlx5_ifc_roce_addr_layout_bits roce_address; | |
3318 | }; | |
3319 | ||
3320 | struct mlx5_ifc_query_roce_address_in_bits { | |
3321 | u8 opcode[0x10]; | |
b4ff3a36 | 3322 | u8 reserved_at_10[0x10]; |
e281682b | 3323 | |
b4ff3a36 | 3324 | u8 reserved_at_20[0x10]; |
e281682b SM |
3325 | u8 op_mod[0x10]; |
3326 | ||
3327 | u8 roce_address_index[0x10]; | |
b4ff3a36 | 3328 | u8 reserved_at_50[0x10]; |
e281682b | 3329 | |
b4ff3a36 | 3330 | u8 reserved_at_60[0x20]; |
e281682b SM |
3331 | }; |
3332 | ||
3333 | struct mlx5_ifc_query_rmp_out_bits { | |
3334 | u8 status[0x8]; | |
b4ff3a36 | 3335 | u8 reserved_at_8[0x18]; |
e281682b SM |
3336 | |
3337 | u8 syndrome[0x20]; | |
3338 | ||
b4ff3a36 | 3339 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3340 | |
3341 | struct mlx5_ifc_rmpc_bits rmp_context; | |
3342 | }; | |
3343 | ||
3344 | struct mlx5_ifc_query_rmp_in_bits { | |
3345 | u8 opcode[0x10]; | |
b4ff3a36 | 3346 | u8 reserved_at_10[0x10]; |
e281682b | 3347 | |
b4ff3a36 | 3348 | u8 reserved_at_20[0x10]; |
e281682b SM |
3349 | u8 op_mod[0x10]; |
3350 | ||
b4ff3a36 | 3351 | u8 reserved_at_40[0x8]; |
e281682b SM |
3352 | u8 rmpn[0x18]; |
3353 | ||
b4ff3a36 | 3354 | u8 reserved_at_60[0x20]; |
e281682b SM |
3355 | }; |
3356 | ||
3357 | struct mlx5_ifc_query_qp_out_bits { | |
3358 | u8 status[0x8]; | |
b4ff3a36 | 3359 | u8 reserved_at_8[0x18]; |
e281682b SM |
3360 | |
3361 | u8 syndrome[0x20]; | |
3362 | ||
b4ff3a36 | 3363 | u8 reserved_at_40[0x40]; |
e281682b SM |
3364 | |
3365 | u8 opt_param_mask[0x20]; | |
3366 | ||
b4ff3a36 | 3367 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3368 | |
3369 | struct mlx5_ifc_qpc_bits qpc; | |
3370 | ||
b4ff3a36 | 3371 | u8 reserved_at_800[0x80]; |
e281682b SM |
3372 | |
3373 | u8 pas[0][0x40]; | |
3374 | }; | |
3375 | ||
3376 | struct mlx5_ifc_query_qp_in_bits { | |
3377 | u8 opcode[0x10]; | |
b4ff3a36 | 3378 | u8 reserved_at_10[0x10]; |
e281682b | 3379 | |
b4ff3a36 | 3380 | u8 reserved_at_20[0x10]; |
e281682b SM |
3381 | u8 op_mod[0x10]; |
3382 | ||
b4ff3a36 | 3383 | u8 reserved_at_40[0x8]; |
e281682b SM |
3384 | u8 qpn[0x18]; |
3385 | ||
b4ff3a36 | 3386 | u8 reserved_at_60[0x20]; |
e281682b SM |
3387 | }; |
3388 | ||
3389 | struct mlx5_ifc_query_q_counter_out_bits { | |
3390 | u8 status[0x8]; | |
b4ff3a36 | 3391 | u8 reserved_at_8[0x18]; |
e281682b SM |
3392 | |
3393 | u8 syndrome[0x20]; | |
3394 | ||
b4ff3a36 | 3395 | u8 reserved_at_40[0x40]; |
e281682b SM |
3396 | |
3397 | u8 rx_write_requests[0x20]; | |
3398 | ||
b4ff3a36 | 3399 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3400 | |
3401 | u8 rx_read_requests[0x20]; | |
3402 | ||
b4ff3a36 | 3403 | u8 reserved_at_e0[0x20]; |
e281682b SM |
3404 | |
3405 | u8 rx_atomic_requests[0x20]; | |
3406 | ||
b4ff3a36 | 3407 | u8 reserved_at_120[0x20]; |
e281682b SM |
3408 | |
3409 | u8 rx_dct_connect[0x20]; | |
3410 | ||
b4ff3a36 | 3411 | u8 reserved_at_160[0x20]; |
e281682b SM |
3412 | |
3413 | u8 out_of_buffer[0x20]; | |
3414 | ||
b4ff3a36 | 3415 | u8 reserved_at_1a0[0x20]; |
e281682b SM |
3416 | |
3417 | u8 out_of_sequence[0x20]; | |
3418 | ||
b4ff3a36 | 3419 | u8 reserved_at_1e0[0x620]; |
e281682b SM |
3420 | }; |
3421 | ||
3422 | struct mlx5_ifc_query_q_counter_in_bits { | |
3423 | u8 opcode[0x10]; | |
b4ff3a36 | 3424 | u8 reserved_at_10[0x10]; |
e281682b | 3425 | |
b4ff3a36 | 3426 | u8 reserved_at_20[0x10]; |
e281682b SM |
3427 | u8 op_mod[0x10]; |
3428 | ||
b4ff3a36 | 3429 | u8 reserved_at_40[0x80]; |
e281682b SM |
3430 | |
3431 | u8 clear[0x1]; | |
b4ff3a36 | 3432 | u8 reserved_at_c1[0x1f]; |
e281682b | 3433 | |
b4ff3a36 | 3434 | u8 reserved_at_e0[0x18]; |
e281682b SM |
3435 | u8 counter_set_id[0x8]; |
3436 | }; | |
3437 | ||
3438 | struct mlx5_ifc_query_pages_out_bits { | |
3439 | u8 status[0x8]; | |
b4ff3a36 | 3440 | u8 reserved_at_8[0x18]; |
e281682b SM |
3441 | |
3442 | u8 syndrome[0x20]; | |
3443 | ||
b4ff3a36 | 3444 | u8 reserved_at_40[0x10]; |
e281682b SM |
3445 | u8 function_id[0x10]; |
3446 | ||
3447 | u8 num_pages[0x20]; | |
3448 | }; | |
3449 | ||
3450 | enum { | |
3451 | MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, | |
3452 | MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, | |
3453 | MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, | |
3454 | }; | |
3455 | ||
3456 | struct mlx5_ifc_query_pages_in_bits { | |
3457 | u8 opcode[0x10]; | |
b4ff3a36 | 3458 | u8 reserved_at_10[0x10]; |
e281682b | 3459 | |
b4ff3a36 | 3460 | u8 reserved_at_20[0x10]; |
e281682b SM |
3461 | u8 op_mod[0x10]; |
3462 | ||
b4ff3a36 | 3463 | u8 reserved_at_40[0x10]; |
e281682b SM |
3464 | u8 function_id[0x10]; |
3465 | ||
b4ff3a36 | 3466 | u8 reserved_at_60[0x20]; |
e281682b SM |
3467 | }; |
3468 | ||
3469 | struct mlx5_ifc_query_nic_vport_context_out_bits { | |
3470 | u8 status[0x8]; | |
b4ff3a36 | 3471 | u8 reserved_at_8[0x18]; |
e281682b SM |
3472 | |
3473 | u8 syndrome[0x20]; | |
3474 | ||
b4ff3a36 | 3475 | u8 reserved_at_40[0x40]; |
e281682b SM |
3476 | |
3477 | struct mlx5_ifc_nic_vport_context_bits nic_vport_context; | |
3478 | }; | |
3479 | ||
3480 | struct mlx5_ifc_query_nic_vport_context_in_bits { | |
3481 | u8 opcode[0x10]; | |
b4ff3a36 | 3482 | u8 reserved_at_10[0x10]; |
e281682b | 3483 | |
b4ff3a36 | 3484 | u8 reserved_at_20[0x10]; |
e281682b SM |
3485 | u8 op_mod[0x10]; |
3486 | ||
3487 | u8 other_vport[0x1]; | |
b4ff3a36 | 3488 | u8 reserved_at_41[0xf]; |
e281682b SM |
3489 | u8 vport_number[0x10]; |
3490 | ||
b4ff3a36 | 3491 | u8 reserved_at_60[0x5]; |
e281682b | 3492 | u8 allowed_list_type[0x3]; |
b4ff3a36 | 3493 | u8 reserved_at_68[0x18]; |
e281682b SM |
3494 | }; |
3495 | ||
3496 | struct mlx5_ifc_query_mkey_out_bits { | |
3497 | u8 status[0x8]; | |
b4ff3a36 | 3498 | u8 reserved_at_8[0x18]; |
e281682b SM |
3499 | |
3500 | u8 syndrome[0x20]; | |
3501 | ||
b4ff3a36 | 3502 | u8 reserved_at_40[0x40]; |
e281682b SM |
3503 | |
3504 | struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | |
3505 | ||
b4ff3a36 | 3506 | u8 reserved_at_280[0x600]; |
e281682b SM |
3507 | |
3508 | u8 bsf0_klm0_pas_mtt0_1[16][0x8]; | |
3509 | ||
3510 | u8 bsf1_klm1_pas_mtt2_3[16][0x8]; | |
3511 | }; | |
3512 | ||
3513 | struct mlx5_ifc_query_mkey_in_bits { | |
3514 | u8 opcode[0x10]; | |
b4ff3a36 | 3515 | u8 reserved_at_10[0x10]; |
e281682b | 3516 | |
b4ff3a36 | 3517 | u8 reserved_at_20[0x10]; |
e281682b SM |
3518 | u8 op_mod[0x10]; |
3519 | ||
b4ff3a36 | 3520 | u8 reserved_at_40[0x8]; |
e281682b SM |
3521 | u8 mkey_index[0x18]; |
3522 | ||
3523 | u8 pg_access[0x1]; | |
b4ff3a36 | 3524 | u8 reserved_at_61[0x1f]; |
e281682b SM |
3525 | }; |
3526 | ||
3527 | struct mlx5_ifc_query_mad_demux_out_bits { | |
3528 | u8 status[0x8]; | |
b4ff3a36 | 3529 | u8 reserved_at_8[0x18]; |
e281682b SM |
3530 | |
3531 | u8 syndrome[0x20]; | |
3532 | ||
b4ff3a36 | 3533 | u8 reserved_at_40[0x40]; |
e281682b SM |
3534 | |
3535 | u8 mad_dumux_parameters_block[0x20]; | |
3536 | }; | |
3537 | ||
3538 | struct mlx5_ifc_query_mad_demux_in_bits { | |
3539 | u8 opcode[0x10]; | |
b4ff3a36 | 3540 | u8 reserved_at_10[0x10]; |
e281682b | 3541 | |
b4ff3a36 | 3542 | u8 reserved_at_20[0x10]; |
e281682b SM |
3543 | u8 op_mod[0x10]; |
3544 | ||
b4ff3a36 | 3545 | u8 reserved_at_40[0x40]; |
e281682b SM |
3546 | }; |
3547 | ||
3548 | struct mlx5_ifc_query_l2_table_entry_out_bits { | |
3549 | u8 status[0x8]; | |
b4ff3a36 | 3550 | u8 reserved_at_8[0x18]; |
e281682b SM |
3551 | |
3552 | u8 syndrome[0x20]; | |
3553 | ||
b4ff3a36 | 3554 | u8 reserved_at_40[0xa0]; |
e281682b | 3555 | |
b4ff3a36 | 3556 | u8 reserved_at_e0[0x13]; |
e281682b SM |
3557 | u8 vlan_valid[0x1]; |
3558 | u8 vlan[0xc]; | |
3559 | ||
3560 | struct mlx5_ifc_mac_address_layout_bits mac_address; | |
3561 | ||
b4ff3a36 | 3562 | u8 reserved_at_140[0xc0]; |
e281682b SM |
3563 | }; |
3564 | ||
3565 | struct mlx5_ifc_query_l2_table_entry_in_bits { | |
3566 | u8 opcode[0x10]; | |
b4ff3a36 | 3567 | u8 reserved_at_10[0x10]; |
e281682b | 3568 | |
b4ff3a36 | 3569 | u8 reserved_at_20[0x10]; |
e281682b SM |
3570 | u8 op_mod[0x10]; |
3571 | ||
b4ff3a36 | 3572 | u8 reserved_at_40[0x60]; |
e281682b | 3573 | |
b4ff3a36 | 3574 | u8 reserved_at_a0[0x8]; |
e281682b SM |
3575 | u8 table_index[0x18]; |
3576 | ||
b4ff3a36 | 3577 | u8 reserved_at_c0[0x140]; |
e281682b SM |
3578 | }; |
3579 | ||
3580 | struct mlx5_ifc_query_issi_out_bits { | |
3581 | u8 status[0x8]; | |
b4ff3a36 | 3582 | u8 reserved_at_8[0x18]; |
e281682b SM |
3583 | |
3584 | u8 syndrome[0x20]; | |
3585 | ||
b4ff3a36 | 3586 | u8 reserved_at_40[0x10]; |
e281682b SM |
3587 | u8 current_issi[0x10]; |
3588 | ||
b4ff3a36 | 3589 | u8 reserved_at_60[0xa0]; |
e281682b | 3590 | |
b4ff3a36 | 3591 | u8 reserved_at_100[76][0x8]; |
e281682b SM |
3592 | u8 supported_issi_dw0[0x20]; |
3593 | }; | |
3594 | ||
3595 | struct mlx5_ifc_query_issi_in_bits { | |
3596 | u8 opcode[0x10]; | |
b4ff3a36 | 3597 | u8 reserved_at_10[0x10]; |
e281682b | 3598 | |
b4ff3a36 | 3599 | u8 reserved_at_20[0x10]; |
e281682b SM |
3600 | u8 op_mod[0x10]; |
3601 | ||
b4ff3a36 | 3602 | u8 reserved_at_40[0x40]; |
e281682b SM |
3603 | }; |
3604 | ||
3605 | struct mlx5_ifc_query_hca_vport_pkey_out_bits { | |
3606 | u8 status[0x8]; | |
b4ff3a36 | 3607 | u8 reserved_at_8[0x18]; |
e281682b SM |
3608 | |
3609 | u8 syndrome[0x20]; | |
3610 | ||
b4ff3a36 | 3611 | u8 reserved_at_40[0x40]; |
e281682b SM |
3612 | |
3613 | struct mlx5_ifc_pkey_bits pkey[0]; | |
3614 | }; | |
3615 | ||
3616 | struct mlx5_ifc_query_hca_vport_pkey_in_bits { | |
3617 | u8 opcode[0x10]; | |
b4ff3a36 | 3618 | u8 reserved_at_10[0x10]; |
e281682b | 3619 | |
b4ff3a36 | 3620 | u8 reserved_at_20[0x10]; |
e281682b SM |
3621 | u8 op_mod[0x10]; |
3622 | ||
3623 | u8 other_vport[0x1]; | |
b4ff3a36 | 3624 | u8 reserved_at_41[0xb]; |
707c4602 | 3625 | u8 port_num[0x4]; |
e281682b SM |
3626 | u8 vport_number[0x10]; |
3627 | ||
b4ff3a36 | 3628 | u8 reserved_at_60[0x10]; |
e281682b SM |
3629 | u8 pkey_index[0x10]; |
3630 | }; | |
3631 | ||
3632 | struct mlx5_ifc_query_hca_vport_gid_out_bits { | |
3633 | u8 status[0x8]; | |
b4ff3a36 | 3634 | u8 reserved_at_8[0x18]; |
e281682b SM |
3635 | |
3636 | u8 syndrome[0x20]; | |
3637 | ||
b4ff3a36 | 3638 | u8 reserved_at_40[0x20]; |
e281682b SM |
3639 | |
3640 | u8 gids_num[0x10]; | |
b4ff3a36 | 3641 | u8 reserved_at_70[0x10]; |
e281682b SM |
3642 | |
3643 | struct mlx5_ifc_array128_auto_bits gid[0]; | |
3644 | }; | |
3645 | ||
3646 | struct mlx5_ifc_query_hca_vport_gid_in_bits { | |
3647 | u8 opcode[0x10]; | |
b4ff3a36 | 3648 | u8 reserved_at_10[0x10]; |
e281682b | 3649 | |
b4ff3a36 | 3650 | u8 reserved_at_20[0x10]; |
e281682b SM |
3651 | u8 op_mod[0x10]; |
3652 | ||
3653 | u8 other_vport[0x1]; | |
b4ff3a36 | 3654 | u8 reserved_at_41[0xb]; |
707c4602 | 3655 | u8 port_num[0x4]; |
e281682b SM |
3656 | u8 vport_number[0x10]; |
3657 | ||
b4ff3a36 | 3658 | u8 reserved_at_60[0x10]; |
e281682b SM |
3659 | u8 gid_index[0x10]; |
3660 | }; | |
3661 | ||
3662 | struct mlx5_ifc_query_hca_vport_context_out_bits { | |
3663 | u8 status[0x8]; | |
b4ff3a36 | 3664 | u8 reserved_at_8[0x18]; |
e281682b SM |
3665 | |
3666 | u8 syndrome[0x20]; | |
3667 | ||
b4ff3a36 | 3668 | u8 reserved_at_40[0x40]; |
e281682b SM |
3669 | |
3670 | struct mlx5_ifc_hca_vport_context_bits hca_vport_context; | |
3671 | }; | |
3672 | ||
3673 | struct mlx5_ifc_query_hca_vport_context_in_bits { | |
3674 | u8 opcode[0x10]; | |
b4ff3a36 | 3675 | u8 reserved_at_10[0x10]; |
e281682b | 3676 | |
b4ff3a36 | 3677 | u8 reserved_at_20[0x10]; |
e281682b SM |
3678 | u8 op_mod[0x10]; |
3679 | ||
3680 | u8 other_vport[0x1]; | |
b4ff3a36 | 3681 | u8 reserved_at_41[0xb]; |
707c4602 | 3682 | u8 port_num[0x4]; |
e281682b SM |
3683 | u8 vport_number[0x10]; |
3684 | ||
b4ff3a36 | 3685 | u8 reserved_at_60[0x20]; |
e281682b SM |
3686 | }; |
3687 | ||
3688 | struct mlx5_ifc_query_hca_cap_out_bits { | |
3689 | u8 status[0x8]; | |
b4ff3a36 | 3690 | u8 reserved_at_8[0x18]; |
e281682b SM |
3691 | |
3692 | u8 syndrome[0x20]; | |
3693 | ||
b4ff3a36 | 3694 | u8 reserved_at_40[0x40]; |
e281682b SM |
3695 | |
3696 | union mlx5_ifc_hca_cap_union_bits capability; | |
3697 | }; | |
3698 | ||
3699 | struct mlx5_ifc_query_hca_cap_in_bits { | |
3700 | u8 opcode[0x10]; | |
b4ff3a36 | 3701 | u8 reserved_at_10[0x10]; |
e281682b | 3702 | |
b4ff3a36 | 3703 | u8 reserved_at_20[0x10]; |
e281682b SM |
3704 | u8 op_mod[0x10]; |
3705 | ||
b4ff3a36 | 3706 | u8 reserved_at_40[0x40]; |
e281682b SM |
3707 | }; |
3708 | ||
3709 | struct mlx5_ifc_query_flow_table_out_bits { | |
3710 | u8 status[0x8]; | |
b4ff3a36 | 3711 | u8 reserved_at_8[0x18]; |
e281682b SM |
3712 | |
3713 | u8 syndrome[0x20]; | |
3714 | ||
b4ff3a36 | 3715 | u8 reserved_at_40[0x80]; |
e281682b | 3716 | |
b4ff3a36 | 3717 | u8 reserved_at_c0[0x8]; |
e281682b | 3718 | u8 level[0x8]; |
b4ff3a36 | 3719 | u8 reserved_at_d0[0x8]; |
e281682b SM |
3720 | u8 log_size[0x8]; |
3721 | ||
b4ff3a36 | 3722 | u8 reserved_at_e0[0x120]; |
e281682b SM |
3723 | }; |
3724 | ||
3725 | struct mlx5_ifc_query_flow_table_in_bits { | |
3726 | u8 opcode[0x10]; | |
b4ff3a36 | 3727 | u8 reserved_at_10[0x10]; |
e281682b | 3728 | |
b4ff3a36 | 3729 | u8 reserved_at_20[0x10]; |
e281682b SM |
3730 | u8 op_mod[0x10]; |
3731 | ||
b4ff3a36 | 3732 | u8 reserved_at_40[0x40]; |
e281682b SM |
3733 | |
3734 | u8 table_type[0x8]; | |
b4ff3a36 | 3735 | u8 reserved_at_88[0x18]; |
e281682b | 3736 | |
b4ff3a36 | 3737 | u8 reserved_at_a0[0x8]; |
e281682b SM |
3738 | u8 table_id[0x18]; |
3739 | ||
b4ff3a36 | 3740 | u8 reserved_at_c0[0x140]; |
e281682b SM |
3741 | }; |
3742 | ||
3743 | struct mlx5_ifc_query_fte_out_bits { | |
3744 | u8 status[0x8]; | |
b4ff3a36 | 3745 | u8 reserved_at_8[0x18]; |
e281682b SM |
3746 | |
3747 | u8 syndrome[0x20]; | |
3748 | ||
b4ff3a36 | 3749 | u8 reserved_at_40[0x1c0]; |
e281682b SM |
3750 | |
3751 | struct mlx5_ifc_flow_context_bits flow_context; | |
3752 | }; | |
3753 | ||
3754 | struct mlx5_ifc_query_fte_in_bits { | |
3755 | u8 opcode[0x10]; | |
b4ff3a36 | 3756 | u8 reserved_at_10[0x10]; |
e281682b | 3757 | |
b4ff3a36 | 3758 | u8 reserved_at_20[0x10]; |
e281682b SM |
3759 | u8 op_mod[0x10]; |
3760 | ||
b4ff3a36 | 3761 | u8 reserved_at_40[0x40]; |
e281682b SM |
3762 | |
3763 | u8 table_type[0x8]; | |
b4ff3a36 | 3764 | u8 reserved_at_88[0x18]; |
e281682b | 3765 | |
b4ff3a36 | 3766 | u8 reserved_at_a0[0x8]; |
e281682b SM |
3767 | u8 table_id[0x18]; |
3768 | ||
b4ff3a36 | 3769 | u8 reserved_at_c0[0x40]; |
e281682b SM |
3770 | |
3771 | u8 flow_index[0x20]; | |
3772 | ||
b4ff3a36 | 3773 | u8 reserved_at_120[0xe0]; |
e281682b SM |
3774 | }; |
3775 | ||
3776 | enum { | |
3777 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, | |
3778 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, | |
3779 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, | |
3780 | }; | |
3781 | ||
3782 | struct mlx5_ifc_query_flow_group_out_bits { | |
3783 | u8 status[0x8]; | |
b4ff3a36 | 3784 | u8 reserved_at_8[0x18]; |
e281682b SM |
3785 | |
3786 | u8 syndrome[0x20]; | |
3787 | ||
b4ff3a36 | 3788 | u8 reserved_at_40[0xa0]; |
e281682b SM |
3789 | |
3790 | u8 start_flow_index[0x20]; | |
3791 | ||
b4ff3a36 | 3792 | u8 reserved_at_100[0x20]; |
e281682b SM |
3793 | |
3794 | u8 end_flow_index[0x20]; | |
3795 | ||
b4ff3a36 | 3796 | u8 reserved_at_140[0xa0]; |
e281682b | 3797 | |
b4ff3a36 | 3798 | u8 reserved_at_1e0[0x18]; |
e281682b SM |
3799 | u8 match_criteria_enable[0x8]; |
3800 | ||
3801 | struct mlx5_ifc_fte_match_param_bits match_criteria; | |
3802 | ||
b4ff3a36 | 3803 | u8 reserved_at_1200[0xe00]; |
e281682b SM |
3804 | }; |
3805 | ||
3806 | struct mlx5_ifc_query_flow_group_in_bits { | |
3807 | u8 opcode[0x10]; | |
b4ff3a36 | 3808 | u8 reserved_at_10[0x10]; |
e281682b | 3809 | |
b4ff3a36 | 3810 | u8 reserved_at_20[0x10]; |
e281682b SM |
3811 | u8 op_mod[0x10]; |
3812 | ||
b4ff3a36 | 3813 | u8 reserved_at_40[0x40]; |
e281682b SM |
3814 | |
3815 | u8 table_type[0x8]; | |
b4ff3a36 | 3816 | u8 reserved_at_88[0x18]; |
e281682b | 3817 | |
b4ff3a36 | 3818 | u8 reserved_at_a0[0x8]; |
e281682b SM |
3819 | u8 table_id[0x18]; |
3820 | ||
3821 | u8 group_id[0x20]; | |
3822 | ||
b4ff3a36 | 3823 | u8 reserved_at_e0[0x120]; |
e281682b SM |
3824 | }; |
3825 | ||
d6666753 SM |
3826 | struct mlx5_ifc_query_esw_vport_context_out_bits { |
3827 | u8 status[0x8]; | |
b4ff3a36 | 3828 | u8 reserved_at_8[0x18]; |
d6666753 SM |
3829 | |
3830 | u8 syndrome[0x20]; | |
3831 | ||
b4ff3a36 | 3832 | u8 reserved_at_40[0x40]; |
d6666753 SM |
3833 | |
3834 | struct mlx5_ifc_esw_vport_context_bits esw_vport_context; | |
3835 | }; | |
3836 | ||
3837 | struct mlx5_ifc_query_esw_vport_context_in_bits { | |
3838 | u8 opcode[0x10]; | |
b4ff3a36 | 3839 | u8 reserved_at_10[0x10]; |
d6666753 | 3840 | |
b4ff3a36 | 3841 | u8 reserved_at_20[0x10]; |
d6666753 SM |
3842 | u8 op_mod[0x10]; |
3843 | ||
3844 | u8 other_vport[0x1]; | |
b4ff3a36 | 3845 | u8 reserved_at_41[0xf]; |
d6666753 SM |
3846 | u8 vport_number[0x10]; |
3847 | ||
b4ff3a36 | 3848 | u8 reserved_at_60[0x20]; |
d6666753 SM |
3849 | }; |
3850 | ||
3851 | struct mlx5_ifc_modify_esw_vport_context_out_bits { | |
3852 | u8 status[0x8]; | |
b4ff3a36 | 3853 | u8 reserved_at_8[0x18]; |
d6666753 SM |
3854 | |
3855 | u8 syndrome[0x20]; | |
3856 | ||
b4ff3a36 | 3857 | u8 reserved_at_40[0x40]; |
d6666753 SM |
3858 | }; |
3859 | ||
3860 | struct mlx5_ifc_esw_vport_context_fields_select_bits { | |
b4ff3a36 | 3861 | u8 reserved_at_0[0x1c]; |
d6666753 SM |
3862 | u8 vport_cvlan_insert[0x1]; |
3863 | u8 vport_svlan_insert[0x1]; | |
3864 | u8 vport_cvlan_strip[0x1]; | |
3865 | u8 vport_svlan_strip[0x1]; | |
3866 | }; | |
3867 | ||
3868 | struct mlx5_ifc_modify_esw_vport_context_in_bits { | |
3869 | u8 opcode[0x10]; | |
b4ff3a36 | 3870 | u8 reserved_at_10[0x10]; |
d6666753 | 3871 | |
b4ff3a36 | 3872 | u8 reserved_at_20[0x10]; |
d6666753 SM |
3873 | u8 op_mod[0x10]; |
3874 | ||
3875 | u8 other_vport[0x1]; | |
b4ff3a36 | 3876 | u8 reserved_at_41[0xf]; |
d6666753 SM |
3877 | u8 vport_number[0x10]; |
3878 | ||
3879 | struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; | |
3880 | ||
3881 | struct mlx5_ifc_esw_vport_context_bits esw_vport_context; | |
3882 | }; | |
3883 | ||
e281682b SM |
3884 | struct mlx5_ifc_query_eq_out_bits { |
3885 | u8 status[0x8]; | |
b4ff3a36 | 3886 | u8 reserved_at_8[0x18]; |
e281682b SM |
3887 | |
3888 | u8 syndrome[0x20]; | |
3889 | ||
b4ff3a36 | 3890 | u8 reserved_at_40[0x40]; |
e281682b SM |
3891 | |
3892 | struct mlx5_ifc_eqc_bits eq_context_entry; | |
3893 | ||
b4ff3a36 | 3894 | u8 reserved_at_280[0x40]; |
e281682b SM |
3895 | |
3896 | u8 event_bitmask[0x40]; | |
3897 | ||
b4ff3a36 | 3898 | u8 reserved_at_300[0x580]; |
e281682b SM |
3899 | |
3900 | u8 pas[0][0x40]; | |
3901 | }; | |
3902 | ||
3903 | struct mlx5_ifc_query_eq_in_bits { | |
3904 | u8 opcode[0x10]; | |
b4ff3a36 | 3905 | u8 reserved_at_10[0x10]; |
e281682b | 3906 | |
b4ff3a36 | 3907 | u8 reserved_at_20[0x10]; |
e281682b SM |
3908 | u8 op_mod[0x10]; |
3909 | ||
b4ff3a36 | 3910 | u8 reserved_at_40[0x18]; |
e281682b SM |
3911 | u8 eq_number[0x8]; |
3912 | ||
b4ff3a36 | 3913 | u8 reserved_at_60[0x20]; |
e281682b SM |
3914 | }; |
3915 | ||
3916 | struct mlx5_ifc_query_dct_out_bits { | |
3917 | u8 status[0x8]; | |
b4ff3a36 | 3918 | u8 reserved_at_8[0x18]; |
e281682b SM |
3919 | |
3920 | u8 syndrome[0x20]; | |
3921 | ||
b4ff3a36 | 3922 | u8 reserved_at_40[0x40]; |
e281682b SM |
3923 | |
3924 | struct mlx5_ifc_dctc_bits dct_context_entry; | |
3925 | ||
b4ff3a36 | 3926 | u8 reserved_at_280[0x180]; |
e281682b SM |
3927 | }; |
3928 | ||
3929 | struct mlx5_ifc_query_dct_in_bits { | |
3930 | u8 opcode[0x10]; | |
b4ff3a36 | 3931 | u8 reserved_at_10[0x10]; |
e281682b | 3932 | |
b4ff3a36 | 3933 | u8 reserved_at_20[0x10]; |
e281682b SM |
3934 | u8 op_mod[0x10]; |
3935 | ||
b4ff3a36 | 3936 | u8 reserved_at_40[0x8]; |
e281682b SM |
3937 | u8 dctn[0x18]; |
3938 | ||
b4ff3a36 | 3939 | u8 reserved_at_60[0x20]; |
e281682b SM |
3940 | }; |
3941 | ||
3942 | struct mlx5_ifc_query_cq_out_bits { | |
3943 | u8 status[0x8]; | |
b4ff3a36 | 3944 | u8 reserved_at_8[0x18]; |
e281682b SM |
3945 | |
3946 | u8 syndrome[0x20]; | |
3947 | ||
b4ff3a36 | 3948 | u8 reserved_at_40[0x40]; |
e281682b SM |
3949 | |
3950 | struct mlx5_ifc_cqc_bits cq_context; | |
3951 | ||
b4ff3a36 | 3952 | u8 reserved_at_280[0x600]; |
e281682b SM |
3953 | |
3954 | u8 pas[0][0x40]; | |
3955 | }; | |
3956 | ||
3957 | struct mlx5_ifc_query_cq_in_bits { | |
3958 | u8 opcode[0x10]; | |
b4ff3a36 | 3959 | u8 reserved_at_10[0x10]; |
e281682b | 3960 | |
b4ff3a36 | 3961 | u8 reserved_at_20[0x10]; |
e281682b SM |
3962 | u8 op_mod[0x10]; |
3963 | ||
b4ff3a36 | 3964 | u8 reserved_at_40[0x8]; |
e281682b SM |
3965 | u8 cqn[0x18]; |
3966 | ||
b4ff3a36 | 3967 | u8 reserved_at_60[0x20]; |
e281682b SM |
3968 | }; |
3969 | ||
3970 | struct mlx5_ifc_query_cong_status_out_bits { | |
3971 | u8 status[0x8]; | |
b4ff3a36 | 3972 | u8 reserved_at_8[0x18]; |
e281682b SM |
3973 | |
3974 | u8 syndrome[0x20]; | |
3975 | ||
b4ff3a36 | 3976 | u8 reserved_at_40[0x20]; |
e281682b SM |
3977 | |
3978 | u8 enable[0x1]; | |
3979 | u8 tag_enable[0x1]; | |
b4ff3a36 | 3980 | u8 reserved_at_62[0x1e]; |
e281682b SM |
3981 | }; |
3982 | ||
3983 | struct mlx5_ifc_query_cong_status_in_bits { | |
3984 | u8 opcode[0x10]; | |
b4ff3a36 | 3985 | u8 reserved_at_10[0x10]; |
e281682b | 3986 | |
b4ff3a36 | 3987 | u8 reserved_at_20[0x10]; |
e281682b SM |
3988 | u8 op_mod[0x10]; |
3989 | ||
b4ff3a36 | 3990 | u8 reserved_at_40[0x18]; |
e281682b SM |
3991 | u8 priority[0x4]; |
3992 | u8 cong_protocol[0x4]; | |
3993 | ||
b4ff3a36 | 3994 | u8 reserved_at_60[0x20]; |
e281682b SM |
3995 | }; |
3996 | ||
3997 | struct mlx5_ifc_query_cong_statistics_out_bits { | |
3998 | u8 status[0x8]; | |
b4ff3a36 | 3999 | u8 reserved_at_8[0x18]; |
e281682b SM |
4000 | |
4001 | u8 syndrome[0x20]; | |
4002 | ||
b4ff3a36 | 4003 | u8 reserved_at_40[0x40]; |
e281682b SM |
4004 | |
4005 | u8 cur_flows[0x20]; | |
4006 | ||
4007 | u8 sum_flows[0x20]; | |
4008 | ||
4009 | u8 cnp_ignored_high[0x20]; | |
4010 | ||
4011 | u8 cnp_ignored_low[0x20]; | |
4012 | ||
4013 | u8 cnp_handled_high[0x20]; | |
4014 | ||
4015 | u8 cnp_handled_low[0x20]; | |
4016 | ||
b4ff3a36 | 4017 | u8 reserved_at_140[0x100]; |
e281682b SM |
4018 | |
4019 | u8 time_stamp_high[0x20]; | |
4020 | ||
4021 | u8 time_stamp_low[0x20]; | |
4022 | ||
4023 | u8 accumulators_period[0x20]; | |
4024 | ||
4025 | u8 ecn_marked_roce_packets_high[0x20]; | |
4026 | ||
4027 | u8 ecn_marked_roce_packets_low[0x20]; | |
4028 | ||
4029 | u8 cnps_sent_high[0x20]; | |
4030 | ||
4031 | u8 cnps_sent_low[0x20]; | |
4032 | ||
b4ff3a36 | 4033 | u8 reserved_at_320[0x560]; |
e281682b SM |
4034 | }; |
4035 | ||
4036 | struct mlx5_ifc_query_cong_statistics_in_bits { | |
4037 | u8 opcode[0x10]; | |
b4ff3a36 | 4038 | u8 reserved_at_10[0x10]; |
e281682b | 4039 | |
b4ff3a36 | 4040 | u8 reserved_at_20[0x10]; |
e281682b SM |
4041 | u8 op_mod[0x10]; |
4042 | ||
4043 | u8 clear[0x1]; | |
b4ff3a36 | 4044 | u8 reserved_at_41[0x1f]; |
e281682b | 4045 | |
b4ff3a36 | 4046 | u8 reserved_at_60[0x20]; |
e281682b SM |
4047 | }; |
4048 | ||
4049 | struct mlx5_ifc_query_cong_params_out_bits { | |
4050 | u8 status[0x8]; | |
b4ff3a36 | 4051 | u8 reserved_at_8[0x18]; |
e281682b SM |
4052 | |
4053 | u8 syndrome[0x20]; | |
4054 | ||
b4ff3a36 | 4055 | u8 reserved_at_40[0x40]; |
e281682b SM |
4056 | |
4057 | union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; | |
4058 | }; | |
4059 | ||
4060 | struct mlx5_ifc_query_cong_params_in_bits { | |
4061 | u8 opcode[0x10]; | |
b4ff3a36 | 4062 | u8 reserved_at_10[0x10]; |
e281682b | 4063 | |
b4ff3a36 | 4064 | u8 reserved_at_20[0x10]; |
e281682b SM |
4065 | u8 op_mod[0x10]; |
4066 | ||
b4ff3a36 | 4067 | u8 reserved_at_40[0x1c]; |
e281682b SM |
4068 | u8 cong_protocol[0x4]; |
4069 | ||
b4ff3a36 | 4070 | u8 reserved_at_60[0x20]; |
e281682b SM |
4071 | }; |
4072 | ||
4073 | struct mlx5_ifc_query_adapter_out_bits { | |
4074 | u8 status[0x8]; | |
b4ff3a36 | 4075 | u8 reserved_at_8[0x18]; |
e281682b SM |
4076 | |
4077 | u8 syndrome[0x20]; | |
4078 | ||
b4ff3a36 | 4079 | u8 reserved_at_40[0x40]; |
e281682b SM |
4080 | |
4081 | struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; | |
4082 | }; | |
4083 | ||
4084 | struct mlx5_ifc_query_adapter_in_bits { | |
4085 | u8 opcode[0x10]; | |
b4ff3a36 | 4086 | u8 reserved_at_10[0x10]; |
e281682b | 4087 | |
b4ff3a36 | 4088 | u8 reserved_at_20[0x10]; |
e281682b SM |
4089 | u8 op_mod[0x10]; |
4090 | ||
b4ff3a36 | 4091 | u8 reserved_at_40[0x40]; |
e281682b SM |
4092 | }; |
4093 | ||
4094 | struct mlx5_ifc_qp_2rst_out_bits { | |
4095 | u8 status[0x8]; | |
b4ff3a36 | 4096 | u8 reserved_at_8[0x18]; |
e281682b SM |
4097 | |
4098 | u8 syndrome[0x20]; | |
4099 | ||
b4ff3a36 | 4100 | u8 reserved_at_40[0x40]; |
e281682b SM |
4101 | }; |
4102 | ||
4103 | struct mlx5_ifc_qp_2rst_in_bits { | |
4104 | u8 opcode[0x10]; | |
b4ff3a36 | 4105 | u8 reserved_at_10[0x10]; |
e281682b | 4106 | |
b4ff3a36 | 4107 | u8 reserved_at_20[0x10]; |
e281682b SM |
4108 | u8 op_mod[0x10]; |
4109 | ||
b4ff3a36 | 4110 | u8 reserved_at_40[0x8]; |
e281682b SM |
4111 | u8 qpn[0x18]; |
4112 | ||
b4ff3a36 | 4113 | u8 reserved_at_60[0x20]; |
e281682b SM |
4114 | }; |
4115 | ||
4116 | struct mlx5_ifc_qp_2err_out_bits { | |
4117 | u8 status[0x8]; | |
b4ff3a36 | 4118 | u8 reserved_at_8[0x18]; |
e281682b SM |
4119 | |
4120 | u8 syndrome[0x20]; | |
4121 | ||
b4ff3a36 | 4122 | u8 reserved_at_40[0x40]; |
e281682b SM |
4123 | }; |
4124 | ||
4125 | struct mlx5_ifc_qp_2err_in_bits { | |
4126 | u8 opcode[0x10]; | |
b4ff3a36 | 4127 | u8 reserved_at_10[0x10]; |
e281682b | 4128 | |
b4ff3a36 | 4129 | u8 reserved_at_20[0x10]; |
e281682b SM |
4130 | u8 op_mod[0x10]; |
4131 | ||
b4ff3a36 | 4132 | u8 reserved_at_40[0x8]; |
e281682b SM |
4133 | u8 qpn[0x18]; |
4134 | ||
b4ff3a36 | 4135 | u8 reserved_at_60[0x20]; |
e281682b SM |
4136 | }; |
4137 | ||
4138 | struct mlx5_ifc_page_fault_resume_out_bits { | |
4139 | u8 status[0x8]; | |
b4ff3a36 | 4140 | u8 reserved_at_8[0x18]; |
e281682b SM |
4141 | |
4142 | u8 syndrome[0x20]; | |
4143 | ||
b4ff3a36 | 4144 | u8 reserved_at_40[0x40]; |
e281682b SM |
4145 | }; |
4146 | ||
4147 | struct mlx5_ifc_page_fault_resume_in_bits { | |
4148 | u8 opcode[0x10]; | |
b4ff3a36 | 4149 | u8 reserved_at_10[0x10]; |
e281682b | 4150 | |
b4ff3a36 | 4151 | u8 reserved_at_20[0x10]; |
e281682b SM |
4152 | u8 op_mod[0x10]; |
4153 | ||
4154 | u8 error[0x1]; | |
b4ff3a36 | 4155 | u8 reserved_at_41[0x4]; |
e281682b SM |
4156 | u8 rdma[0x1]; |
4157 | u8 read_write[0x1]; | |
4158 | u8 req_res[0x1]; | |
4159 | u8 qpn[0x18]; | |
4160 | ||
b4ff3a36 | 4161 | u8 reserved_at_60[0x20]; |
e281682b SM |
4162 | }; |
4163 | ||
4164 | struct mlx5_ifc_nop_out_bits { | |
4165 | u8 status[0x8]; | |
b4ff3a36 | 4166 | u8 reserved_at_8[0x18]; |
e281682b SM |
4167 | |
4168 | u8 syndrome[0x20]; | |
4169 | ||
b4ff3a36 | 4170 | u8 reserved_at_40[0x40]; |
e281682b SM |
4171 | }; |
4172 | ||
4173 | struct mlx5_ifc_nop_in_bits { | |
4174 | u8 opcode[0x10]; | |
b4ff3a36 | 4175 | u8 reserved_at_10[0x10]; |
e281682b | 4176 | |
b4ff3a36 | 4177 | u8 reserved_at_20[0x10]; |
e281682b SM |
4178 | u8 op_mod[0x10]; |
4179 | ||
b4ff3a36 | 4180 | u8 reserved_at_40[0x40]; |
e281682b SM |
4181 | }; |
4182 | ||
4183 | struct mlx5_ifc_modify_vport_state_out_bits { | |
4184 | u8 status[0x8]; | |
b4ff3a36 | 4185 | u8 reserved_at_8[0x18]; |
e281682b SM |
4186 | |
4187 | u8 syndrome[0x20]; | |
4188 | ||
b4ff3a36 | 4189 | u8 reserved_at_40[0x40]; |
e281682b SM |
4190 | }; |
4191 | ||
4192 | struct mlx5_ifc_modify_vport_state_in_bits { | |
4193 | u8 opcode[0x10]; | |
b4ff3a36 | 4194 | u8 reserved_at_10[0x10]; |
e281682b | 4195 | |
b4ff3a36 | 4196 | u8 reserved_at_20[0x10]; |
e281682b SM |
4197 | u8 op_mod[0x10]; |
4198 | ||
4199 | u8 other_vport[0x1]; | |
b4ff3a36 | 4200 | u8 reserved_at_41[0xf]; |
e281682b SM |
4201 | u8 vport_number[0x10]; |
4202 | ||
b4ff3a36 | 4203 | u8 reserved_at_60[0x18]; |
e281682b | 4204 | u8 admin_state[0x4]; |
b4ff3a36 | 4205 | u8 reserved_at_7c[0x4]; |
e281682b SM |
4206 | }; |
4207 | ||
4208 | struct mlx5_ifc_modify_tis_out_bits { | |
4209 | u8 status[0x8]; | |
b4ff3a36 | 4210 | u8 reserved_at_8[0x18]; |
e281682b SM |
4211 | |
4212 | u8 syndrome[0x20]; | |
4213 | ||
b4ff3a36 | 4214 | u8 reserved_at_40[0x40]; |
e281682b SM |
4215 | }; |
4216 | ||
75850d0b | 4217 | struct mlx5_ifc_modify_tis_bitmask_bits { |
b4ff3a36 | 4218 | u8 reserved_at_0[0x20]; |
75850d0b | 4219 | |
b4ff3a36 | 4220 | u8 reserved_at_20[0x1f]; |
75850d0b | 4221 | u8 prio[0x1]; |
4222 | }; | |
4223 | ||
e281682b SM |
4224 | struct mlx5_ifc_modify_tis_in_bits { |
4225 | u8 opcode[0x10]; | |
b4ff3a36 | 4226 | u8 reserved_at_10[0x10]; |
e281682b | 4227 | |
b4ff3a36 | 4228 | u8 reserved_at_20[0x10]; |
e281682b SM |
4229 | u8 op_mod[0x10]; |
4230 | ||
b4ff3a36 | 4231 | u8 reserved_at_40[0x8]; |
e281682b SM |
4232 | u8 tisn[0x18]; |
4233 | ||
b4ff3a36 | 4234 | u8 reserved_at_60[0x20]; |
e281682b | 4235 | |
75850d0b | 4236 | struct mlx5_ifc_modify_tis_bitmask_bits bitmask; |
e281682b | 4237 | |
b4ff3a36 | 4238 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4239 | |
4240 | struct mlx5_ifc_tisc_bits ctx; | |
4241 | }; | |
4242 | ||
d9eea403 | 4243 | struct mlx5_ifc_modify_tir_bitmask_bits { |
b4ff3a36 | 4244 | u8 reserved_at_0[0x20]; |
d9eea403 | 4245 | |
b4ff3a36 | 4246 | u8 reserved_at_20[0x1b]; |
66189961 | 4247 | u8 self_lb_en[0x1]; |
b4ff3a36 | 4248 | u8 reserved_at_3c[0x3]; |
d9eea403 AS |
4249 | u8 lro[0x1]; |
4250 | }; | |
4251 | ||
e281682b SM |
4252 | struct mlx5_ifc_modify_tir_out_bits { |
4253 | u8 status[0x8]; | |
b4ff3a36 | 4254 | u8 reserved_at_8[0x18]; |
e281682b SM |
4255 | |
4256 | u8 syndrome[0x20]; | |
4257 | ||
b4ff3a36 | 4258 | u8 reserved_at_40[0x40]; |
e281682b SM |
4259 | }; |
4260 | ||
4261 | struct mlx5_ifc_modify_tir_in_bits { | |
4262 | u8 opcode[0x10]; | |
b4ff3a36 | 4263 | u8 reserved_at_10[0x10]; |
e281682b | 4264 | |
b4ff3a36 | 4265 | u8 reserved_at_20[0x10]; |
e281682b SM |
4266 | u8 op_mod[0x10]; |
4267 | ||
b4ff3a36 | 4268 | u8 reserved_at_40[0x8]; |
e281682b SM |
4269 | u8 tirn[0x18]; |
4270 | ||
b4ff3a36 | 4271 | u8 reserved_at_60[0x20]; |
e281682b | 4272 | |
d9eea403 | 4273 | struct mlx5_ifc_modify_tir_bitmask_bits bitmask; |
e281682b | 4274 | |
b4ff3a36 | 4275 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4276 | |
4277 | struct mlx5_ifc_tirc_bits ctx; | |
4278 | }; | |
4279 | ||
4280 | struct mlx5_ifc_modify_sq_out_bits { | |
4281 | u8 status[0x8]; | |
b4ff3a36 | 4282 | u8 reserved_at_8[0x18]; |
e281682b SM |
4283 | |
4284 | u8 syndrome[0x20]; | |
4285 | ||
b4ff3a36 | 4286 | u8 reserved_at_40[0x40]; |
e281682b SM |
4287 | }; |
4288 | ||
4289 | struct mlx5_ifc_modify_sq_in_bits { | |
4290 | u8 opcode[0x10]; | |
b4ff3a36 | 4291 | u8 reserved_at_10[0x10]; |
e281682b | 4292 | |
b4ff3a36 | 4293 | u8 reserved_at_20[0x10]; |
e281682b SM |
4294 | u8 op_mod[0x10]; |
4295 | ||
4296 | u8 sq_state[0x4]; | |
b4ff3a36 | 4297 | u8 reserved_at_44[0x4]; |
e281682b SM |
4298 | u8 sqn[0x18]; |
4299 | ||
b4ff3a36 | 4300 | u8 reserved_at_60[0x20]; |
e281682b SM |
4301 | |
4302 | u8 modify_bitmask[0x40]; | |
4303 | ||
b4ff3a36 | 4304 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4305 | |
4306 | struct mlx5_ifc_sqc_bits ctx; | |
4307 | }; | |
4308 | ||
4309 | struct mlx5_ifc_modify_rqt_out_bits { | |
4310 | u8 status[0x8]; | |
b4ff3a36 | 4311 | u8 reserved_at_8[0x18]; |
e281682b SM |
4312 | |
4313 | u8 syndrome[0x20]; | |
4314 | ||
b4ff3a36 | 4315 | u8 reserved_at_40[0x40]; |
e281682b SM |
4316 | }; |
4317 | ||
5c50368f | 4318 | struct mlx5_ifc_rqt_bitmask_bits { |
b4ff3a36 | 4319 | u8 reserved_at_0[0x20]; |
5c50368f | 4320 | |
b4ff3a36 | 4321 | u8 reserved_at_20[0x1f]; |
5c50368f AS |
4322 | u8 rqn_list[0x1]; |
4323 | }; | |
4324 | ||
e281682b SM |
4325 | struct mlx5_ifc_modify_rqt_in_bits { |
4326 | u8 opcode[0x10]; | |
b4ff3a36 | 4327 | u8 reserved_at_10[0x10]; |
e281682b | 4328 | |
b4ff3a36 | 4329 | u8 reserved_at_20[0x10]; |
e281682b SM |
4330 | u8 op_mod[0x10]; |
4331 | ||
b4ff3a36 | 4332 | u8 reserved_at_40[0x8]; |
e281682b SM |
4333 | u8 rqtn[0x18]; |
4334 | ||
b4ff3a36 | 4335 | u8 reserved_at_60[0x20]; |
e281682b | 4336 | |
5c50368f | 4337 | struct mlx5_ifc_rqt_bitmask_bits bitmask; |
e281682b | 4338 | |
b4ff3a36 | 4339 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4340 | |
4341 | struct mlx5_ifc_rqtc_bits ctx; | |
4342 | }; | |
4343 | ||
4344 | struct mlx5_ifc_modify_rq_out_bits { | |
4345 | u8 status[0x8]; | |
b4ff3a36 | 4346 | u8 reserved_at_8[0x18]; |
e281682b SM |
4347 | |
4348 | u8 syndrome[0x20]; | |
4349 | ||
b4ff3a36 | 4350 | u8 reserved_at_40[0x40]; |
e281682b SM |
4351 | }; |
4352 | ||
4353 | struct mlx5_ifc_modify_rq_in_bits { | |
4354 | u8 opcode[0x10]; | |
b4ff3a36 | 4355 | u8 reserved_at_10[0x10]; |
e281682b | 4356 | |
b4ff3a36 | 4357 | u8 reserved_at_20[0x10]; |
e281682b SM |
4358 | u8 op_mod[0x10]; |
4359 | ||
4360 | u8 rq_state[0x4]; | |
b4ff3a36 | 4361 | u8 reserved_at_44[0x4]; |
e281682b SM |
4362 | u8 rqn[0x18]; |
4363 | ||
b4ff3a36 | 4364 | u8 reserved_at_60[0x20]; |
e281682b SM |
4365 | |
4366 | u8 modify_bitmask[0x40]; | |
4367 | ||
b4ff3a36 | 4368 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4369 | |
4370 | struct mlx5_ifc_rqc_bits ctx; | |
4371 | }; | |
4372 | ||
4373 | struct mlx5_ifc_modify_rmp_out_bits { | |
4374 | u8 status[0x8]; | |
b4ff3a36 | 4375 | u8 reserved_at_8[0x18]; |
e281682b SM |
4376 | |
4377 | u8 syndrome[0x20]; | |
4378 | ||
b4ff3a36 | 4379 | u8 reserved_at_40[0x40]; |
e281682b SM |
4380 | }; |
4381 | ||
01949d01 | 4382 | struct mlx5_ifc_rmp_bitmask_bits { |
b4ff3a36 | 4383 | u8 reserved_at_0[0x20]; |
01949d01 | 4384 | |
b4ff3a36 | 4385 | u8 reserved_at_20[0x1f]; |
01949d01 HA |
4386 | u8 lwm[0x1]; |
4387 | }; | |
4388 | ||
e281682b SM |
4389 | struct mlx5_ifc_modify_rmp_in_bits { |
4390 | u8 opcode[0x10]; | |
b4ff3a36 | 4391 | u8 reserved_at_10[0x10]; |
e281682b | 4392 | |
b4ff3a36 | 4393 | u8 reserved_at_20[0x10]; |
e281682b SM |
4394 | u8 op_mod[0x10]; |
4395 | ||
4396 | u8 rmp_state[0x4]; | |
b4ff3a36 | 4397 | u8 reserved_at_44[0x4]; |
e281682b SM |
4398 | u8 rmpn[0x18]; |
4399 | ||
b4ff3a36 | 4400 | u8 reserved_at_60[0x20]; |
e281682b | 4401 | |
01949d01 | 4402 | struct mlx5_ifc_rmp_bitmask_bits bitmask; |
e281682b | 4403 | |
b4ff3a36 | 4404 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4405 | |
4406 | struct mlx5_ifc_rmpc_bits ctx; | |
4407 | }; | |
4408 | ||
4409 | struct mlx5_ifc_modify_nic_vport_context_out_bits { | |
4410 | u8 status[0x8]; | |
b4ff3a36 | 4411 | u8 reserved_at_8[0x18]; |
e281682b SM |
4412 | |
4413 | u8 syndrome[0x20]; | |
4414 | ||
b4ff3a36 | 4415 | u8 reserved_at_40[0x40]; |
e281682b SM |
4416 | }; |
4417 | ||
4418 | struct mlx5_ifc_modify_nic_vport_field_select_bits { | |
b4ff3a36 | 4419 | u8 reserved_at_0[0x19]; |
d82b7318 SM |
4420 | u8 mtu[0x1]; |
4421 | u8 change_event[0x1]; | |
4422 | u8 promisc[0x1]; | |
e281682b SM |
4423 | u8 permanent_address[0x1]; |
4424 | u8 addresses_list[0x1]; | |
4425 | u8 roce_en[0x1]; | |
b4ff3a36 | 4426 | u8 reserved_at_1f[0x1]; |
e281682b SM |
4427 | }; |
4428 | ||
4429 | struct mlx5_ifc_modify_nic_vport_context_in_bits { | |
4430 | u8 opcode[0x10]; | |
b4ff3a36 | 4431 | u8 reserved_at_10[0x10]; |
e281682b | 4432 | |
b4ff3a36 | 4433 | u8 reserved_at_20[0x10]; |
e281682b SM |
4434 | u8 op_mod[0x10]; |
4435 | ||
4436 | u8 other_vport[0x1]; | |
b4ff3a36 | 4437 | u8 reserved_at_41[0xf]; |
e281682b SM |
4438 | u8 vport_number[0x10]; |
4439 | ||
4440 | struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; | |
4441 | ||
b4ff3a36 | 4442 | u8 reserved_at_80[0x780]; |
e281682b SM |
4443 | |
4444 | struct mlx5_ifc_nic_vport_context_bits nic_vport_context; | |
4445 | }; | |
4446 | ||
4447 | struct mlx5_ifc_modify_hca_vport_context_out_bits { | |
4448 | u8 status[0x8]; | |
b4ff3a36 | 4449 | u8 reserved_at_8[0x18]; |
e281682b SM |
4450 | |
4451 | u8 syndrome[0x20]; | |
4452 | ||
b4ff3a36 | 4453 | u8 reserved_at_40[0x40]; |
e281682b SM |
4454 | }; |
4455 | ||
4456 | struct mlx5_ifc_modify_hca_vport_context_in_bits { | |
4457 | u8 opcode[0x10]; | |
b4ff3a36 | 4458 | u8 reserved_at_10[0x10]; |
e281682b | 4459 | |
b4ff3a36 | 4460 | u8 reserved_at_20[0x10]; |
e281682b SM |
4461 | u8 op_mod[0x10]; |
4462 | ||
4463 | u8 other_vport[0x1]; | |
b4ff3a36 | 4464 | u8 reserved_at_41[0xb]; |
707c4602 | 4465 | u8 port_num[0x4]; |
e281682b SM |
4466 | u8 vport_number[0x10]; |
4467 | ||
b4ff3a36 | 4468 | u8 reserved_at_60[0x20]; |
e281682b SM |
4469 | |
4470 | struct mlx5_ifc_hca_vport_context_bits hca_vport_context; | |
4471 | }; | |
4472 | ||
4473 | struct mlx5_ifc_modify_cq_out_bits { | |
4474 | u8 status[0x8]; | |
b4ff3a36 | 4475 | u8 reserved_at_8[0x18]; |
e281682b SM |
4476 | |
4477 | u8 syndrome[0x20]; | |
4478 | ||
b4ff3a36 | 4479 | u8 reserved_at_40[0x40]; |
e281682b SM |
4480 | }; |
4481 | ||
4482 | enum { | |
4483 | MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, | |
4484 | MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, | |
4485 | }; | |
4486 | ||
4487 | struct mlx5_ifc_modify_cq_in_bits { | |
4488 | u8 opcode[0x10]; | |
b4ff3a36 | 4489 | u8 reserved_at_10[0x10]; |
e281682b | 4490 | |
b4ff3a36 | 4491 | u8 reserved_at_20[0x10]; |
e281682b SM |
4492 | u8 op_mod[0x10]; |
4493 | ||
b4ff3a36 | 4494 | u8 reserved_at_40[0x8]; |
e281682b SM |
4495 | u8 cqn[0x18]; |
4496 | ||
4497 | union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; | |
4498 | ||
4499 | struct mlx5_ifc_cqc_bits cq_context; | |
4500 | ||
b4ff3a36 | 4501 | u8 reserved_at_280[0x600]; |
e281682b SM |
4502 | |
4503 | u8 pas[0][0x40]; | |
4504 | }; | |
4505 | ||
4506 | struct mlx5_ifc_modify_cong_status_out_bits { | |
4507 | u8 status[0x8]; | |
b4ff3a36 | 4508 | u8 reserved_at_8[0x18]; |
e281682b SM |
4509 | |
4510 | u8 syndrome[0x20]; | |
4511 | ||
b4ff3a36 | 4512 | u8 reserved_at_40[0x40]; |
e281682b SM |
4513 | }; |
4514 | ||
4515 | struct mlx5_ifc_modify_cong_status_in_bits { | |
4516 | u8 opcode[0x10]; | |
b4ff3a36 | 4517 | u8 reserved_at_10[0x10]; |
e281682b | 4518 | |
b4ff3a36 | 4519 | u8 reserved_at_20[0x10]; |
e281682b SM |
4520 | u8 op_mod[0x10]; |
4521 | ||
b4ff3a36 | 4522 | u8 reserved_at_40[0x18]; |
e281682b SM |
4523 | u8 priority[0x4]; |
4524 | u8 cong_protocol[0x4]; | |
4525 | ||
4526 | u8 enable[0x1]; | |
4527 | u8 tag_enable[0x1]; | |
b4ff3a36 | 4528 | u8 reserved_at_62[0x1e]; |
e281682b SM |
4529 | }; |
4530 | ||
4531 | struct mlx5_ifc_modify_cong_params_out_bits { | |
4532 | u8 status[0x8]; | |
b4ff3a36 | 4533 | u8 reserved_at_8[0x18]; |
e281682b SM |
4534 | |
4535 | u8 syndrome[0x20]; | |
4536 | ||
b4ff3a36 | 4537 | u8 reserved_at_40[0x40]; |
e281682b SM |
4538 | }; |
4539 | ||
4540 | struct mlx5_ifc_modify_cong_params_in_bits { | |
4541 | u8 opcode[0x10]; | |
b4ff3a36 | 4542 | u8 reserved_at_10[0x10]; |
e281682b | 4543 | |
b4ff3a36 | 4544 | u8 reserved_at_20[0x10]; |
e281682b SM |
4545 | u8 op_mod[0x10]; |
4546 | ||
b4ff3a36 | 4547 | u8 reserved_at_40[0x1c]; |
e281682b SM |
4548 | u8 cong_protocol[0x4]; |
4549 | ||
4550 | union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; | |
4551 | ||
b4ff3a36 | 4552 | u8 reserved_at_80[0x80]; |
e281682b SM |
4553 | |
4554 | union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; | |
4555 | }; | |
4556 | ||
4557 | struct mlx5_ifc_manage_pages_out_bits { | |
4558 | u8 status[0x8]; | |
b4ff3a36 | 4559 | u8 reserved_at_8[0x18]; |
e281682b SM |
4560 | |
4561 | u8 syndrome[0x20]; | |
4562 | ||
4563 | u8 output_num_entries[0x20]; | |
4564 | ||
b4ff3a36 | 4565 | u8 reserved_at_60[0x20]; |
e281682b SM |
4566 | |
4567 | u8 pas[0][0x40]; | |
4568 | }; | |
4569 | ||
4570 | enum { | |
4571 | MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, | |
4572 | MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, | |
4573 | MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, | |
4574 | }; | |
4575 | ||
4576 | struct mlx5_ifc_manage_pages_in_bits { | |
4577 | u8 opcode[0x10]; | |
b4ff3a36 | 4578 | u8 reserved_at_10[0x10]; |
e281682b | 4579 | |
b4ff3a36 | 4580 | u8 reserved_at_20[0x10]; |
e281682b SM |
4581 | u8 op_mod[0x10]; |
4582 | ||
b4ff3a36 | 4583 | u8 reserved_at_40[0x10]; |
e281682b SM |
4584 | u8 function_id[0x10]; |
4585 | ||
4586 | u8 input_num_entries[0x20]; | |
4587 | ||
4588 | u8 pas[0][0x40]; | |
4589 | }; | |
4590 | ||
4591 | struct mlx5_ifc_mad_ifc_out_bits { | |
4592 | u8 status[0x8]; | |
b4ff3a36 | 4593 | u8 reserved_at_8[0x18]; |
e281682b SM |
4594 | |
4595 | u8 syndrome[0x20]; | |
4596 | ||
b4ff3a36 | 4597 | u8 reserved_at_40[0x40]; |
e281682b SM |
4598 | |
4599 | u8 response_mad_packet[256][0x8]; | |
4600 | }; | |
4601 | ||
4602 | struct mlx5_ifc_mad_ifc_in_bits { | |
4603 | u8 opcode[0x10]; | |
b4ff3a36 | 4604 | u8 reserved_at_10[0x10]; |
e281682b | 4605 | |
b4ff3a36 | 4606 | u8 reserved_at_20[0x10]; |
e281682b SM |
4607 | u8 op_mod[0x10]; |
4608 | ||
4609 | u8 remote_lid[0x10]; | |
b4ff3a36 | 4610 | u8 reserved_at_50[0x8]; |
e281682b SM |
4611 | u8 port[0x8]; |
4612 | ||
b4ff3a36 | 4613 | u8 reserved_at_60[0x20]; |
e281682b SM |
4614 | |
4615 | u8 mad[256][0x8]; | |
4616 | }; | |
4617 | ||
4618 | struct mlx5_ifc_init_hca_out_bits { | |
4619 | u8 status[0x8]; | |
b4ff3a36 | 4620 | u8 reserved_at_8[0x18]; |
e281682b SM |
4621 | |
4622 | u8 syndrome[0x20]; | |
4623 | ||
b4ff3a36 | 4624 | u8 reserved_at_40[0x40]; |
e281682b SM |
4625 | }; |
4626 | ||
4627 | struct mlx5_ifc_init_hca_in_bits { | |
4628 | u8 opcode[0x10]; | |
b4ff3a36 | 4629 | u8 reserved_at_10[0x10]; |
e281682b | 4630 | |
b4ff3a36 | 4631 | u8 reserved_at_20[0x10]; |
e281682b SM |
4632 | u8 op_mod[0x10]; |
4633 | ||
b4ff3a36 | 4634 | u8 reserved_at_40[0x40]; |
e281682b SM |
4635 | }; |
4636 | ||
4637 | struct mlx5_ifc_init2rtr_qp_out_bits { | |
4638 | u8 status[0x8]; | |
b4ff3a36 | 4639 | u8 reserved_at_8[0x18]; |
e281682b SM |
4640 | |
4641 | u8 syndrome[0x20]; | |
4642 | ||
b4ff3a36 | 4643 | u8 reserved_at_40[0x40]; |
e281682b SM |
4644 | }; |
4645 | ||
4646 | struct mlx5_ifc_init2rtr_qp_in_bits { | |
4647 | u8 opcode[0x10]; | |
b4ff3a36 | 4648 | u8 reserved_at_10[0x10]; |
e281682b | 4649 | |
b4ff3a36 | 4650 | u8 reserved_at_20[0x10]; |
e281682b SM |
4651 | u8 op_mod[0x10]; |
4652 | ||
b4ff3a36 | 4653 | u8 reserved_at_40[0x8]; |
e281682b SM |
4654 | u8 qpn[0x18]; |
4655 | ||
b4ff3a36 | 4656 | u8 reserved_at_60[0x20]; |
e281682b SM |
4657 | |
4658 | u8 opt_param_mask[0x20]; | |
4659 | ||
b4ff3a36 | 4660 | u8 reserved_at_a0[0x20]; |
e281682b SM |
4661 | |
4662 | struct mlx5_ifc_qpc_bits qpc; | |
4663 | ||
b4ff3a36 | 4664 | u8 reserved_at_800[0x80]; |
e281682b SM |
4665 | }; |
4666 | ||
4667 | struct mlx5_ifc_init2init_qp_out_bits { | |
4668 | u8 status[0x8]; | |
b4ff3a36 | 4669 | u8 reserved_at_8[0x18]; |
e281682b SM |
4670 | |
4671 | u8 syndrome[0x20]; | |
4672 | ||
b4ff3a36 | 4673 | u8 reserved_at_40[0x40]; |
e281682b SM |
4674 | }; |
4675 | ||
4676 | struct mlx5_ifc_init2init_qp_in_bits { | |
4677 | u8 opcode[0x10]; | |
b4ff3a36 | 4678 | u8 reserved_at_10[0x10]; |
e281682b | 4679 | |
b4ff3a36 | 4680 | u8 reserved_at_20[0x10]; |
e281682b SM |
4681 | u8 op_mod[0x10]; |
4682 | ||
b4ff3a36 | 4683 | u8 reserved_at_40[0x8]; |
e281682b SM |
4684 | u8 qpn[0x18]; |
4685 | ||
b4ff3a36 | 4686 | u8 reserved_at_60[0x20]; |
e281682b SM |
4687 | |
4688 | u8 opt_param_mask[0x20]; | |
4689 | ||
b4ff3a36 | 4690 | u8 reserved_at_a0[0x20]; |
e281682b SM |
4691 | |
4692 | struct mlx5_ifc_qpc_bits qpc; | |
4693 | ||
b4ff3a36 | 4694 | u8 reserved_at_800[0x80]; |
e281682b SM |
4695 | }; |
4696 | ||
4697 | struct mlx5_ifc_get_dropped_packet_log_out_bits { | |
4698 | u8 status[0x8]; | |
b4ff3a36 | 4699 | u8 reserved_at_8[0x18]; |
e281682b SM |
4700 | |
4701 | u8 syndrome[0x20]; | |
4702 | ||
b4ff3a36 | 4703 | u8 reserved_at_40[0x40]; |
e281682b SM |
4704 | |
4705 | u8 packet_headers_log[128][0x8]; | |
4706 | ||
4707 | u8 packet_syndrome[64][0x8]; | |
4708 | }; | |
4709 | ||
4710 | struct mlx5_ifc_get_dropped_packet_log_in_bits { | |
4711 | u8 opcode[0x10]; | |
b4ff3a36 | 4712 | u8 reserved_at_10[0x10]; |
e281682b | 4713 | |
b4ff3a36 | 4714 | u8 reserved_at_20[0x10]; |
e281682b SM |
4715 | u8 op_mod[0x10]; |
4716 | ||
b4ff3a36 | 4717 | u8 reserved_at_40[0x40]; |
e281682b SM |
4718 | }; |
4719 | ||
4720 | struct mlx5_ifc_gen_eqe_in_bits { | |
4721 | u8 opcode[0x10]; | |
b4ff3a36 | 4722 | u8 reserved_at_10[0x10]; |
e281682b | 4723 | |
b4ff3a36 | 4724 | u8 reserved_at_20[0x10]; |
e281682b SM |
4725 | u8 op_mod[0x10]; |
4726 | ||
b4ff3a36 | 4727 | u8 reserved_at_40[0x18]; |
e281682b SM |
4728 | u8 eq_number[0x8]; |
4729 | ||
b4ff3a36 | 4730 | u8 reserved_at_60[0x20]; |
e281682b SM |
4731 | |
4732 | u8 eqe[64][0x8]; | |
4733 | }; | |
4734 | ||
4735 | struct mlx5_ifc_gen_eq_out_bits { | |
4736 | u8 status[0x8]; | |
b4ff3a36 | 4737 | u8 reserved_at_8[0x18]; |
e281682b SM |
4738 | |
4739 | u8 syndrome[0x20]; | |
4740 | ||
b4ff3a36 | 4741 | u8 reserved_at_40[0x40]; |
e281682b SM |
4742 | }; |
4743 | ||
4744 | struct mlx5_ifc_enable_hca_out_bits { | |
4745 | u8 status[0x8]; | |
b4ff3a36 | 4746 | u8 reserved_at_8[0x18]; |
e281682b SM |
4747 | |
4748 | u8 syndrome[0x20]; | |
4749 | ||
b4ff3a36 | 4750 | u8 reserved_at_40[0x20]; |
e281682b SM |
4751 | }; |
4752 | ||
4753 | struct mlx5_ifc_enable_hca_in_bits { | |
4754 | u8 opcode[0x10]; | |
b4ff3a36 | 4755 | u8 reserved_at_10[0x10]; |
e281682b | 4756 | |
b4ff3a36 | 4757 | u8 reserved_at_20[0x10]; |
e281682b SM |
4758 | u8 op_mod[0x10]; |
4759 | ||
b4ff3a36 | 4760 | u8 reserved_at_40[0x10]; |
e281682b SM |
4761 | u8 function_id[0x10]; |
4762 | ||
b4ff3a36 | 4763 | u8 reserved_at_60[0x20]; |
e281682b SM |
4764 | }; |
4765 | ||
4766 | struct mlx5_ifc_drain_dct_out_bits { | |
4767 | u8 status[0x8]; | |
b4ff3a36 | 4768 | u8 reserved_at_8[0x18]; |
e281682b SM |
4769 | |
4770 | u8 syndrome[0x20]; | |
4771 | ||
b4ff3a36 | 4772 | u8 reserved_at_40[0x40]; |
e281682b SM |
4773 | }; |
4774 | ||
4775 | struct mlx5_ifc_drain_dct_in_bits { | |
4776 | u8 opcode[0x10]; | |
b4ff3a36 | 4777 | u8 reserved_at_10[0x10]; |
e281682b | 4778 | |
b4ff3a36 | 4779 | u8 reserved_at_20[0x10]; |
e281682b SM |
4780 | u8 op_mod[0x10]; |
4781 | ||
b4ff3a36 | 4782 | u8 reserved_at_40[0x8]; |
e281682b SM |
4783 | u8 dctn[0x18]; |
4784 | ||
b4ff3a36 | 4785 | u8 reserved_at_60[0x20]; |
e281682b SM |
4786 | }; |
4787 | ||
4788 | struct mlx5_ifc_disable_hca_out_bits { | |
4789 | u8 status[0x8]; | |
b4ff3a36 | 4790 | u8 reserved_at_8[0x18]; |
e281682b SM |
4791 | |
4792 | u8 syndrome[0x20]; | |
4793 | ||
b4ff3a36 | 4794 | u8 reserved_at_40[0x20]; |
e281682b SM |
4795 | }; |
4796 | ||
4797 | struct mlx5_ifc_disable_hca_in_bits { | |
4798 | u8 opcode[0x10]; | |
b4ff3a36 | 4799 | u8 reserved_at_10[0x10]; |
e281682b | 4800 | |
b4ff3a36 | 4801 | u8 reserved_at_20[0x10]; |
e281682b SM |
4802 | u8 op_mod[0x10]; |
4803 | ||
b4ff3a36 | 4804 | u8 reserved_at_40[0x10]; |
e281682b SM |
4805 | u8 function_id[0x10]; |
4806 | ||
b4ff3a36 | 4807 | u8 reserved_at_60[0x20]; |
e281682b SM |
4808 | }; |
4809 | ||
4810 | struct mlx5_ifc_detach_from_mcg_out_bits { | |
4811 | u8 status[0x8]; | |
b4ff3a36 | 4812 | u8 reserved_at_8[0x18]; |
e281682b SM |
4813 | |
4814 | u8 syndrome[0x20]; | |
4815 | ||
b4ff3a36 | 4816 | u8 reserved_at_40[0x40]; |
e281682b SM |
4817 | }; |
4818 | ||
4819 | struct mlx5_ifc_detach_from_mcg_in_bits { | |
4820 | u8 opcode[0x10]; | |
b4ff3a36 | 4821 | u8 reserved_at_10[0x10]; |
e281682b | 4822 | |
b4ff3a36 | 4823 | u8 reserved_at_20[0x10]; |
e281682b SM |
4824 | u8 op_mod[0x10]; |
4825 | ||
b4ff3a36 | 4826 | u8 reserved_at_40[0x8]; |
e281682b SM |
4827 | u8 qpn[0x18]; |
4828 | ||
b4ff3a36 | 4829 | u8 reserved_at_60[0x20]; |
e281682b SM |
4830 | |
4831 | u8 multicast_gid[16][0x8]; | |
4832 | }; | |
4833 | ||
4834 | struct mlx5_ifc_destroy_xrc_srq_out_bits { | |
4835 | u8 status[0x8]; | |
b4ff3a36 | 4836 | u8 reserved_at_8[0x18]; |
e281682b SM |
4837 | |
4838 | u8 syndrome[0x20]; | |
4839 | ||
b4ff3a36 | 4840 | u8 reserved_at_40[0x40]; |
e281682b SM |
4841 | }; |
4842 | ||
4843 | struct mlx5_ifc_destroy_xrc_srq_in_bits { | |
4844 | u8 opcode[0x10]; | |
b4ff3a36 | 4845 | u8 reserved_at_10[0x10]; |
e281682b | 4846 | |
b4ff3a36 | 4847 | u8 reserved_at_20[0x10]; |
e281682b SM |
4848 | u8 op_mod[0x10]; |
4849 | ||
b4ff3a36 | 4850 | u8 reserved_at_40[0x8]; |
e281682b SM |
4851 | u8 xrc_srqn[0x18]; |
4852 | ||
b4ff3a36 | 4853 | u8 reserved_at_60[0x20]; |
e281682b SM |
4854 | }; |
4855 | ||
4856 | struct mlx5_ifc_destroy_tis_out_bits { | |
4857 | u8 status[0x8]; | |
b4ff3a36 | 4858 | u8 reserved_at_8[0x18]; |
e281682b SM |
4859 | |
4860 | u8 syndrome[0x20]; | |
4861 | ||
b4ff3a36 | 4862 | u8 reserved_at_40[0x40]; |
e281682b SM |
4863 | }; |
4864 | ||
4865 | struct mlx5_ifc_destroy_tis_in_bits { | |
4866 | u8 opcode[0x10]; | |
b4ff3a36 | 4867 | u8 reserved_at_10[0x10]; |
e281682b | 4868 | |
b4ff3a36 | 4869 | u8 reserved_at_20[0x10]; |
e281682b SM |
4870 | u8 op_mod[0x10]; |
4871 | ||
b4ff3a36 | 4872 | u8 reserved_at_40[0x8]; |
e281682b SM |
4873 | u8 tisn[0x18]; |
4874 | ||
b4ff3a36 | 4875 | u8 reserved_at_60[0x20]; |
e281682b SM |
4876 | }; |
4877 | ||
4878 | struct mlx5_ifc_destroy_tir_out_bits { | |
4879 | u8 status[0x8]; | |
b4ff3a36 | 4880 | u8 reserved_at_8[0x18]; |
e281682b SM |
4881 | |
4882 | u8 syndrome[0x20]; | |
4883 | ||
b4ff3a36 | 4884 | u8 reserved_at_40[0x40]; |
e281682b SM |
4885 | }; |
4886 | ||
4887 | struct mlx5_ifc_destroy_tir_in_bits { | |
4888 | u8 opcode[0x10]; | |
b4ff3a36 | 4889 | u8 reserved_at_10[0x10]; |
e281682b | 4890 | |
b4ff3a36 | 4891 | u8 reserved_at_20[0x10]; |
e281682b SM |
4892 | u8 op_mod[0x10]; |
4893 | ||
b4ff3a36 | 4894 | u8 reserved_at_40[0x8]; |
e281682b SM |
4895 | u8 tirn[0x18]; |
4896 | ||
b4ff3a36 | 4897 | u8 reserved_at_60[0x20]; |
e281682b SM |
4898 | }; |
4899 | ||
4900 | struct mlx5_ifc_destroy_srq_out_bits { | |
4901 | u8 status[0x8]; | |
b4ff3a36 | 4902 | u8 reserved_at_8[0x18]; |
e281682b SM |
4903 | |
4904 | u8 syndrome[0x20]; | |
4905 | ||
b4ff3a36 | 4906 | u8 reserved_at_40[0x40]; |
e281682b SM |
4907 | }; |
4908 | ||
4909 | struct mlx5_ifc_destroy_srq_in_bits { | |
4910 | u8 opcode[0x10]; | |
b4ff3a36 | 4911 | u8 reserved_at_10[0x10]; |
e281682b | 4912 | |
b4ff3a36 | 4913 | u8 reserved_at_20[0x10]; |
e281682b SM |
4914 | u8 op_mod[0x10]; |
4915 | ||
b4ff3a36 | 4916 | u8 reserved_at_40[0x8]; |
e281682b SM |
4917 | u8 srqn[0x18]; |
4918 | ||
b4ff3a36 | 4919 | u8 reserved_at_60[0x20]; |
e281682b SM |
4920 | }; |
4921 | ||
4922 | struct mlx5_ifc_destroy_sq_out_bits { | |
4923 | u8 status[0x8]; | |
b4ff3a36 | 4924 | u8 reserved_at_8[0x18]; |
e281682b SM |
4925 | |
4926 | u8 syndrome[0x20]; | |
4927 | ||
b4ff3a36 | 4928 | u8 reserved_at_40[0x40]; |
e281682b SM |
4929 | }; |
4930 | ||
4931 | struct mlx5_ifc_destroy_sq_in_bits { | |
4932 | u8 opcode[0x10]; | |
b4ff3a36 | 4933 | u8 reserved_at_10[0x10]; |
e281682b | 4934 | |
b4ff3a36 | 4935 | u8 reserved_at_20[0x10]; |
e281682b SM |
4936 | u8 op_mod[0x10]; |
4937 | ||
b4ff3a36 | 4938 | u8 reserved_at_40[0x8]; |
e281682b SM |
4939 | u8 sqn[0x18]; |
4940 | ||
b4ff3a36 | 4941 | u8 reserved_at_60[0x20]; |
e281682b SM |
4942 | }; |
4943 | ||
4944 | struct mlx5_ifc_destroy_rqt_out_bits { | |
4945 | u8 status[0x8]; | |
b4ff3a36 | 4946 | u8 reserved_at_8[0x18]; |
e281682b SM |
4947 | |
4948 | u8 syndrome[0x20]; | |
4949 | ||
b4ff3a36 | 4950 | u8 reserved_at_40[0x40]; |
e281682b SM |
4951 | }; |
4952 | ||
4953 | struct mlx5_ifc_destroy_rqt_in_bits { | |
4954 | u8 opcode[0x10]; | |
b4ff3a36 | 4955 | u8 reserved_at_10[0x10]; |
e281682b | 4956 | |
b4ff3a36 | 4957 | u8 reserved_at_20[0x10]; |
e281682b SM |
4958 | u8 op_mod[0x10]; |
4959 | ||
b4ff3a36 | 4960 | u8 reserved_at_40[0x8]; |
e281682b SM |
4961 | u8 rqtn[0x18]; |
4962 | ||
b4ff3a36 | 4963 | u8 reserved_at_60[0x20]; |
e281682b SM |
4964 | }; |
4965 | ||
4966 | struct mlx5_ifc_destroy_rq_out_bits { | |
4967 | u8 status[0x8]; | |
b4ff3a36 | 4968 | u8 reserved_at_8[0x18]; |
e281682b SM |
4969 | |
4970 | u8 syndrome[0x20]; | |
4971 | ||
b4ff3a36 | 4972 | u8 reserved_at_40[0x40]; |
e281682b SM |
4973 | }; |
4974 | ||
4975 | struct mlx5_ifc_destroy_rq_in_bits { | |
4976 | u8 opcode[0x10]; | |
b4ff3a36 | 4977 | u8 reserved_at_10[0x10]; |
e281682b | 4978 | |
b4ff3a36 | 4979 | u8 reserved_at_20[0x10]; |
e281682b SM |
4980 | u8 op_mod[0x10]; |
4981 | ||
b4ff3a36 | 4982 | u8 reserved_at_40[0x8]; |
e281682b SM |
4983 | u8 rqn[0x18]; |
4984 | ||
b4ff3a36 | 4985 | u8 reserved_at_60[0x20]; |
e281682b SM |
4986 | }; |
4987 | ||
4988 | struct mlx5_ifc_destroy_rmp_out_bits { | |
4989 | u8 status[0x8]; | |
b4ff3a36 | 4990 | u8 reserved_at_8[0x18]; |
e281682b SM |
4991 | |
4992 | u8 syndrome[0x20]; | |
4993 | ||
b4ff3a36 | 4994 | u8 reserved_at_40[0x40]; |
e281682b SM |
4995 | }; |
4996 | ||
4997 | struct mlx5_ifc_destroy_rmp_in_bits { | |
4998 | u8 opcode[0x10]; | |
b4ff3a36 | 4999 | u8 reserved_at_10[0x10]; |
e281682b | 5000 | |
b4ff3a36 | 5001 | u8 reserved_at_20[0x10]; |
e281682b SM |
5002 | u8 op_mod[0x10]; |
5003 | ||
b4ff3a36 | 5004 | u8 reserved_at_40[0x8]; |
e281682b SM |
5005 | u8 rmpn[0x18]; |
5006 | ||
b4ff3a36 | 5007 | u8 reserved_at_60[0x20]; |
e281682b SM |
5008 | }; |
5009 | ||
5010 | struct mlx5_ifc_destroy_qp_out_bits { | |
5011 | u8 status[0x8]; | |
b4ff3a36 | 5012 | u8 reserved_at_8[0x18]; |
e281682b SM |
5013 | |
5014 | u8 syndrome[0x20]; | |
5015 | ||
b4ff3a36 | 5016 | u8 reserved_at_40[0x40]; |
e281682b SM |
5017 | }; |
5018 | ||
5019 | struct mlx5_ifc_destroy_qp_in_bits { | |
5020 | u8 opcode[0x10]; | |
b4ff3a36 | 5021 | u8 reserved_at_10[0x10]; |
e281682b | 5022 | |
b4ff3a36 | 5023 | u8 reserved_at_20[0x10]; |
e281682b SM |
5024 | u8 op_mod[0x10]; |
5025 | ||
b4ff3a36 | 5026 | u8 reserved_at_40[0x8]; |
e281682b SM |
5027 | u8 qpn[0x18]; |
5028 | ||
b4ff3a36 | 5029 | u8 reserved_at_60[0x20]; |
e281682b SM |
5030 | }; |
5031 | ||
5032 | struct mlx5_ifc_destroy_psv_out_bits { | |
5033 | u8 status[0x8]; | |
b4ff3a36 | 5034 | u8 reserved_at_8[0x18]; |
e281682b SM |
5035 | |
5036 | u8 syndrome[0x20]; | |
5037 | ||
b4ff3a36 | 5038 | u8 reserved_at_40[0x40]; |
e281682b SM |
5039 | }; |
5040 | ||
5041 | struct mlx5_ifc_destroy_psv_in_bits { | |
5042 | u8 opcode[0x10]; | |
b4ff3a36 | 5043 | u8 reserved_at_10[0x10]; |
e281682b | 5044 | |
b4ff3a36 | 5045 | u8 reserved_at_20[0x10]; |
e281682b SM |
5046 | u8 op_mod[0x10]; |
5047 | ||
b4ff3a36 | 5048 | u8 reserved_at_40[0x8]; |
e281682b SM |
5049 | u8 psvn[0x18]; |
5050 | ||
b4ff3a36 | 5051 | u8 reserved_at_60[0x20]; |
e281682b SM |
5052 | }; |
5053 | ||
5054 | struct mlx5_ifc_destroy_mkey_out_bits { | |
5055 | u8 status[0x8]; | |
b4ff3a36 | 5056 | u8 reserved_at_8[0x18]; |
e281682b SM |
5057 | |
5058 | u8 syndrome[0x20]; | |
5059 | ||
b4ff3a36 | 5060 | u8 reserved_at_40[0x40]; |
e281682b SM |
5061 | }; |
5062 | ||
5063 | struct mlx5_ifc_destroy_mkey_in_bits { | |
5064 | u8 opcode[0x10]; | |
b4ff3a36 | 5065 | u8 reserved_at_10[0x10]; |
e281682b | 5066 | |
b4ff3a36 | 5067 | u8 reserved_at_20[0x10]; |
e281682b SM |
5068 | u8 op_mod[0x10]; |
5069 | ||
b4ff3a36 | 5070 | u8 reserved_at_40[0x8]; |
e281682b SM |
5071 | u8 mkey_index[0x18]; |
5072 | ||
b4ff3a36 | 5073 | u8 reserved_at_60[0x20]; |
e281682b SM |
5074 | }; |
5075 | ||
5076 | struct mlx5_ifc_destroy_flow_table_out_bits { | |
5077 | u8 status[0x8]; | |
b4ff3a36 | 5078 | u8 reserved_at_8[0x18]; |
e281682b SM |
5079 | |
5080 | u8 syndrome[0x20]; | |
5081 | ||
b4ff3a36 | 5082 | u8 reserved_at_40[0x40]; |
e281682b SM |
5083 | }; |
5084 | ||
5085 | struct mlx5_ifc_destroy_flow_table_in_bits { | |
5086 | u8 opcode[0x10]; | |
b4ff3a36 | 5087 | u8 reserved_at_10[0x10]; |
e281682b | 5088 | |
b4ff3a36 | 5089 | u8 reserved_at_20[0x10]; |
e281682b SM |
5090 | u8 op_mod[0x10]; |
5091 | ||
b4ff3a36 | 5092 | u8 reserved_at_40[0x40]; |
e281682b SM |
5093 | |
5094 | u8 table_type[0x8]; | |
b4ff3a36 | 5095 | u8 reserved_at_88[0x18]; |
e281682b | 5096 | |
b4ff3a36 | 5097 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5098 | u8 table_id[0x18]; |
5099 | ||
b4ff3a36 | 5100 | u8 reserved_at_c0[0x140]; |
e281682b SM |
5101 | }; |
5102 | ||
5103 | struct mlx5_ifc_destroy_flow_group_out_bits { | |
5104 | u8 status[0x8]; | |
b4ff3a36 | 5105 | u8 reserved_at_8[0x18]; |
e281682b SM |
5106 | |
5107 | u8 syndrome[0x20]; | |
5108 | ||
b4ff3a36 | 5109 | u8 reserved_at_40[0x40]; |
e281682b SM |
5110 | }; |
5111 | ||
5112 | struct mlx5_ifc_destroy_flow_group_in_bits { | |
5113 | u8 opcode[0x10]; | |
b4ff3a36 | 5114 | u8 reserved_at_10[0x10]; |
e281682b | 5115 | |
b4ff3a36 | 5116 | u8 reserved_at_20[0x10]; |
e281682b SM |
5117 | u8 op_mod[0x10]; |
5118 | ||
b4ff3a36 | 5119 | u8 reserved_at_40[0x40]; |
e281682b SM |
5120 | |
5121 | u8 table_type[0x8]; | |
b4ff3a36 | 5122 | u8 reserved_at_88[0x18]; |
e281682b | 5123 | |
b4ff3a36 | 5124 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5125 | u8 table_id[0x18]; |
5126 | ||
5127 | u8 group_id[0x20]; | |
5128 | ||
b4ff3a36 | 5129 | u8 reserved_at_e0[0x120]; |
e281682b SM |
5130 | }; |
5131 | ||
5132 | struct mlx5_ifc_destroy_eq_out_bits { | |
5133 | u8 status[0x8]; | |
b4ff3a36 | 5134 | u8 reserved_at_8[0x18]; |
e281682b SM |
5135 | |
5136 | u8 syndrome[0x20]; | |
5137 | ||
b4ff3a36 | 5138 | u8 reserved_at_40[0x40]; |
e281682b SM |
5139 | }; |
5140 | ||
5141 | struct mlx5_ifc_destroy_eq_in_bits { | |
5142 | u8 opcode[0x10]; | |
b4ff3a36 | 5143 | u8 reserved_at_10[0x10]; |
e281682b | 5144 | |
b4ff3a36 | 5145 | u8 reserved_at_20[0x10]; |
e281682b SM |
5146 | u8 op_mod[0x10]; |
5147 | ||
b4ff3a36 | 5148 | u8 reserved_at_40[0x18]; |
e281682b SM |
5149 | u8 eq_number[0x8]; |
5150 | ||
b4ff3a36 | 5151 | u8 reserved_at_60[0x20]; |
e281682b SM |
5152 | }; |
5153 | ||
5154 | struct mlx5_ifc_destroy_dct_out_bits { | |
5155 | u8 status[0x8]; | |
b4ff3a36 | 5156 | u8 reserved_at_8[0x18]; |
e281682b SM |
5157 | |
5158 | u8 syndrome[0x20]; | |
5159 | ||
b4ff3a36 | 5160 | u8 reserved_at_40[0x40]; |
e281682b SM |
5161 | }; |
5162 | ||
5163 | struct mlx5_ifc_destroy_dct_in_bits { | |
5164 | u8 opcode[0x10]; | |
b4ff3a36 | 5165 | u8 reserved_at_10[0x10]; |
e281682b | 5166 | |
b4ff3a36 | 5167 | u8 reserved_at_20[0x10]; |
e281682b SM |
5168 | u8 op_mod[0x10]; |
5169 | ||
b4ff3a36 | 5170 | u8 reserved_at_40[0x8]; |
e281682b SM |
5171 | u8 dctn[0x18]; |
5172 | ||
b4ff3a36 | 5173 | u8 reserved_at_60[0x20]; |
e281682b SM |
5174 | }; |
5175 | ||
5176 | struct mlx5_ifc_destroy_cq_out_bits { | |
5177 | u8 status[0x8]; | |
b4ff3a36 | 5178 | u8 reserved_at_8[0x18]; |
e281682b SM |
5179 | |
5180 | u8 syndrome[0x20]; | |
5181 | ||
b4ff3a36 | 5182 | u8 reserved_at_40[0x40]; |
e281682b SM |
5183 | }; |
5184 | ||
5185 | struct mlx5_ifc_destroy_cq_in_bits { | |
5186 | u8 opcode[0x10]; | |
b4ff3a36 | 5187 | u8 reserved_at_10[0x10]; |
e281682b | 5188 | |
b4ff3a36 | 5189 | u8 reserved_at_20[0x10]; |
e281682b SM |
5190 | u8 op_mod[0x10]; |
5191 | ||
b4ff3a36 | 5192 | u8 reserved_at_40[0x8]; |
e281682b SM |
5193 | u8 cqn[0x18]; |
5194 | ||
b4ff3a36 | 5195 | u8 reserved_at_60[0x20]; |
e281682b SM |
5196 | }; |
5197 | ||
5198 | struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { | |
5199 | u8 status[0x8]; | |
b4ff3a36 | 5200 | u8 reserved_at_8[0x18]; |
e281682b SM |
5201 | |
5202 | u8 syndrome[0x20]; | |
5203 | ||
b4ff3a36 | 5204 | u8 reserved_at_40[0x40]; |
e281682b SM |
5205 | }; |
5206 | ||
5207 | struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { | |
5208 | u8 opcode[0x10]; | |
b4ff3a36 | 5209 | u8 reserved_at_10[0x10]; |
e281682b | 5210 | |
b4ff3a36 | 5211 | u8 reserved_at_20[0x10]; |
e281682b SM |
5212 | u8 op_mod[0x10]; |
5213 | ||
b4ff3a36 | 5214 | u8 reserved_at_40[0x20]; |
e281682b | 5215 | |
b4ff3a36 | 5216 | u8 reserved_at_60[0x10]; |
e281682b SM |
5217 | u8 vxlan_udp_port[0x10]; |
5218 | }; | |
5219 | ||
5220 | struct mlx5_ifc_delete_l2_table_entry_out_bits { | |
5221 | u8 status[0x8]; | |
b4ff3a36 | 5222 | u8 reserved_at_8[0x18]; |
e281682b SM |
5223 | |
5224 | u8 syndrome[0x20]; | |
5225 | ||
b4ff3a36 | 5226 | u8 reserved_at_40[0x40]; |
e281682b SM |
5227 | }; |
5228 | ||
5229 | struct mlx5_ifc_delete_l2_table_entry_in_bits { | |
5230 | u8 opcode[0x10]; | |
b4ff3a36 | 5231 | u8 reserved_at_10[0x10]; |
e281682b | 5232 | |
b4ff3a36 | 5233 | u8 reserved_at_20[0x10]; |
e281682b SM |
5234 | u8 op_mod[0x10]; |
5235 | ||
b4ff3a36 | 5236 | u8 reserved_at_40[0x60]; |
e281682b | 5237 | |
b4ff3a36 | 5238 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5239 | u8 table_index[0x18]; |
5240 | ||
b4ff3a36 | 5241 | u8 reserved_at_c0[0x140]; |
e281682b SM |
5242 | }; |
5243 | ||
5244 | struct mlx5_ifc_delete_fte_out_bits { | |
5245 | u8 status[0x8]; | |
b4ff3a36 | 5246 | u8 reserved_at_8[0x18]; |
e281682b SM |
5247 | |
5248 | u8 syndrome[0x20]; | |
5249 | ||
b4ff3a36 | 5250 | u8 reserved_at_40[0x40]; |
e281682b SM |
5251 | }; |
5252 | ||
5253 | struct mlx5_ifc_delete_fte_in_bits { | |
5254 | u8 opcode[0x10]; | |
b4ff3a36 | 5255 | u8 reserved_at_10[0x10]; |
e281682b | 5256 | |
b4ff3a36 | 5257 | u8 reserved_at_20[0x10]; |
e281682b SM |
5258 | u8 op_mod[0x10]; |
5259 | ||
b4ff3a36 | 5260 | u8 reserved_at_40[0x40]; |
e281682b SM |
5261 | |
5262 | u8 table_type[0x8]; | |
b4ff3a36 | 5263 | u8 reserved_at_88[0x18]; |
e281682b | 5264 | |
b4ff3a36 | 5265 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5266 | u8 table_id[0x18]; |
5267 | ||
b4ff3a36 | 5268 | u8 reserved_at_c0[0x40]; |
e281682b SM |
5269 | |
5270 | u8 flow_index[0x20]; | |
5271 | ||
b4ff3a36 | 5272 | u8 reserved_at_120[0xe0]; |
e281682b SM |
5273 | }; |
5274 | ||
5275 | struct mlx5_ifc_dealloc_xrcd_out_bits { | |
5276 | u8 status[0x8]; | |
b4ff3a36 | 5277 | u8 reserved_at_8[0x18]; |
e281682b SM |
5278 | |
5279 | u8 syndrome[0x20]; | |
5280 | ||
b4ff3a36 | 5281 | u8 reserved_at_40[0x40]; |
e281682b SM |
5282 | }; |
5283 | ||
5284 | struct mlx5_ifc_dealloc_xrcd_in_bits { | |
5285 | u8 opcode[0x10]; | |
b4ff3a36 | 5286 | u8 reserved_at_10[0x10]; |
e281682b | 5287 | |
b4ff3a36 | 5288 | u8 reserved_at_20[0x10]; |
e281682b SM |
5289 | u8 op_mod[0x10]; |
5290 | ||
b4ff3a36 | 5291 | u8 reserved_at_40[0x8]; |
e281682b SM |
5292 | u8 xrcd[0x18]; |
5293 | ||
b4ff3a36 | 5294 | u8 reserved_at_60[0x20]; |
e281682b SM |
5295 | }; |
5296 | ||
5297 | struct mlx5_ifc_dealloc_uar_out_bits { | |
5298 | u8 status[0x8]; | |
b4ff3a36 | 5299 | u8 reserved_at_8[0x18]; |
e281682b SM |
5300 | |
5301 | u8 syndrome[0x20]; | |
5302 | ||
b4ff3a36 | 5303 | u8 reserved_at_40[0x40]; |
e281682b SM |
5304 | }; |
5305 | ||
5306 | struct mlx5_ifc_dealloc_uar_in_bits { | |
5307 | u8 opcode[0x10]; | |
b4ff3a36 | 5308 | u8 reserved_at_10[0x10]; |
e281682b | 5309 | |
b4ff3a36 | 5310 | u8 reserved_at_20[0x10]; |
e281682b SM |
5311 | u8 op_mod[0x10]; |
5312 | ||
b4ff3a36 | 5313 | u8 reserved_at_40[0x8]; |
e281682b SM |
5314 | u8 uar[0x18]; |
5315 | ||
b4ff3a36 | 5316 | u8 reserved_at_60[0x20]; |
e281682b SM |
5317 | }; |
5318 | ||
5319 | struct mlx5_ifc_dealloc_transport_domain_out_bits { | |
5320 | u8 status[0x8]; | |
b4ff3a36 | 5321 | u8 reserved_at_8[0x18]; |
e281682b SM |
5322 | |
5323 | u8 syndrome[0x20]; | |
5324 | ||
b4ff3a36 | 5325 | u8 reserved_at_40[0x40]; |
e281682b SM |
5326 | }; |
5327 | ||
5328 | struct mlx5_ifc_dealloc_transport_domain_in_bits { | |
5329 | u8 opcode[0x10]; | |
b4ff3a36 | 5330 | u8 reserved_at_10[0x10]; |
e281682b | 5331 | |
b4ff3a36 | 5332 | u8 reserved_at_20[0x10]; |
e281682b SM |
5333 | u8 op_mod[0x10]; |
5334 | ||
b4ff3a36 | 5335 | u8 reserved_at_40[0x8]; |
e281682b SM |
5336 | u8 transport_domain[0x18]; |
5337 | ||
b4ff3a36 | 5338 | u8 reserved_at_60[0x20]; |
e281682b SM |
5339 | }; |
5340 | ||
5341 | struct mlx5_ifc_dealloc_q_counter_out_bits { | |
5342 | u8 status[0x8]; | |
b4ff3a36 | 5343 | u8 reserved_at_8[0x18]; |
e281682b SM |
5344 | |
5345 | u8 syndrome[0x20]; | |
5346 | ||
b4ff3a36 | 5347 | u8 reserved_at_40[0x40]; |
e281682b SM |
5348 | }; |
5349 | ||
5350 | struct mlx5_ifc_dealloc_q_counter_in_bits { | |
5351 | u8 opcode[0x10]; | |
b4ff3a36 | 5352 | u8 reserved_at_10[0x10]; |
e281682b | 5353 | |
b4ff3a36 | 5354 | u8 reserved_at_20[0x10]; |
e281682b SM |
5355 | u8 op_mod[0x10]; |
5356 | ||
b4ff3a36 | 5357 | u8 reserved_at_40[0x18]; |
e281682b SM |
5358 | u8 counter_set_id[0x8]; |
5359 | ||
b4ff3a36 | 5360 | u8 reserved_at_60[0x20]; |
e281682b SM |
5361 | }; |
5362 | ||
5363 | struct mlx5_ifc_dealloc_pd_out_bits { | |
5364 | u8 status[0x8]; | |
b4ff3a36 | 5365 | u8 reserved_at_8[0x18]; |
e281682b SM |
5366 | |
5367 | u8 syndrome[0x20]; | |
5368 | ||
b4ff3a36 | 5369 | u8 reserved_at_40[0x40]; |
e281682b SM |
5370 | }; |
5371 | ||
5372 | struct mlx5_ifc_dealloc_pd_in_bits { | |
5373 | u8 opcode[0x10]; | |
b4ff3a36 | 5374 | u8 reserved_at_10[0x10]; |
e281682b | 5375 | |
b4ff3a36 | 5376 | u8 reserved_at_20[0x10]; |
e281682b SM |
5377 | u8 op_mod[0x10]; |
5378 | ||
b4ff3a36 | 5379 | u8 reserved_at_40[0x8]; |
e281682b SM |
5380 | u8 pd[0x18]; |
5381 | ||
b4ff3a36 | 5382 | u8 reserved_at_60[0x20]; |
e281682b SM |
5383 | }; |
5384 | ||
5385 | struct mlx5_ifc_create_xrc_srq_out_bits { | |
5386 | u8 status[0x8]; | |
b4ff3a36 | 5387 | u8 reserved_at_8[0x18]; |
e281682b SM |
5388 | |
5389 | u8 syndrome[0x20]; | |
5390 | ||
b4ff3a36 | 5391 | u8 reserved_at_40[0x8]; |
e281682b SM |
5392 | u8 xrc_srqn[0x18]; |
5393 | ||
b4ff3a36 | 5394 | u8 reserved_at_60[0x20]; |
e281682b SM |
5395 | }; |
5396 | ||
5397 | struct mlx5_ifc_create_xrc_srq_in_bits { | |
5398 | u8 opcode[0x10]; | |
b4ff3a36 | 5399 | u8 reserved_at_10[0x10]; |
e281682b | 5400 | |
b4ff3a36 | 5401 | u8 reserved_at_20[0x10]; |
e281682b SM |
5402 | u8 op_mod[0x10]; |
5403 | ||
b4ff3a36 | 5404 | u8 reserved_at_40[0x40]; |
e281682b SM |
5405 | |
5406 | struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | |
5407 | ||
b4ff3a36 | 5408 | u8 reserved_at_280[0x600]; |
e281682b SM |
5409 | |
5410 | u8 pas[0][0x40]; | |
5411 | }; | |
5412 | ||
5413 | struct mlx5_ifc_create_tis_out_bits { | |
5414 | u8 status[0x8]; | |
b4ff3a36 | 5415 | u8 reserved_at_8[0x18]; |
e281682b SM |
5416 | |
5417 | u8 syndrome[0x20]; | |
5418 | ||
b4ff3a36 | 5419 | u8 reserved_at_40[0x8]; |
e281682b SM |
5420 | u8 tisn[0x18]; |
5421 | ||
b4ff3a36 | 5422 | u8 reserved_at_60[0x20]; |
e281682b SM |
5423 | }; |
5424 | ||
5425 | struct mlx5_ifc_create_tis_in_bits { | |
5426 | u8 opcode[0x10]; | |
b4ff3a36 | 5427 | u8 reserved_at_10[0x10]; |
e281682b | 5428 | |
b4ff3a36 | 5429 | u8 reserved_at_20[0x10]; |
e281682b SM |
5430 | u8 op_mod[0x10]; |
5431 | ||
b4ff3a36 | 5432 | u8 reserved_at_40[0xc0]; |
e281682b SM |
5433 | |
5434 | struct mlx5_ifc_tisc_bits ctx; | |
5435 | }; | |
5436 | ||
5437 | struct mlx5_ifc_create_tir_out_bits { | |
5438 | u8 status[0x8]; | |
b4ff3a36 | 5439 | u8 reserved_at_8[0x18]; |
e281682b SM |
5440 | |
5441 | u8 syndrome[0x20]; | |
5442 | ||
b4ff3a36 | 5443 | u8 reserved_at_40[0x8]; |
e281682b SM |
5444 | u8 tirn[0x18]; |
5445 | ||
b4ff3a36 | 5446 | u8 reserved_at_60[0x20]; |
e281682b SM |
5447 | }; |
5448 | ||
5449 | struct mlx5_ifc_create_tir_in_bits { | |
5450 | u8 opcode[0x10]; | |
b4ff3a36 | 5451 | u8 reserved_at_10[0x10]; |
e281682b | 5452 | |
b4ff3a36 | 5453 | u8 reserved_at_20[0x10]; |
e281682b SM |
5454 | u8 op_mod[0x10]; |
5455 | ||
b4ff3a36 | 5456 | u8 reserved_at_40[0xc0]; |
e281682b SM |
5457 | |
5458 | struct mlx5_ifc_tirc_bits ctx; | |
5459 | }; | |
5460 | ||
5461 | struct mlx5_ifc_create_srq_out_bits { | |
5462 | u8 status[0x8]; | |
b4ff3a36 | 5463 | u8 reserved_at_8[0x18]; |
e281682b SM |
5464 | |
5465 | u8 syndrome[0x20]; | |
5466 | ||
b4ff3a36 | 5467 | u8 reserved_at_40[0x8]; |
e281682b SM |
5468 | u8 srqn[0x18]; |
5469 | ||
b4ff3a36 | 5470 | u8 reserved_at_60[0x20]; |
e281682b SM |
5471 | }; |
5472 | ||
5473 | struct mlx5_ifc_create_srq_in_bits { | |
5474 | u8 opcode[0x10]; | |
b4ff3a36 | 5475 | u8 reserved_at_10[0x10]; |
e281682b | 5476 | |
b4ff3a36 | 5477 | u8 reserved_at_20[0x10]; |
e281682b SM |
5478 | u8 op_mod[0x10]; |
5479 | ||
b4ff3a36 | 5480 | u8 reserved_at_40[0x40]; |
e281682b SM |
5481 | |
5482 | struct mlx5_ifc_srqc_bits srq_context_entry; | |
5483 | ||
b4ff3a36 | 5484 | u8 reserved_at_280[0x600]; |
e281682b SM |
5485 | |
5486 | u8 pas[0][0x40]; | |
5487 | }; | |
5488 | ||
5489 | struct mlx5_ifc_create_sq_out_bits { | |
5490 | u8 status[0x8]; | |
b4ff3a36 | 5491 | u8 reserved_at_8[0x18]; |
e281682b SM |
5492 | |
5493 | u8 syndrome[0x20]; | |
5494 | ||
b4ff3a36 | 5495 | u8 reserved_at_40[0x8]; |
e281682b SM |
5496 | u8 sqn[0x18]; |
5497 | ||
b4ff3a36 | 5498 | u8 reserved_at_60[0x20]; |
e281682b SM |
5499 | }; |
5500 | ||
5501 | struct mlx5_ifc_create_sq_in_bits { | |
5502 | u8 opcode[0x10]; | |
b4ff3a36 | 5503 | u8 reserved_at_10[0x10]; |
e281682b | 5504 | |
b4ff3a36 | 5505 | u8 reserved_at_20[0x10]; |
e281682b SM |
5506 | u8 op_mod[0x10]; |
5507 | ||
b4ff3a36 | 5508 | u8 reserved_at_40[0xc0]; |
e281682b SM |
5509 | |
5510 | struct mlx5_ifc_sqc_bits ctx; | |
5511 | }; | |
5512 | ||
5513 | struct mlx5_ifc_create_rqt_out_bits { | |
5514 | u8 status[0x8]; | |
b4ff3a36 | 5515 | u8 reserved_at_8[0x18]; |
e281682b SM |
5516 | |
5517 | u8 syndrome[0x20]; | |
5518 | ||
b4ff3a36 | 5519 | u8 reserved_at_40[0x8]; |
e281682b SM |
5520 | u8 rqtn[0x18]; |
5521 | ||
b4ff3a36 | 5522 | u8 reserved_at_60[0x20]; |
e281682b SM |
5523 | }; |
5524 | ||
5525 | struct mlx5_ifc_create_rqt_in_bits { | |
5526 | u8 opcode[0x10]; | |
b4ff3a36 | 5527 | u8 reserved_at_10[0x10]; |
e281682b | 5528 | |
b4ff3a36 | 5529 | u8 reserved_at_20[0x10]; |
e281682b SM |
5530 | u8 op_mod[0x10]; |
5531 | ||
b4ff3a36 | 5532 | u8 reserved_at_40[0xc0]; |
e281682b SM |
5533 | |
5534 | struct mlx5_ifc_rqtc_bits rqt_context; | |
5535 | }; | |
5536 | ||
5537 | struct mlx5_ifc_create_rq_out_bits { | |
5538 | u8 status[0x8]; | |
b4ff3a36 | 5539 | u8 reserved_at_8[0x18]; |
e281682b SM |
5540 | |
5541 | u8 syndrome[0x20]; | |
5542 | ||
b4ff3a36 | 5543 | u8 reserved_at_40[0x8]; |
e281682b SM |
5544 | u8 rqn[0x18]; |
5545 | ||
b4ff3a36 | 5546 | u8 reserved_at_60[0x20]; |
e281682b SM |
5547 | }; |
5548 | ||
5549 | struct mlx5_ifc_create_rq_in_bits { | |
5550 | u8 opcode[0x10]; | |
b4ff3a36 | 5551 | u8 reserved_at_10[0x10]; |
e281682b | 5552 | |
b4ff3a36 | 5553 | u8 reserved_at_20[0x10]; |
e281682b SM |
5554 | u8 op_mod[0x10]; |
5555 | ||
b4ff3a36 | 5556 | u8 reserved_at_40[0xc0]; |
e281682b SM |
5557 | |
5558 | struct mlx5_ifc_rqc_bits ctx; | |
5559 | }; | |
5560 | ||
5561 | struct mlx5_ifc_create_rmp_out_bits { | |
5562 | u8 status[0x8]; | |
b4ff3a36 | 5563 | u8 reserved_at_8[0x18]; |
e281682b SM |
5564 | |
5565 | u8 syndrome[0x20]; | |
5566 | ||
b4ff3a36 | 5567 | u8 reserved_at_40[0x8]; |
e281682b SM |
5568 | u8 rmpn[0x18]; |
5569 | ||
b4ff3a36 | 5570 | u8 reserved_at_60[0x20]; |
e281682b SM |
5571 | }; |
5572 | ||
5573 | struct mlx5_ifc_create_rmp_in_bits { | |
5574 | u8 opcode[0x10]; | |
b4ff3a36 | 5575 | u8 reserved_at_10[0x10]; |
e281682b | 5576 | |
b4ff3a36 | 5577 | u8 reserved_at_20[0x10]; |
e281682b SM |
5578 | u8 op_mod[0x10]; |
5579 | ||
b4ff3a36 | 5580 | u8 reserved_at_40[0xc0]; |
e281682b SM |
5581 | |
5582 | struct mlx5_ifc_rmpc_bits ctx; | |
5583 | }; | |
5584 | ||
5585 | struct mlx5_ifc_create_qp_out_bits { | |
5586 | u8 status[0x8]; | |
b4ff3a36 | 5587 | u8 reserved_at_8[0x18]; |
e281682b SM |
5588 | |
5589 | u8 syndrome[0x20]; | |
5590 | ||
b4ff3a36 | 5591 | u8 reserved_at_40[0x8]; |
e281682b SM |
5592 | u8 qpn[0x18]; |
5593 | ||
b4ff3a36 | 5594 | u8 reserved_at_60[0x20]; |
e281682b SM |
5595 | }; |
5596 | ||
5597 | struct mlx5_ifc_create_qp_in_bits { | |
5598 | u8 opcode[0x10]; | |
b4ff3a36 | 5599 | u8 reserved_at_10[0x10]; |
e281682b | 5600 | |
b4ff3a36 | 5601 | u8 reserved_at_20[0x10]; |
e281682b SM |
5602 | u8 op_mod[0x10]; |
5603 | ||
b4ff3a36 | 5604 | u8 reserved_at_40[0x40]; |
e281682b SM |
5605 | |
5606 | u8 opt_param_mask[0x20]; | |
5607 | ||
b4ff3a36 | 5608 | u8 reserved_at_a0[0x20]; |
e281682b SM |
5609 | |
5610 | struct mlx5_ifc_qpc_bits qpc; | |
5611 | ||
b4ff3a36 | 5612 | u8 reserved_at_800[0x80]; |
e281682b SM |
5613 | |
5614 | u8 pas[0][0x40]; | |
5615 | }; | |
5616 | ||
5617 | struct mlx5_ifc_create_psv_out_bits { | |
5618 | u8 status[0x8]; | |
b4ff3a36 | 5619 | u8 reserved_at_8[0x18]; |
e281682b SM |
5620 | |
5621 | u8 syndrome[0x20]; | |
5622 | ||
b4ff3a36 | 5623 | u8 reserved_at_40[0x40]; |
e281682b | 5624 | |
b4ff3a36 | 5625 | u8 reserved_at_80[0x8]; |
e281682b SM |
5626 | u8 psv0_index[0x18]; |
5627 | ||
b4ff3a36 | 5628 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5629 | u8 psv1_index[0x18]; |
5630 | ||
b4ff3a36 | 5631 | u8 reserved_at_c0[0x8]; |
e281682b SM |
5632 | u8 psv2_index[0x18]; |
5633 | ||
b4ff3a36 | 5634 | u8 reserved_at_e0[0x8]; |
e281682b SM |
5635 | u8 psv3_index[0x18]; |
5636 | }; | |
5637 | ||
5638 | struct mlx5_ifc_create_psv_in_bits { | |
5639 | u8 opcode[0x10]; | |
b4ff3a36 | 5640 | u8 reserved_at_10[0x10]; |
e281682b | 5641 | |
b4ff3a36 | 5642 | u8 reserved_at_20[0x10]; |
e281682b SM |
5643 | u8 op_mod[0x10]; |
5644 | ||
5645 | u8 num_psv[0x4]; | |
b4ff3a36 | 5646 | u8 reserved_at_44[0x4]; |
e281682b SM |
5647 | u8 pd[0x18]; |
5648 | ||
b4ff3a36 | 5649 | u8 reserved_at_60[0x20]; |
e281682b SM |
5650 | }; |
5651 | ||
5652 | struct mlx5_ifc_create_mkey_out_bits { | |
5653 | u8 status[0x8]; | |
b4ff3a36 | 5654 | u8 reserved_at_8[0x18]; |
e281682b SM |
5655 | |
5656 | u8 syndrome[0x20]; | |
5657 | ||
b4ff3a36 | 5658 | u8 reserved_at_40[0x8]; |
e281682b SM |
5659 | u8 mkey_index[0x18]; |
5660 | ||
b4ff3a36 | 5661 | u8 reserved_at_60[0x20]; |
e281682b SM |
5662 | }; |
5663 | ||
5664 | struct mlx5_ifc_create_mkey_in_bits { | |
5665 | u8 opcode[0x10]; | |
b4ff3a36 | 5666 | u8 reserved_at_10[0x10]; |
e281682b | 5667 | |
b4ff3a36 | 5668 | u8 reserved_at_20[0x10]; |
e281682b SM |
5669 | u8 op_mod[0x10]; |
5670 | ||
b4ff3a36 | 5671 | u8 reserved_at_40[0x20]; |
e281682b SM |
5672 | |
5673 | u8 pg_access[0x1]; | |
b4ff3a36 | 5674 | u8 reserved_at_61[0x1f]; |
e281682b SM |
5675 | |
5676 | struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | |
5677 | ||
b4ff3a36 | 5678 | u8 reserved_at_280[0x80]; |
e281682b SM |
5679 | |
5680 | u8 translations_octword_actual_size[0x20]; | |
5681 | ||
b4ff3a36 | 5682 | u8 reserved_at_320[0x560]; |
e281682b SM |
5683 | |
5684 | u8 klm_pas_mtt[0][0x20]; | |
5685 | }; | |
5686 | ||
5687 | struct mlx5_ifc_create_flow_table_out_bits { | |
5688 | u8 status[0x8]; | |
b4ff3a36 | 5689 | u8 reserved_at_8[0x18]; |
e281682b SM |
5690 | |
5691 | u8 syndrome[0x20]; | |
5692 | ||
b4ff3a36 | 5693 | u8 reserved_at_40[0x8]; |
e281682b SM |
5694 | u8 table_id[0x18]; |
5695 | ||
b4ff3a36 | 5696 | u8 reserved_at_60[0x20]; |
e281682b SM |
5697 | }; |
5698 | ||
5699 | struct mlx5_ifc_create_flow_table_in_bits { | |
5700 | u8 opcode[0x10]; | |
b4ff3a36 | 5701 | u8 reserved_at_10[0x10]; |
e281682b | 5702 | |
b4ff3a36 | 5703 | u8 reserved_at_20[0x10]; |
e281682b SM |
5704 | u8 op_mod[0x10]; |
5705 | ||
b4ff3a36 | 5706 | u8 reserved_at_40[0x40]; |
e281682b SM |
5707 | |
5708 | u8 table_type[0x8]; | |
b4ff3a36 | 5709 | u8 reserved_at_88[0x18]; |
e281682b | 5710 | |
b4ff3a36 | 5711 | u8 reserved_at_a0[0x20]; |
e281682b | 5712 | |
b4ff3a36 | 5713 | u8 reserved_at_c0[0x4]; |
34a40e68 | 5714 | u8 table_miss_mode[0x4]; |
e281682b | 5715 | u8 level[0x8]; |
b4ff3a36 | 5716 | u8 reserved_at_d0[0x8]; |
e281682b SM |
5717 | u8 log_size[0x8]; |
5718 | ||
b4ff3a36 | 5719 | u8 reserved_at_e0[0x8]; |
34a40e68 MG |
5720 | u8 table_miss_id[0x18]; |
5721 | ||
b4ff3a36 | 5722 | u8 reserved_at_100[0x100]; |
e281682b SM |
5723 | }; |
5724 | ||
5725 | struct mlx5_ifc_create_flow_group_out_bits { | |
5726 | u8 status[0x8]; | |
b4ff3a36 | 5727 | u8 reserved_at_8[0x18]; |
e281682b SM |
5728 | |
5729 | u8 syndrome[0x20]; | |
5730 | ||
b4ff3a36 | 5731 | u8 reserved_at_40[0x8]; |
e281682b SM |
5732 | u8 group_id[0x18]; |
5733 | ||
b4ff3a36 | 5734 | u8 reserved_at_60[0x20]; |
e281682b SM |
5735 | }; |
5736 | ||
5737 | enum { | |
5738 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, | |
5739 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, | |
5740 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, | |
5741 | }; | |
5742 | ||
5743 | struct mlx5_ifc_create_flow_group_in_bits { | |
5744 | u8 opcode[0x10]; | |
b4ff3a36 | 5745 | u8 reserved_at_10[0x10]; |
e281682b | 5746 | |
b4ff3a36 | 5747 | u8 reserved_at_20[0x10]; |
e281682b SM |
5748 | u8 op_mod[0x10]; |
5749 | ||
b4ff3a36 | 5750 | u8 reserved_at_40[0x40]; |
e281682b SM |
5751 | |
5752 | u8 table_type[0x8]; | |
b4ff3a36 | 5753 | u8 reserved_at_88[0x18]; |
e281682b | 5754 | |
b4ff3a36 | 5755 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5756 | u8 table_id[0x18]; |
5757 | ||
b4ff3a36 | 5758 | u8 reserved_at_c0[0x20]; |
e281682b SM |
5759 | |
5760 | u8 start_flow_index[0x20]; | |
5761 | ||
b4ff3a36 | 5762 | u8 reserved_at_100[0x20]; |
e281682b SM |
5763 | |
5764 | u8 end_flow_index[0x20]; | |
5765 | ||
b4ff3a36 | 5766 | u8 reserved_at_140[0xa0]; |
e281682b | 5767 | |
b4ff3a36 | 5768 | u8 reserved_at_1e0[0x18]; |
e281682b SM |
5769 | u8 match_criteria_enable[0x8]; |
5770 | ||
5771 | struct mlx5_ifc_fte_match_param_bits match_criteria; | |
5772 | ||
b4ff3a36 | 5773 | u8 reserved_at_1200[0xe00]; |
e281682b SM |
5774 | }; |
5775 | ||
5776 | struct mlx5_ifc_create_eq_out_bits { | |
5777 | u8 status[0x8]; | |
b4ff3a36 | 5778 | u8 reserved_at_8[0x18]; |
e281682b SM |
5779 | |
5780 | u8 syndrome[0x20]; | |
5781 | ||
b4ff3a36 | 5782 | u8 reserved_at_40[0x18]; |
e281682b SM |
5783 | u8 eq_number[0x8]; |
5784 | ||
b4ff3a36 | 5785 | u8 reserved_at_60[0x20]; |
e281682b SM |
5786 | }; |
5787 | ||
5788 | struct mlx5_ifc_create_eq_in_bits { | |
5789 | u8 opcode[0x10]; | |
b4ff3a36 | 5790 | u8 reserved_at_10[0x10]; |
e281682b | 5791 | |
b4ff3a36 | 5792 | u8 reserved_at_20[0x10]; |
e281682b SM |
5793 | u8 op_mod[0x10]; |
5794 | ||
b4ff3a36 | 5795 | u8 reserved_at_40[0x40]; |
e281682b SM |
5796 | |
5797 | struct mlx5_ifc_eqc_bits eq_context_entry; | |
5798 | ||
b4ff3a36 | 5799 | u8 reserved_at_280[0x40]; |
e281682b SM |
5800 | |
5801 | u8 event_bitmask[0x40]; | |
5802 | ||
b4ff3a36 | 5803 | u8 reserved_at_300[0x580]; |
e281682b SM |
5804 | |
5805 | u8 pas[0][0x40]; | |
5806 | }; | |
5807 | ||
5808 | struct mlx5_ifc_create_dct_out_bits { | |
5809 | u8 status[0x8]; | |
b4ff3a36 | 5810 | u8 reserved_at_8[0x18]; |
e281682b SM |
5811 | |
5812 | u8 syndrome[0x20]; | |
5813 | ||
b4ff3a36 | 5814 | u8 reserved_at_40[0x8]; |
e281682b SM |
5815 | u8 dctn[0x18]; |
5816 | ||
b4ff3a36 | 5817 | u8 reserved_at_60[0x20]; |
e281682b SM |
5818 | }; |
5819 | ||
5820 | struct mlx5_ifc_create_dct_in_bits { | |
5821 | u8 opcode[0x10]; | |
b4ff3a36 | 5822 | u8 reserved_at_10[0x10]; |
e281682b | 5823 | |
b4ff3a36 | 5824 | u8 reserved_at_20[0x10]; |
e281682b SM |
5825 | u8 op_mod[0x10]; |
5826 | ||
b4ff3a36 | 5827 | u8 reserved_at_40[0x40]; |
e281682b SM |
5828 | |
5829 | struct mlx5_ifc_dctc_bits dct_context_entry; | |
5830 | ||
b4ff3a36 | 5831 | u8 reserved_at_280[0x180]; |
e281682b SM |
5832 | }; |
5833 | ||
5834 | struct mlx5_ifc_create_cq_out_bits { | |
5835 | u8 status[0x8]; | |
b4ff3a36 | 5836 | u8 reserved_at_8[0x18]; |
e281682b SM |
5837 | |
5838 | u8 syndrome[0x20]; | |
5839 | ||
b4ff3a36 | 5840 | u8 reserved_at_40[0x8]; |
e281682b SM |
5841 | u8 cqn[0x18]; |
5842 | ||
b4ff3a36 | 5843 | u8 reserved_at_60[0x20]; |
e281682b SM |
5844 | }; |
5845 | ||
5846 | struct mlx5_ifc_create_cq_in_bits { | |
5847 | u8 opcode[0x10]; | |
b4ff3a36 | 5848 | u8 reserved_at_10[0x10]; |
e281682b | 5849 | |
b4ff3a36 | 5850 | u8 reserved_at_20[0x10]; |
e281682b SM |
5851 | u8 op_mod[0x10]; |
5852 | ||
b4ff3a36 | 5853 | u8 reserved_at_40[0x40]; |
e281682b SM |
5854 | |
5855 | struct mlx5_ifc_cqc_bits cq_context; | |
5856 | ||
b4ff3a36 | 5857 | u8 reserved_at_280[0x600]; |
e281682b SM |
5858 | |
5859 | u8 pas[0][0x40]; | |
5860 | }; | |
5861 | ||
5862 | struct mlx5_ifc_config_int_moderation_out_bits { | |
5863 | u8 status[0x8]; | |
b4ff3a36 | 5864 | u8 reserved_at_8[0x18]; |
e281682b SM |
5865 | |
5866 | u8 syndrome[0x20]; | |
5867 | ||
b4ff3a36 | 5868 | u8 reserved_at_40[0x4]; |
e281682b SM |
5869 | u8 min_delay[0xc]; |
5870 | u8 int_vector[0x10]; | |
5871 | ||
b4ff3a36 | 5872 | u8 reserved_at_60[0x20]; |
e281682b SM |
5873 | }; |
5874 | ||
5875 | enum { | |
5876 | MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, | |
5877 | MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, | |
5878 | }; | |
5879 | ||
5880 | struct mlx5_ifc_config_int_moderation_in_bits { | |
5881 | u8 opcode[0x10]; | |
b4ff3a36 | 5882 | u8 reserved_at_10[0x10]; |
e281682b | 5883 | |
b4ff3a36 | 5884 | u8 reserved_at_20[0x10]; |
e281682b SM |
5885 | u8 op_mod[0x10]; |
5886 | ||
b4ff3a36 | 5887 | u8 reserved_at_40[0x4]; |
e281682b SM |
5888 | u8 min_delay[0xc]; |
5889 | u8 int_vector[0x10]; | |
5890 | ||
b4ff3a36 | 5891 | u8 reserved_at_60[0x20]; |
e281682b SM |
5892 | }; |
5893 | ||
5894 | struct mlx5_ifc_attach_to_mcg_out_bits { | |
5895 | u8 status[0x8]; | |
b4ff3a36 | 5896 | u8 reserved_at_8[0x18]; |
e281682b SM |
5897 | |
5898 | u8 syndrome[0x20]; | |
5899 | ||
b4ff3a36 | 5900 | u8 reserved_at_40[0x40]; |
e281682b SM |
5901 | }; |
5902 | ||
5903 | struct mlx5_ifc_attach_to_mcg_in_bits { | |
5904 | u8 opcode[0x10]; | |
b4ff3a36 | 5905 | u8 reserved_at_10[0x10]; |
e281682b | 5906 | |
b4ff3a36 | 5907 | u8 reserved_at_20[0x10]; |
e281682b SM |
5908 | u8 op_mod[0x10]; |
5909 | ||
b4ff3a36 | 5910 | u8 reserved_at_40[0x8]; |
e281682b SM |
5911 | u8 qpn[0x18]; |
5912 | ||
b4ff3a36 | 5913 | u8 reserved_at_60[0x20]; |
e281682b SM |
5914 | |
5915 | u8 multicast_gid[16][0x8]; | |
5916 | }; | |
5917 | ||
5918 | struct mlx5_ifc_arm_xrc_srq_out_bits { | |
5919 | u8 status[0x8]; | |
b4ff3a36 | 5920 | u8 reserved_at_8[0x18]; |
e281682b SM |
5921 | |
5922 | u8 syndrome[0x20]; | |
5923 | ||
b4ff3a36 | 5924 | u8 reserved_at_40[0x40]; |
e281682b SM |
5925 | }; |
5926 | ||
5927 | enum { | |
5928 | MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, | |
5929 | }; | |
5930 | ||
5931 | struct mlx5_ifc_arm_xrc_srq_in_bits { | |
5932 | u8 opcode[0x10]; | |
b4ff3a36 | 5933 | u8 reserved_at_10[0x10]; |
e281682b | 5934 | |
b4ff3a36 | 5935 | u8 reserved_at_20[0x10]; |
e281682b SM |
5936 | u8 op_mod[0x10]; |
5937 | ||
b4ff3a36 | 5938 | u8 reserved_at_40[0x8]; |
e281682b SM |
5939 | u8 xrc_srqn[0x18]; |
5940 | ||
b4ff3a36 | 5941 | u8 reserved_at_60[0x10]; |
e281682b SM |
5942 | u8 lwm[0x10]; |
5943 | }; | |
5944 | ||
5945 | struct mlx5_ifc_arm_rq_out_bits { | |
5946 | u8 status[0x8]; | |
b4ff3a36 | 5947 | u8 reserved_at_8[0x18]; |
e281682b SM |
5948 | |
5949 | u8 syndrome[0x20]; | |
5950 | ||
b4ff3a36 | 5951 | u8 reserved_at_40[0x40]; |
e281682b SM |
5952 | }; |
5953 | ||
5954 | enum { | |
5955 | MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1, | |
5956 | }; | |
5957 | ||
5958 | struct mlx5_ifc_arm_rq_in_bits { | |
5959 | u8 opcode[0x10]; | |
b4ff3a36 | 5960 | u8 reserved_at_10[0x10]; |
e281682b | 5961 | |
b4ff3a36 | 5962 | u8 reserved_at_20[0x10]; |
e281682b SM |
5963 | u8 op_mod[0x10]; |
5964 | ||
b4ff3a36 | 5965 | u8 reserved_at_40[0x8]; |
e281682b SM |
5966 | u8 srq_number[0x18]; |
5967 | ||
b4ff3a36 | 5968 | u8 reserved_at_60[0x10]; |
e281682b SM |
5969 | u8 lwm[0x10]; |
5970 | }; | |
5971 | ||
5972 | struct mlx5_ifc_arm_dct_out_bits { | |
5973 | u8 status[0x8]; | |
b4ff3a36 | 5974 | u8 reserved_at_8[0x18]; |
e281682b SM |
5975 | |
5976 | u8 syndrome[0x20]; | |
5977 | ||
b4ff3a36 | 5978 | u8 reserved_at_40[0x40]; |
e281682b SM |
5979 | }; |
5980 | ||
5981 | struct mlx5_ifc_arm_dct_in_bits { | |
5982 | u8 opcode[0x10]; | |
b4ff3a36 | 5983 | u8 reserved_at_10[0x10]; |
e281682b | 5984 | |
b4ff3a36 | 5985 | u8 reserved_at_20[0x10]; |
e281682b SM |
5986 | u8 op_mod[0x10]; |
5987 | ||
b4ff3a36 | 5988 | u8 reserved_at_40[0x8]; |
e281682b SM |
5989 | u8 dct_number[0x18]; |
5990 | ||
b4ff3a36 | 5991 | u8 reserved_at_60[0x20]; |
e281682b SM |
5992 | }; |
5993 | ||
5994 | struct mlx5_ifc_alloc_xrcd_out_bits { | |
5995 | u8 status[0x8]; | |
b4ff3a36 | 5996 | u8 reserved_at_8[0x18]; |
e281682b SM |
5997 | |
5998 | u8 syndrome[0x20]; | |
5999 | ||
b4ff3a36 | 6000 | u8 reserved_at_40[0x8]; |
e281682b SM |
6001 | u8 xrcd[0x18]; |
6002 | ||
b4ff3a36 | 6003 | u8 reserved_at_60[0x20]; |
e281682b SM |
6004 | }; |
6005 | ||
6006 | struct mlx5_ifc_alloc_xrcd_in_bits { | |
6007 | u8 opcode[0x10]; | |
b4ff3a36 | 6008 | u8 reserved_at_10[0x10]; |
e281682b | 6009 | |
b4ff3a36 | 6010 | u8 reserved_at_20[0x10]; |
e281682b SM |
6011 | u8 op_mod[0x10]; |
6012 | ||
b4ff3a36 | 6013 | u8 reserved_at_40[0x40]; |
e281682b SM |
6014 | }; |
6015 | ||
6016 | struct mlx5_ifc_alloc_uar_out_bits { | |
6017 | u8 status[0x8]; | |
b4ff3a36 | 6018 | u8 reserved_at_8[0x18]; |
e281682b SM |
6019 | |
6020 | u8 syndrome[0x20]; | |
6021 | ||
b4ff3a36 | 6022 | u8 reserved_at_40[0x8]; |
e281682b SM |
6023 | u8 uar[0x18]; |
6024 | ||
b4ff3a36 | 6025 | u8 reserved_at_60[0x20]; |
e281682b SM |
6026 | }; |
6027 | ||
6028 | struct mlx5_ifc_alloc_uar_in_bits { | |
6029 | u8 opcode[0x10]; | |
b4ff3a36 | 6030 | u8 reserved_at_10[0x10]; |
e281682b | 6031 | |
b4ff3a36 | 6032 | u8 reserved_at_20[0x10]; |
e281682b SM |
6033 | u8 op_mod[0x10]; |
6034 | ||
b4ff3a36 | 6035 | u8 reserved_at_40[0x40]; |
e281682b SM |
6036 | }; |
6037 | ||
6038 | struct mlx5_ifc_alloc_transport_domain_out_bits { | |
6039 | u8 status[0x8]; | |
b4ff3a36 | 6040 | u8 reserved_at_8[0x18]; |
e281682b SM |
6041 | |
6042 | u8 syndrome[0x20]; | |
6043 | ||
b4ff3a36 | 6044 | u8 reserved_at_40[0x8]; |
e281682b SM |
6045 | u8 transport_domain[0x18]; |
6046 | ||
b4ff3a36 | 6047 | u8 reserved_at_60[0x20]; |
e281682b SM |
6048 | }; |
6049 | ||
6050 | struct mlx5_ifc_alloc_transport_domain_in_bits { | |
6051 | u8 opcode[0x10]; | |
b4ff3a36 | 6052 | u8 reserved_at_10[0x10]; |
e281682b | 6053 | |
b4ff3a36 | 6054 | u8 reserved_at_20[0x10]; |
e281682b SM |
6055 | u8 op_mod[0x10]; |
6056 | ||
b4ff3a36 | 6057 | u8 reserved_at_40[0x40]; |
e281682b SM |
6058 | }; |
6059 | ||
6060 | struct mlx5_ifc_alloc_q_counter_out_bits { | |
6061 | u8 status[0x8]; | |
b4ff3a36 | 6062 | u8 reserved_at_8[0x18]; |
e281682b SM |
6063 | |
6064 | u8 syndrome[0x20]; | |
6065 | ||
b4ff3a36 | 6066 | u8 reserved_at_40[0x18]; |
e281682b SM |
6067 | u8 counter_set_id[0x8]; |
6068 | ||
b4ff3a36 | 6069 | u8 reserved_at_60[0x20]; |
e281682b SM |
6070 | }; |
6071 | ||
6072 | struct mlx5_ifc_alloc_q_counter_in_bits { | |
6073 | u8 opcode[0x10]; | |
b4ff3a36 | 6074 | u8 reserved_at_10[0x10]; |
e281682b | 6075 | |
b4ff3a36 | 6076 | u8 reserved_at_20[0x10]; |
e281682b SM |
6077 | u8 op_mod[0x10]; |
6078 | ||
b4ff3a36 | 6079 | u8 reserved_at_40[0x40]; |
e281682b SM |
6080 | }; |
6081 | ||
6082 | struct mlx5_ifc_alloc_pd_out_bits { | |
6083 | u8 status[0x8]; | |
b4ff3a36 | 6084 | u8 reserved_at_8[0x18]; |
e281682b SM |
6085 | |
6086 | u8 syndrome[0x20]; | |
6087 | ||
b4ff3a36 | 6088 | u8 reserved_at_40[0x8]; |
e281682b SM |
6089 | u8 pd[0x18]; |
6090 | ||
b4ff3a36 | 6091 | u8 reserved_at_60[0x20]; |
e281682b SM |
6092 | }; |
6093 | ||
6094 | struct mlx5_ifc_alloc_pd_in_bits { | |
6095 | u8 opcode[0x10]; | |
b4ff3a36 | 6096 | u8 reserved_at_10[0x10]; |
e281682b | 6097 | |
b4ff3a36 | 6098 | u8 reserved_at_20[0x10]; |
e281682b SM |
6099 | u8 op_mod[0x10]; |
6100 | ||
b4ff3a36 | 6101 | u8 reserved_at_40[0x40]; |
e281682b SM |
6102 | }; |
6103 | ||
6104 | struct mlx5_ifc_add_vxlan_udp_dport_out_bits { | |
6105 | u8 status[0x8]; | |
b4ff3a36 | 6106 | u8 reserved_at_8[0x18]; |
e281682b SM |
6107 | |
6108 | u8 syndrome[0x20]; | |
6109 | ||
b4ff3a36 | 6110 | u8 reserved_at_40[0x40]; |
e281682b SM |
6111 | }; |
6112 | ||
6113 | struct mlx5_ifc_add_vxlan_udp_dport_in_bits { | |
6114 | u8 opcode[0x10]; | |
b4ff3a36 | 6115 | u8 reserved_at_10[0x10]; |
e281682b | 6116 | |
b4ff3a36 | 6117 | u8 reserved_at_20[0x10]; |
e281682b SM |
6118 | u8 op_mod[0x10]; |
6119 | ||
b4ff3a36 | 6120 | u8 reserved_at_40[0x20]; |
e281682b | 6121 | |
b4ff3a36 | 6122 | u8 reserved_at_60[0x10]; |
e281682b SM |
6123 | u8 vxlan_udp_port[0x10]; |
6124 | }; | |
6125 | ||
6126 | struct mlx5_ifc_access_register_out_bits { | |
6127 | u8 status[0x8]; | |
b4ff3a36 | 6128 | u8 reserved_at_8[0x18]; |
e281682b SM |
6129 | |
6130 | u8 syndrome[0x20]; | |
6131 | ||
b4ff3a36 | 6132 | u8 reserved_at_40[0x40]; |
e281682b SM |
6133 | |
6134 | u8 register_data[0][0x20]; | |
6135 | }; | |
6136 | ||
6137 | enum { | |
6138 | MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, | |
6139 | MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, | |
6140 | }; | |
6141 | ||
6142 | struct mlx5_ifc_access_register_in_bits { | |
6143 | u8 opcode[0x10]; | |
b4ff3a36 | 6144 | u8 reserved_at_10[0x10]; |
e281682b | 6145 | |
b4ff3a36 | 6146 | u8 reserved_at_20[0x10]; |
e281682b SM |
6147 | u8 op_mod[0x10]; |
6148 | ||
b4ff3a36 | 6149 | u8 reserved_at_40[0x10]; |
e281682b SM |
6150 | u8 register_id[0x10]; |
6151 | ||
6152 | u8 argument[0x20]; | |
6153 | ||
6154 | u8 register_data[0][0x20]; | |
6155 | }; | |
6156 | ||
6157 | struct mlx5_ifc_sltp_reg_bits { | |
6158 | u8 status[0x4]; | |
6159 | u8 version[0x4]; | |
6160 | u8 local_port[0x8]; | |
6161 | u8 pnat[0x2]; | |
b4ff3a36 | 6162 | u8 reserved_at_12[0x2]; |
e281682b | 6163 | u8 lane[0x4]; |
b4ff3a36 | 6164 | u8 reserved_at_18[0x8]; |
e281682b | 6165 | |
b4ff3a36 | 6166 | u8 reserved_at_20[0x20]; |
e281682b | 6167 | |
b4ff3a36 | 6168 | u8 reserved_at_40[0x7]; |
e281682b SM |
6169 | u8 polarity[0x1]; |
6170 | u8 ob_tap0[0x8]; | |
6171 | u8 ob_tap1[0x8]; | |
6172 | u8 ob_tap2[0x8]; | |
6173 | ||
b4ff3a36 | 6174 | u8 reserved_at_60[0xc]; |
e281682b SM |
6175 | u8 ob_preemp_mode[0x4]; |
6176 | u8 ob_reg[0x8]; | |
6177 | u8 ob_bias[0x8]; | |
6178 | ||
b4ff3a36 | 6179 | u8 reserved_at_80[0x20]; |
e281682b SM |
6180 | }; |
6181 | ||
6182 | struct mlx5_ifc_slrg_reg_bits { | |
6183 | u8 status[0x4]; | |
6184 | u8 version[0x4]; | |
6185 | u8 local_port[0x8]; | |
6186 | u8 pnat[0x2]; | |
b4ff3a36 | 6187 | u8 reserved_at_12[0x2]; |
e281682b | 6188 | u8 lane[0x4]; |
b4ff3a36 | 6189 | u8 reserved_at_18[0x8]; |
e281682b SM |
6190 | |
6191 | u8 time_to_link_up[0x10]; | |
b4ff3a36 | 6192 | u8 reserved_at_30[0xc]; |
e281682b SM |
6193 | u8 grade_lane_speed[0x4]; |
6194 | ||
6195 | u8 grade_version[0x8]; | |
6196 | u8 grade[0x18]; | |
6197 | ||
b4ff3a36 | 6198 | u8 reserved_at_60[0x4]; |
e281682b SM |
6199 | u8 height_grade_type[0x4]; |
6200 | u8 height_grade[0x18]; | |
6201 | ||
6202 | u8 height_dz[0x10]; | |
6203 | u8 height_dv[0x10]; | |
6204 | ||
b4ff3a36 | 6205 | u8 reserved_at_a0[0x10]; |
e281682b SM |
6206 | u8 height_sigma[0x10]; |
6207 | ||
b4ff3a36 | 6208 | u8 reserved_at_c0[0x20]; |
e281682b | 6209 | |
b4ff3a36 | 6210 | u8 reserved_at_e0[0x4]; |
e281682b SM |
6211 | u8 phase_grade_type[0x4]; |
6212 | u8 phase_grade[0x18]; | |
6213 | ||
b4ff3a36 | 6214 | u8 reserved_at_100[0x8]; |
e281682b | 6215 | u8 phase_eo_pos[0x8]; |
b4ff3a36 | 6216 | u8 reserved_at_110[0x8]; |
e281682b SM |
6217 | u8 phase_eo_neg[0x8]; |
6218 | ||
6219 | u8 ffe_set_tested[0x10]; | |
6220 | u8 test_errors_per_lane[0x10]; | |
6221 | }; | |
6222 | ||
6223 | struct mlx5_ifc_pvlc_reg_bits { | |
b4ff3a36 | 6224 | u8 reserved_at_0[0x8]; |
e281682b | 6225 | u8 local_port[0x8]; |
b4ff3a36 | 6226 | u8 reserved_at_10[0x10]; |
e281682b | 6227 | |
b4ff3a36 | 6228 | u8 reserved_at_20[0x1c]; |
e281682b SM |
6229 | u8 vl_hw_cap[0x4]; |
6230 | ||
b4ff3a36 | 6231 | u8 reserved_at_40[0x1c]; |
e281682b SM |
6232 | u8 vl_admin[0x4]; |
6233 | ||
b4ff3a36 | 6234 | u8 reserved_at_60[0x1c]; |
e281682b SM |
6235 | u8 vl_operational[0x4]; |
6236 | }; | |
6237 | ||
6238 | struct mlx5_ifc_pude_reg_bits { | |
6239 | u8 swid[0x8]; | |
6240 | u8 local_port[0x8]; | |
b4ff3a36 | 6241 | u8 reserved_at_10[0x4]; |
e281682b | 6242 | u8 admin_status[0x4]; |
b4ff3a36 | 6243 | u8 reserved_at_18[0x4]; |
e281682b SM |
6244 | u8 oper_status[0x4]; |
6245 | ||
b4ff3a36 | 6246 | u8 reserved_at_20[0x60]; |
e281682b SM |
6247 | }; |
6248 | ||
6249 | struct mlx5_ifc_ptys_reg_bits { | |
b4ff3a36 | 6250 | u8 reserved_at_0[0x8]; |
e281682b | 6251 | u8 local_port[0x8]; |
b4ff3a36 | 6252 | u8 reserved_at_10[0xd]; |
e281682b SM |
6253 | u8 proto_mask[0x3]; |
6254 | ||
b4ff3a36 | 6255 | u8 reserved_at_20[0x40]; |
e281682b SM |
6256 | |
6257 | u8 eth_proto_capability[0x20]; | |
6258 | ||
6259 | u8 ib_link_width_capability[0x10]; | |
6260 | u8 ib_proto_capability[0x10]; | |
6261 | ||
b4ff3a36 | 6262 | u8 reserved_at_a0[0x20]; |
e281682b SM |
6263 | |
6264 | u8 eth_proto_admin[0x20]; | |
6265 | ||
6266 | u8 ib_link_width_admin[0x10]; | |
6267 | u8 ib_proto_admin[0x10]; | |
6268 | ||
b4ff3a36 | 6269 | u8 reserved_at_100[0x20]; |
e281682b SM |
6270 | |
6271 | u8 eth_proto_oper[0x20]; | |
6272 | ||
6273 | u8 ib_link_width_oper[0x10]; | |
6274 | u8 ib_proto_oper[0x10]; | |
6275 | ||
b4ff3a36 | 6276 | u8 reserved_at_160[0x20]; |
e281682b SM |
6277 | |
6278 | u8 eth_proto_lp_advertise[0x20]; | |
6279 | ||
b4ff3a36 | 6280 | u8 reserved_at_1a0[0x60]; |
e281682b SM |
6281 | }; |
6282 | ||
6283 | struct mlx5_ifc_ptas_reg_bits { | |
b4ff3a36 | 6284 | u8 reserved_at_0[0x20]; |
e281682b SM |
6285 | |
6286 | u8 algorithm_options[0x10]; | |
b4ff3a36 | 6287 | u8 reserved_at_30[0x4]; |
e281682b SM |
6288 | u8 repetitions_mode[0x4]; |
6289 | u8 num_of_repetitions[0x8]; | |
6290 | ||
6291 | u8 grade_version[0x8]; | |
6292 | u8 height_grade_type[0x4]; | |
6293 | u8 phase_grade_type[0x4]; | |
6294 | u8 height_grade_weight[0x8]; | |
6295 | u8 phase_grade_weight[0x8]; | |
6296 | ||
6297 | u8 gisim_measure_bits[0x10]; | |
6298 | u8 adaptive_tap_measure_bits[0x10]; | |
6299 | ||
6300 | u8 ber_bath_high_error_threshold[0x10]; | |
6301 | u8 ber_bath_mid_error_threshold[0x10]; | |
6302 | ||
6303 | u8 ber_bath_low_error_threshold[0x10]; | |
6304 | u8 one_ratio_high_threshold[0x10]; | |
6305 | ||
6306 | u8 one_ratio_high_mid_threshold[0x10]; | |
6307 | u8 one_ratio_low_mid_threshold[0x10]; | |
6308 | ||
6309 | u8 one_ratio_low_threshold[0x10]; | |
6310 | u8 ndeo_error_threshold[0x10]; | |
6311 | ||
6312 | u8 mixer_offset_step_size[0x10]; | |
b4ff3a36 | 6313 | u8 reserved_at_110[0x8]; |
e281682b SM |
6314 | u8 mix90_phase_for_voltage_bath[0x8]; |
6315 | ||
6316 | u8 mixer_offset_start[0x10]; | |
6317 | u8 mixer_offset_end[0x10]; | |
6318 | ||
b4ff3a36 | 6319 | u8 reserved_at_140[0x15]; |
e281682b SM |
6320 | u8 ber_test_time[0xb]; |
6321 | }; | |
6322 | ||
6323 | struct mlx5_ifc_pspa_reg_bits { | |
6324 | u8 swid[0x8]; | |
6325 | u8 local_port[0x8]; | |
6326 | u8 sub_port[0x8]; | |
b4ff3a36 | 6327 | u8 reserved_at_18[0x8]; |
e281682b | 6328 | |
b4ff3a36 | 6329 | u8 reserved_at_20[0x20]; |
e281682b SM |
6330 | }; |
6331 | ||
6332 | struct mlx5_ifc_pqdr_reg_bits { | |
b4ff3a36 | 6333 | u8 reserved_at_0[0x8]; |
e281682b | 6334 | u8 local_port[0x8]; |
b4ff3a36 | 6335 | u8 reserved_at_10[0x5]; |
e281682b | 6336 | u8 prio[0x3]; |
b4ff3a36 | 6337 | u8 reserved_at_18[0x6]; |
e281682b SM |
6338 | u8 mode[0x2]; |
6339 | ||
b4ff3a36 | 6340 | u8 reserved_at_20[0x20]; |
e281682b | 6341 | |
b4ff3a36 | 6342 | u8 reserved_at_40[0x10]; |
e281682b SM |
6343 | u8 min_threshold[0x10]; |
6344 | ||
b4ff3a36 | 6345 | u8 reserved_at_60[0x10]; |
e281682b SM |
6346 | u8 max_threshold[0x10]; |
6347 | ||
b4ff3a36 | 6348 | u8 reserved_at_80[0x10]; |
e281682b SM |
6349 | u8 mark_probability_denominator[0x10]; |
6350 | ||
b4ff3a36 | 6351 | u8 reserved_at_a0[0x60]; |
e281682b SM |
6352 | }; |
6353 | ||
6354 | struct mlx5_ifc_ppsc_reg_bits { | |
b4ff3a36 | 6355 | u8 reserved_at_0[0x8]; |
e281682b | 6356 | u8 local_port[0x8]; |
b4ff3a36 | 6357 | u8 reserved_at_10[0x10]; |
e281682b | 6358 | |
b4ff3a36 | 6359 | u8 reserved_at_20[0x60]; |
e281682b | 6360 | |
b4ff3a36 | 6361 | u8 reserved_at_80[0x1c]; |
e281682b SM |
6362 | u8 wrps_admin[0x4]; |
6363 | ||
b4ff3a36 | 6364 | u8 reserved_at_a0[0x1c]; |
e281682b SM |
6365 | u8 wrps_status[0x4]; |
6366 | ||
b4ff3a36 | 6367 | u8 reserved_at_c0[0x8]; |
e281682b | 6368 | u8 up_threshold[0x8]; |
b4ff3a36 | 6369 | u8 reserved_at_d0[0x8]; |
e281682b SM |
6370 | u8 down_threshold[0x8]; |
6371 | ||
b4ff3a36 | 6372 | u8 reserved_at_e0[0x20]; |
e281682b | 6373 | |
b4ff3a36 | 6374 | u8 reserved_at_100[0x1c]; |
e281682b SM |
6375 | u8 srps_admin[0x4]; |
6376 | ||
b4ff3a36 | 6377 | u8 reserved_at_120[0x1c]; |
e281682b SM |
6378 | u8 srps_status[0x4]; |
6379 | ||
b4ff3a36 | 6380 | u8 reserved_at_140[0x40]; |
e281682b SM |
6381 | }; |
6382 | ||
6383 | struct mlx5_ifc_pplr_reg_bits { | |
b4ff3a36 | 6384 | u8 reserved_at_0[0x8]; |
e281682b | 6385 | u8 local_port[0x8]; |
b4ff3a36 | 6386 | u8 reserved_at_10[0x10]; |
e281682b | 6387 | |
b4ff3a36 | 6388 | u8 reserved_at_20[0x8]; |
e281682b | 6389 | u8 lb_cap[0x8]; |
b4ff3a36 | 6390 | u8 reserved_at_30[0x8]; |
e281682b SM |
6391 | u8 lb_en[0x8]; |
6392 | }; | |
6393 | ||
6394 | struct mlx5_ifc_pplm_reg_bits { | |
b4ff3a36 | 6395 | u8 reserved_at_0[0x8]; |
e281682b | 6396 | u8 local_port[0x8]; |
b4ff3a36 | 6397 | u8 reserved_at_10[0x10]; |
e281682b | 6398 | |
b4ff3a36 | 6399 | u8 reserved_at_20[0x20]; |
e281682b SM |
6400 | |
6401 | u8 port_profile_mode[0x8]; | |
6402 | u8 static_port_profile[0x8]; | |
6403 | u8 active_port_profile[0x8]; | |
b4ff3a36 | 6404 | u8 reserved_at_58[0x8]; |
e281682b SM |
6405 | |
6406 | u8 retransmission_active[0x8]; | |
6407 | u8 fec_mode_active[0x18]; | |
6408 | ||
b4ff3a36 | 6409 | u8 reserved_at_80[0x20]; |
e281682b SM |
6410 | }; |
6411 | ||
6412 | struct mlx5_ifc_ppcnt_reg_bits { | |
6413 | u8 swid[0x8]; | |
6414 | u8 local_port[0x8]; | |
6415 | u8 pnat[0x2]; | |
b4ff3a36 | 6416 | u8 reserved_at_12[0x8]; |
e281682b SM |
6417 | u8 grp[0x6]; |
6418 | ||
6419 | u8 clr[0x1]; | |
b4ff3a36 | 6420 | u8 reserved_at_21[0x1c]; |
e281682b SM |
6421 | u8 prio_tc[0x3]; |
6422 | ||
6423 | union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; | |
6424 | }; | |
6425 | ||
6426 | struct mlx5_ifc_ppad_reg_bits { | |
b4ff3a36 | 6427 | u8 reserved_at_0[0x3]; |
e281682b | 6428 | u8 single_mac[0x1]; |
b4ff3a36 | 6429 | u8 reserved_at_4[0x4]; |
e281682b SM |
6430 | u8 local_port[0x8]; |
6431 | u8 mac_47_32[0x10]; | |
6432 | ||
6433 | u8 mac_31_0[0x20]; | |
6434 | ||
b4ff3a36 | 6435 | u8 reserved_at_40[0x40]; |
e281682b SM |
6436 | }; |
6437 | ||
6438 | struct mlx5_ifc_pmtu_reg_bits { | |
b4ff3a36 | 6439 | u8 reserved_at_0[0x8]; |
e281682b | 6440 | u8 local_port[0x8]; |
b4ff3a36 | 6441 | u8 reserved_at_10[0x10]; |
e281682b SM |
6442 | |
6443 | u8 max_mtu[0x10]; | |
b4ff3a36 | 6444 | u8 reserved_at_30[0x10]; |
e281682b SM |
6445 | |
6446 | u8 admin_mtu[0x10]; | |
b4ff3a36 | 6447 | u8 reserved_at_50[0x10]; |
e281682b SM |
6448 | |
6449 | u8 oper_mtu[0x10]; | |
b4ff3a36 | 6450 | u8 reserved_at_70[0x10]; |
e281682b SM |
6451 | }; |
6452 | ||
6453 | struct mlx5_ifc_pmpr_reg_bits { | |
b4ff3a36 | 6454 | u8 reserved_at_0[0x8]; |
e281682b | 6455 | u8 module[0x8]; |
b4ff3a36 | 6456 | u8 reserved_at_10[0x10]; |
e281682b | 6457 | |
b4ff3a36 | 6458 | u8 reserved_at_20[0x18]; |
e281682b SM |
6459 | u8 attenuation_5g[0x8]; |
6460 | ||
b4ff3a36 | 6461 | u8 reserved_at_40[0x18]; |
e281682b SM |
6462 | u8 attenuation_7g[0x8]; |
6463 | ||
b4ff3a36 | 6464 | u8 reserved_at_60[0x18]; |
e281682b SM |
6465 | u8 attenuation_12g[0x8]; |
6466 | }; | |
6467 | ||
6468 | struct mlx5_ifc_pmpe_reg_bits { | |
b4ff3a36 | 6469 | u8 reserved_at_0[0x8]; |
e281682b | 6470 | u8 module[0x8]; |
b4ff3a36 | 6471 | u8 reserved_at_10[0xc]; |
e281682b SM |
6472 | u8 module_status[0x4]; |
6473 | ||
b4ff3a36 | 6474 | u8 reserved_at_20[0x60]; |
e281682b SM |
6475 | }; |
6476 | ||
6477 | struct mlx5_ifc_pmpc_reg_bits { | |
6478 | u8 module_state_updated[32][0x8]; | |
6479 | }; | |
6480 | ||
6481 | struct mlx5_ifc_pmlpn_reg_bits { | |
b4ff3a36 | 6482 | u8 reserved_at_0[0x4]; |
e281682b SM |
6483 | u8 mlpn_status[0x4]; |
6484 | u8 local_port[0x8]; | |
b4ff3a36 | 6485 | u8 reserved_at_10[0x10]; |
e281682b SM |
6486 | |
6487 | u8 e[0x1]; | |
b4ff3a36 | 6488 | u8 reserved_at_21[0x1f]; |
e281682b SM |
6489 | }; |
6490 | ||
6491 | struct mlx5_ifc_pmlp_reg_bits { | |
6492 | u8 rxtx[0x1]; | |
b4ff3a36 | 6493 | u8 reserved_at_1[0x7]; |
e281682b | 6494 | u8 local_port[0x8]; |
b4ff3a36 | 6495 | u8 reserved_at_10[0x8]; |
e281682b SM |
6496 | u8 width[0x8]; |
6497 | ||
6498 | u8 lane0_module_mapping[0x20]; | |
6499 | ||
6500 | u8 lane1_module_mapping[0x20]; | |
6501 | ||
6502 | u8 lane2_module_mapping[0x20]; | |
6503 | ||
6504 | u8 lane3_module_mapping[0x20]; | |
6505 | ||
b4ff3a36 | 6506 | u8 reserved_at_a0[0x160]; |
e281682b SM |
6507 | }; |
6508 | ||
6509 | struct mlx5_ifc_pmaos_reg_bits { | |
b4ff3a36 | 6510 | u8 reserved_at_0[0x8]; |
e281682b | 6511 | u8 module[0x8]; |
b4ff3a36 | 6512 | u8 reserved_at_10[0x4]; |
e281682b | 6513 | u8 admin_status[0x4]; |
b4ff3a36 | 6514 | u8 reserved_at_18[0x4]; |
e281682b SM |
6515 | u8 oper_status[0x4]; |
6516 | ||
6517 | u8 ase[0x1]; | |
6518 | u8 ee[0x1]; | |
b4ff3a36 | 6519 | u8 reserved_at_22[0x1c]; |
e281682b SM |
6520 | u8 e[0x2]; |
6521 | ||
b4ff3a36 | 6522 | u8 reserved_at_40[0x40]; |
e281682b SM |
6523 | }; |
6524 | ||
6525 | struct mlx5_ifc_plpc_reg_bits { | |
b4ff3a36 | 6526 | u8 reserved_at_0[0x4]; |
e281682b | 6527 | u8 profile_id[0xc]; |
b4ff3a36 | 6528 | u8 reserved_at_10[0x4]; |
e281682b | 6529 | u8 proto_mask[0x4]; |
b4ff3a36 | 6530 | u8 reserved_at_18[0x8]; |
e281682b | 6531 | |
b4ff3a36 | 6532 | u8 reserved_at_20[0x10]; |
e281682b SM |
6533 | u8 lane_speed[0x10]; |
6534 | ||
b4ff3a36 | 6535 | u8 reserved_at_40[0x17]; |
e281682b SM |
6536 | u8 lpbf[0x1]; |
6537 | u8 fec_mode_policy[0x8]; | |
6538 | ||
6539 | u8 retransmission_capability[0x8]; | |
6540 | u8 fec_mode_capability[0x18]; | |
6541 | ||
6542 | u8 retransmission_support_admin[0x8]; | |
6543 | u8 fec_mode_support_admin[0x18]; | |
6544 | ||
6545 | u8 retransmission_request_admin[0x8]; | |
6546 | u8 fec_mode_request_admin[0x18]; | |
6547 | ||
b4ff3a36 | 6548 | u8 reserved_at_c0[0x80]; |
e281682b SM |
6549 | }; |
6550 | ||
6551 | struct mlx5_ifc_plib_reg_bits { | |
b4ff3a36 | 6552 | u8 reserved_at_0[0x8]; |
e281682b | 6553 | u8 local_port[0x8]; |
b4ff3a36 | 6554 | u8 reserved_at_10[0x8]; |
e281682b SM |
6555 | u8 ib_port[0x8]; |
6556 | ||
b4ff3a36 | 6557 | u8 reserved_at_20[0x60]; |
e281682b SM |
6558 | }; |
6559 | ||
6560 | struct mlx5_ifc_plbf_reg_bits { | |
b4ff3a36 | 6561 | u8 reserved_at_0[0x8]; |
e281682b | 6562 | u8 local_port[0x8]; |
b4ff3a36 | 6563 | u8 reserved_at_10[0xd]; |
e281682b SM |
6564 | u8 lbf_mode[0x3]; |
6565 | ||
b4ff3a36 | 6566 | u8 reserved_at_20[0x20]; |
e281682b SM |
6567 | }; |
6568 | ||
6569 | struct mlx5_ifc_pipg_reg_bits { | |
b4ff3a36 | 6570 | u8 reserved_at_0[0x8]; |
e281682b | 6571 | u8 local_port[0x8]; |
b4ff3a36 | 6572 | u8 reserved_at_10[0x10]; |
e281682b SM |
6573 | |
6574 | u8 dic[0x1]; | |
b4ff3a36 | 6575 | u8 reserved_at_21[0x19]; |
e281682b | 6576 | u8 ipg[0x4]; |
b4ff3a36 | 6577 | u8 reserved_at_3e[0x2]; |
e281682b SM |
6578 | }; |
6579 | ||
6580 | struct mlx5_ifc_pifr_reg_bits { | |
b4ff3a36 | 6581 | u8 reserved_at_0[0x8]; |
e281682b | 6582 | u8 local_port[0x8]; |
b4ff3a36 | 6583 | u8 reserved_at_10[0x10]; |
e281682b | 6584 | |
b4ff3a36 | 6585 | u8 reserved_at_20[0xe0]; |
e281682b SM |
6586 | |
6587 | u8 port_filter[8][0x20]; | |
6588 | ||
6589 | u8 port_filter_update_en[8][0x20]; | |
6590 | }; | |
6591 | ||
6592 | struct mlx5_ifc_pfcc_reg_bits { | |
b4ff3a36 | 6593 | u8 reserved_at_0[0x8]; |
e281682b | 6594 | u8 local_port[0x8]; |
b4ff3a36 | 6595 | u8 reserved_at_10[0x10]; |
e281682b SM |
6596 | |
6597 | u8 ppan[0x4]; | |
b4ff3a36 | 6598 | u8 reserved_at_24[0x4]; |
e281682b | 6599 | u8 prio_mask_tx[0x8]; |
b4ff3a36 | 6600 | u8 reserved_at_30[0x8]; |
e281682b SM |
6601 | u8 prio_mask_rx[0x8]; |
6602 | ||
6603 | u8 pptx[0x1]; | |
6604 | u8 aptx[0x1]; | |
b4ff3a36 | 6605 | u8 reserved_at_42[0x6]; |
e281682b | 6606 | u8 pfctx[0x8]; |
b4ff3a36 | 6607 | u8 reserved_at_50[0x10]; |
e281682b SM |
6608 | |
6609 | u8 pprx[0x1]; | |
6610 | u8 aprx[0x1]; | |
b4ff3a36 | 6611 | u8 reserved_at_62[0x6]; |
e281682b | 6612 | u8 pfcrx[0x8]; |
b4ff3a36 | 6613 | u8 reserved_at_70[0x10]; |
e281682b | 6614 | |
b4ff3a36 | 6615 | u8 reserved_at_80[0x80]; |
e281682b SM |
6616 | }; |
6617 | ||
6618 | struct mlx5_ifc_pelc_reg_bits { | |
6619 | u8 op[0x4]; | |
b4ff3a36 | 6620 | u8 reserved_at_4[0x4]; |
e281682b | 6621 | u8 local_port[0x8]; |
b4ff3a36 | 6622 | u8 reserved_at_10[0x10]; |
e281682b SM |
6623 | |
6624 | u8 op_admin[0x8]; | |
6625 | u8 op_capability[0x8]; | |
6626 | u8 op_request[0x8]; | |
6627 | u8 op_active[0x8]; | |
6628 | ||
6629 | u8 admin[0x40]; | |
6630 | ||
6631 | u8 capability[0x40]; | |
6632 | ||
6633 | u8 request[0x40]; | |
6634 | ||
6635 | u8 active[0x40]; | |
6636 | ||
b4ff3a36 | 6637 | u8 reserved_at_140[0x80]; |
e281682b SM |
6638 | }; |
6639 | ||
6640 | struct mlx5_ifc_peir_reg_bits { | |
b4ff3a36 | 6641 | u8 reserved_at_0[0x8]; |
e281682b | 6642 | u8 local_port[0x8]; |
b4ff3a36 | 6643 | u8 reserved_at_10[0x10]; |
e281682b | 6644 | |
b4ff3a36 | 6645 | u8 reserved_at_20[0xc]; |
e281682b | 6646 | u8 error_count[0x4]; |
b4ff3a36 | 6647 | u8 reserved_at_30[0x10]; |
e281682b | 6648 | |
b4ff3a36 | 6649 | u8 reserved_at_40[0xc]; |
e281682b | 6650 | u8 lane[0x4]; |
b4ff3a36 | 6651 | u8 reserved_at_50[0x8]; |
e281682b SM |
6652 | u8 error_type[0x8]; |
6653 | }; | |
6654 | ||
6655 | struct mlx5_ifc_pcap_reg_bits { | |
b4ff3a36 | 6656 | u8 reserved_at_0[0x8]; |
e281682b | 6657 | u8 local_port[0x8]; |
b4ff3a36 | 6658 | u8 reserved_at_10[0x10]; |
e281682b SM |
6659 | |
6660 | u8 port_capability_mask[4][0x20]; | |
6661 | }; | |
6662 | ||
6663 | struct mlx5_ifc_paos_reg_bits { | |
6664 | u8 swid[0x8]; | |
6665 | u8 local_port[0x8]; | |
b4ff3a36 | 6666 | u8 reserved_at_10[0x4]; |
e281682b | 6667 | u8 admin_status[0x4]; |
b4ff3a36 | 6668 | u8 reserved_at_18[0x4]; |
e281682b SM |
6669 | u8 oper_status[0x4]; |
6670 | ||
6671 | u8 ase[0x1]; | |
6672 | u8 ee[0x1]; | |
b4ff3a36 | 6673 | u8 reserved_at_22[0x1c]; |
e281682b SM |
6674 | u8 e[0x2]; |
6675 | ||
b4ff3a36 | 6676 | u8 reserved_at_40[0x40]; |
e281682b SM |
6677 | }; |
6678 | ||
6679 | struct mlx5_ifc_pamp_reg_bits { | |
b4ff3a36 | 6680 | u8 reserved_at_0[0x8]; |
e281682b | 6681 | u8 opamp_group[0x8]; |
b4ff3a36 | 6682 | u8 reserved_at_10[0xc]; |
e281682b SM |
6683 | u8 opamp_group_type[0x4]; |
6684 | ||
6685 | u8 start_index[0x10]; | |
b4ff3a36 | 6686 | u8 reserved_at_30[0x4]; |
e281682b SM |
6687 | u8 num_of_indices[0xc]; |
6688 | ||
6689 | u8 index_data[18][0x10]; | |
6690 | }; | |
6691 | ||
6692 | struct mlx5_ifc_lane_2_module_mapping_bits { | |
b4ff3a36 | 6693 | u8 reserved_at_0[0x6]; |
e281682b | 6694 | u8 rx_lane[0x2]; |
b4ff3a36 | 6695 | u8 reserved_at_8[0x6]; |
e281682b | 6696 | u8 tx_lane[0x2]; |
b4ff3a36 | 6697 | u8 reserved_at_10[0x8]; |
e281682b SM |
6698 | u8 module[0x8]; |
6699 | }; | |
6700 | ||
6701 | struct mlx5_ifc_bufferx_reg_bits { | |
b4ff3a36 | 6702 | u8 reserved_at_0[0x6]; |
e281682b SM |
6703 | u8 lossy[0x1]; |
6704 | u8 epsb[0x1]; | |
b4ff3a36 | 6705 | u8 reserved_at_8[0xc]; |
e281682b SM |
6706 | u8 size[0xc]; |
6707 | ||
6708 | u8 xoff_threshold[0x10]; | |
6709 | u8 xon_threshold[0x10]; | |
6710 | }; | |
6711 | ||
6712 | struct mlx5_ifc_set_node_in_bits { | |
6713 | u8 node_description[64][0x8]; | |
6714 | }; | |
6715 | ||
6716 | struct mlx5_ifc_register_power_settings_bits { | |
b4ff3a36 | 6717 | u8 reserved_at_0[0x18]; |
e281682b SM |
6718 | u8 power_settings_level[0x8]; |
6719 | ||
b4ff3a36 | 6720 | u8 reserved_at_20[0x60]; |
e281682b SM |
6721 | }; |
6722 | ||
6723 | struct mlx5_ifc_register_host_endianness_bits { | |
6724 | u8 he[0x1]; | |
b4ff3a36 | 6725 | u8 reserved_at_1[0x1f]; |
e281682b | 6726 | |
b4ff3a36 | 6727 | u8 reserved_at_20[0x60]; |
e281682b SM |
6728 | }; |
6729 | ||
6730 | struct mlx5_ifc_umr_pointer_desc_argument_bits { | |
b4ff3a36 | 6731 | u8 reserved_at_0[0x20]; |
e281682b SM |
6732 | |
6733 | u8 mkey[0x20]; | |
6734 | ||
6735 | u8 addressh_63_32[0x20]; | |
6736 | ||
6737 | u8 addressl_31_0[0x20]; | |
6738 | }; | |
6739 | ||
6740 | struct mlx5_ifc_ud_adrs_vector_bits { | |
6741 | u8 dc_key[0x40]; | |
6742 | ||
6743 | u8 ext[0x1]; | |
b4ff3a36 | 6744 | u8 reserved_at_41[0x7]; |
e281682b SM |
6745 | u8 destination_qp_dct[0x18]; |
6746 | ||
6747 | u8 static_rate[0x4]; | |
6748 | u8 sl_eth_prio[0x4]; | |
6749 | u8 fl[0x1]; | |
6750 | u8 mlid[0x7]; | |
6751 | u8 rlid_udp_sport[0x10]; | |
6752 | ||
b4ff3a36 | 6753 | u8 reserved_at_80[0x20]; |
e281682b SM |
6754 | |
6755 | u8 rmac_47_16[0x20]; | |
6756 | ||
6757 | u8 rmac_15_0[0x10]; | |
6758 | u8 tclass[0x8]; | |
6759 | u8 hop_limit[0x8]; | |
6760 | ||
b4ff3a36 | 6761 | u8 reserved_at_e0[0x1]; |
e281682b | 6762 | u8 grh[0x1]; |
b4ff3a36 | 6763 | u8 reserved_at_e2[0x2]; |
e281682b SM |
6764 | u8 src_addr_index[0x8]; |
6765 | u8 flow_label[0x14]; | |
6766 | ||
6767 | u8 rgid_rip[16][0x8]; | |
6768 | }; | |
6769 | ||
6770 | struct mlx5_ifc_pages_req_event_bits { | |
b4ff3a36 | 6771 | u8 reserved_at_0[0x10]; |
e281682b SM |
6772 | u8 function_id[0x10]; |
6773 | ||
6774 | u8 num_pages[0x20]; | |
6775 | ||
b4ff3a36 | 6776 | u8 reserved_at_40[0xa0]; |
e281682b SM |
6777 | }; |
6778 | ||
6779 | struct mlx5_ifc_eqe_bits { | |
b4ff3a36 | 6780 | u8 reserved_at_0[0x8]; |
e281682b | 6781 | u8 event_type[0x8]; |
b4ff3a36 | 6782 | u8 reserved_at_10[0x8]; |
e281682b SM |
6783 | u8 event_sub_type[0x8]; |
6784 | ||
b4ff3a36 | 6785 | u8 reserved_at_20[0xe0]; |
e281682b SM |
6786 | |
6787 | union mlx5_ifc_event_auto_bits event_data; | |
6788 | ||
b4ff3a36 | 6789 | u8 reserved_at_1e0[0x10]; |
e281682b | 6790 | u8 signature[0x8]; |
b4ff3a36 | 6791 | u8 reserved_at_1f8[0x7]; |
e281682b SM |
6792 | u8 owner[0x1]; |
6793 | }; | |
6794 | ||
6795 | enum { | |
6796 | MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, | |
6797 | }; | |
6798 | ||
6799 | struct mlx5_ifc_cmd_queue_entry_bits { | |
6800 | u8 type[0x8]; | |
b4ff3a36 | 6801 | u8 reserved_at_8[0x18]; |
e281682b SM |
6802 | |
6803 | u8 input_length[0x20]; | |
6804 | ||
6805 | u8 input_mailbox_pointer_63_32[0x20]; | |
6806 | ||
6807 | u8 input_mailbox_pointer_31_9[0x17]; | |
b4ff3a36 | 6808 | u8 reserved_at_77[0x9]; |
e281682b SM |
6809 | |
6810 | u8 command_input_inline_data[16][0x8]; | |
6811 | ||
6812 | u8 command_output_inline_data[16][0x8]; | |
6813 | ||
6814 | u8 output_mailbox_pointer_63_32[0x20]; | |
6815 | ||
6816 | u8 output_mailbox_pointer_31_9[0x17]; | |
b4ff3a36 | 6817 | u8 reserved_at_1b7[0x9]; |
e281682b SM |
6818 | |
6819 | u8 output_length[0x20]; | |
6820 | ||
6821 | u8 token[0x8]; | |
6822 | u8 signature[0x8]; | |
b4ff3a36 | 6823 | u8 reserved_at_1f0[0x8]; |
e281682b SM |
6824 | u8 status[0x7]; |
6825 | u8 ownership[0x1]; | |
6826 | }; | |
6827 | ||
6828 | struct mlx5_ifc_cmd_out_bits { | |
6829 | u8 status[0x8]; | |
b4ff3a36 | 6830 | u8 reserved_at_8[0x18]; |
e281682b SM |
6831 | |
6832 | u8 syndrome[0x20]; | |
6833 | ||
6834 | u8 command_output[0x20]; | |
6835 | }; | |
6836 | ||
6837 | struct mlx5_ifc_cmd_in_bits { | |
6838 | u8 opcode[0x10]; | |
b4ff3a36 | 6839 | u8 reserved_at_10[0x10]; |
e281682b | 6840 | |
b4ff3a36 | 6841 | u8 reserved_at_20[0x10]; |
e281682b SM |
6842 | u8 op_mod[0x10]; |
6843 | ||
6844 | u8 command[0][0x20]; | |
6845 | }; | |
6846 | ||
6847 | struct mlx5_ifc_cmd_if_box_bits { | |
6848 | u8 mailbox_data[512][0x8]; | |
6849 | ||
b4ff3a36 | 6850 | u8 reserved_at_1000[0x180]; |
e281682b SM |
6851 | |
6852 | u8 next_pointer_63_32[0x20]; | |
6853 | ||
6854 | u8 next_pointer_31_10[0x16]; | |
b4ff3a36 | 6855 | u8 reserved_at_11b6[0xa]; |
e281682b SM |
6856 | |
6857 | u8 block_number[0x20]; | |
6858 | ||
b4ff3a36 | 6859 | u8 reserved_at_11e0[0x8]; |
e281682b SM |
6860 | u8 token[0x8]; |
6861 | u8 ctrl_signature[0x8]; | |
6862 | u8 signature[0x8]; | |
6863 | }; | |
6864 | ||
6865 | struct mlx5_ifc_mtt_bits { | |
6866 | u8 ptag_63_32[0x20]; | |
6867 | ||
6868 | u8 ptag_31_8[0x18]; | |
b4ff3a36 | 6869 | u8 reserved_at_38[0x6]; |
e281682b SM |
6870 | u8 wr_en[0x1]; |
6871 | u8 rd_en[0x1]; | |
6872 | }; | |
6873 | ||
6874 | enum { | |
6875 | MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, | |
6876 | MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, | |
6877 | MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, | |
6878 | }; | |
6879 | ||
6880 | enum { | |
6881 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, | |
6882 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, | |
6883 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, | |
6884 | }; | |
6885 | ||
6886 | enum { | |
6887 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, | |
6888 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, | |
6889 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, | |
6890 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, | |
6891 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, | |
6892 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, | |
6893 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, | |
6894 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, | |
6895 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, | |
6896 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, | |
6897 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, | |
6898 | }; | |
6899 | ||
6900 | struct mlx5_ifc_initial_seg_bits { | |
6901 | u8 fw_rev_minor[0x10]; | |
6902 | u8 fw_rev_major[0x10]; | |
6903 | ||
6904 | u8 cmd_interface_rev[0x10]; | |
6905 | u8 fw_rev_subminor[0x10]; | |
6906 | ||
b4ff3a36 | 6907 | u8 reserved_at_40[0x40]; |
e281682b SM |
6908 | |
6909 | u8 cmdq_phy_addr_63_32[0x20]; | |
6910 | ||
6911 | u8 cmdq_phy_addr_31_12[0x14]; | |
b4ff3a36 | 6912 | u8 reserved_at_b4[0x2]; |
e281682b SM |
6913 | u8 nic_interface[0x2]; |
6914 | u8 log_cmdq_size[0x4]; | |
6915 | u8 log_cmdq_stride[0x4]; | |
6916 | ||
6917 | u8 command_doorbell_vector[0x20]; | |
6918 | ||
b4ff3a36 | 6919 | u8 reserved_at_e0[0xf00]; |
e281682b SM |
6920 | |
6921 | u8 initializing[0x1]; | |
b4ff3a36 | 6922 | u8 reserved_at_fe1[0x4]; |
e281682b | 6923 | u8 nic_interface_supported[0x3]; |
b4ff3a36 | 6924 | u8 reserved_at_fe8[0x18]; |
e281682b SM |
6925 | |
6926 | struct mlx5_ifc_health_buffer_bits health_buffer; | |
6927 | ||
6928 | u8 no_dram_nic_offset[0x20]; | |
6929 | ||
b4ff3a36 | 6930 | u8 reserved_at_1220[0x6e40]; |
e281682b | 6931 | |
b4ff3a36 | 6932 | u8 reserved_at_8060[0x1f]; |
e281682b SM |
6933 | u8 clear_int[0x1]; |
6934 | ||
6935 | u8 health_syndrome[0x8]; | |
6936 | u8 health_counter[0x18]; | |
6937 | ||
b4ff3a36 | 6938 | u8 reserved_at_80a0[0x17fc0]; |
e281682b SM |
6939 | }; |
6940 | ||
6941 | union mlx5_ifc_ports_control_registers_document_bits { | |
6942 | struct mlx5_ifc_bufferx_reg_bits bufferx_reg; | |
6943 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; | |
6944 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; | |
6945 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; | |
6946 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; | |
6947 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; | |
6948 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; | |
6949 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; | |
6950 | struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; | |
6951 | struct mlx5_ifc_pamp_reg_bits pamp_reg; | |
6952 | struct mlx5_ifc_paos_reg_bits paos_reg; | |
6953 | struct mlx5_ifc_pcap_reg_bits pcap_reg; | |
6954 | struct mlx5_ifc_peir_reg_bits peir_reg; | |
6955 | struct mlx5_ifc_pelc_reg_bits pelc_reg; | |
6956 | struct mlx5_ifc_pfcc_reg_bits pfcc_reg; | |
6957 | struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; | |
6958 | struct mlx5_ifc_pifr_reg_bits pifr_reg; | |
6959 | struct mlx5_ifc_pipg_reg_bits pipg_reg; | |
6960 | struct mlx5_ifc_plbf_reg_bits plbf_reg; | |
6961 | struct mlx5_ifc_plib_reg_bits plib_reg; | |
6962 | struct mlx5_ifc_plpc_reg_bits plpc_reg; | |
6963 | struct mlx5_ifc_pmaos_reg_bits pmaos_reg; | |
6964 | struct mlx5_ifc_pmlp_reg_bits pmlp_reg; | |
6965 | struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; | |
6966 | struct mlx5_ifc_pmpc_reg_bits pmpc_reg; | |
6967 | struct mlx5_ifc_pmpe_reg_bits pmpe_reg; | |
6968 | struct mlx5_ifc_pmpr_reg_bits pmpr_reg; | |
6969 | struct mlx5_ifc_pmtu_reg_bits pmtu_reg; | |
6970 | struct mlx5_ifc_ppad_reg_bits ppad_reg; | |
6971 | struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; | |
6972 | struct mlx5_ifc_pplm_reg_bits pplm_reg; | |
6973 | struct mlx5_ifc_pplr_reg_bits pplr_reg; | |
6974 | struct mlx5_ifc_ppsc_reg_bits ppsc_reg; | |
6975 | struct mlx5_ifc_pqdr_reg_bits pqdr_reg; | |
6976 | struct mlx5_ifc_pspa_reg_bits pspa_reg; | |
6977 | struct mlx5_ifc_ptas_reg_bits ptas_reg; | |
6978 | struct mlx5_ifc_ptys_reg_bits ptys_reg; | |
6979 | struct mlx5_ifc_pude_reg_bits pude_reg; | |
6980 | struct mlx5_ifc_pvlc_reg_bits pvlc_reg; | |
6981 | struct mlx5_ifc_slrg_reg_bits slrg_reg; | |
6982 | struct mlx5_ifc_sltp_reg_bits sltp_reg; | |
b4ff3a36 | 6983 | u8 reserved_at_0[0x60e0]; |
e281682b SM |
6984 | }; |
6985 | ||
6986 | union mlx5_ifc_debug_enhancements_document_bits { | |
6987 | struct mlx5_ifc_health_buffer_bits health_buffer; | |
b4ff3a36 | 6988 | u8 reserved_at_0[0x200]; |
e281682b SM |
6989 | }; |
6990 | ||
6991 | union mlx5_ifc_uplink_pci_interface_document_bits { | |
6992 | struct mlx5_ifc_initial_seg_bits initial_seg; | |
b4ff3a36 | 6993 | u8 reserved_at_0[0x20060]; |
b775516b EC |
6994 | }; |
6995 | ||
2cc43b49 MG |
6996 | struct mlx5_ifc_set_flow_table_root_out_bits { |
6997 | u8 status[0x8]; | |
b4ff3a36 | 6998 | u8 reserved_at_8[0x18]; |
2cc43b49 MG |
6999 | |
7000 | u8 syndrome[0x20]; | |
7001 | ||
b4ff3a36 | 7002 | u8 reserved_at_40[0x40]; |
2cc43b49 MG |
7003 | }; |
7004 | ||
7005 | struct mlx5_ifc_set_flow_table_root_in_bits { | |
7006 | u8 opcode[0x10]; | |
b4ff3a36 | 7007 | u8 reserved_at_10[0x10]; |
2cc43b49 | 7008 | |
b4ff3a36 | 7009 | u8 reserved_at_20[0x10]; |
2cc43b49 MG |
7010 | u8 op_mod[0x10]; |
7011 | ||
b4ff3a36 | 7012 | u8 reserved_at_40[0x40]; |
2cc43b49 MG |
7013 | |
7014 | u8 table_type[0x8]; | |
b4ff3a36 | 7015 | u8 reserved_at_88[0x18]; |
2cc43b49 | 7016 | |
b4ff3a36 | 7017 | u8 reserved_at_a0[0x8]; |
2cc43b49 MG |
7018 | u8 table_id[0x18]; |
7019 | ||
b4ff3a36 | 7020 | u8 reserved_at_c0[0x140]; |
2cc43b49 MG |
7021 | }; |
7022 | ||
34a40e68 MG |
7023 | enum { |
7024 | MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1, | |
7025 | }; | |
7026 | ||
7027 | struct mlx5_ifc_modify_flow_table_out_bits { | |
7028 | u8 status[0x8]; | |
b4ff3a36 | 7029 | u8 reserved_at_8[0x18]; |
34a40e68 MG |
7030 | |
7031 | u8 syndrome[0x20]; | |
7032 | ||
b4ff3a36 | 7033 | u8 reserved_at_40[0x40]; |
34a40e68 MG |
7034 | }; |
7035 | ||
7036 | struct mlx5_ifc_modify_flow_table_in_bits { | |
7037 | u8 opcode[0x10]; | |
b4ff3a36 | 7038 | u8 reserved_at_10[0x10]; |
34a40e68 | 7039 | |
b4ff3a36 | 7040 | u8 reserved_at_20[0x10]; |
34a40e68 MG |
7041 | u8 op_mod[0x10]; |
7042 | ||
b4ff3a36 | 7043 | u8 reserved_at_40[0x20]; |
34a40e68 | 7044 | |
b4ff3a36 | 7045 | u8 reserved_at_60[0x10]; |
34a40e68 MG |
7046 | u8 modify_field_select[0x10]; |
7047 | ||
7048 | u8 table_type[0x8]; | |
b4ff3a36 | 7049 | u8 reserved_at_88[0x18]; |
34a40e68 | 7050 | |
b4ff3a36 | 7051 | u8 reserved_at_a0[0x8]; |
34a40e68 MG |
7052 | u8 table_id[0x18]; |
7053 | ||
b4ff3a36 | 7054 | u8 reserved_at_c0[0x4]; |
34a40e68 | 7055 | u8 table_miss_mode[0x4]; |
b4ff3a36 | 7056 | u8 reserved_at_c8[0x18]; |
34a40e68 | 7057 | |
b4ff3a36 | 7058 | u8 reserved_at_e0[0x8]; |
34a40e68 MG |
7059 | u8 table_miss_id[0x18]; |
7060 | ||
b4ff3a36 | 7061 | u8 reserved_at_100[0x100]; |
34a40e68 MG |
7062 | }; |
7063 | ||
d29b796a | 7064 | #endif /* MLX5_IFC_H */ |