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net/mlx5: Introduce access functions to modify/query vport promisc mode
[deliverable/linux.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
d29b796a
EC		 69enum {
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
d29b796a
EC		 164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
197};
198
199struct mlx5_ifc_flow_table_fields_supported_bits {
200 u8 outer_dmac[0x1];
201 u8 outer_smac[0x1];
202 u8 outer_ether_type[0x1];
203 u8 reserved_0[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
207 u8 reserved_1[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
211 u8 reserved_2[0x1];
212 u8 outer_sip[0x1];
213 u8 outer_dip[0x1];
214 u8 outer_frag[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
226 u8 reserved_3[0x5];
227 u8 source_eswitch_port[0x1];
228
229 u8 inner_dmac[0x1];
230 u8 inner_smac[0x1];
231 u8 inner_ether_type[0x1];
232 u8 reserved_4[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
236 u8 reserved_5[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
240 u8 reserved_6[0x1];
241 u8 inner_sip[0x1];
242 u8 inner_dip[0x1];
243 u8 inner_frag[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
252 u8 reserved_7[0x9];
253
254 u8 reserved_8[0x40];
255};
256
257struct mlx5_ifc_flow_table_prop_layout_bits {
258 u8 ft_support[0x1];
259 u8 reserved_0[0x1f];
260
261 u8 reserved_1[0x2];
262 u8 log_max_ft_size[0x6];
263 u8 reserved_2[0x10];
264 u8 max_ft_level[0x8];
265
266 u8 reserved_3[0x20];
267
268 u8 reserved_4[0x18];
269 u8 log_max_ft_num[0x8];
270
271 u8 reserved_5[0x18];
272 u8 log_max_destination[0x8];
273
274 u8 reserved_6[0x18];
275 u8 log_max_flow[0x8];
276
277 u8 reserved_7[0x40];
278
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
280
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
282};
283
284struct mlx5_ifc_odp_per_transport_service_cap_bits {
285 u8 send[0x1];
286 u8 receive[0x1];
287 u8 write[0x1];
288 u8 read[0x1];
289 u8 reserved_0[0x1];
290 u8 srq_receive[0x1];
291 u8 reserved_1[0x1a];
292};
293
294struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
295 u8 smac_47_16[0x20];
296
297 u8 smac_15_0[0x10];
298 u8 ethertype[0x10];
299
300 u8 dmac_47_16[0x20];
301
302 u8 dmac_15_0[0x10];
303 u8 first_prio[0x3];
304 u8 first_cfi[0x1];
305 u8 first_vid[0xc];
306
307 u8 ip_protocol[0x8];
308 u8 ip_dscp[0x6];
309 u8 ip_ecn[0x2];
310 u8 vlan_tag[0x1];
311 u8 reserved_0[0x1];
312 u8 frag[0x1];
313 u8 reserved_1[0x4];
314 u8 tcp_flags[0x9];
315
316 u8 tcp_sport[0x10];
317 u8 tcp_dport[0x10];
318
319 u8 reserved_2[0x20];
320
321 u8 udp_sport[0x10];
322 u8 udp_dport[0x10];
323
324 u8 src_ip[4][0x20];
325
326 u8 dst_ip[4][0x20];
327};
328
329struct mlx5_ifc_fte_match_set_misc_bits {
330 u8 reserved_0[0x20];
331
332 u8 reserved_1[0x10];
333 u8 source_port[0x10];
334
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
341
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
344 u8 reserved_2[0xe];
345 u8 gre_protocol[0x10];
346
347 u8 gre_key_h[0x18];
348 u8 gre_key_l[0x8];
349
350 u8 vxlan_vni[0x18];
351 u8 reserved_3[0x8];
352
353 u8 reserved_4[0x20];
354
355 u8 reserved_5[0xc];
356 u8 outer_ipv6_flow_label[0x14];
357
358 u8 reserved_6[0xc];
359 u8 inner_ipv6_flow_label[0x14];
360
361 u8 reserved_7[0xe0];
362};
363
364struct mlx5_ifc_cmd_pas_bits {
365 u8 pa_h[0x20];
366
367 u8 pa_l[0x14];
368 u8 reserved_0[0xc];
369};
370
371struct mlx5_ifc_uint64_bits {
372 u8 hi[0x20];
373
374 u8 lo[0x20];
375};
376
377enum {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
388};
389
390struct mlx5_ifc_ads_bits {
391 u8 fl[0x1];
392 u8 free_ar[0x1];
393 u8 reserved_0[0xe];
394 u8 pkey_index[0x10];
395
396 u8 reserved_1[0x8];
397 u8 grh[0x1];
398 u8 mlid[0x7];
399 u8 rlid[0x10];
400
401 u8 ack_timeout[0x5];
402 u8 reserved_2[0x3];
403 u8 src_addr_index[0x8];
404 u8 reserved_3[0x4];
405 u8 stat_rate[0x4];
406 u8 hop_limit[0x8];
407
408 u8 reserved_4[0x4];
409 u8 tclass[0x8];
410 u8 flow_label[0x14];
411
412 u8 rgid_rip[16][0x8];
413
414 u8 reserved_5[0x4];
415 u8 f_dscp[0x1];
416 u8 f_ecn[0x1];
417 u8 reserved_6[0x1];
418 u8 f_eth_prio[0x1];
419 u8 ecn[0x2];
420 u8 dscp[0x6];
421 u8 udp_sport[0x10];
422
423 u8 dei_cfi[0x1];
424 u8 eth_prio[0x3];
425 u8 sl[0x4];
426 u8 port[0x8];
427 u8 rmac_47_32[0x10];
428
429 u8 rmac_31_0[0x20];
430};
431
432struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
434
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
436
437 u8 reserved_1[0x200];
438
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
440
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
442
443 u8 reserved_2[0x200];
444
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
446
447 u8 reserved_3[0x7200];
448};
449
450struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
451 u8 csum_cap[0x1];
452 u8 vlan_cap[0x1];
453 u8 lro_cap[0x1];
454 u8 lro_psh_flag[0x1];
455 u8 lro_time_stamp[0x1];
66189961
TT		 456 u8 reserved_0[0x3];
457 u8 self_lb_en_modifiable[0x1];
458 u8 reserved_1[0x2];
e281682b 459 u8 max_lso_cap[0x5];
66189961 460 u8 reserved_2[0x4];
e281682b 461 u8 rss_ind_tbl_cap[0x4];
66189961 462 u8 reserved_3[0x3];
e281682b 463 u8 tunnel_lso_const_out_ip_id[0x1];
66189961 464 u8 reserved_4[0x2];
e281682b
SM		 465 u8 tunnel_statless_gre[0x1];
466 u8 tunnel_stateless_vxlan[0x1];
467
66189961 468 u8 reserved_5[0x20];
e281682b 469
66189961 470 u8 reserved_6[0x10];
e281682b
SM		 471 u8 lro_min_mss_size[0x10];
472
66189961 473 u8 reserved_7[0x120];
e281682b
SM		 474
475 u8 lro_timer_supported_periods[4][0x20];
476
66189961 477 u8 reserved_8[0x600];
e281682b
SM		 478};
479
480struct mlx5_ifc_roce_cap_bits {
481 u8 roce_apm[0x1];
482 u8 reserved_0[0x1f];
483
484 u8 reserved_1[0x60];
485
486 u8 reserved_2[0xc];
487 u8 l3_type[0x4];
488 u8 reserved_3[0x8];
489 u8 roce_version[0x8];
490
491 u8 reserved_4[0x10];
492 u8 r_roce_dest_udp_port[0x10];
493
494 u8 r_roce_max_src_udp_port[0x10];
495 u8 r_roce_min_src_udp_port[0x10];
496
497 u8 reserved_5[0x10];
498 u8 roce_address_table_size[0x10];
499
500 u8 reserved_6[0x700];
501};
502
503enum {
504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
511 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
512 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
513};
514
515enum {
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
525};
526
527struct mlx5_ifc_atomic_caps_bits {
528 u8 reserved_0[0x40];
529
530 u8 atomic_req_endianness[0x1];
531 u8 reserved_1[0x1f];
532
533 u8 reserved_2[0x20];
534
535 u8 reserved_3[0x10];
536 u8 atomic_operations[0x10];
537
538 u8 reserved_4[0x10];
539 u8 atomic_size_qp[0x10];
540
541 u8 reserved_5[0x10];
542 u8 atomic_size_dc[0x10];
543
544 u8 reserved_6[0x720];
545};
546
547struct mlx5_ifc_odp_cap_bits {
548 u8 reserved_0[0x40];
549
550 u8 sig[0x1];
551 u8 reserved_1[0x1f];
552
553 u8 reserved_2[0x20];
554
555 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
556
557 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
558
559 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
560
561 u8 reserved_3[0x720];
562};
563
564enum {
565 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
566 MLX5_WQ_TYPE_CYCLIC = 0x1,
567 MLX5_WQ_TYPE_STRQ = 0x2,
568};
569
570enum {
571 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
572 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
573};
574
575enum {
576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
579 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
580 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
581};
582
583enum {
584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
588 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
589 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
590};
591
592enum {
593 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
594 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
595};
596
597enum {
598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
599 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
600 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
601};
602
603enum {
604 MLX5_CAP_PORT_TYPE_IB = 0x0,
605 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 606};
607
b775516b
EC		 608struct mlx5_ifc_cmd_hca_cap_bits {
609 u8 reserved_0[0x80];
610
611 u8 log_max_srq_sz[0x8];
612 u8 log_max_qp_sz[0x8];
613 u8 reserved_1[0xb];
614 u8 log_max_qp[0x5];
615
e281682b
SM		 616 u8 reserved_2[0xb];
617 u8 log_max_srq[0x5];
b775516b
EC		 618 u8 reserved_3[0x10];
619
620 u8 reserved_4[0x8];
621 u8 log_max_cq_sz[0x8];
622 u8 reserved_5[0xb];
623 u8 log_max_cq[0x5];
624
625 u8 log_max_eq_sz[0x8];
626 u8 reserved_6[0x2];
627 u8 log_max_mkey[0x6];
628 u8 reserved_7[0xc];
629 u8 log_max_eq[0x4];
630
631 u8 max_indirection[0x8];
632 u8 reserved_8[0x1];
633 u8 log_max_mrw_sz[0x7];
634 u8 reserved_9[0x2];
635 u8 log_max_bsf_list_size[0x6];
636 u8 reserved_10[0x2];
637 u8 log_max_klm_list_size[0x6];
638
639 u8 reserved_11[0xa];
640 u8 log_max_ra_req_dc[0x6];
641 u8 reserved_12[0xa];
642 u8 log_max_ra_res_dc[0x6];
643
644 u8 reserved_13[0xa];
645 u8 log_max_ra_req_qp[0x6];
646 u8 reserved_14[0xa];
647 u8 log_max_ra_res_qp[0x6];
648
649 u8 pad_cap[0x1];
650 u8 cc_query_allowed[0x1];
651 u8 cc_modify_allowed[0x1];
e281682b
SM		 652 u8 reserved_15[0xd];
653 u8 gid_table_size[0x10];
b775516b 654
e281682b
SM		 655 u8 out_of_seq_cnt[0x1];
656 u8 vport_counters[0x1];
657 u8 reserved_16[0x4];
b775516b
EC		 658 u8 max_qp_cnt[0xa];
659 u8 pkey_table_size[0x10];
660
e281682b
SM		 661 u8 vport_group_manager[0x1];
662 u8 vhca_group_manager[0x1];
663 u8 ib_virt[0x1];
664 u8 eth_virt[0x1];
665 u8 reserved_17[0x1];
666 u8 ets[0x1];
667 u8 nic_flow_table[0x1];
54f0a411 668 u8 eswitch_flow_table[0x1];
fc50db98
EC		 669 u8 early_vf_enable;
670 u8 reserved_18[0x2];
b775516b 671 u8 local_ca_ack_delay[0x5];
e281682b
SM		 672 u8 reserved_19[0x6];
673 u8 port_type[0x2];
b775516b
EC		 674 u8 num_ports[0x8];
675
e281682b 676 u8 reserved_20[0x3];
b775516b 677 u8 log_max_msg[0x5];
e281682b 678 u8 reserved_21[0x18];
b775516b
EC		 679
680 u8 stat_rate_support[0x10];
e281682b
SM		 681 u8 reserved_22[0xc];
682 u8 cqe_version[0x4];
b775516b 683
e281682b
SM		 684 u8 compact_address_vector[0x1];
685 u8 reserved_23[0xe];
686 u8 drain_sigerr[0x1];
b775516b
EC		 687 u8 cmdif_checksum[0x2];
688 u8 sigerr_cqe[0x1];
e281682b 689 u8 reserved_24[0x1];
b775516b
EC		 690 u8 wq_signature[0x1];
691 u8 sctr_data_cqe[0x1];
e281682b 692 u8 reserved_25[0x1];
b775516b
EC		 693 u8 sho[0x1];
694 u8 tph[0x1];
695 u8 rf[0x1];
e281682b
SM		 696 u8 dct[0x1];
697 u8 reserved_26[0x1];
698 u8 eth_net_offloads[0x1];
b775516b
EC		 699 u8 roce[0x1];
700 u8 atomic[0x1];
e281682b 701 u8 reserved_27[0x1];
b775516b
EC		 702
703 u8 cq_oi[0x1];
704 u8 cq_resize[0x1];
705 u8 cq_moderation[0x1];
e281682b
SM		 706 u8 reserved_28[0x3];
707 u8 cq_eq_remap[0x1];
b775516b
EC		 708 u8 pg[0x1];
709 u8 block_lb_mc[0x1];
e281682b
SM		 710 u8 reserved_29[0x1];
711 u8 scqe_break_moderation[0x1];
712 u8 reserved_30[0x1];
b775516b 713 u8 cd[0x1];
e281682b 714 u8 reserved_31[0x1];
b775516b 715 u8 apm[0x1];
e281682b 716 u8 reserved_32[0x7];
b775516b
EC		 717 u8 qkv[0x1];
718 u8 pkv[0x1];
e281682b 719 u8 reserved_33[0x4];
b775516b
EC		 720 u8 xrc[0x1];
721 u8 ud[0x1];
722 u8 uc[0x1];
723 u8 rc[0x1];
724
e281682b 725 u8 reserved_34[0xa];
b775516b 726 u8 uar_sz[0x6];
e281682b 727 u8 reserved_35[0x8];
b775516b
EC		 728 u8 log_pg_sz[0x8];
729
730 u8 bf[0x1];
e281682b
SM		 731 u8 reserved_36[0x1];
732 u8 pad_tx_eth_packet[0x1];
733 u8 reserved_37[0x8];
b775516b 734 u8 log_bf_reg_size[0x5];
e281682b 735 u8 reserved_38[0x10];
b775516b 736
e281682b 737 u8 reserved_39[0x10];
b775516b
EC		 738 u8 max_wqe_sz_sq[0x10];
739
e281682b 740 u8 reserved_40[0x10];
b775516b
EC		 741 u8 max_wqe_sz_rq[0x10];
742
e281682b 743 u8 reserved_41[0x10];
b775516b
EC		 744 u8 max_wqe_sz_sq_dc[0x10];
745
e281682b 746 u8 reserved_42[0x7];
b775516b
EC		 747 u8 max_qp_mcg[0x19];
748
e281682b 749 u8 reserved_43[0x18];
b775516b
EC		 750 u8 log_max_mcg[0x8];
751
e281682b
SM		 752 u8 reserved_44[0x3];
753 u8 log_max_transport_domain[0x5];
754 u8 reserved_45[0x3];
b775516b 755 u8 log_max_pd[0x5];
e281682b 756 u8 reserved_46[0xb];
b775516b
EC		 757 u8 log_max_xrcd[0x5];
758
e281682b 759 u8 reserved_47[0x20];
b775516b 760
e281682b 761 u8 reserved_48[0x3];
b775516b 762 u8 log_max_rq[0x5];
e281682b 763 u8 reserved_49[0x3];
b775516b 764 u8 log_max_sq[0x5];
e281682b 765 u8 reserved_50[0x3];
b775516b 766 u8 log_max_tir[0x5];
e281682b 767 u8 reserved_51[0x3];
b775516b
EC		 768 u8 log_max_tis[0x5];
769
e281682b
SM		 770 u8 basic_cyclic_rcv_wqe[0x1];
771 u8 reserved_52[0x2];
772 u8 log_max_rmp[0x5];
773 u8 reserved_53[0x3];
774 u8 log_max_rqt[0x5];
775 u8 reserved_54[0x3];
776 u8 log_max_rqt_size[0x5];
777 u8 reserved_55[0x3];
b775516b
EC		 778 u8 log_max_tis_per_sq[0x5];
779
e281682b
SM		 780 u8 reserved_56[0x3];
781 u8 log_max_stride_sz_rq[0x5];
782 u8 reserved_57[0x3];
783 u8 log_min_stride_sz_rq[0x5];
784 u8 reserved_58[0x3];
785 u8 log_max_stride_sz_sq[0x5];
786 u8 reserved_59[0x3];
787 u8 log_min_stride_sz_sq[0x5];
788
789 u8 reserved_60[0x1b];
790 u8 log_max_wq_sz[0x5];
791
54f0a411
SM		 792 u8 nic_vport_change_event[0x1];
793 u8 reserved_61[0xa];
794 u8 log_max_vlan_list[0x5];
e281682b 795 u8 reserved_62[0x3];
54f0a411
SM		 796 u8 log_max_current_mc_list[0x5];
797 u8 reserved_63[0x3];
798 u8 log_max_current_uc_list[0x5];
799
800 u8 reserved_64[0x80];
801
802 u8 reserved_65[0x3];
e281682b 803 u8 log_max_l2_table[0x5];
54f0a411 804 u8 reserved_66[0x8];
b775516b
EC		 805 u8 log_uar_page_sz[0x10];
806
54f0a411 807 u8 reserved_67[0xe0];
b775516b 808
54f0a411 809 u8 reserved_68[0x1f];
b775516b
EC		 810 u8 cqe_zip[0x1];
811
812 u8 cqe_zip_timeout[0x10];
813 u8 cqe_zip_max_num[0x10];
814
54f0a411 815 u8 reserved_69[0x220];
b775516b
EC		 816};
817
e281682b
SM		 818enum {
819 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
820 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
821};
b775516b 822
e281682b
SM		 823struct mlx5_ifc_dest_format_struct_bits {
824 u8 destination_type[0x8];
825 u8 destination_id[0x18];
b775516b 826
e281682b
SM		 827 u8 reserved_0[0x20];
828};
829
830struct mlx5_ifc_fte_match_param_bits {
831 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
832
833 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
834
835 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 836
e281682b 837 u8 reserved_0[0xa00];
b775516b
EC		 838};
839
e281682b
SM		 840enum {
841 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
842 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
843 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
844 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
845 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
846};
b775516b 847
e281682b
SM		 848struct mlx5_ifc_rx_hash_field_select_bits {
849 u8 l3_prot_type[0x1];
850 u8 l4_prot_type[0x1];
851 u8 selected_fields[0x1e];
852};
b775516b 853
e281682b
SM		 854enum {
855 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
856 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 857};
858
e281682b
SM		 859enum {
860 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
861 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
862};
863
864struct mlx5_ifc_wq_bits {
865 u8 wq_type[0x4];
866 u8 wq_signature[0x1];
867 u8 end_padding_mode[0x2];
868 u8 cd_slave[0x1];
b775516b
EC		 869 u8 reserved_0[0x18];
870
e281682b
SM		 871 u8 hds_skip_first_sge[0x1];
872 u8 log2_hds_buf_size[0x3];
873 u8 reserved_1[0x7];
874 u8 page_offset[0x5];
875 u8 lwm[0x10];
b775516b 876
e281682b
SM		 877 u8 reserved_2[0x8];
878 u8 pd[0x18];
879
880 u8 reserved_3[0x8];
881 u8 uar_page[0x18];
882
883 u8 dbr_addr[0x40];
884
885 u8 hw_counter[0x20];
886
887 u8 sw_counter[0x20];
888
889 u8 reserved_4[0xc];
890 u8 log_wq_stride[0x4];
891 u8 reserved_5[0x3];
892 u8 log_wq_pg_sz[0x5];
893 u8 reserved_6[0x3];
894 u8 log_wq_sz[0x5];
895
896 u8 reserved_7[0x4e0];
b775516b 897
e281682b 898 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 899};
900
e281682b
SM		 901struct mlx5_ifc_rq_num_bits {
902 u8 reserved_0[0x8];
903 u8 rq_num[0x18];
904};
b775516b 905
e281682b
SM		 906struct mlx5_ifc_mac_address_layout_bits {
907 u8 reserved_0[0x10];
908 u8 mac_addr_47_32[0x10];
b775516b 909
e281682b
SM		 910 u8 mac_addr_31_0[0x20];
911};
912
913struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
914 u8 reserved_0[0xa0];
915
916 u8 min_time_between_cnps[0x20];
917
918 u8 reserved_1[0x12];
919 u8 cnp_dscp[0x6];
920 u8 reserved_2[0x5];
921 u8 cnp_802p_prio[0x3];
922
923 u8 reserved_3[0x720];
924};
925
926struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
927 u8 reserved_0[0x60];
928
929 u8 reserved_1[0x4];
930 u8 clamp_tgt_rate[0x1];
931 u8 reserved_2[0x3];
932 u8 clamp_tgt_rate_after_time_inc[0x1];
933 u8 reserved_3[0x17];
934
935 u8 reserved_4[0x20];
936
937 u8 rpg_time_reset[0x20];
938
939 u8 rpg_byte_reset[0x20];
940
941 u8 rpg_threshold[0x20];
942
943 u8 rpg_max_rate[0x20];
944
945 u8 rpg_ai_rate[0x20];
946
947 u8 rpg_hai_rate[0x20];
948
949 u8 rpg_gd[0x20];
950
951 u8 rpg_min_dec_fac[0x20];
952
953 u8 rpg_min_rate[0x20];
954
955 u8 reserved_5[0xe0];
956
957 u8 rate_to_set_on_first_cnp[0x20];
958
959 u8 dce_tcp_g[0x20];
960
961 u8 dce_tcp_rtt[0x20];
962
963 u8 rate_reduce_monitor_period[0x20];
964
965 u8 reserved_6[0x20];
966
967 u8 initial_alpha_value[0x20];
968
969 u8 reserved_7[0x4a0];
970};
971
972struct mlx5_ifc_cong_control_802_1qau_rp_bits {
973 u8 reserved_0[0x80];
974
975 u8 rppp_max_rps[0x20];
976
977 u8 rpg_time_reset[0x20];
978
979 u8 rpg_byte_reset[0x20];
980
981 u8 rpg_threshold[0x20];
982
983 u8 rpg_max_rate[0x20];
984
985 u8 rpg_ai_rate[0x20];
986
987 u8 rpg_hai_rate[0x20];
988
989 u8 rpg_gd[0x20];
990
991 u8 rpg_min_dec_fac[0x20];
992
993 u8 rpg_min_rate[0x20];
994
995 u8 reserved_1[0x640];
996};
997
998enum {
999 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1000 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1001 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1002};
1003
1004struct mlx5_ifc_resize_field_select_bits {
1005 u8 resize_field_select[0x20];
1006};
1007
1008enum {
1009 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1010 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1011 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1012 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1013};
1014
1015struct mlx5_ifc_modify_field_select_bits {
1016 u8 modify_field_select[0x20];
1017};
1018
1019struct mlx5_ifc_field_select_r_roce_np_bits {
1020 u8 field_select_r_roce_np[0x20];
1021};
1022
1023struct mlx5_ifc_field_select_r_roce_rp_bits {
1024 u8 field_select_r_roce_rp[0x20];
1025};
1026
1027enum {
1028 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1029 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1030 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1031 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1032 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1033 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1034 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1035 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1036 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1037 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1038};
1039
1040struct mlx5_ifc_field_select_802_1qau_rp_bits {
1041 u8 field_select_8021qaurp[0x20];
1042};
1043
1044struct mlx5_ifc_phys_layer_cntrs_bits {
1045 u8 time_since_last_clear_high[0x20];
1046
1047 u8 time_since_last_clear_low[0x20];
1048
1049 u8 symbol_errors_high[0x20];
1050
1051 u8 symbol_errors_low[0x20];
1052
1053 u8 sync_headers_errors_high[0x20];
1054
1055 u8 sync_headers_errors_low[0x20];
1056
1057 u8 edpl_bip_errors_lane0_high[0x20];
1058
1059 u8 edpl_bip_errors_lane0_low[0x20];
1060
1061 u8 edpl_bip_errors_lane1_high[0x20];
1062
1063 u8 edpl_bip_errors_lane1_low[0x20];
1064
1065 u8 edpl_bip_errors_lane2_high[0x20];
1066
1067 u8 edpl_bip_errors_lane2_low[0x20];
1068
1069 u8 edpl_bip_errors_lane3_high[0x20];
1070
1071 u8 edpl_bip_errors_lane3_low[0x20];
1072
1073 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1074
1075 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1076
1077 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1078
1079 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1080
1081 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1082
1083 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1084
1085 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1086
1087 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1088
1089 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1090
1091 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1092
1093 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1094
1095 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1096
1097 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1098
1099 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1100
1101 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1102
1103 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1104
1105 u8 rs_fec_corrected_blocks_high[0x20];
1106
1107 u8 rs_fec_corrected_blocks_low[0x20];
1108
1109 u8 rs_fec_uncorrectable_blocks_high[0x20];
1110
1111 u8 rs_fec_uncorrectable_blocks_low[0x20];
1112
1113 u8 rs_fec_no_errors_blocks_high[0x20];
1114
1115 u8 rs_fec_no_errors_blocks_low[0x20];
1116
1117 u8 rs_fec_single_error_blocks_high[0x20];
1118
1119 u8 rs_fec_single_error_blocks_low[0x20];
1120
1121 u8 rs_fec_corrected_symbols_total_high[0x20];
1122
1123 u8 rs_fec_corrected_symbols_total_low[0x20];
1124
1125 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1126
1127 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1128
1129 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1130
1131 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1132
1133 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1134
1135 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1136
1137 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1138
1139 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1140
1141 u8 link_down_events[0x20];
1142
1143 u8 successful_recovery_events[0x20];
1144
1145 u8 reserved_0[0x180];
1146};
1147
1148struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1149 u8 transmit_queue_high[0x20];
1150
1151 u8 transmit_queue_low[0x20];
1152
1153 u8 reserved_0[0x780];
1154};
1155
1156struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1157 u8 rx_octets_high[0x20];
1158
1159 u8 rx_octets_low[0x20];
1160
1161 u8 reserved_0[0xc0];
1162
1163 u8 rx_frames_high[0x20];
1164
1165 u8 rx_frames_low[0x20];
1166
1167 u8 tx_octets_high[0x20];
1168
1169 u8 tx_octets_low[0x20];
1170
1171 u8 reserved_1[0xc0];
1172
1173 u8 tx_frames_high[0x20];
1174
1175 u8 tx_frames_low[0x20];
1176
1177 u8 rx_pause_high[0x20];
1178
1179 u8 rx_pause_low[0x20];
1180
1181 u8 rx_pause_duration_high[0x20];
1182
1183 u8 rx_pause_duration_low[0x20];
1184
1185 u8 tx_pause_high[0x20];
1186
1187 u8 tx_pause_low[0x20];
1188
1189 u8 tx_pause_duration_high[0x20];
1190
1191 u8 tx_pause_duration_low[0x20];
1192
1193 u8 rx_pause_transition_high[0x20];
1194
1195 u8 rx_pause_transition_low[0x20];
1196
1197 u8 reserved_2[0x400];
1198};
1199
1200struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1201 u8 port_transmit_wait_high[0x20];
1202
1203 u8 port_transmit_wait_low[0x20];
1204
1205 u8 reserved_0[0x780];
1206};
1207
1208struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1209 u8 dot3stats_alignment_errors_high[0x20];
1210
1211 u8 dot3stats_alignment_errors_low[0x20];
1212
1213 u8 dot3stats_fcs_errors_high[0x20];
1214
1215 u8 dot3stats_fcs_errors_low[0x20];
1216
1217 u8 dot3stats_single_collision_frames_high[0x20];
1218
1219 u8 dot3stats_single_collision_frames_low[0x20];
1220
1221 u8 dot3stats_multiple_collision_frames_high[0x20];
1222
1223 u8 dot3stats_multiple_collision_frames_low[0x20];
1224
1225 u8 dot3stats_sqe_test_errors_high[0x20];
1226
1227 u8 dot3stats_sqe_test_errors_low[0x20];
1228
1229 u8 dot3stats_deferred_transmissions_high[0x20];
1230
1231 u8 dot3stats_deferred_transmissions_low[0x20];
1232
1233 u8 dot3stats_late_collisions_high[0x20];
1234
1235 u8 dot3stats_late_collisions_low[0x20];
1236
1237 u8 dot3stats_excessive_collisions_high[0x20];
1238
1239 u8 dot3stats_excessive_collisions_low[0x20];
1240
1241 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1242
1243 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1244
1245 u8 dot3stats_carrier_sense_errors_high[0x20];
1246
1247 u8 dot3stats_carrier_sense_errors_low[0x20];
1248
1249 u8 dot3stats_frame_too_longs_high[0x20];
1250
1251 u8 dot3stats_frame_too_longs_low[0x20];
1252
1253 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1254
1255 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1256
1257 u8 dot3stats_symbol_errors_high[0x20];
1258
1259 u8 dot3stats_symbol_errors_low[0x20];
1260
1261 u8 dot3control_in_unknown_opcodes_high[0x20];
1262
1263 u8 dot3control_in_unknown_opcodes_low[0x20];
1264
1265 u8 dot3in_pause_frames_high[0x20];
1266
1267 u8 dot3in_pause_frames_low[0x20];
1268
1269 u8 dot3out_pause_frames_high[0x20];
1270
1271 u8 dot3out_pause_frames_low[0x20];
1272
1273 u8 reserved_0[0x3c0];
1274};
1275
1276struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1277 u8 ether_stats_drop_events_high[0x20];
1278
1279 u8 ether_stats_drop_events_low[0x20];
1280
1281 u8 ether_stats_octets_high[0x20];
1282
1283 u8 ether_stats_octets_low[0x20];
1284
1285 u8 ether_stats_pkts_high[0x20];
1286
1287 u8 ether_stats_pkts_low[0x20];
1288
1289 u8 ether_stats_broadcast_pkts_high[0x20];
1290
1291 u8 ether_stats_broadcast_pkts_low[0x20];
1292
1293 u8 ether_stats_multicast_pkts_high[0x20];
1294
1295 u8 ether_stats_multicast_pkts_low[0x20];
1296
1297 u8 ether_stats_crc_align_errors_high[0x20];
1298
1299 u8 ether_stats_crc_align_errors_low[0x20];
1300
1301 u8 ether_stats_undersize_pkts_high[0x20];
1302
1303 u8 ether_stats_undersize_pkts_low[0x20];
1304
1305 u8 ether_stats_oversize_pkts_high[0x20];
1306
1307 u8 ether_stats_oversize_pkts_low[0x20];
1308
1309 u8 ether_stats_fragments_high[0x20];
1310
1311 u8 ether_stats_fragments_low[0x20];
1312
1313 u8 ether_stats_jabbers_high[0x20];
1314
1315 u8 ether_stats_jabbers_low[0x20];
1316
1317 u8 ether_stats_collisions_high[0x20];
1318
1319 u8 ether_stats_collisions_low[0x20];
1320
1321 u8 ether_stats_pkts64octets_high[0x20];
1322
1323 u8 ether_stats_pkts64octets_low[0x20];
1324
1325 u8 ether_stats_pkts65to127octets_high[0x20];
1326
1327 u8 ether_stats_pkts65to127octets_low[0x20];
1328
1329 u8 ether_stats_pkts128to255octets_high[0x20];
1330
1331 u8 ether_stats_pkts128to255octets_low[0x20];
1332
1333 u8 ether_stats_pkts256to511octets_high[0x20];
1334
1335 u8 ether_stats_pkts256to511octets_low[0x20];
1336
1337 u8 ether_stats_pkts512to1023octets_high[0x20];
1338
1339 u8 ether_stats_pkts512to1023octets_low[0x20];
1340
1341 u8 ether_stats_pkts1024to1518octets_high[0x20];
1342
1343 u8 ether_stats_pkts1024to1518octets_low[0x20];
1344
1345 u8 ether_stats_pkts1519to2047octets_high[0x20];
1346
1347 u8 ether_stats_pkts1519to2047octets_low[0x20];
1348
1349 u8 ether_stats_pkts2048to4095octets_high[0x20];
1350
1351 u8 ether_stats_pkts2048to4095octets_low[0x20];
1352
1353 u8 ether_stats_pkts4096to8191octets_high[0x20];
1354
1355 u8 ether_stats_pkts4096to8191octets_low[0x20];
1356
1357 u8 ether_stats_pkts8192to10239octets_high[0x20];
1358
1359 u8 ether_stats_pkts8192to10239octets_low[0x20];
1360
1361 u8 reserved_0[0x280];
1362};
1363
1364struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1365 u8 if_in_octets_high[0x20];
1366
1367 u8 if_in_octets_low[0x20];
1368
1369 u8 if_in_ucast_pkts_high[0x20];
1370
1371 u8 if_in_ucast_pkts_low[0x20];
1372
1373 u8 if_in_discards_high[0x20];
1374
1375 u8 if_in_discards_low[0x20];
1376
1377 u8 if_in_errors_high[0x20];
1378
1379 u8 if_in_errors_low[0x20];
1380
1381 u8 if_in_unknown_protos_high[0x20];
1382
1383 u8 if_in_unknown_protos_low[0x20];
1384
1385 u8 if_out_octets_high[0x20];
1386
1387 u8 if_out_octets_low[0x20];
1388
1389 u8 if_out_ucast_pkts_high[0x20];
1390
1391 u8 if_out_ucast_pkts_low[0x20];
1392
1393 u8 if_out_discards_high[0x20];
1394
1395 u8 if_out_discards_low[0x20];
1396
1397 u8 if_out_errors_high[0x20];
1398
1399 u8 if_out_errors_low[0x20];
1400
1401 u8 if_in_multicast_pkts_high[0x20];
1402
1403 u8 if_in_multicast_pkts_low[0x20];
1404
1405 u8 if_in_broadcast_pkts_high[0x20];
1406
1407 u8 if_in_broadcast_pkts_low[0x20];
1408
1409 u8 if_out_multicast_pkts_high[0x20];
1410
1411 u8 if_out_multicast_pkts_low[0x20];
1412
1413 u8 if_out_broadcast_pkts_high[0x20];
1414
1415 u8 if_out_broadcast_pkts_low[0x20];
1416
1417 u8 reserved_0[0x480];
1418};
1419
1420struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1421 u8 a_frames_transmitted_ok_high[0x20];
1422
1423 u8 a_frames_transmitted_ok_low[0x20];
1424
1425 u8 a_frames_received_ok_high[0x20];
1426
1427 u8 a_frames_received_ok_low[0x20];
1428
1429 u8 a_frame_check_sequence_errors_high[0x20];
1430
1431 u8 a_frame_check_sequence_errors_low[0x20];
1432
1433 u8 a_alignment_errors_high[0x20];
1434
1435 u8 a_alignment_errors_low[0x20];
1436
1437 u8 a_octets_transmitted_ok_high[0x20];
1438
1439 u8 a_octets_transmitted_ok_low[0x20];
1440
1441 u8 a_octets_received_ok_high[0x20];
1442
1443 u8 a_octets_received_ok_low[0x20];
1444
1445 u8 a_multicast_frames_xmitted_ok_high[0x20];
1446
1447 u8 a_multicast_frames_xmitted_ok_low[0x20];
1448
1449 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1450
1451 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1452
1453 u8 a_multicast_frames_received_ok_high[0x20];
1454
1455 u8 a_multicast_frames_received_ok_low[0x20];
1456
1457 u8 a_broadcast_frames_received_ok_high[0x20];
1458
1459 u8 a_broadcast_frames_received_ok_low[0x20];
1460
1461 u8 a_in_range_length_errors_high[0x20];
1462
1463 u8 a_in_range_length_errors_low[0x20];
1464
1465 u8 a_out_of_range_length_field_high[0x20];
1466
1467 u8 a_out_of_range_length_field_low[0x20];
1468
1469 u8 a_frame_too_long_errors_high[0x20];
1470
1471 u8 a_frame_too_long_errors_low[0x20];
1472
1473 u8 a_symbol_error_during_carrier_high[0x20];
1474
1475 u8 a_symbol_error_during_carrier_low[0x20];
1476
1477 u8 a_mac_control_frames_transmitted_high[0x20];
1478
1479 u8 a_mac_control_frames_transmitted_low[0x20];
1480
1481 u8 a_mac_control_frames_received_high[0x20];
1482
1483 u8 a_mac_control_frames_received_low[0x20];
1484
1485 u8 a_unsupported_opcodes_received_high[0x20];
1486
1487 u8 a_unsupported_opcodes_received_low[0x20];
1488
1489 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1490
1491 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1492
1493 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1494
1495 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1496
1497 u8 reserved_0[0x300];
1498};
1499
1500struct mlx5_ifc_cmd_inter_comp_event_bits {
1501 u8 command_completion_vector[0x20];
1502
1503 u8 reserved_0[0xc0];
1504};
1505
1506struct mlx5_ifc_stall_vl_event_bits {
1507 u8 reserved_0[0x18];
1508 u8 port_num[0x1];
1509 u8 reserved_1[0x3];
1510 u8 vl[0x4];
1511
1512 u8 reserved_2[0xa0];
1513};
1514
1515struct mlx5_ifc_db_bf_congestion_event_bits {
1516 u8 event_subtype[0x8];
1517 u8 reserved_0[0x8];
1518 u8 congestion_level[0x8];
1519 u8 reserved_1[0x8];
1520
1521 u8 reserved_2[0xa0];
1522};
1523
1524struct mlx5_ifc_gpio_event_bits {
1525 u8 reserved_0[0x60];
1526
1527 u8 gpio_event_hi[0x20];
1528
1529 u8 gpio_event_lo[0x20];
1530
1531 u8 reserved_1[0x40];
1532};
1533
1534struct mlx5_ifc_port_state_change_event_bits {
1535 u8 reserved_0[0x40];
1536
1537 u8 port_num[0x4];
1538 u8 reserved_1[0x1c];
1539
1540 u8 reserved_2[0x80];
1541};
1542
1543struct mlx5_ifc_dropped_packet_logged_bits {
1544 u8 reserved_0[0xe0];
1545};
1546
1547enum {
1548 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1549 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1550};
1551
1552struct mlx5_ifc_cq_error_bits {
1553 u8 reserved_0[0x8];
1554 u8 cqn[0x18];
1555
1556 u8 reserved_1[0x20];
1557
1558 u8 reserved_2[0x18];
1559 u8 syndrome[0x8];
1560
1561 u8 reserved_3[0x80];
1562};
1563
1564struct mlx5_ifc_rdma_page_fault_event_bits {
1565 u8 bytes_committed[0x20];
1566
1567 u8 r_key[0x20];
1568
1569 u8 reserved_0[0x10];
1570 u8 packet_len[0x10];
1571
1572 u8 rdma_op_len[0x20];
1573
1574 u8 rdma_va[0x40];
1575
1576 u8 reserved_1[0x5];
1577 u8 rdma[0x1];
1578 u8 write[0x1];
1579 u8 requestor[0x1];
1580 u8 qp_number[0x18];
1581};
1582
1583struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1584 u8 bytes_committed[0x20];
1585
1586 u8 reserved_0[0x10];
1587 u8 wqe_index[0x10];
1588
1589 u8 reserved_1[0x10];
1590 u8 len[0x10];
1591
1592 u8 reserved_2[0x60];
1593
1594 u8 reserved_3[0x5];
1595 u8 rdma[0x1];
1596 u8 write_read[0x1];
1597 u8 requestor[0x1];
1598 u8 qpn[0x18];
1599};
1600
1601struct mlx5_ifc_qp_events_bits {
1602 u8 reserved_0[0xa0];
1603
1604 u8 type[0x8];
1605 u8 reserved_1[0x18];
1606
1607 u8 reserved_2[0x8];
1608 u8 qpn_rqn_sqn[0x18];
1609};
1610
1611struct mlx5_ifc_dct_events_bits {
1612 u8 reserved_0[0xc0];
1613
1614 u8 reserved_1[0x8];
1615 u8 dct_number[0x18];
1616};
1617
1618struct mlx5_ifc_comp_event_bits {
1619 u8 reserved_0[0xc0];
1620
1621 u8 reserved_1[0x8];
1622 u8 cq_number[0x18];
1623};
1624
1625enum {
1626 MLX5_QPC_STATE_RST = 0x0,
1627 MLX5_QPC_STATE_INIT = 0x1,
1628 MLX5_QPC_STATE_RTR = 0x2,
1629 MLX5_QPC_STATE_RTS = 0x3,
1630 MLX5_QPC_STATE_SQER = 0x4,
1631 MLX5_QPC_STATE_ERR = 0x6,
1632 MLX5_QPC_STATE_SQD = 0x7,
1633 MLX5_QPC_STATE_SUSPENDED = 0x9,
1634};
1635
1636enum {
1637 MLX5_QPC_ST_RC = 0x0,
1638 MLX5_QPC_ST_UC = 0x1,
1639 MLX5_QPC_ST_UD = 0x2,
1640 MLX5_QPC_ST_XRC = 0x3,
1641 MLX5_QPC_ST_DCI = 0x5,
1642 MLX5_QPC_ST_QP0 = 0x7,
1643 MLX5_QPC_ST_QP1 = 0x8,
1644 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1645 MLX5_QPC_ST_REG_UMR = 0xc,
1646};
1647
1648enum {
1649 MLX5_QPC_PM_STATE_ARMED = 0x0,
1650 MLX5_QPC_PM_STATE_REARM = 0x1,
1651 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1652 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1653};
1654
1655enum {
1656 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1657 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1658};
1659
1660enum {
1661 MLX5_QPC_MTU_256_BYTES = 0x1,
1662 MLX5_QPC_MTU_512_BYTES = 0x2,
1663 MLX5_QPC_MTU_1K_BYTES = 0x3,
1664 MLX5_QPC_MTU_2K_BYTES = 0x4,
1665 MLX5_QPC_MTU_4K_BYTES = 0x5,
1666 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1667};
1668
1669enum {
1670 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1671 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1672 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1673 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1674 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1675 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1676 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1677 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1678};
1679
1680enum {
1681 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1682 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1683 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1684};
1685
1686enum {
1687 MLX5_QPC_CS_RES_DISABLE = 0x0,
1688 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1689 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1690};
1691
1692struct mlx5_ifc_qpc_bits {
1693 u8 state[0x4];
1694 u8 reserved_0[0x4];
1695 u8 st[0x8];
1696 u8 reserved_1[0x3];
1697 u8 pm_state[0x2];
1698 u8 reserved_2[0x7];
1699 u8 end_padding_mode[0x2];
1700 u8 reserved_3[0x2];
1701
1702 u8 wq_signature[0x1];
1703 u8 block_lb_mc[0x1];
1704 u8 atomic_like_write_en[0x1];
1705 u8 latency_sensitive[0x1];
1706 u8 reserved_4[0x1];
1707 u8 drain_sigerr[0x1];
1708 u8 reserved_5[0x2];
1709 u8 pd[0x18];
1710
1711 u8 mtu[0x3];
1712 u8 log_msg_max[0x5];
1713 u8 reserved_6[0x1];
1714 u8 log_rq_size[0x4];
1715 u8 log_rq_stride[0x3];
1716 u8 no_sq[0x1];
1717 u8 log_sq_size[0x4];
1718 u8 reserved_7[0x6];
1719 u8 rlky[0x1];
1720 u8 reserved_8[0x4];
1721
1722 u8 counter_set_id[0x8];
1723 u8 uar_page[0x18];
1724
1725 u8 reserved_9[0x8];
1726 u8 user_index[0x18];
1727
1728 u8 reserved_10[0x3];
1729 u8 log_page_size[0x5];
1730 u8 remote_qpn[0x18];
1731
1732 struct mlx5_ifc_ads_bits primary_address_path;
1733
1734 struct mlx5_ifc_ads_bits secondary_address_path;
1735
1736 u8 log_ack_req_freq[0x4];
1737 u8 reserved_11[0x4];
1738 u8 log_sra_max[0x3];
1739 u8 reserved_12[0x2];
1740 u8 retry_count[0x3];
1741 u8 rnr_retry[0x3];
1742 u8 reserved_13[0x1];
1743 u8 fre[0x1];
1744 u8 cur_rnr_retry[0x3];
1745 u8 cur_retry_count[0x3];
1746 u8 reserved_14[0x5];
1747
1748 u8 reserved_15[0x20];
1749
1750 u8 reserved_16[0x8];
1751 u8 next_send_psn[0x18];
1752
1753 u8 reserved_17[0x8];
1754 u8 cqn_snd[0x18];
1755
1756 u8 reserved_18[0x40];
1757
1758 u8 reserved_19[0x8];
1759 u8 last_acked_psn[0x18];
1760
1761 u8 reserved_20[0x8];
1762 u8 ssn[0x18];
1763
1764 u8 reserved_21[0x8];
1765 u8 log_rra_max[0x3];
1766 u8 reserved_22[0x1];
1767 u8 atomic_mode[0x4];
1768 u8 rre[0x1];
1769 u8 rwe[0x1];
1770 u8 rae[0x1];
1771 u8 reserved_23[0x1];
1772 u8 page_offset[0x6];
1773 u8 reserved_24[0x3];
1774 u8 cd_slave_receive[0x1];
1775 u8 cd_slave_send[0x1];
1776 u8 cd_master[0x1];
1777
1778 u8 reserved_25[0x3];
1779 u8 min_rnr_nak[0x5];
1780 u8 next_rcv_psn[0x18];
1781
1782 u8 reserved_26[0x8];
1783 u8 xrcd[0x18];
1784
1785 u8 reserved_27[0x8];
1786 u8 cqn_rcv[0x18];
1787
1788 u8 dbr_addr[0x40];
1789
1790 u8 q_key[0x20];
1791
1792 u8 reserved_28[0x5];
1793 u8 rq_type[0x3];
1794 u8 srqn_rmpn[0x18];
1795
1796 u8 reserved_29[0x8];
1797 u8 rmsn[0x18];
1798
1799 u8 hw_sq_wqebb_counter[0x10];
1800 u8 sw_sq_wqebb_counter[0x10];
1801
1802 u8 hw_rq_counter[0x20];
1803
1804 u8 sw_rq_counter[0x20];
1805
1806 u8 reserved_30[0x20];
1807
1808 u8 reserved_31[0xf];
1809 u8 cgs[0x1];
1810 u8 cs_req[0x8];
1811 u8 cs_res[0x8];
1812
1813 u8 dc_access_key[0x40];
1814
1815 u8 reserved_32[0xc0];
1816};
1817
1818struct mlx5_ifc_roce_addr_layout_bits {
1819 u8 source_l3_address[16][0x8];
1820
1821 u8 reserved_0[0x3];
1822 u8 vlan_valid[0x1];
1823 u8 vlan_id[0xc];
1824 u8 source_mac_47_32[0x10];
1825
1826 u8 source_mac_31_0[0x20];
1827
1828 u8 reserved_1[0x14];
1829 u8 roce_l3_type[0x4];
1830 u8 roce_version[0x8];
1831
1832 u8 reserved_2[0x20];
1833};
1834
1835union mlx5_ifc_hca_cap_union_bits {
1836 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1837 struct mlx5_ifc_odp_cap_bits odp_cap;
1838 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1839 struct mlx5_ifc_roce_cap_bits roce_cap;
1840 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1841 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1842 u8 reserved_0[0x8000];
1843};
1844
1845enum {
1846 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1847 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1848 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1849};
1850
1851struct mlx5_ifc_flow_context_bits {
1852 u8 reserved_0[0x20];
1853
1854 u8 group_id[0x20];
1855
1856 u8 reserved_1[0x8];
1857 u8 flow_tag[0x18];
1858
1859 u8 reserved_2[0x10];
1860 u8 action[0x10];
1861
1862 u8 reserved_3[0x8];
1863 u8 destination_list_size[0x18];
1864
1865 u8 reserved_4[0x160];
1866
1867 struct mlx5_ifc_fte_match_param_bits match_value;
1868
1869 u8 reserved_5[0x600];
1870
1871 struct mlx5_ifc_dest_format_struct_bits destination[0];
1872};
1873
1874enum {
1875 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1876 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1877};
1878
1879struct mlx5_ifc_xrc_srqc_bits {
1880 u8 state[0x4];
1881 u8 log_xrc_srq_size[0x4];
1882 u8 reserved_0[0x18];
1883
1884 u8 wq_signature[0x1];
1885 u8 cont_srq[0x1];
1886 u8 reserved_1[0x1];
1887 u8 rlky[0x1];
1888 u8 basic_cyclic_rcv_wqe[0x1];
1889 u8 log_rq_stride[0x3];
1890 u8 xrcd[0x18];
1891
1892 u8 page_offset[0x6];
1893 u8 reserved_2[0x2];
1894 u8 cqn[0x18];
1895
1896 u8 reserved_3[0x20];
1897
1898 u8 user_index_equal_xrc_srqn[0x1];
1899 u8 reserved_4[0x1];
1900 u8 log_page_size[0x6];
1901 u8 user_index[0x18];
1902
1903 u8 reserved_5[0x20];
1904
1905 u8 reserved_6[0x8];
1906 u8 pd[0x18];
1907
1908 u8 lwm[0x10];
1909 u8 wqe_cnt[0x10];
1910
1911 u8 reserved_7[0x40];
1912
1913 u8 db_record_addr_h[0x20];
1914
1915 u8 db_record_addr_l[0x1e];
1916 u8 reserved_8[0x2];
1917
1918 u8 reserved_9[0x80];
1919};
1920
1921struct mlx5_ifc_traffic_counter_bits {
1922 u8 packets[0x40];
1923
1924 u8 octets[0x40];
1925};
1926
1927struct mlx5_ifc_tisc_bits {
1928 u8 reserved_0[0xc];
1929 u8 prio[0x4];
1930 u8 reserved_1[0x10];
1931
1932 u8 reserved_2[0x100];
1933
1934 u8 reserved_3[0x8];
1935 u8 transport_domain[0x18];
1936
1937 u8 reserved_4[0x3c0];
1938};
1939
1940enum {
1941 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1942 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1943};
1944
1945enum {
1946 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1947 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1948};
1949
1950enum {
2be6967c
SM		 1951 MLX5_RX_HASH_FN_NONE = 0x0,
1952 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1953 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 1954};
1955
1956enum {
1957 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1958 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1959};
1960
1961struct mlx5_ifc_tirc_bits {
1962 u8 reserved_0[0x20];
1963
1964 u8 disp_type[0x4];
1965 u8 reserved_1[0x1c];
1966
1967 u8 reserved_2[0x40];
1968
1969 u8 reserved_3[0x4];
1970 u8 lro_timeout_period_usecs[0x10];
1971 u8 lro_enable_mask[0x4];
1972 u8 lro_max_ip_payload_size[0x8];
1973
1974 u8 reserved_4[0x40];
1975
1976 u8 reserved_5[0x8];
1977 u8 inline_rqn[0x18];
1978
1979 u8 rx_hash_symmetric[0x1];
1980 u8 reserved_6[0x1];
1981 u8 tunneled_offload_en[0x1];
1982 u8 reserved_7[0x5];
1983 u8 indirect_table[0x18];
1984
1985 u8 rx_hash_fn[0x4];
1986 u8 reserved_8[0x2];
1987 u8 self_lb_block[0x2];
1988 u8 transport_domain[0x18];
1989
1990 u8 rx_hash_toeplitz_key[10][0x20];
1991
1992 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1993
1994 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1995
1996 u8 reserved_9[0x4c0];
1997};
1998
1999enum {
2000 MLX5_SRQC_STATE_GOOD = 0x0,
2001 MLX5_SRQC_STATE_ERROR = 0x1,
2002};
2003
2004struct mlx5_ifc_srqc_bits {
2005 u8 state[0x4];
2006 u8 log_srq_size[0x4];
2007 u8 reserved_0[0x18];
2008
2009 u8 wq_signature[0x1];
2010 u8 cont_srq[0x1];
2011 u8 reserved_1[0x1];
2012 u8 rlky[0x1];
2013 u8 reserved_2[0x1];
2014 u8 log_rq_stride[0x3];
2015 u8 xrcd[0x18];
2016
2017 u8 page_offset[0x6];
2018 u8 reserved_3[0x2];
2019 u8 cqn[0x18];
2020
2021 u8 reserved_4[0x20];
2022
2023 u8 reserved_5[0x2];
2024 u8 log_page_size[0x6];
2025 u8 reserved_6[0x18];
2026
2027 u8 reserved_7[0x20];
2028
2029 u8 reserved_8[0x8];
2030 u8 pd[0x18];
2031
2032 u8 lwm[0x10];
2033 u8 wqe_cnt[0x10];
2034
2035 u8 reserved_9[0x40];
2036
01949d01 2037 u8 dbr_addr[0x40];
e281682b 2038
01949d01 2039 u8 reserved_10[0x80];
e281682b
SM		 2040};
2041
2042enum {
2043 MLX5_SQC_STATE_RST = 0x0,
2044 MLX5_SQC_STATE_RDY = 0x1,
2045 MLX5_SQC_STATE_ERR = 0x3,
2046};
2047
2048struct mlx5_ifc_sqc_bits {
2049 u8 rlky[0x1];
2050 u8 cd_master[0x1];
2051 u8 fre[0x1];
2052 u8 flush_in_error_en[0x1];
2053 u8 reserved_0[0x4];
2054 u8 state[0x4];
2055 u8 reserved_1[0x14];
2056
2057 u8 reserved_2[0x8];
2058 u8 user_index[0x18];
2059
2060 u8 reserved_3[0x8];
2061 u8 cqn[0x18];
2062
2063 u8 reserved_4[0xa0];
2064
2065 u8 tis_lst_sz[0x10];
2066 u8 reserved_5[0x10];
2067
2068 u8 reserved_6[0x40];
2069
2070 u8 reserved_7[0x8];
2071 u8 tis_num_0[0x18];
2072
2073 struct mlx5_ifc_wq_bits wq;
2074};
2075
2076struct mlx5_ifc_rqtc_bits {
2077 u8 reserved_0[0xa0];
2078
2079 u8 reserved_1[0x10];
2080 u8 rqt_max_size[0x10];
2081
2082 u8 reserved_2[0x10];
2083 u8 rqt_actual_size[0x10];
2084
2085 u8 reserved_3[0x6a0];
2086
2087 struct mlx5_ifc_rq_num_bits rq_num[0];
2088};
2089
2090enum {
2091 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2092 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2093};
2094
2095enum {
2096 MLX5_RQC_STATE_RST = 0x0,
2097 MLX5_RQC_STATE_RDY = 0x1,
2098 MLX5_RQC_STATE_ERR = 0x3,
2099};
2100
2101struct mlx5_ifc_rqc_bits {
2102 u8 rlky[0x1];
2103 u8 reserved_0[0x2];
2104 u8 vsd[0x1];
2105 u8 mem_rq_type[0x4];
2106 u8 state[0x4];
2107 u8 reserved_1[0x1];
2108 u8 flush_in_error_en[0x1];
2109 u8 reserved_2[0x12];
2110
2111 u8 reserved_3[0x8];
2112 u8 user_index[0x18];
2113
2114 u8 reserved_4[0x8];
2115 u8 cqn[0x18];
2116
2117 u8 counter_set_id[0x8];
2118 u8 reserved_5[0x18];
2119
2120 u8 reserved_6[0x8];
2121 u8 rmpn[0x18];
2122
2123 u8 reserved_7[0xe0];
2124
2125 struct mlx5_ifc_wq_bits wq;
2126};
2127
2128enum {
2129 MLX5_RMPC_STATE_RDY = 0x1,
2130 MLX5_RMPC_STATE_ERR = 0x3,
2131};
2132
2133struct mlx5_ifc_rmpc_bits {
2134 u8 reserved_0[0x8];
2135 u8 state[0x4];
2136 u8 reserved_1[0x14];
2137
2138 u8 basic_cyclic_rcv_wqe[0x1];
2139 u8 reserved_2[0x1f];
2140
2141 u8 reserved_3[0x140];
2142
2143 struct mlx5_ifc_wq_bits wq;
2144};
2145
e281682b
SM		 2146struct mlx5_ifc_nic_vport_context_bits {
2147 u8 reserved_0[0x1f];
2148 u8 roce_en[0x1];
2149
d82b7318
SM		 2150 u8 arm_change_event[0x1];
2151 u8 reserved_1[0x1a];
2152 u8 event_on_mtu[0x1];
2153 u8 event_on_promisc_change[0x1];
2154 u8 event_on_vlan_change[0x1];
2155 u8 event_on_mc_address_change[0x1];
2156 u8 event_on_uc_address_change[0x1];
e281682b 2157
d82b7318
SM		 2158 u8 reserved_2[0xf0];
2159
2160 u8 mtu[0x10];
2161
2162 u8 reserved_3[0x640];
2163
2164 u8 promisc_uc[0x1];
2165 u8 promisc_mc[0x1];
2166 u8 promisc_all[0x1];
2167 u8 reserved_4[0x2];
e281682b 2168 u8 allowed_list_type[0x3];
d82b7318 2169 u8 reserved_5[0xc];
e281682b
SM		 2170 u8 allowed_list_size[0xc];
2171
2172 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2173
d82b7318 2174 u8 reserved_6[0x20];
e281682b
SM		 2175
2176 u8 current_uc_mac_address[0][0x40];
2177};
2178
2179enum {
2180 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2181 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2182 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2183};
2184
2185struct mlx5_ifc_mkc_bits {
2186 u8 reserved_0[0x1];
2187 u8 free[0x1];
2188 u8 reserved_1[0xd];
2189 u8 small_fence_on_rdma_read_response[0x1];
2190 u8 umr_en[0x1];
2191 u8 a[0x1];
2192 u8 rw[0x1];
2193 u8 rr[0x1];
2194 u8 lw[0x1];
2195 u8 lr[0x1];
2196 u8 access_mode[0x2];
2197 u8 reserved_2[0x8];
2198
2199 u8 qpn[0x18];
2200 u8 mkey_7_0[0x8];
2201
2202 u8 reserved_3[0x20];
2203
2204 u8 length64[0x1];
2205 u8 bsf_en[0x1];
2206 u8 sync_umr[0x1];
2207 u8 reserved_4[0x2];
2208 u8 expected_sigerr_count[0x1];
2209 u8 reserved_5[0x1];
2210 u8 en_rinval[0x1];
2211 u8 pd[0x18];
2212
2213 u8 start_addr[0x40];
2214
2215 u8 len[0x40];
2216
2217 u8 bsf_octword_size[0x20];
2218
2219 u8 reserved_6[0x80];
2220
2221 u8 translations_octword_size[0x20];
2222
2223 u8 reserved_7[0x1b];
2224 u8 log_page_size[0x5];
2225
2226 u8 reserved_8[0x20];
2227};
2228
2229struct mlx5_ifc_pkey_bits {
2230 u8 reserved_0[0x10];
2231 u8 pkey[0x10];
2232};
2233
2234struct mlx5_ifc_array128_auto_bits {
2235 u8 array128_auto[16][0x8];
2236};
2237
2238struct mlx5_ifc_hca_vport_context_bits {
2239 u8 field_select[0x20];
2240
2241 u8 reserved_0[0xe0];
2242
2243 u8 sm_virt_aware[0x1];
2244 u8 has_smi[0x1];
2245 u8 has_raw[0x1];
2246 u8 grh_required[0x1];
707c4602
MD		 2247 u8 reserved_1[0xc];
2248 u8 port_physical_state[0x4];
2249 u8 vport_state_policy[0x4];
2250 u8 port_state[0x4];
e281682b
SM		 2251 u8 vport_state[0x4];
2252
707c4602
MD		 2253 u8 reserved_2[0x20];
2254
2255 u8 system_image_guid[0x40];
e281682b
SM		 2256
2257 u8 port_guid[0x40];
2258
2259 u8 node_guid[0x40];
2260
2261 u8 cap_mask1[0x20];
2262
2263 u8 cap_mask1_field_select[0x20];
2264
2265 u8 cap_mask2[0x20];
2266
2267 u8 cap_mask2_field_select[0x20];
2268
2269 u8 reserved_3[0x80];
2270
2271 u8 lid[0x10];
2272 u8 reserved_4[0x4];
2273 u8 init_type_reply[0x4];
2274 u8 lmc[0x3];
2275 u8 subnet_timeout[0x5];
2276
2277 u8 sm_lid[0x10];
2278 u8 sm_sl[0x4];
2279 u8 reserved_5[0xc];
2280
2281 u8 qkey_violation_counter[0x10];
2282 u8 pkey_violation_counter[0x10];
2283
2284 u8 reserved_6[0xca0];
2285};
2286
2287enum {
2288 MLX5_EQC_STATUS_OK = 0x0,
2289 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2290};
2291
2292enum {
2293 MLX5_EQC_ST_ARMED = 0x9,
2294 MLX5_EQC_ST_FIRED = 0xa,
2295};
2296
2297struct mlx5_ifc_eqc_bits {
2298 u8 status[0x4];
2299 u8 reserved_0[0x9];
2300 u8 ec[0x1];
2301 u8 oi[0x1];
2302 u8 reserved_1[0x5];
2303 u8 st[0x4];
2304 u8 reserved_2[0x8];
2305
2306 u8 reserved_3[0x20];
2307
2308 u8 reserved_4[0x14];
2309 u8 page_offset[0x6];
2310 u8 reserved_5[0x6];
2311
2312 u8 reserved_6[0x3];
2313 u8 log_eq_size[0x5];
2314 u8 uar_page[0x18];
2315
2316 u8 reserved_7[0x20];
2317
2318 u8 reserved_8[0x18];
2319 u8 intr[0x8];
2320
2321 u8 reserved_9[0x3];
2322 u8 log_page_size[0x5];
2323 u8 reserved_10[0x18];
2324
2325 u8 reserved_11[0x60];
2326
2327 u8 reserved_12[0x8];
2328 u8 consumer_counter[0x18];
2329
2330 u8 reserved_13[0x8];
2331 u8 producer_counter[0x18];
2332
2333 u8 reserved_14[0x80];
2334};
2335
2336enum {
2337 MLX5_DCTC_STATE_ACTIVE = 0x0,
2338 MLX5_DCTC_STATE_DRAINING = 0x1,
2339 MLX5_DCTC_STATE_DRAINED = 0x2,
2340};
2341
2342enum {
2343 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2344 MLX5_DCTC_CS_RES_NA = 0x1,
2345 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2346};
2347
2348enum {
2349 MLX5_DCTC_MTU_256_BYTES = 0x1,
2350 MLX5_DCTC_MTU_512_BYTES = 0x2,
2351 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2352 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2353 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2354};
2355
2356struct mlx5_ifc_dctc_bits {
2357 u8 reserved_0[0x4];
2358 u8 state[0x4];
2359 u8 reserved_1[0x18];
2360
2361 u8 reserved_2[0x8];
2362 u8 user_index[0x18];
2363
2364 u8 reserved_3[0x8];
2365 u8 cqn[0x18];
2366
2367 u8 counter_set_id[0x8];
2368 u8 atomic_mode[0x4];
2369 u8 rre[0x1];
2370 u8 rwe[0x1];
2371 u8 rae[0x1];
2372 u8 atomic_like_write_en[0x1];
2373 u8 latency_sensitive[0x1];
2374 u8 rlky[0x1];
2375 u8 free_ar[0x1];
2376 u8 reserved_4[0xd];
2377
2378 u8 reserved_5[0x8];
2379 u8 cs_res[0x8];
2380 u8 reserved_6[0x3];
2381 u8 min_rnr_nak[0x5];
2382 u8 reserved_7[0x8];
2383
2384 u8 reserved_8[0x8];
2385 u8 srqn[0x18];
2386
2387 u8 reserved_9[0x8];
2388 u8 pd[0x18];
2389
2390 u8 tclass[0x8];
2391 u8 reserved_10[0x4];
2392 u8 flow_label[0x14];
2393
2394 u8 dc_access_key[0x40];
2395
2396 u8 reserved_11[0x5];
2397 u8 mtu[0x3];
2398 u8 port[0x8];
2399 u8 pkey_index[0x10];
2400
2401 u8 reserved_12[0x8];
2402 u8 my_addr_index[0x8];
2403 u8 reserved_13[0x8];
2404 u8 hop_limit[0x8];
2405
2406 u8 dc_access_key_violation_count[0x20];
2407
2408 u8 reserved_14[0x14];
2409 u8 dei_cfi[0x1];
2410 u8 eth_prio[0x3];
2411 u8 ecn[0x2];
2412 u8 dscp[0x6];
2413
2414 u8 reserved_15[0x40];
2415};
2416
2417enum {
2418 MLX5_CQC_STATUS_OK = 0x0,
2419 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2420 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2421};
2422
2423enum {
2424 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2425 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2426};
2427
2428enum {
2429 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2430 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2431 MLX5_CQC_ST_FIRED = 0xa,
2432};
2433
2434struct mlx5_ifc_cqc_bits {
2435 u8 status[0x4];
2436 u8 reserved_0[0x4];
2437 u8 cqe_sz[0x3];
2438 u8 cc[0x1];
2439 u8 reserved_1[0x1];
2440 u8 scqe_break_moderation_en[0x1];
2441 u8 oi[0x1];
2442 u8 reserved_2[0x2];
2443 u8 cqe_zip_en[0x1];
2444 u8 mini_cqe_res_format[0x2];
2445 u8 st[0x4];
2446 u8 reserved_3[0x8];
2447
2448 u8 reserved_4[0x20];
2449
2450 u8 reserved_5[0x14];
2451 u8 page_offset[0x6];
2452 u8 reserved_6[0x6];
2453
2454 u8 reserved_7[0x3];
2455 u8 log_cq_size[0x5];
2456 u8 uar_page[0x18];
2457
2458 u8 reserved_8[0x4];
2459 u8 cq_period[0xc];
2460 u8 cq_max_count[0x10];
2461
2462 u8 reserved_9[0x18];
2463 u8 c_eqn[0x8];
2464
2465 u8 reserved_10[0x3];
2466 u8 log_page_size[0x5];
2467 u8 reserved_11[0x18];
2468
2469 u8 reserved_12[0x20];
2470
2471 u8 reserved_13[0x8];
2472 u8 last_notified_index[0x18];
2473
2474 u8 reserved_14[0x8];
2475 u8 last_solicit_index[0x18];
2476
2477 u8 reserved_15[0x8];
2478 u8 consumer_counter[0x18];
2479
2480 u8 reserved_16[0x8];
2481 u8 producer_counter[0x18];
2482
2483 u8 reserved_17[0x40];
2484
2485 u8 dbr_addr[0x40];
2486};
2487
2488union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2489 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2490 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2491 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2492 u8 reserved_0[0x800];
2493};
2494
2495struct mlx5_ifc_query_adapter_param_block_bits {
211e6c80 2496 u8 reserved_0[0xc0];
e281682b 2497
211e6c80
MD		 2498 u8 reserved_1[0x8];
2499 u8 ieee_vendor_id[0x18];
2500
2501 u8 reserved_2[0x10];
e281682b
SM		 2502 u8 vsd_vendor_id[0x10];
2503
2504 u8 vsd[208][0x8];
2505
2506 u8 vsd_contd_psid[16][0x8];
2507};
2508
2509union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2510 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2511 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2512 u8 reserved_0[0x20];
2513};
2514
2515union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2516 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2517 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2518 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2519 u8 reserved_0[0x20];
2520};
2521
2522union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2523 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2524 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2525 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2526 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2527 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2528 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2529 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2530 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2531 u8 reserved_0[0x7c0];
2532};
2533
2534union mlx5_ifc_event_auto_bits {
2535 struct mlx5_ifc_comp_event_bits comp_event;
2536 struct mlx5_ifc_dct_events_bits dct_events;
2537 struct mlx5_ifc_qp_events_bits qp_events;
2538 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2539 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2540 struct mlx5_ifc_cq_error_bits cq_error;
2541 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2542 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2543 struct mlx5_ifc_gpio_event_bits gpio_event;
2544 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2545 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2546 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2547 u8 reserved_0[0xe0];
2548};
2549
2550struct mlx5_ifc_health_buffer_bits {
2551 u8 reserved_0[0x100];
2552
2553 u8 assert_existptr[0x20];
2554
2555 u8 assert_callra[0x20];
2556
2557 u8 reserved_1[0x40];
2558
2559 u8 fw_version[0x20];
2560
2561 u8 hw_id[0x20];
2562
2563 u8 reserved_2[0x20];
2564
2565 u8 irisc_index[0x8];
2566 u8 synd[0x8];
2567 u8 ext_synd[0x10];
2568};
2569
2570struct mlx5_ifc_register_loopback_control_bits {
2571 u8 no_lb[0x1];
2572 u8 reserved_0[0x7];
2573 u8 port[0x8];
2574 u8 reserved_1[0x10];
2575
2576 u8 reserved_2[0x60];
2577};
2578
2579struct mlx5_ifc_teardown_hca_out_bits {
2580 u8 status[0x8];
2581 u8 reserved_0[0x18];
2582
2583 u8 syndrome[0x20];
2584
2585 u8 reserved_1[0x40];
2586};
2587
2588enum {
2589 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2590 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2591};
2592
2593struct mlx5_ifc_teardown_hca_in_bits {
2594 u8 opcode[0x10];
2595 u8 reserved_0[0x10];
2596
2597 u8 reserved_1[0x10];
2598 u8 op_mod[0x10];
2599
2600 u8 reserved_2[0x10];
2601 u8 profile[0x10];
2602
2603 u8 reserved_3[0x20];
2604};
2605
2606struct mlx5_ifc_sqerr2rts_qp_out_bits {
2607 u8 status[0x8];
2608 u8 reserved_0[0x18];
2609
2610 u8 syndrome[0x20];
2611
2612 u8 reserved_1[0x40];
2613};
2614
2615struct mlx5_ifc_sqerr2rts_qp_in_bits {
2616 u8 opcode[0x10];
2617 u8 reserved_0[0x10];
2618
2619 u8 reserved_1[0x10];
2620 u8 op_mod[0x10];
2621
2622 u8 reserved_2[0x8];
2623 u8 qpn[0x18];
2624
2625 u8 reserved_3[0x20];
2626
2627 u8 opt_param_mask[0x20];
2628
2629 u8 reserved_4[0x20];
2630
2631 struct mlx5_ifc_qpc_bits qpc;
2632
2633 u8 reserved_5[0x80];
2634};
2635
2636struct mlx5_ifc_sqd2rts_qp_out_bits {
2637 u8 status[0x8];
2638 u8 reserved_0[0x18];
2639
2640 u8 syndrome[0x20];
2641
2642 u8 reserved_1[0x40];
2643};
2644
2645struct mlx5_ifc_sqd2rts_qp_in_bits {
2646 u8 opcode[0x10];
2647 u8 reserved_0[0x10];
2648
2649 u8 reserved_1[0x10];
2650 u8 op_mod[0x10];
2651
2652 u8 reserved_2[0x8];
2653 u8 qpn[0x18];
2654
2655 u8 reserved_3[0x20];
2656
2657 u8 opt_param_mask[0x20];
2658
2659 u8 reserved_4[0x20];
2660
2661 struct mlx5_ifc_qpc_bits qpc;
2662
2663 u8 reserved_5[0x80];
2664};
2665
2666struct mlx5_ifc_set_roce_address_out_bits {
2667 u8 status[0x8];
2668 u8 reserved_0[0x18];
2669
2670 u8 syndrome[0x20];
2671
2672 u8 reserved_1[0x40];
2673};
2674
2675struct mlx5_ifc_set_roce_address_in_bits {
2676 u8 opcode[0x10];
2677 u8 reserved_0[0x10];
2678
2679 u8 reserved_1[0x10];
2680 u8 op_mod[0x10];
2681
2682 u8 roce_address_index[0x10];
2683 u8 reserved_2[0x10];
2684
2685 u8 reserved_3[0x20];
2686
2687 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2688};
2689
2690struct mlx5_ifc_set_mad_demux_out_bits {
2691 u8 status[0x8];
2692 u8 reserved_0[0x18];
2693
2694 u8 syndrome[0x20];
2695
2696 u8 reserved_1[0x40];
2697};
2698
2699enum {
2700 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2701 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2702};
2703
2704struct mlx5_ifc_set_mad_demux_in_bits {
2705 u8 opcode[0x10];
2706 u8 reserved_0[0x10];
2707
2708 u8 reserved_1[0x10];
2709 u8 op_mod[0x10];
2710
2711 u8 reserved_2[0x20];
2712
2713 u8 reserved_3[0x6];
2714 u8 demux_mode[0x2];
2715 u8 reserved_4[0x18];
2716};
2717
2718struct mlx5_ifc_set_l2_table_entry_out_bits {
2719 u8 status[0x8];
2720 u8 reserved_0[0x18];
2721
2722 u8 syndrome[0x20];
2723
2724 u8 reserved_1[0x40];
2725};
2726
2727struct mlx5_ifc_set_l2_table_entry_in_bits {
2728 u8 opcode[0x10];
2729 u8 reserved_0[0x10];
2730
2731 u8 reserved_1[0x10];
2732 u8 op_mod[0x10];
2733
2734 u8 reserved_2[0x60];
2735
2736 u8 reserved_3[0x8];
2737 u8 table_index[0x18];
2738
2739 u8 reserved_4[0x20];
2740
2741 u8 reserved_5[0x13];
2742 u8 vlan_valid[0x1];
2743 u8 vlan[0xc];
2744
2745 struct mlx5_ifc_mac_address_layout_bits mac_address;
2746
2747 u8 reserved_6[0xc0];
2748};
2749
2750struct mlx5_ifc_set_issi_out_bits {
2751 u8 status[0x8];
2752 u8 reserved_0[0x18];
2753
2754 u8 syndrome[0x20];
2755
2756 u8 reserved_1[0x40];
2757};
2758
2759struct mlx5_ifc_set_issi_in_bits {
2760 u8 opcode[0x10];
2761 u8 reserved_0[0x10];
2762
2763 u8 reserved_1[0x10];
2764 u8 op_mod[0x10];
2765
2766 u8 reserved_2[0x10];
2767 u8 current_issi[0x10];
2768
2769 u8 reserved_3[0x20];
2770};
2771
2772struct mlx5_ifc_set_hca_cap_out_bits {
2773 u8 status[0x8];
2774 u8 reserved_0[0x18];
2775
2776 u8 syndrome[0x20];
2777
2778 u8 reserved_1[0x40];
2779};
2780
2781struct mlx5_ifc_set_hca_cap_in_bits {
2782 u8 opcode[0x10];
2783 u8 reserved_0[0x10];
2784
2785 u8 reserved_1[0x10];
2786 u8 op_mod[0x10];
2787
2788 u8 reserved_2[0x40];
2789
2790 union mlx5_ifc_hca_cap_union_bits capability;
2791};
2792
2793struct mlx5_ifc_set_fte_out_bits {
2794 u8 status[0x8];
2795 u8 reserved_0[0x18];
2796
2797 u8 syndrome[0x20];
2798
2799 u8 reserved_1[0x40];
2800};
2801
2802struct mlx5_ifc_set_fte_in_bits {
2803 u8 opcode[0x10];
2804 u8 reserved_0[0x10];
2805
2806 u8 reserved_1[0x10];
2807 u8 op_mod[0x10];
2808
2809 u8 reserved_2[0x40];
2810
2811 u8 table_type[0x8];
2812 u8 reserved_3[0x18];
2813
2814 u8 reserved_4[0x8];
2815 u8 table_id[0x18];
2816
2817 u8 reserved_5[0x40];
2818
2819 u8 flow_index[0x20];
2820
2821 u8 reserved_6[0xe0];
2822
2823 struct mlx5_ifc_flow_context_bits flow_context;
2824};
2825
2826struct mlx5_ifc_rts2rts_qp_out_bits {
2827 u8 status[0x8];
2828 u8 reserved_0[0x18];
2829
2830 u8 syndrome[0x20];
2831
2832 u8 reserved_1[0x40];
2833};
2834
2835struct mlx5_ifc_rts2rts_qp_in_bits {
2836 u8 opcode[0x10];
2837 u8 reserved_0[0x10];
2838
2839 u8 reserved_1[0x10];
2840 u8 op_mod[0x10];
2841
2842 u8 reserved_2[0x8];
2843 u8 qpn[0x18];
2844
2845 u8 reserved_3[0x20];
2846
2847 u8 opt_param_mask[0x20];
2848
2849 u8 reserved_4[0x20];
2850
2851 struct mlx5_ifc_qpc_bits qpc;
2852
2853 u8 reserved_5[0x80];
2854};
2855
2856struct mlx5_ifc_rtr2rts_qp_out_bits {
2857 u8 status[0x8];
2858 u8 reserved_0[0x18];
2859
2860 u8 syndrome[0x20];
2861
2862 u8 reserved_1[0x40];
2863};
2864
2865struct mlx5_ifc_rtr2rts_qp_in_bits {
2866 u8 opcode[0x10];
2867 u8 reserved_0[0x10];
2868
2869 u8 reserved_1[0x10];
2870 u8 op_mod[0x10];
2871
2872 u8 reserved_2[0x8];
2873 u8 qpn[0x18];
2874
2875 u8 reserved_3[0x20];
2876
2877 u8 opt_param_mask[0x20];
2878
2879 u8 reserved_4[0x20];
2880
2881 struct mlx5_ifc_qpc_bits qpc;
2882
2883 u8 reserved_5[0x80];
2884};
2885
2886struct mlx5_ifc_rst2init_qp_out_bits {
2887 u8 status[0x8];
2888 u8 reserved_0[0x18];
2889
2890 u8 syndrome[0x20];
2891
2892 u8 reserved_1[0x40];
2893};
2894
2895struct mlx5_ifc_rst2init_qp_in_bits {
2896 u8 opcode[0x10];
2897 u8 reserved_0[0x10];
2898
2899 u8 reserved_1[0x10];
2900 u8 op_mod[0x10];
2901
2902 u8 reserved_2[0x8];
2903 u8 qpn[0x18];
2904
2905 u8 reserved_3[0x20];
2906
2907 u8 opt_param_mask[0x20];
2908
2909 u8 reserved_4[0x20];
2910
2911 struct mlx5_ifc_qpc_bits qpc;
2912
2913 u8 reserved_5[0x80];
2914};
2915
2916struct mlx5_ifc_query_xrc_srq_out_bits {
2917 u8 status[0x8];
2918 u8 reserved_0[0x18];
2919
2920 u8 syndrome[0x20];
2921
2922 u8 reserved_1[0x40];
2923
2924 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2925
2926 u8 reserved_2[0x600];
2927
2928 u8 pas[0][0x40];
2929};
2930
2931struct mlx5_ifc_query_xrc_srq_in_bits {
2932 u8 opcode[0x10];
2933 u8 reserved_0[0x10];
2934
2935 u8 reserved_1[0x10];
2936 u8 op_mod[0x10];
2937
2938 u8 reserved_2[0x8];
2939 u8 xrc_srqn[0x18];
2940
2941 u8 reserved_3[0x20];
2942};
2943
2944enum {
2945 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2946 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2947};
2948
2949struct mlx5_ifc_query_vport_state_out_bits {
2950 u8 status[0x8];
2951 u8 reserved_0[0x18];
2952
2953 u8 syndrome[0x20];
2954
2955 u8 reserved_1[0x20];
2956
2957 u8 reserved_2[0x18];
2958 u8 admin_state[0x4];
2959 u8 state[0x4];
2960};
2961
2962enum {
2963 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 2964 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 2965};
2966
2967struct mlx5_ifc_query_vport_state_in_bits {
2968 u8 opcode[0x10];
2969 u8 reserved_0[0x10];
2970
2971 u8 reserved_1[0x10];
2972 u8 op_mod[0x10];
2973
2974 u8 other_vport[0x1];
2975 u8 reserved_2[0xf];
2976 u8 vport_number[0x10];
2977
2978 u8 reserved_3[0x20];
2979};
2980
2981struct mlx5_ifc_query_vport_counter_out_bits {
2982 u8 status[0x8];
2983 u8 reserved_0[0x18];
2984
2985 u8 syndrome[0x20];
2986
2987 u8 reserved_1[0x40];
2988
2989 struct mlx5_ifc_traffic_counter_bits received_errors;
2990
2991 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2992
2993 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2994
2995 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2996
2997 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2998
2999 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3000
3001 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3002
3003 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3004
3005 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3006
3007 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3008
3009 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3010
3011 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3012
3013 u8 reserved_2[0xa00];
3014};
3015
3016enum {
3017 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3018};
3019
3020struct mlx5_ifc_query_vport_counter_in_bits {
3021 u8 opcode[0x10];
3022 u8 reserved_0[0x10];
3023
3024 u8 reserved_1[0x10];
3025 u8 op_mod[0x10];
3026
3027 u8 other_vport[0x1];
3028 u8 reserved_2[0xf];
3029 u8 vport_number[0x10];
3030
3031 u8 reserved_3[0x60];
3032
3033 u8 clear[0x1];
3034 u8 reserved_4[0x1f];
3035
3036 u8 reserved_5[0x20];
3037};
3038
3039struct mlx5_ifc_query_tis_out_bits {
3040 u8 status[0x8];
3041 u8 reserved_0[0x18];
3042
3043 u8 syndrome[0x20];
3044
3045 u8 reserved_1[0x40];
3046
3047 struct mlx5_ifc_tisc_bits tis_context;
3048};
3049
3050struct mlx5_ifc_query_tis_in_bits {
3051 u8 opcode[0x10];
3052 u8 reserved_0[0x10];
3053
3054 u8 reserved_1[0x10];
3055 u8 op_mod[0x10];
3056
3057 u8 reserved_2[0x8];
3058 u8 tisn[0x18];
3059
3060 u8 reserved_3[0x20];
3061};
3062
3063struct mlx5_ifc_query_tir_out_bits {
3064 u8 status[0x8];
3065 u8 reserved_0[0x18];
3066
3067 u8 syndrome[0x20];
3068
3069 u8 reserved_1[0xc0];
3070
3071 struct mlx5_ifc_tirc_bits tir_context;
3072};
3073
3074struct mlx5_ifc_query_tir_in_bits {
3075 u8 opcode[0x10];
3076 u8 reserved_0[0x10];
3077
3078 u8 reserved_1[0x10];
3079 u8 op_mod[0x10];
3080
3081 u8 reserved_2[0x8];
3082 u8 tirn[0x18];
3083
3084 u8 reserved_3[0x20];
3085};
3086
3087struct mlx5_ifc_query_srq_out_bits {
3088 u8 status[0x8];
3089 u8 reserved_0[0x18];
3090
3091 u8 syndrome[0x20];
3092
3093 u8 reserved_1[0x40];
3094
3095 struct mlx5_ifc_srqc_bits srq_context_entry;
3096
3097 u8 reserved_2[0x600];
3098
3099 u8 pas[0][0x40];
3100};
3101
3102struct mlx5_ifc_query_srq_in_bits {
3103 u8 opcode[0x10];
3104 u8 reserved_0[0x10];
3105
3106 u8 reserved_1[0x10];
3107 u8 op_mod[0x10];
3108
3109 u8 reserved_2[0x8];
3110 u8 srqn[0x18];
3111
3112 u8 reserved_3[0x20];
3113};
3114
3115struct mlx5_ifc_query_sq_out_bits {
3116 u8 status[0x8];
3117 u8 reserved_0[0x18];
3118
3119 u8 syndrome[0x20];
3120
3121 u8 reserved_1[0xc0];
3122
3123 struct mlx5_ifc_sqc_bits sq_context;
3124};
3125
3126struct mlx5_ifc_query_sq_in_bits {
3127 u8 opcode[0x10];
3128 u8 reserved_0[0x10];
3129
3130 u8 reserved_1[0x10];
3131 u8 op_mod[0x10];
3132
3133 u8 reserved_2[0x8];
3134 u8 sqn[0x18];
3135
3136 u8 reserved_3[0x20];
3137};
3138
3139struct mlx5_ifc_query_special_contexts_out_bits {
3140 u8 status[0x8];
3141 u8 reserved_0[0x18];
3142
3143 u8 syndrome[0x20];
3144
3145 u8 reserved_1[0x20];
3146
3147 u8 resd_lkey[0x20];
3148};
3149
3150struct mlx5_ifc_query_special_contexts_in_bits {
3151 u8 opcode[0x10];
3152 u8 reserved_0[0x10];
3153
3154 u8 reserved_1[0x10];
3155 u8 op_mod[0x10];
3156
3157 u8 reserved_2[0x40];
3158};
3159
3160struct mlx5_ifc_query_rqt_out_bits {
3161 u8 status[0x8];
3162 u8 reserved_0[0x18];
3163
3164 u8 syndrome[0x20];
3165
3166 u8 reserved_1[0xc0];
3167
3168 struct mlx5_ifc_rqtc_bits rqt_context;
3169};
3170
3171struct mlx5_ifc_query_rqt_in_bits {
3172 u8 opcode[0x10];
3173 u8 reserved_0[0x10];
3174
3175 u8 reserved_1[0x10];
3176 u8 op_mod[0x10];
3177
3178 u8 reserved_2[0x8];
3179 u8 rqtn[0x18];
3180
3181 u8 reserved_3[0x20];
3182};
3183
3184struct mlx5_ifc_query_rq_out_bits {
3185 u8 status[0x8];
3186 u8 reserved_0[0x18];
3187
3188 u8 syndrome[0x20];
3189
3190 u8 reserved_1[0xc0];
3191
3192 struct mlx5_ifc_rqc_bits rq_context;
3193};
3194
3195struct mlx5_ifc_query_rq_in_bits {
3196 u8 opcode[0x10];
3197 u8 reserved_0[0x10];
3198
3199 u8 reserved_1[0x10];
3200 u8 op_mod[0x10];
3201
3202 u8 reserved_2[0x8];
3203 u8 rqn[0x18];
3204
3205 u8 reserved_3[0x20];
3206};
3207
3208struct mlx5_ifc_query_roce_address_out_bits {
3209 u8 status[0x8];
3210 u8 reserved_0[0x18];
3211
3212 u8 syndrome[0x20];
3213
3214 u8 reserved_1[0x40];
3215
3216 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3217};
3218
3219struct mlx5_ifc_query_roce_address_in_bits {
3220 u8 opcode[0x10];
3221 u8 reserved_0[0x10];
3222
3223 u8 reserved_1[0x10];
3224 u8 op_mod[0x10];
3225
3226 u8 roce_address_index[0x10];
3227 u8 reserved_2[0x10];
3228
3229 u8 reserved_3[0x20];
3230};
3231
3232struct mlx5_ifc_query_rmp_out_bits {
3233 u8 status[0x8];
3234 u8 reserved_0[0x18];
3235
3236 u8 syndrome[0x20];
3237
3238 u8 reserved_1[0xc0];
3239
3240 struct mlx5_ifc_rmpc_bits rmp_context;
3241};
3242
3243struct mlx5_ifc_query_rmp_in_bits {
3244 u8 opcode[0x10];
3245 u8 reserved_0[0x10];
3246
3247 u8 reserved_1[0x10];
3248 u8 op_mod[0x10];
3249
3250 u8 reserved_2[0x8];
3251 u8 rmpn[0x18];
3252
3253 u8 reserved_3[0x20];
3254};
3255
3256struct mlx5_ifc_query_qp_out_bits {
3257 u8 status[0x8];
3258 u8 reserved_0[0x18];
3259
3260 u8 syndrome[0x20];
3261
3262 u8 reserved_1[0x40];
3263
3264 u8 opt_param_mask[0x20];
3265
3266 u8 reserved_2[0x20];
3267
3268 struct mlx5_ifc_qpc_bits qpc;
3269
3270 u8 reserved_3[0x80];
3271
3272 u8 pas[0][0x40];
3273};
3274
3275struct mlx5_ifc_query_qp_in_bits {
3276 u8 opcode[0x10];
3277 u8 reserved_0[0x10];
3278
3279 u8 reserved_1[0x10];
3280 u8 op_mod[0x10];
3281
3282 u8 reserved_2[0x8];
3283 u8 qpn[0x18];
3284
3285 u8 reserved_3[0x20];
3286};
3287
3288struct mlx5_ifc_query_q_counter_out_bits {
3289 u8 status[0x8];
3290 u8 reserved_0[0x18];
3291
3292 u8 syndrome[0x20];
3293
3294 u8 reserved_1[0x40];
3295
3296 u8 rx_write_requests[0x20];
3297
3298 u8 reserved_2[0x20];
3299
3300 u8 rx_read_requests[0x20];
3301
3302 u8 reserved_3[0x20];
3303
3304 u8 rx_atomic_requests[0x20];
3305
3306 u8 reserved_4[0x20];
3307
3308 u8 rx_dct_connect[0x20];
3309
3310 u8 reserved_5[0x20];
3311
3312 u8 out_of_buffer[0x20];
3313
3314 u8 reserved_6[0x20];
3315
3316 u8 out_of_sequence[0x20];
3317
3318 u8 reserved_7[0x620];
3319};
3320
3321struct mlx5_ifc_query_q_counter_in_bits {
3322 u8 opcode[0x10];
3323 u8 reserved_0[0x10];
3324
3325 u8 reserved_1[0x10];
3326 u8 op_mod[0x10];
3327
3328 u8 reserved_2[0x80];
3329
3330 u8 clear[0x1];
3331 u8 reserved_3[0x1f];
3332
3333 u8 reserved_4[0x18];
3334 u8 counter_set_id[0x8];
3335};
3336
3337struct mlx5_ifc_query_pages_out_bits {
3338 u8 status[0x8];
3339 u8 reserved_0[0x18];
3340
3341 u8 syndrome[0x20];
3342
3343 u8 reserved_1[0x10];
3344 u8 function_id[0x10];
3345
3346 u8 num_pages[0x20];
3347};
3348
3349enum {
3350 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3351 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3352 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3353};
3354
3355struct mlx5_ifc_query_pages_in_bits {
3356 u8 opcode[0x10];
3357 u8 reserved_0[0x10];
3358
3359 u8 reserved_1[0x10];
3360 u8 op_mod[0x10];
3361
3362 u8 reserved_2[0x10];
3363 u8 function_id[0x10];
3364
3365 u8 reserved_3[0x20];
3366};
3367
3368struct mlx5_ifc_query_nic_vport_context_out_bits {
3369 u8 status[0x8];
3370 u8 reserved_0[0x18];
3371
3372 u8 syndrome[0x20];
3373
3374 u8 reserved_1[0x40];
3375
3376 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3377};
3378
3379struct mlx5_ifc_query_nic_vport_context_in_bits {
3380 u8 opcode[0x10];
3381 u8 reserved_0[0x10];
3382
3383 u8 reserved_1[0x10];
3384 u8 op_mod[0x10];
3385
3386 u8 other_vport[0x1];
3387 u8 reserved_2[0xf];
3388 u8 vport_number[0x10];
3389
3390 u8 reserved_3[0x5];
3391 u8 allowed_list_type[0x3];
3392 u8 reserved_4[0x18];
3393};
3394
3395struct mlx5_ifc_query_mkey_out_bits {
3396 u8 status[0x8];
3397 u8 reserved_0[0x18];
3398
3399 u8 syndrome[0x20];
3400
3401 u8 reserved_1[0x40];
3402
3403 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3404
3405 u8 reserved_2[0x600];
3406
3407 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3408
3409 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3410};
3411
3412struct mlx5_ifc_query_mkey_in_bits {
3413 u8 opcode[0x10];
3414 u8 reserved_0[0x10];
3415
3416 u8 reserved_1[0x10];
3417 u8 op_mod[0x10];
3418
3419 u8 reserved_2[0x8];
3420 u8 mkey_index[0x18];
3421
3422 u8 pg_access[0x1];
3423 u8 reserved_3[0x1f];
3424};
3425
3426struct mlx5_ifc_query_mad_demux_out_bits {
3427 u8 status[0x8];
3428 u8 reserved_0[0x18];
3429
3430 u8 syndrome[0x20];
3431
3432 u8 reserved_1[0x40];
3433
3434 u8 mad_dumux_parameters_block[0x20];
3435};
3436
3437struct mlx5_ifc_query_mad_demux_in_bits {
3438 u8 opcode[0x10];
3439 u8 reserved_0[0x10];
3440
3441 u8 reserved_1[0x10];
3442 u8 op_mod[0x10];
3443
3444 u8 reserved_2[0x40];
3445};
3446
3447struct mlx5_ifc_query_l2_table_entry_out_bits {
3448 u8 status[0x8];
3449 u8 reserved_0[0x18];
3450
3451 u8 syndrome[0x20];
3452
3453 u8 reserved_1[0xa0];
3454
3455 u8 reserved_2[0x13];
3456 u8 vlan_valid[0x1];
3457 u8 vlan[0xc];
3458
3459 struct mlx5_ifc_mac_address_layout_bits mac_address;
3460
3461 u8 reserved_3[0xc0];
3462};
3463
3464struct mlx5_ifc_query_l2_table_entry_in_bits {
3465 u8 opcode[0x10];
3466 u8 reserved_0[0x10];
3467
3468 u8 reserved_1[0x10];
3469 u8 op_mod[0x10];
3470
3471 u8 reserved_2[0x60];
3472
3473 u8 reserved_3[0x8];
3474 u8 table_index[0x18];
3475
3476 u8 reserved_4[0x140];
3477};
3478
3479struct mlx5_ifc_query_issi_out_bits {
3480 u8 status[0x8];
3481 u8 reserved_0[0x18];
3482
3483 u8 syndrome[0x20];
3484
3485 u8 reserved_1[0x10];
3486 u8 current_issi[0x10];
3487
3488 u8 reserved_2[0xa0];
3489
3490 u8 supported_issi_reserved[76][0x8];
3491 u8 supported_issi_dw0[0x20];
3492};
3493
3494struct mlx5_ifc_query_issi_in_bits {
3495 u8 opcode[0x10];
3496 u8 reserved_0[0x10];
3497
3498 u8 reserved_1[0x10];
3499 u8 op_mod[0x10];
3500
3501 u8 reserved_2[0x40];
3502};
3503
3504struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3505 u8 status[0x8];
3506 u8 reserved_0[0x18];
3507
3508 u8 syndrome[0x20];
3509
3510 u8 reserved_1[0x40];
3511
3512 struct mlx5_ifc_pkey_bits pkey[0];
3513};
3514
3515struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3516 u8 opcode[0x10];
3517 u8 reserved_0[0x10];
3518
3519 u8 reserved_1[0x10];
3520 u8 op_mod[0x10];
3521
3522 u8 other_vport[0x1];
707c4602
MD		 3523 u8 reserved_2[0xb];
3524 u8 port_num[0x4];
e281682b
SM		 3525 u8 vport_number[0x10];
3526
3527 u8 reserved_3[0x10];
3528 u8 pkey_index[0x10];
3529};
3530
3531struct mlx5_ifc_query_hca_vport_gid_out_bits {
3532 u8 status[0x8];
3533 u8 reserved_0[0x18];
3534
3535 u8 syndrome[0x20];
3536
3537 u8 reserved_1[0x20];
3538
3539 u8 gids_num[0x10];
3540 u8 reserved_2[0x10];
3541
3542 struct mlx5_ifc_array128_auto_bits gid[0];
3543};
3544
3545struct mlx5_ifc_query_hca_vport_gid_in_bits {
3546 u8 opcode[0x10];
3547 u8 reserved_0[0x10];
3548
3549 u8 reserved_1[0x10];
3550 u8 op_mod[0x10];
3551
3552 u8 other_vport[0x1];
707c4602
MD		 3553 u8 reserved_2[0xb];
3554 u8 port_num[0x4];
e281682b
SM		 3555 u8 vport_number[0x10];
3556
3557 u8 reserved_3[0x10];
3558 u8 gid_index[0x10];
3559};
3560
3561struct mlx5_ifc_query_hca_vport_context_out_bits {
3562 u8 status[0x8];
3563 u8 reserved_0[0x18];
3564
3565 u8 syndrome[0x20];
3566
3567 u8 reserved_1[0x40];
3568
3569 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3570};
3571
3572struct mlx5_ifc_query_hca_vport_context_in_bits {
3573 u8 opcode[0x10];
3574 u8 reserved_0[0x10];
3575
3576 u8 reserved_1[0x10];
3577 u8 op_mod[0x10];
3578
3579 u8 other_vport[0x1];
707c4602
MD		 3580 u8 reserved_2[0xb];
3581 u8 port_num[0x4];
e281682b
SM		 3582 u8 vport_number[0x10];
3583
3584 u8 reserved_3[0x20];
3585};
3586
3587struct mlx5_ifc_query_hca_cap_out_bits {
3588 u8 status[0x8];
3589 u8 reserved_0[0x18];
3590
3591 u8 syndrome[0x20];
3592
3593 u8 reserved_1[0x40];
3594
3595 union mlx5_ifc_hca_cap_union_bits capability;
3596};
3597
3598struct mlx5_ifc_query_hca_cap_in_bits {
3599 u8 opcode[0x10];
3600 u8 reserved_0[0x10];
3601
3602 u8 reserved_1[0x10];
3603 u8 op_mod[0x10];
3604
3605 u8 reserved_2[0x40];
3606};
3607
3608struct mlx5_ifc_query_flow_table_out_bits {
3609 u8 status[0x8];
3610 u8 reserved_0[0x18];
3611
3612 u8 syndrome[0x20];
3613
3614 u8 reserved_1[0x80];
3615
3616 u8 reserved_2[0x8];
3617 u8 level[0x8];
3618 u8 reserved_3[0x8];
3619 u8 log_size[0x8];
3620
3621 u8 reserved_4[0x120];
3622};
3623
3624struct mlx5_ifc_query_flow_table_in_bits {
3625 u8 opcode[0x10];
3626 u8 reserved_0[0x10];
3627
3628 u8 reserved_1[0x10];
3629 u8 op_mod[0x10];
3630
3631 u8 reserved_2[0x40];
3632
3633 u8 table_type[0x8];
3634 u8 reserved_3[0x18];
3635
3636 u8 reserved_4[0x8];
3637 u8 table_id[0x18];
3638
3639 u8 reserved_5[0x140];
3640};
3641
3642struct mlx5_ifc_query_fte_out_bits {
3643 u8 status[0x8];
3644 u8 reserved_0[0x18];
3645
3646 u8 syndrome[0x20];
3647
3648 u8 reserved_1[0x1c0];
3649
3650 struct mlx5_ifc_flow_context_bits flow_context;
3651};
3652
3653struct mlx5_ifc_query_fte_in_bits {
3654 u8 opcode[0x10];
3655 u8 reserved_0[0x10];
3656
3657 u8 reserved_1[0x10];
3658 u8 op_mod[0x10];
3659
3660 u8 reserved_2[0x40];
3661
3662 u8 table_type[0x8];
3663 u8 reserved_3[0x18];
3664
3665 u8 reserved_4[0x8];
3666 u8 table_id[0x18];
3667
3668 u8 reserved_5[0x40];
3669
3670 u8 flow_index[0x20];
3671
3672 u8 reserved_6[0xe0];
3673};
3674
3675enum {
3676 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3677 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3678 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3679};
3680
3681struct mlx5_ifc_query_flow_group_out_bits {
3682 u8 status[0x8];
3683 u8 reserved_0[0x18];
3684
3685 u8 syndrome[0x20];
3686
3687 u8 reserved_1[0xa0];
3688
3689 u8 start_flow_index[0x20];
3690
3691 u8 reserved_2[0x20];
3692
3693 u8 end_flow_index[0x20];
3694
3695 u8 reserved_3[0xa0];
3696
3697 u8 reserved_4[0x18];
3698 u8 match_criteria_enable[0x8];
3699
3700 struct mlx5_ifc_fte_match_param_bits match_criteria;
3701
3702 u8 reserved_5[0xe00];
3703};
3704
3705struct mlx5_ifc_query_flow_group_in_bits {
3706 u8 opcode[0x10];
3707 u8 reserved_0[0x10];
3708
3709 u8 reserved_1[0x10];
3710 u8 op_mod[0x10];
3711
3712 u8 reserved_2[0x40];
3713
3714 u8 table_type[0x8];
3715 u8 reserved_3[0x18];
3716
3717 u8 reserved_4[0x8];
3718 u8 table_id[0x18];
3719
3720 u8 group_id[0x20];
3721
3722 u8 reserved_5[0x120];
3723};
3724
3725struct mlx5_ifc_query_eq_out_bits {
3726 u8 status[0x8];
3727 u8 reserved_0[0x18];
3728
3729 u8 syndrome[0x20];
3730
3731 u8 reserved_1[0x40];
3732
3733 struct mlx5_ifc_eqc_bits eq_context_entry;
3734
3735 u8 reserved_2[0x40];
3736
3737 u8 event_bitmask[0x40];
3738
3739 u8 reserved_3[0x580];
3740
3741 u8 pas[0][0x40];
3742};
3743
3744struct mlx5_ifc_query_eq_in_bits {
3745 u8 opcode[0x10];
3746 u8 reserved_0[0x10];
3747
3748 u8 reserved_1[0x10];
3749 u8 op_mod[0x10];
3750
3751 u8 reserved_2[0x18];
3752 u8 eq_number[0x8];
3753
3754 u8 reserved_3[0x20];
3755};
3756
3757struct mlx5_ifc_query_dct_out_bits {
3758 u8 status[0x8];
3759 u8 reserved_0[0x18];
3760
3761 u8 syndrome[0x20];
3762
3763 u8 reserved_1[0x40];
3764
3765 struct mlx5_ifc_dctc_bits dct_context_entry;
3766
3767 u8 reserved_2[0x180];
3768};
3769
3770struct mlx5_ifc_query_dct_in_bits {
3771 u8 opcode[0x10];
3772 u8 reserved_0[0x10];
3773
3774 u8 reserved_1[0x10];
3775 u8 op_mod[0x10];
3776
3777 u8 reserved_2[0x8];
3778 u8 dctn[0x18];
3779
3780 u8 reserved_3[0x20];
3781};
3782
3783struct mlx5_ifc_query_cq_out_bits {
3784 u8 status[0x8];
3785 u8 reserved_0[0x18];
3786
3787 u8 syndrome[0x20];
3788
3789 u8 reserved_1[0x40];
3790
3791 struct mlx5_ifc_cqc_bits cq_context;
3792
3793 u8 reserved_2[0x600];
3794
3795 u8 pas[0][0x40];
3796};
3797
3798struct mlx5_ifc_query_cq_in_bits {
3799 u8 opcode[0x10];
3800 u8 reserved_0[0x10];
3801
3802 u8 reserved_1[0x10];
3803 u8 op_mod[0x10];
3804
3805 u8 reserved_2[0x8];
3806 u8 cqn[0x18];
3807
3808 u8 reserved_3[0x20];
3809};
3810
3811struct mlx5_ifc_query_cong_status_out_bits {
3812 u8 status[0x8];
3813 u8 reserved_0[0x18];
3814
3815 u8 syndrome[0x20];
3816
3817 u8 reserved_1[0x20];
3818
3819 u8 enable[0x1];
3820 u8 tag_enable[0x1];
3821 u8 reserved_2[0x1e];
3822};
3823
3824struct mlx5_ifc_query_cong_status_in_bits {
3825 u8 opcode[0x10];
3826 u8 reserved_0[0x10];
3827
3828 u8 reserved_1[0x10];
3829 u8 op_mod[0x10];
3830
3831 u8 reserved_2[0x18];
3832 u8 priority[0x4];
3833 u8 cong_protocol[0x4];
3834
3835 u8 reserved_3[0x20];
3836};
3837
3838struct mlx5_ifc_query_cong_statistics_out_bits {
3839 u8 status[0x8];
3840 u8 reserved_0[0x18];
3841
3842 u8 syndrome[0x20];
3843
3844 u8 reserved_1[0x40];
3845
3846 u8 cur_flows[0x20];
3847
3848 u8 sum_flows[0x20];
3849
3850 u8 cnp_ignored_high[0x20];
3851
3852 u8 cnp_ignored_low[0x20];
3853
3854 u8 cnp_handled_high[0x20];
3855
3856 u8 cnp_handled_low[0x20];
3857
3858 u8 reserved_2[0x100];
3859
3860 u8 time_stamp_high[0x20];
3861
3862 u8 time_stamp_low[0x20];
3863
3864 u8 accumulators_period[0x20];
3865
3866 u8 ecn_marked_roce_packets_high[0x20];
3867
3868 u8 ecn_marked_roce_packets_low[0x20];
3869
3870 u8 cnps_sent_high[0x20];
3871
3872 u8 cnps_sent_low[0x20];
3873
3874 u8 reserved_3[0x560];
3875};
3876
3877struct mlx5_ifc_query_cong_statistics_in_bits {
3878 u8 opcode[0x10];
3879 u8 reserved_0[0x10];
3880
3881 u8 reserved_1[0x10];
3882 u8 op_mod[0x10];
3883
3884 u8 clear[0x1];
3885 u8 reserved_2[0x1f];
3886
3887 u8 reserved_3[0x20];
3888};
3889
3890struct mlx5_ifc_query_cong_params_out_bits {
3891 u8 status[0x8];
3892 u8 reserved_0[0x18];
3893
3894 u8 syndrome[0x20];
3895
3896 u8 reserved_1[0x40];
3897
3898 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3899};
3900
3901struct mlx5_ifc_query_cong_params_in_bits {
3902 u8 opcode[0x10];
3903 u8 reserved_0[0x10];
3904
3905 u8 reserved_1[0x10];
3906 u8 op_mod[0x10];
3907
3908 u8 reserved_2[0x1c];
3909 u8 cong_protocol[0x4];
3910
3911 u8 reserved_3[0x20];
3912};
3913
3914struct mlx5_ifc_query_adapter_out_bits {
3915 u8 status[0x8];
3916 u8 reserved_0[0x18];
3917
3918 u8 syndrome[0x20];
3919
3920 u8 reserved_1[0x40];
3921
3922 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3923};
3924
3925struct mlx5_ifc_query_adapter_in_bits {
3926 u8 opcode[0x10];
3927 u8 reserved_0[0x10];
3928
3929 u8 reserved_1[0x10];
3930 u8 op_mod[0x10];
3931
3932 u8 reserved_2[0x40];
3933};
3934
3935struct mlx5_ifc_qp_2rst_out_bits {
3936 u8 status[0x8];
3937 u8 reserved_0[0x18];
3938
3939 u8 syndrome[0x20];
3940
3941 u8 reserved_1[0x40];
3942};
3943
3944struct mlx5_ifc_qp_2rst_in_bits {
3945 u8 opcode[0x10];
3946 u8 reserved_0[0x10];
3947
3948 u8 reserved_1[0x10];
3949 u8 op_mod[0x10];
3950
3951 u8 reserved_2[0x8];
3952 u8 qpn[0x18];
3953
3954 u8 reserved_3[0x20];
3955};
3956
3957struct mlx5_ifc_qp_2err_out_bits {
3958 u8 status[0x8];
3959 u8 reserved_0[0x18];
3960
3961 u8 syndrome[0x20];
3962
3963 u8 reserved_1[0x40];
3964};
3965
3966struct mlx5_ifc_qp_2err_in_bits {
3967 u8 opcode[0x10];
3968 u8 reserved_0[0x10];
3969
3970 u8 reserved_1[0x10];
3971 u8 op_mod[0x10];
3972
3973 u8 reserved_2[0x8];
3974 u8 qpn[0x18];
3975
3976 u8 reserved_3[0x20];
3977};
3978
3979struct mlx5_ifc_page_fault_resume_out_bits {
3980 u8 status[0x8];
3981 u8 reserved_0[0x18];
3982
3983 u8 syndrome[0x20];
3984
3985 u8 reserved_1[0x40];
3986};
3987
3988struct mlx5_ifc_page_fault_resume_in_bits {
3989 u8 opcode[0x10];
3990 u8 reserved_0[0x10];
3991
3992 u8 reserved_1[0x10];
3993 u8 op_mod[0x10];
3994
3995 u8 error[0x1];
3996 u8 reserved_2[0x4];
3997 u8 rdma[0x1];
3998 u8 read_write[0x1];
3999 u8 req_res[0x1];
4000 u8 qpn[0x18];
4001
4002 u8 reserved_3[0x20];
4003};
4004
4005struct mlx5_ifc_nop_out_bits {
4006 u8 status[0x8];
4007 u8 reserved_0[0x18];
4008
4009 u8 syndrome[0x20];
4010
4011 u8 reserved_1[0x40];
4012};
4013
4014struct mlx5_ifc_nop_in_bits {
4015 u8 opcode[0x10];
4016 u8 reserved_0[0x10];
4017
4018 u8 reserved_1[0x10];
4019 u8 op_mod[0x10];
4020
4021 u8 reserved_2[0x40];
4022};
4023
4024struct mlx5_ifc_modify_vport_state_out_bits {
4025 u8 status[0x8];
4026 u8 reserved_0[0x18];
4027
4028 u8 syndrome[0x20];
4029
4030 u8 reserved_1[0x40];
4031};
4032
4033struct mlx5_ifc_modify_vport_state_in_bits {
4034 u8 opcode[0x10];
4035 u8 reserved_0[0x10];
4036
4037 u8 reserved_1[0x10];
4038 u8 op_mod[0x10];
4039
4040 u8 other_vport[0x1];
4041 u8 reserved_2[0xf];
4042 u8 vport_number[0x10];
4043
4044 u8 reserved_3[0x18];
4045 u8 admin_state[0x4];
4046 u8 reserved_4[0x4];
4047};
4048
4049struct mlx5_ifc_modify_tis_out_bits {
4050 u8 status[0x8];
4051 u8 reserved_0[0x18];
4052
4053 u8 syndrome[0x20];
4054
4055 u8 reserved_1[0x40];
4056};
4057
4058struct mlx5_ifc_modify_tis_in_bits {
4059 u8 opcode[0x10];
4060 u8 reserved_0[0x10];
4061
4062 u8 reserved_1[0x10];
4063 u8 op_mod[0x10];
4064
4065 u8 reserved_2[0x8];
4066 u8 tisn[0x18];
4067
4068 u8 reserved_3[0x20];
4069
4070 u8 modify_bitmask[0x40];
4071
4072 u8 reserved_4[0x40];
4073
4074 struct mlx5_ifc_tisc_bits ctx;
4075};
4076
d9eea403 4077struct mlx5_ifc_modify_tir_bitmask_bits {
66189961 4078 u8 reserved_0[0x20];
d9eea403 4079
66189961
TT		 4080 u8 reserved_1[0x1b];
4081 u8 self_lb_en[0x1];
4082 u8 reserved_2[0x3];
d9eea403
AS		 4083 u8 lro[0x1];
4084};
4085
e281682b
SM		 4086struct mlx5_ifc_modify_tir_out_bits {
4087 u8 status[0x8];
4088 u8 reserved_0[0x18];
4089
4090 u8 syndrome[0x20];
4091
4092 u8 reserved_1[0x40];
4093};
4094
4095struct mlx5_ifc_modify_tir_in_bits {
4096 u8 opcode[0x10];
4097 u8 reserved_0[0x10];
4098
4099 u8 reserved_1[0x10];
4100 u8 op_mod[0x10];
4101
4102 u8 reserved_2[0x8];
4103 u8 tirn[0x18];
4104
4105 u8 reserved_3[0x20];
4106
d9eea403 4107 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b
SM		 4108
4109 u8 reserved_4[0x40];
4110
4111 struct mlx5_ifc_tirc_bits ctx;
4112};
4113
4114struct mlx5_ifc_modify_sq_out_bits {
4115 u8 status[0x8];
4116 u8 reserved_0[0x18];
4117
4118 u8 syndrome[0x20];
4119
4120 u8 reserved_1[0x40];
4121};
4122
4123struct mlx5_ifc_modify_sq_in_bits {
4124 u8 opcode[0x10];
4125 u8 reserved_0[0x10];
4126
4127 u8 reserved_1[0x10];
4128 u8 op_mod[0x10];
4129
4130 u8 sq_state[0x4];
4131 u8 reserved_2[0x4];
4132 u8 sqn[0x18];
4133
4134 u8 reserved_3[0x20];
4135
4136 u8 modify_bitmask[0x40];
4137
4138 u8 reserved_4[0x40];
4139
4140 struct mlx5_ifc_sqc_bits ctx;
4141};
4142
4143struct mlx5_ifc_modify_rqt_out_bits {
4144 u8 status[0x8];
4145 u8 reserved_0[0x18];
4146
4147 u8 syndrome[0x20];
4148
4149 u8 reserved_1[0x40];
4150};
4151
5c50368f
AS		 4152struct mlx5_ifc_rqt_bitmask_bits {
4153 u8 reserved[0x20];
4154
4155 u8 reserved1[0x1f];
4156 u8 rqn_list[0x1];
4157};
4158
e281682b
SM		 4159struct mlx5_ifc_modify_rqt_in_bits {
4160 u8 opcode[0x10];
4161 u8 reserved_0[0x10];
4162
4163 u8 reserved_1[0x10];
4164 u8 op_mod[0x10];
4165
4166 u8 reserved_2[0x8];
4167 u8 rqtn[0x18];
4168
4169 u8 reserved_3[0x20];
4170
5c50368f 4171 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b
SM		 4172
4173 u8 reserved_4[0x40];
4174
4175 struct mlx5_ifc_rqtc_bits ctx;
4176};
4177
4178struct mlx5_ifc_modify_rq_out_bits {
4179 u8 status[0x8];
4180 u8 reserved_0[0x18];
4181
4182 u8 syndrome[0x20];
4183
4184 u8 reserved_1[0x40];
4185};
4186
4187struct mlx5_ifc_modify_rq_in_bits {
4188 u8 opcode[0x10];
4189 u8 reserved_0[0x10];
4190
4191 u8 reserved_1[0x10];
4192 u8 op_mod[0x10];
4193
4194 u8 rq_state[0x4];
4195 u8 reserved_2[0x4];
4196 u8 rqn[0x18];
4197
4198 u8 reserved_3[0x20];
4199
4200 u8 modify_bitmask[0x40];
4201
4202 u8 reserved_4[0x40];
4203
4204 struct mlx5_ifc_rqc_bits ctx;
4205};
4206
4207struct mlx5_ifc_modify_rmp_out_bits {
4208 u8 status[0x8];
4209 u8 reserved_0[0x18];
4210
4211 u8 syndrome[0x20];
4212
4213 u8 reserved_1[0x40];
4214};
4215
01949d01
HA		 4216struct mlx5_ifc_rmp_bitmask_bits {
4217 u8 reserved[0x20];
4218
4219 u8 reserved1[0x1f];
4220 u8 lwm[0x1];
4221};
4222
e281682b
SM		 4223struct mlx5_ifc_modify_rmp_in_bits {
4224 u8 opcode[0x10];
4225 u8 reserved_0[0x10];
4226
4227 u8 reserved_1[0x10];
4228 u8 op_mod[0x10];
4229
4230 u8 rmp_state[0x4];
4231 u8 reserved_2[0x4];
4232 u8 rmpn[0x18];
4233
4234 u8 reserved_3[0x20];
4235
01949d01 4236 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b
SM		 4237
4238 u8 reserved_4[0x40];
4239
4240 struct mlx5_ifc_rmpc_bits ctx;
4241};
4242
4243struct mlx5_ifc_modify_nic_vport_context_out_bits {
4244 u8 status[0x8];
4245 u8 reserved_0[0x18];
4246
4247 u8 syndrome[0x20];
4248
4249 u8 reserved_1[0x40];
4250};
4251
4252struct mlx5_ifc_modify_nic_vport_field_select_bits {
d82b7318
SM		 4253 u8 reserved_0[0x19];
4254 u8 mtu[0x1];
4255 u8 change_event[0x1];
4256 u8 promisc[0x1];
e281682b
SM		 4257 u8 permanent_address[0x1];
4258 u8 addresses_list[0x1];
4259 u8 roce_en[0x1];
4260 u8 reserved_1[0x1];
4261};
4262
4263struct mlx5_ifc_modify_nic_vport_context_in_bits {
4264 u8 opcode[0x10];
4265 u8 reserved_0[0x10];
4266
4267 u8 reserved_1[0x10];
4268 u8 op_mod[0x10];
4269
4270 u8 other_vport[0x1];
4271 u8 reserved_2[0xf];
4272 u8 vport_number[0x10];
4273
4274 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4275
4276 u8 reserved_3[0x780];
4277
4278 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4279};
4280
4281struct mlx5_ifc_modify_hca_vport_context_out_bits {
4282 u8 status[0x8];
4283 u8 reserved_0[0x18];
4284
4285 u8 syndrome[0x20];
4286
4287 u8 reserved_1[0x40];
4288};
4289
4290struct mlx5_ifc_modify_hca_vport_context_in_bits {
4291 u8 opcode[0x10];
4292 u8 reserved_0[0x10];
4293
4294 u8 reserved_1[0x10];
4295 u8 op_mod[0x10];
4296
4297 u8 other_vport[0x1];
707c4602
MD		 4298 u8 reserved_2[0xb];
4299 u8 port_num[0x4];
e281682b
SM		 4300 u8 vport_number[0x10];
4301
4302 u8 reserved_3[0x20];
4303
4304 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4305};
4306
4307struct mlx5_ifc_modify_cq_out_bits {
4308 u8 status[0x8];
4309 u8 reserved_0[0x18];
4310
4311 u8 syndrome[0x20];
4312
4313 u8 reserved_1[0x40];
4314};
4315
4316enum {
4317 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4318 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4319};
4320
4321struct mlx5_ifc_modify_cq_in_bits {
4322 u8 opcode[0x10];
4323 u8 reserved_0[0x10];
4324
4325 u8 reserved_1[0x10];
4326 u8 op_mod[0x10];
4327
4328 u8 reserved_2[0x8];
4329 u8 cqn[0x18];
4330
4331 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4332
4333 struct mlx5_ifc_cqc_bits cq_context;
4334
4335 u8 reserved_3[0x600];
4336
4337 u8 pas[0][0x40];
4338};
4339
4340struct mlx5_ifc_modify_cong_status_out_bits {
4341 u8 status[0x8];
4342 u8 reserved_0[0x18];
4343
4344 u8 syndrome[0x20];
4345
4346 u8 reserved_1[0x40];
4347};
4348
4349struct mlx5_ifc_modify_cong_status_in_bits {
4350 u8 opcode[0x10];
4351 u8 reserved_0[0x10];
4352
4353 u8 reserved_1[0x10];
4354 u8 op_mod[0x10];
4355
4356 u8 reserved_2[0x18];
4357 u8 priority[0x4];
4358 u8 cong_protocol[0x4];
4359
4360 u8 enable[0x1];
4361 u8 tag_enable[0x1];
4362 u8 reserved_3[0x1e];
4363};
4364
4365struct mlx5_ifc_modify_cong_params_out_bits {
4366 u8 status[0x8];
4367 u8 reserved_0[0x18];
4368
4369 u8 syndrome[0x20];
4370
4371 u8 reserved_1[0x40];
4372};
4373
4374struct mlx5_ifc_modify_cong_params_in_bits {
4375 u8 opcode[0x10];
4376 u8 reserved_0[0x10];
4377
4378 u8 reserved_1[0x10];
4379 u8 op_mod[0x10];
4380
4381 u8 reserved_2[0x1c];
4382 u8 cong_protocol[0x4];
4383
4384 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4385
4386 u8 reserved_3[0x80];
4387
4388 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4389};
4390
4391struct mlx5_ifc_manage_pages_out_bits {
4392 u8 status[0x8];
4393 u8 reserved_0[0x18];
4394
4395 u8 syndrome[0x20];
4396
4397 u8 output_num_entries[0x20];
4398
4399 u8 reserved_1[0x20];
4400
4401 u8 pas[0][0x40];
4402};
4403
4404enum {
4405 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4406 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4407 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4408};
4409
4410struct mlx5_ifc_manage_pages_in_bits {
4411 u8 opcode[0x10];
4412 u8 reserved_0[0x10];
4413
4414 u8 reserved_1[0x10];
4415 u8 op_mod[0x10];
4416
4417 u8 reserved_2[0x10];
4418 u8 function_id[0x10];
4419
4420 u8 input_num_entries[0x20];
4421
4422 u8 pas[0][0x40];
4423};
4424
4425struct mlx5_ifc_mad_ifc_out_bits {
4426 u8 status[0x8];
4427 u8 reserved_0[0x18];
4428
4429 u8 syndrome[0x20];
4430
4431 u8 reserved_1[0x40];
4432
4433 u8 response_mad_packet[256][0x8];
4434};
4435
4436struct mlx5_ifc_mad_ifc_in_bits {
4437 u8 opcode[0x10];
4438 u8 reserved_0[0x10];
4439
4440 u8 reserved_1[0x10];
4441 u8 op_mod[0x10];
4442
4443 u8 remote_lid[0x10];
4444 u8 reserved_2[0x8];
4445 u8 port[0x8];
4446
4447 u8 reserved_3[0x20];
4448
4449 u8 mad[256][0x8];
4450};
4451
4452struct mlx5_ifc_init_hca_out_bits {
4453 u8 status[0x8];
4454 u8 reserved_0[0x18];
4455
4456 u8 syndrome[0x20];
4457
4458 u8 reserved_1[0x40];
4459};
4460
4461struct mlx5_ifc_init_hca_in_bits {
4462 u8 opcode[0x10];
4463 u8 reserved_0[0x10];
4464
4465 u8 reserved_1[0x10];
4466 u8 op_mod[0x10];
4467
4468 u8 reserved_2[0x40];
4469};
4470
4471struct mlx5_ifc_init2rtr_qp_out_bits {
4472 u8 status[0x8];
4473 u8 reserved_0[0x18];
4474
4475 u8 syndrome[0x20];
4476
4477 u8 reserved_1[0x40];
4478};
4479
4480struct mlx5_ifc_init2rtr_qp_in_bits {
4481 u8 opcode[0x10];
4482 u8 reserved_0[0x10];
4483
4484 u8 reserved_1[0x10];
4485 u8 op_mod[0x10];
4486
4487 u8 reserved_2[0x8];
4488 u8 qpn[0x18];
4489
4490 u8 reserved_3[0x20];
4491
4492 u8 opt_param_mask[0x20];
4493
4494 u8 reserved_4[0x20];
4495
4496 struct mlx5_ifc_qpc_bits qpc;
4497
4498 u8 reserved_5[0x80];
4499};
4500
4501struct mlx5_ifc_init2init_qp_out_bits {
4502 u8 status[0x8];
4503 u8 reserved_0[0x18];
4504
4505 u8 syndrome[0x20];
4506
4507 u8 reserved_1[0x40];
4508};
4509
4510struct mlx5_ifc_init2init_qp_in_bits {
4511 u8 opcode[0x10];
4512 u8 reserved_0[0x10];
4513
4514 u8 reserved_1[0x10];
4515 u8 op_mod[0x10];
4516
4517 u8 reserved_2[0x8];
4518 u8 qpn[0x18];
4519
4520 u8 reserved_3[0x20];
4521
4522 u8 opt_param_mask[0x20];
4523
4524 u8 reserved_4[0x20];
4525
4526 struct mlx5_ifc_qpc_bits qpc;
4527
4528 u8 reserved_5[0x80];
4529};
4530
4531struct mlx5_ifc_get_dropped_packet_log_out_bits {
4532 u8 status[0x8];
4533 u8 reserved_0[0x18];
4534
4535 u8 syndrome[0x20];
4536
4537 u8 reserved_1[0x40];
4538
4539 u8 packet_headers_log[128][0x8];
4540
4541 u8 packet_syndrome[64][0x8];
4542};
4543
4544struct mlx5_ifc_get_dropped_packet_log_in_bits {
4545 u8 opcode[0x10];
4546 u8 reserved_0[0x10];
4547
4548 u8 reserved_1[0x10];
4549 u8 op_mod[0x10];
4550
4551 u8 reserved_2[0x40];
4552};
4553
4554struct mlx5_ifc_gen_eqe_in_bits {
4555 u8 opcode[0x10];
4556 u8 reserved_0[0x10];
4557
4558 u8 reserved_1[0x10];
4559 u8 op_mod[0x10];
4560
4561 u8 reserved_2[0x18];
4562 u8 eq_number[0x8];
4563
4564 u8 reserved_3[0x20];
4565
4566 u8 eqe[64][0x8];
4567};
4568
4569struct mlx5_ifc_gen_eq_out_bits {
4570 u8 status[0x8];
4571 u8 reserved_0[0x18];
4572
4573 u8 syndrome[0x20];
4574
4575 u8 reserved_1[0x40];
4576};
4577
4578struct mlx5_ifc_enable_hca_out_bits {
4579 u8 status[0x8];
4580 u8 reserved_0[0x18];
4581
4582 u8 syndrome[0x20];
4583
4584 u8 reserved_1[0x20];
4585};
4586
4587struct mlx5_ifc_enable_hca_in_bits {
4588 u8 opcode[0x10];
4589 u8 reserved_0[0x10];
4590
4591 u8 reserved_1[0x10];
4592 u8 op_mod[0x10];
4593
4594 u8 reserved_2[0x10];
4595 u8 function_id[0x10];
4596
4597 u8 reserved_3[0x20];
4598};
4599
4600struct mlx5_ifc_drain_dct_out_bits {
4601 u8 status[0x8];
4602 u8 reserved_0[0x18];
4603
4604 u8 syndrome[0x20];
4605
4606 u8 reserved_1[0x40];
4607};
4608
4609struct mlx5_ifc_drain_dct_in_bits {
4610 u8 opcode[0x10];
4611 u8 reserved_0[0x10];
4612
4613 u8 reserved_1[0x10];
4614 u8 op_mod[0x10];
4615
4616 u8 reserved_2[0x8];
4617 u8 dctn[0x18];
4618
4619 u8 reserved_3[0x20];
4620};
4621
4622struct mlx5_ifc_disable_hca_out_bits {
4623 u8 status[0x8];
4624 u8 reserved_0[0x18];
4625
4626 u8 syndrome[0x20];
4627
4628 u8 reserved_1[0x20];
4629};
4630
4631struct mlx5_ifc_disable_hca_in_bits {
4632 u8 opcode[0x10];
4633 u8 reserved_0[0x10];
4634
4635 u8 reserved_1[0x10];
4636 u8 op_mod[0x10];
4637
4638 u8 reserved_2[0x10];
4639 u8 function_id[0x10];
4640
4641 u8 reserved_3[0x20];
4642};
4643
4644struct mlx5_ifc_detach_from_mcg_out_bits {
4645 u8 status[0x8];
4646 u8 reserved_0[0x18];
4647
4648 u8 syndrome[0x20];
4649
4650 u8 reserved_1[0x40];
4651};
4652
4653struct mlx5_ifc_detach_from_mcg_in_bits {
4654 u8 opcode[0x10];
4655 u8 reserved_0[0x10];
4656
4657 u8 reserved_1[0x10];
4658 u8 op_mod[0x10];
4659
4660 u8 reserved_2[0x8];
4661 u8 qpn[0x18];
4662
4663 u8 reserved_3[0x20];
4664
4665 u8 multicast_gid[16][0x8];
4666};
4667
4668struct mlx5_ifc_destroy_xrc_srq_out_bits {
4669 u8 status[0x8];
4670 u8 reserved_0[0x18];
4671
4672 u8 syndrome[0x20];
4673
4674 u8 reserved_1[0x40];
4675};
4676
4677struct mlx5_ifc_destroy_xrc_srq_in_bits {
4678 u8 opcode[0x10];
4679 u8 reserved_0[0x10];
4680
4681 u8 reserved_1[0x10];
4682 u8 op_mod[0x10];
4683
4684 u8 reserved_2[0x8];
4685 u8 xrc_srqn[0x18];
4686
4687 u8 reserved_3[0x20];
4688};
4689
4690struct mlx5_ifc_destroy_tis_out_bits {
4691 u8 status[0x8];
4692 u8 reserved_0[0x18];
4693
4694 u8 syndrome[0x20];
4695
4696 u8 reserved_1[0x40];
4697};
4698
4699struct mlx5_ifc_destroy_tis_in_bits {
4700 u8 opcode[0x10];
4701 u8 reserved_0[0x10];
4702
4703 u8 reserved_1[0x10];
4704 u8 op_mod[0x10];
4705
4706 u8 reserved_2[0x8];
4707 u8 tisn[0x18];
4708
4709 u8 reserved_3[0x20];
4710};
4711
4712struct mlx5_ifc_destroy_tir_out_bits {
4713 u8 status[0x8];
4714 u8 reserved_0[0x18];
4715
4716 u8 syndrome[0x20];
4717
4718 u8 reserved_1[0x40];
4719};
4720
4721struct mlx5_ifc_destroy_tir_in_bits {
4722 u8 opcode[0x10];
4723 u8 reserved_0[0x10];
4724
4725 u8 reserved_1[0x10];
4726 u8 op_mod[0x10];
4727
4728 u8 reserved_2[0x8];
4729 u8 tirn[0x18];
4730
4731 u8 reserved_3[0x20];
4732};
4733
4734struct mlx5_ifc_destroy_srq_out_bits {
4735 u8 status[0x8];
4736 u8 reserved_0[0x18];
4737
4738 u8 syndrome[0x20];
4739
4740 u8 reserved_1[0x40];
4741};
4742
4743struct mlx5_ifc_destroy_srq_in_bits {
4744 u8 opcode[0x10];
4745 u8 reserved_0[0x10];
4746
4747 u8 reserved_1[0x10];
4748 u8 op_mod[0x10];
4749
4750 u8 reserved_2[0x8];
4751 u8 srqn[0x18];
4752
4753 u8 reserved_3[0x20];
4754};
4755
4756struct mlx5_ifc_destroy_sq_out_bits {
4757 u8 status[0x8];
4758 u8 reserved_0[0x18];
4759
4760 u8 syndrome[0x20];
4761
4762 u8 reserved_1[0x40];
4763};
4764
4765struct mlx5_ifc_destroy_sq_in_bits {
4766 u8 opcode[0x10];
4767 u8 reserved_0[0x10];
4768
4769 u8 reserved_1[0x10];
4770 u8 op_mod[0x10];
4771
4772 u8 reserved_2[0x8];
4773 u8 sqn[0x18];
4774
4775 u8 reserved_3[0x20];
4776};
4777
4778struct mlx5_ifc_destroy_rqt_out_bits {
4779 u8 status[0x8];
4780 u8 reserved_0[0x18];
4781
4782 u8 syndrome[0x20];
4783
4784 u8 reserved_1[0x40];
4785};
4786
4787struct mlx5_ifc_destroy_rqt_in_bits {
4788 u8 opcode[0x10];
4789 u8 reserved_0[0x10];
4790
4791 u8 reserved_1[0x10];
4792 u8 op_mod[0x10];
4793
4794 u8 reserved_2[0x8];
4795 u8 rqtn[0x18];
4796
4797 u8 reserved_3[0x20];
4798};
4799
4800struct mlx5_ifc_destroy_rq_out_bits {
4801 u8 status[0x8];
4802 u8 reserved_0[0x18];
4803
4804 u8 syndrome[0x20];
4805
4806 u8 reserved_1[0x40];
4807};
4808
4809struct mlx5_ifc_destroy_rq_in_bits {
4810 u8 opcode[0x10];
4811 u8 reserved_0[0x10];
4812
4813 u8 reserved_1[0x10];
4814 u8 op_mod[0x10];
4815
4816 u8 reserved_2[0x8];
4817 u8 rqn[0x18];
4818
4819 u8 reserved_3[0x20];
4820};
4821
4822struct mlx5_ifc_destroy_rmp_out_bits {
4823 u8 status[0x8];
4824 u8 reserved_0[0x18];
4825
4826 u8 syndrome[0x20];
4827
4828 u8 reserved_1[0x40];
4829};
4830
4831struct mlx5_ifc_destroy_rmp_in_bits {
4832 u8 opcode[0x10];
4833 u8 reserved_0[0x10];
4834
4835 u8 reserved_1[0x10];
4836 u8 op_mod[0x10];
4837
4838 u8 reserved_2[0x8];
4839 u8 rmpn[0x18];
4840
4841 u8 reserved_3[0x20];
4842};
4843
4844struct mlx5_ifc_destroy_qp_out_bits {
4845 u8 status[0x8];
4846 u8 reserved_0[0x18];
4847
4848 u8 syndrome[0x20];
4849
4850 u8 reserved_1[0x40];
4851};
4852
4853struct mlx5_ifc_destroy_qp_in_bits {
4854 u8 opcode[0x10];
4855 u8 reserved_0[0x10];
4856
4857 u8 reserved_1[0x10];
4858 u8 op_mod[0x10];
4859
4860 u8 reserved_2[0x8];
4861 u8 qpn[0x18];
4862
4863 u8 reserved_3[0x20];
4864};
4865
4866struct mlx5_ifc_destroy_psv_out_bits {
4867 u8 status[0x8];
4868 u8 reserved_0[0x18];
4869
4870 u8 syndrome[0x20];
4871
4872 u8 reserved_1[0x40];
4873};
4874
4875struct mlx5_ifc_destroy_psv_in_bits {
4876 u8 opcode[0x10];
4877 u8 reserved_0[0x10];
4878
4879 u8 reserved_1[0x10];
4880 u8 op_mod[0x10];
4881
4882 u8 reserved_2[0x8];
4883 u8 psvn[0x18];
4884
4885 u8 reserved_3[0x20];
4886};
4887
4888struct mlx5_ifc_destroy_mkey_out_bits {
4889 u8 status[0x8];
4890 u8 reserved_0[0x18];
4891
4892 u8 syndrome[0x20];
4893
4894 u8 reserved_1[0x40];
4895};
4896
4897struct mlx5_ifc_destroy_mkey_in_bits {
4898 u8 opcode[0x10];
4899 u8 reserved_0[0x10];
4900
4901 u8 reserved_1[0x10];
4902 u8 op_mod[0x10];
4903
4904 u8 reserved_2[0x8];
4905 u8 mkey_index[0x18];
4906
4907 u8 reserved_3[0x20];
4908};
4909
4910struct mlx5_ifc_destroy_flow_table_out_bits {
4911 u8 status[0x8];
4912 u8 reserved_0[0x18];
4913
4914 u8 syndrome[0x20];
4915
4916 u8 reserved_1[0x40];
4917};
4918
4919struct mlx5_ifc_destroy_flow_table_in_bits {
4920 u8 opcode[0x10];
4921 u8 reserved_0[0x10];
4922
4923 u8 reserved_1[0x10];
4924 u8 op_mod[0x10];
4925
4926 u8 reserved_2[0x40];
4927
4928 u8 table_type[0x8];
4929 u8 reserved_3[0x18];
4930
4931 u8 reserved_4[0x8];
4932 u8 table_id[0x18];
4933
4934 u8 reserved_5[0x140];
4935};
4936
4937struct mlx5_ifc_destroy_flow_group_out_bits {
4938 u8 status[0x8];
4939 u8 reserved_0[0x18];
4940
4941 u8 syndrome[0x20];
4942
4943 u8 reserved_1[0x40];
4944};
4945
4946struct mlx5_ifc_destroy_flow_group_in_bits {
4947 u8 opcode[0x10];
4948 u8 reserved_0[0x10];
4949
4950 u8 reserved_1[0x10];
4951 u8 op_mod[0x10];
4952
4953 u8 reserved_2[0x40];
4954
4955 u8 table_type[0x8];
4956 u8 reserved_3[0x18];
4957
4958 u8 reserved_4[0x8];
4959 u8 table_id[0x18];
4960
4961 u8 group_id[0x20];
4962
4963 u8 reserved_5[0x120];
4964};
4965
4966struct mlx5_ifc_destroy_eq_out_bits {
4967 u8 status[0x8];
4968 u8 reserved_0[0x18];
4969
4970 u8 syndrome[0x20];
4971
4972 u8 reserved_1[0x40];
4973};
4974
4975struct mlx5_ifc_destroy_eq_in_bits {
4976 u8 opcode[0x10];
4977 u8 reserved_0[0x10];
4978
4979 u8 reserved_1[0x10];
4980 u8 op_mod[0x10];
4981
4982 u8 reserved_2[0x18];
4983 u8 eq_number[0x8];
4984
4985 u8 reserved_3[0x20];
4986};
4987
4988struct mlx5_ifc_destroy_dct_out_bits {
4989 u8 status[0x8];
4990 u8 reserved_0[0x18];
4991
4992 u8 syndrome[0x20];
4993
4994 u8 reserved_1[0x40];
4995};
4996
4997struct mlx5_ifc_destroy_dct_in_bits {
4998 u8 opcode[0x10];
4999 u8 reserved_0[0x10];
5000
5001 u8 reserved_1[0x10];
5002 u8 op_mod[0x10];
5003
5004 u8 reserved_2[0x8];
5005 u8 dctn[0x18];
5006
5007 u8 reserved_3[0x20];
5008};
5009
5010struct mlx5_ifc_destroy_cq_out_bits {
5011 u8 status[0x8];
5012 u8 reserved_0[0x18];
5013
5014 u8 syndrome[0x20];
5015
5016 u8 reserved_1[0x40];
5017};
5018
5019struct mlx5_ifc_destroy_cq_in_bits {
5020 u8 opcode[0x10];
5021 u8 reserved_0[0x10];
5022
5023 u8 reserved_1[0x10];
5024 u8 op_mod[0x10];
5025
5026 u8 reserved_2[0x8];
5027 u8 cqn[0x18];
5028
5029 u8 reserved_3[0x20];
5030};
5031
5032struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5033 u8 status[0x8];
5034 u8 reserved_0[0x18];
5035
5036 u8 syndrome[0x20];
5037
5038 u8 reserved_1[0x40];
5039};
5040
5041struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5042 u8 opcode[0x10];
5043 u8 reserved_0[0x10];
5044
5045 u8 reserved_1[0x10];
5046 u8 op_mod[0x10];
5047
5048 u8 reserved_2[0x20];
5049
5050 u8 reserved_3[0x10];
5051 u8 vxlan_udp_port[0x10];
5052};
5053
5054struct mlx5_ifc_delete_l2_table_entry_out_bits {
5055 u8 status[0x8];
5056 u8 reserved_0[0x18];
5057
5058 u8 syndrome[0x20];
5059
5060 u8 reserved_1[0x40];
5061};
5062
5063struct mlx5_ifc_delete_l2_table_entry_in_bits {
5064 u8 opcode[0x10];
5065 u8 reserved_0[0x10];
5066
5067 u8 reserved_1[0x10];
5068 u8 op_mod[0x10];
5069
5070 u8 reserved_2[0x60];
5071
5072 u8 reserved_3[0x8];
5073 u8 table_index[0x18];
5074
5075 u8 reserved_4[0x140];
5076};
5077
5078struct mlx5_ifc_delete_fte_out_bits {
5079 u8 status[0x8];
5080 u8 reserved_0[0x18];
5081
5082 u8 syndrome[0x20];
5083
5084 u8 reserved_1[0x40];
5085};
5086
5087struct mlx5_ifc_delete_fte_in_bits {
5088 u8 opcode[0x10];
5089 u8 reserved_0[0x10];
5090
5091 u8 reserved_1[0x10];
5092 u8 op_mod[0x10];
5093
5094 u8 reserved_2[0x40];
5095
5096 u8 table_type[0x8];
5097 u8 reserved_3[0x18];
5098
5099 u8 reserved_4[0x8];
5100 u8 table_id[0x18];
5101
5102 u8 reserved_5[0x40];
5103
5104 u8 flow_index[0x20];
5105
5106 u8 reserved_6[0xe0];
5107};
5108
5109struct mlx5_ifc_dealloc_xrcd_out_bits {
5110 u8 status[0x8];
5111 u8 reserved_0[0x18];
5112
5113 u8 syndrome[0x20];
5114
5115 u8 reserved_1[0x40];
5116};
5117
5118struct mlx5_ifc_dealloc_xrcd_in_bits {
5119 u8 opcode[0x10];
5120 u8 reserved_0[0x10];
5121
5122 u8 reserved_1[0x10];
5123 u8 op_mod[0x10];
5124
5125 u8 reserved_2[0x8];
5126 u8 xrcd[0x18];
5127
5128 u8 reserved_3[0x20];
5129};
5130
5131struct mlx5_ifc_dealloc_uar_out_bits {
5132 u8 status[0x8];
5133 u8 reserved_0[0x18];
5134
5135 u8 syndrome[0x20];
5136
5137 u8 reserved_1[0x40];
5138};
5139
5140struct mlx5_ifc_dealloc_uar_in_bits {
5141 u8 opcode[0x10];
5142 u8 reserved_0[0x10];
5143
5144 u8 reserved_1[0x10];
5145 u8 op_mod[0x10];
5146
5147 u8 reserved_2[0x8];
5148 u8 uar[0x18];
5149
5150 u8 reserved_3[0x20];
5151};
5152
5153struct mlx5_ifc_dealloc_transport_domain_out_bits {
5154 u8 status[0x8];
5155 u8 reserved_0[0x18];
5156
5157 u8 syndrome[0x20];
5158
5159 u8 reserved_1[0x40];
5160};
5161
5162struct mlx5_ifc_dealloc_transport_domain_in_bits {
5163 u8 opcode[0x10];
5164 u8 reserved_0[0x10];
5165
5166 u8 reserved_1[0x10];
5167 u8 op_mod[0x10];
5168
5169 u8 reserved_2[0x8];
5170 u8 transport_domain[0x18];
5171
5172 u8 reserved_3[0x20];
5173};
5174
5175struct mlx5_ifc_dealloc_q_counter_out_bits {
5176 u8 status[0x8];
5177 u8 reserved_0[0x18];
5178
5179 u8 syndrome[0x20];
5180
5181 u8 reserved_1[0x40];
5182};
5183
5184struct mlx5_ifc_dealloc_q_counter_in_bits {
5185 u8 opcode[0x10];
5186 u8 reserved_0[0x10];
5187
5188 u8 reserved_1[0x10];
5189 u8 op_mod[0x10];
5190
5191 u8 reserved_2[0x18];
5192 u8 counter_set_id[0x8];
5193
5194 u8 reserved_3[0x20];
5195};
5196
5197struct mlx5_ifc_dealloc_pd_out_bits {
5198 u8 status[0x8];
5199 u8 reserved_0[0x18];
5200
5201 u8 syndrome[0x20];
5202
5203 u8 reserved_1[0x40];
5204};
5205
5206struct mlx5_ifc_dealloc_pd_in_bits {
5207 u8 opcode[0x10];
5208 u8 reserved_0[0x10];
5209
5210 u8 reserved_1[0x10];
5211 u8 op_mod[0x10];
5212
5213 u8 reserved_2[0x8];
5214 u8 pd[0x18];
5215
5216 u8 reserved_3[0x20];
5217};
5218
5219struct mlx5_ifc_create_xrc_srq_out_bits {
5220 u8 status[0x8];
5221 u8 reserved_0[0x18];
5222
5223 u8 syndrome[0x20];
5224
5225 u8 reserved_1[0x8];
5226 u8 xrc_srqn[0x18];
5227
5228 u8 reserved_2[0x20];
5229};
5230
5231struct mlx5_ifc_create_xrc_srq_in_bits {
5232 u8 opcode[0x10];
5233 u8 reserved_0[0x10];
5234
5235 u8 reserved_1[0x10];
5236 u8 op_mod[0x10];
5237
5238 u8 reserved_2[0x40];
5239
5240 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5241
5242 u8 reserved_3[0x600];
5243
5244 u8 pas[0][0x40];
5245};
5246
5247struct mlx5_ifc_create_tis_out_bits {
5248 u8 status[0x8];
5249 u8 reserved_0[0x18];
5250
5251 u8 syndrome[0x20];
5252
5253 u8 reserved_1[0x8];
5254 u8 tisn[0x18];
5255
5256 u8 reserved_2[0x20];
5257};
5258
5259struct mlx5_ifc_create_tis_in_bits {
5260 u8 opcode[0x10];
5261 u8 reserved_0[0x10];
5262
5263 u8 reserved_1[0x10];
5264 u8 op_mod[0x10];
5265
5266 u8 reserved_2[0xc0];
5267
5268 struct mlx5_ifc_tisc_bits ctx;
5269};
5270
5271struct mlx5_ifc_create_tir_out_bits {
5272 u8 status[0x8];
5273 u8 reserved_0[0x18];
5274
5275 u8 syndrome[0x20];
5276
5277 u8 reserved_1[0x8];
5278 u8 tirn[0x18];
5279
5280 u8 reserved_2[0x20];
5281};
5282
5283struct mlx5_ifc_create_tir_in_bits {
5284 u8 opcode[0x10];
5285 u8 reserved_0[0x10];
5286
5287 u8 reserved_1[0x10];
5288 u8 op_mod[0x10];
5289
5290 u8 reserved_2[0xc0];
5291
5292 struct mlx5_ifc_tirc_bits ctx;
5293};
5294
5295struct mlx5_ifc_create_srq_out_bits {
5296 u8 status[0x8];
5297 u8 reserved_0[0x18];
5298
5299 u8 syndrome[0x20];
5300
5301 u8 reserved_1[0x8];
5302 u8 srqn[0x18];
5303
5304 u8 reserved_2[0x20];
5305};
5306
5307struct mlx5_ifc_create_srq_in_bits {
5308 u8 opcode[0x10];
5309 u8 reserved_0[0x10];
5310
5311 u8 reserved_1[0x10];
5312 u8 op_mod[0x10];
5313
5314 u8 reserved_2[0x40];
5315
5316 struct mlx5_ifc_srqc_bits srq_context_entry;
5317
5318 u8 reserved_3[0x600];
5319
5320 u8 pas[0][0x40];
5321};
5322
5323struct mlx5_ifc_create_sq_out_bits {
5324 u8 status[0x8];
5325 u8 reserved_0[0x18];
5326
5327 u8 syndrome[0x20];
5328
5329 u8 reserved_1[0x8];
5330 u8 sqn[0x18];
5331
5332 u8 reserved_2[0x20];
5333};
5334
5335struct mlx5_ifc_create_sq_in_bits {
5336 u8 opcode[0x10];
5337 u8 reserved_0[0x10];
5338
5339 u8 reserved_1[0x10];
5340 u8 op_mod[0x10];
5341
5342 u8 reserved_2[0xc0];
5343
5344 struct mlx5_ifc_sqc_bits ctx;
5345};
5346
5347struct mlx5_ifc_create_rqt_out_bits {
5348 u8 status[0x8];
5349 u8 reserved_0[0x18];
5350
5351 u8 syndrome[0x20];
5352
5353 u8 reserved_1[0x8];
5354 u8 rqtn[0x18];
5355
5356 u8 reserved_2[0x20];
5357};
5358
5359struct mlx5_ifc_create_rqt_in_bits {
5360 u8 opcode[0x10];
5361 u8 reserved_0[0x10];
5362
5363 u8 reserved_1[0x10];
5364 u8 op_mod[0x10];
5365
5366 u8 reserved_2[0xc0];
5367
5368 struct mlx5_ifc_rqtc_bits rqt_context;
5369};
5370
5371struct mlx5_ifc_create_rq_out_bits {
5372 u8 status[0x8];
5373 u8 reserved_0[0x18];
5374
5375 u8 syndrome[0x20];
5376
5377 u8 reserved_1[0x8];
5378 u8 rqn[0x18];
5379
5380 u8 reserved_2[0x20];
5381};
5382
5383struct mlx5_ifc_create_rq_in_bits {
5384 u8 opcode[0x10];
5385 u8 reserved_0[0x10];
5386
5387 u8 reserved_1[0x10];
5388 u8 op_mod[0x10];
5389
5390 u8 reserved_2[0xc0];
5391
5392 struct mlx5_ifc_rqc_bits ctx;
5393};
5394
5395struct mlx5_ifc_create_rmp_out_bits {
5396 u8 status[0x8];
5397 u8 reserved_0[0x18];
5398
5399 u8 syndrome[0x20];
5400
5401 u8 reserved_1[0x8];
5402 u8 rmpn[0x18];
5403
5404 u8 reserved_2[0x20];
5405};
5406
5407struct mlx5_ifc_create_rmp_in_bits {
5408 u8 opcode[0x10];
5409 u8 reserved_0[0x10];
5410
5411 u8 reserved_1[0x10];
5412 u8 op_mod[0x10];
5413
5414 u8 reserved_2[0xc0];
5415
5416 struct mlx5_ifc_rmpc_bits ctx;
5417};
5418
5419struct mlx5_ifc_create_qp_out_bits {
5420 u8 status[0x8];
5421 u8 reserved_0[0x18];
5422
5423 u8 syndrome[0x20];
5424
5425 u8 reserved_1[0x8];
5426 u8 qpn[0x18];
5427
5428 u8 reserved_2[0x20];
5429};
5430
5431struct mlx5_ifc_create_qp_in_bits {
5432 u8 opcode[0x10];
5433 u8 reserved_0[0x10];
5434
5435 u8 reserved_1[0x10];
5436 u8 op_mod[0x10];
5437
5438 u8 reserved_2[0x40];
5439
5440 u8 opt_param_mask[0x20];
5441
5442 u8 reserved_3[0x20];
5443
5444 struct mlx5_ifc_qpc_bits qpc;
5445
5446 u8 reserved_4[0x80];
5447
5448 u8 pas[0][0x40];
5449};
5450
5451struct mlx5_ifc_create_psv_out_bits {
5452 u8 status[0x8];
5453 u8 reserved_0[0x18];
5454
5455 u8 syndrome[0x20];
5456
5457 u8 reserved_1[0x40];
5458
5459 u8 reserved_2[0x8];
5460 u8 psv0_index[0x18];
5461
5462 u8 reserved_3[0x8];
5463 u8 psv1_index[0x18];
5464
5465 u8 reserved_4[0x8];
5466 u8 psv2_index[0x18];
5467
5468 u8 reserved_5[0x8];
5469 u8 psv3_index[0x18];
5470};
5471
5472struct mlx5_ifc_create_psv_in_bits {
5473 u8 opcode[0x10];
5474 u8 reserved_0[0x10];
5475
5476 u8 reserved_1[0x10];
5477 u8 op_mod[0x10];
5478
5479 u8 num_psv[0x4];
5480 u8 reserved_2[0x4];
5481 u8 pd[0x18];
5482
5483 u8 reserved_3[0x20];
5484};
5485
5486struct mlx5_ifc_create_mkey_out_bits {
5487 u8 status[0x8];
5488 u8 reserved_0[0x18];
5489
5490 u8 syndrome[0x20];
5491
5492 u8 reserved_1[0x8];
5493 u8 mkey_index[0x18];
5494
5495 u8 reserved_2[0x20];
5496};
5497
5498struct mlx5_ifc_create_mkey_in_bits {
5499 u8 opcode[0x10];
5500 u8 reserved_0[0x10];
5501
5502 u8 reserved_1[0x10];
5503 u8 op_mod[0x10];
5504
5505 u8 reserved_2[0x20];
5506
5507 u8 pg_access[0x1];
5508 u8 reserved_3[0x1f];
5509
5510 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5511
5512 u8 reserved_4[0x80];
5513
5514 u8 translations_octword_actual_size[0x20];
5515
5516 u8 reserved_5[0x560];
5517
5518 u8 klm_pas_mtt[0][0x20];
5519};
5520
5521struct mlx5_ifc_create_flow_table_out_bits {
5522 u8 status[0x8];
5523 u8 reserved_0[0x18];
5524
5525 u8 syndrome[0x20];
5526
5527 u8 reserved_1[0x8];
5528 u8 table_id[0x18];
5529
5530 u8 reserved_2[0x20];
5531};
5532
5533struct mlx5_ifc_create_flow_table_in_bits {
5534 u8 opcode[0x10];
5535 u8 reserved_0[0x10];
5536
5537 u8 reserved_1[0x10];
5538 u8 op_mod[0x10];
5539
5540 u8 reserved_2[0x40];
5541
5542 u8 table_type[0x8];
5543 u8 reserved_3[0x18];
5544
5545 u8 reserved_4[0x20];
5546
5547 u8 reserved_5[0x8];
5548 u8 level[0x8];
5549 u8 reserved_6[0x8];
5550 u8 log_size[0x8];
5551
5552 u8 reserved_7[0x120];
5553};
5554
5555struct mlx5_ifc_create_flow_group_out_bits {
5556 u8 status[0x8];
5557 u8 reserved_0[0x18];
5558
5559 u8 syndrome[0x20];
5560
5561 u8 reserved_1[0x8];
5562 u8 group_id[0x18];
5563
5564 u8 reserved_2[0x20];
5565};
5566
5567enum {
5568 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5569 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5570 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5571};
5572
5573struct mlx5_ifc_create_flow_group_in_bits {
5574 u8 opcode[0x10];
5575 u8 reserved_0[0x10];
5576
5577 u8 reserved_1[0x10];
5578 u8 op_mod[0x10];
5579
5580 u8 reserved_2[0x40];
5581
5582 u8 table_type[0x8];
5583 u8 reserved_3[0x18];
5584
5585 u8 reserved_4[0x8];
5586 u8 table_id[0x18];
5587
5588 u8 reserved_5[0x20];
5589
5590 u8 start_flow_index[0x20];
5591
5592 u8 reserved_6[0x20];
5593
5594 u8 end_flow_index[0x20];
5595
5596 u8 reserved_7[0xa0];
5597
5598 u8 reserved_8[0x18];
5599 u8 match_criteria_enable[0x8];
5600
5601 struct mlx5_ifc_fte_match_param_bits match_criteria;
5602
5603 u8 reserved_9[0xe00];
5604};
5605
5606struct mlx5_ifc_create_eq_out_bits {
5607 u8 status[0x8];
5608 u8 reserved_0[0x18];
5609
5610 u8 syndrome[0x20];
5611
5612 u8 reserved_1[0x18];
5613 u8 eq_number[0x8];
5614
5615 u8 reserved_2[0x20];
5616};
5617
5618struct mlx5_ifc_create_eq_in_bits {
5619 u8 opcode[0x10];
5620 u8 reserved_0[0x10];
5621
5622 u8 reserved_1[0x10];
5623 u8 op_mod[0x10];
5624
5625 u8 reserved_2[0x40];
5626
5627 struct mlx5_ifc_eqc_bits eq_context_entry;
5628
5629 u8 reserved_3[0x40];
5630
5631 u8 event_bitmask[0x40];
5632
5633 u8 reserved_4[0x580];
5634
5635 u8 pas[0][0x40];
5636};
5637
5638struct mlx5_ifc_create_dct_out_bits {
5639 u8 status[0x8];
5640 u8 reserved_0[0x18];
5641
5642 u8 syndrome[0x20];
5643
5644 u8 reserved_1[0x8];
5645 u8 dctn[0x18];
5646
5647 u8 reserved_2[0x20];
5648};
5649
5650struct mlx5_ifc_create_dct_in_bits {
5651 u8 opcode[0x10];
5652 u8 reserved_0[0x10];
5653
5654 u8 reserved_1[0x10];
5655 u8 op_mod[0x10];
5656
5657 u8 reserved_2[0x40];
5658
5659 struct mlx5_ifc_dctc_bits dct_context_entry;
5660
5661 u8 reserved_3[0x180];
5662};
5663
5664struct mlx5_ifc_create_cq_out_bits {
5665 u8 status[0x8];
5666 u8 reserved_0[0x18];
5667
5668 u8 syndrome[0x20];
5669
5670 u8 reserved_1[0x8];
5671 u8 cqn[0x18];
5672
5673 u8 reserved_2[0x20];
5674};
5675
5676struct mlx5_ifc_create_cq_in_bits {
5677 u8 opcode[0x10];
5678 u8 reserved_0[0x10];
5679
5680 u8 reserved_1[0x10];
5681 u8 op_mod[0x10];
5682
5683 u8 reserved_2[0x40];
5684
5685 struct mlx5_ifc_cqc_bits cq_context;
5686
5687 u8 reserved_3[0x600];
5688
5689 u8 pas[0][0x40];
5690};
5691
5692struct mlx5_ifc_config_int_moderation_out_bits {
5693 u8 status[0x8];
5694 u8 reserved_0[0x18];
5695
5696 u8 syndrome[0x20];
5697
5698 u8 reserved_1[0x4];
5699 u8 min_delay[0xc];
5700 u8 int_vector[0x10];
5701
5702 u8 reserved_2[0x20];
5703};
5704
5705enum {
5706 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5707 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5708};
5709
5710struct mlx5_ifc_config_int_moderation_in_bits {
5711 u8 opcode[0x10];
5712 u8 reserved_0[0x10];
5713
5714 u8 reserved_1[0x10];
5715 u8 op_mod[0x10];
5716
5717 u8 reserved_2[0x4];
5718 u8 min_delay[0xc];
5719 u8 int_vector[0x10];
5720
5721 u8 reserved_3[0x20];
5722};
5723
5724struct mlx5_ifc_attach_to_mcg_out_bits {
5725 u8 status[0x8];
5726 u8 reserved_0[0x18];
5727
5728 u8 syndrome[0x20];
5729
5730 u8 reserved_1[0x40];
5731};
5732
5733struct mlx5_ifc_attach_to_mcg_in_bits {
5734 u8 opcode[0x10];
5735 u8 reserved_0[0x10];
5736
5737 u8 reserved_1[0x10];
5738 u8 op_mod[0x10];
5739
5740 u8 reserved_2[0x8];
5741 u8 qpn[0x18];
5742
5743 u8 reserved_3[0x20];
5744
5745 u8 multicast_gid[16][0x8];
5746};
5747
5748struct mlx5_ifc_arm_xrc_srq_out_bits {
5749 u8 status[0x8];
5750 u8 reserved_0[0x18];
5751
5752 u8 syndrome[0x20];
5753
5754 u8 reserved_1[0x40];
5755};
5756
5757enum {
5758 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5759};
5760
5761struct mlx5_ifc_arm_xrc_srq_in_bits {
5762 u8 opcode[0x10];
5763 u8 reserved_0[0x10];
5764
5765 u8 reserved_1[0x10];
5766 u8 op_mod[0x10];
5767
5768 u8 reserved_2[0x8];
5769 u8 xrc_srqn[0x18];
5770
5771 u8 reserved_3[0x10];
5772 u8 lwm[0x10];
5773};
5774
5775struct mlx5_ifc_arm_rq_out_bits {
5776 u8 status[0x8];
5777 u8 reserved_0[0x18];
5778
5779 u8 syndrome[0x20];
5780
5781 u8 reserved_1[0x40];
5782};
5783
5784enum {
5785 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5786};
5787
5788struct mlx5_ifc_arm_rq_in_bits {
5789 u8 opcode[0x10];
5790 u8 reserved_0[0x10];
5791
5792 u8 reserved_1[0x10];
5793 u8 op_mod[0x10];
5794
5795 u8 reserved_2[0x8];
5796 u8 srq_number[0x18];
5797
5798 u8 reserved_3[0x10];
5799 u8 lwm[0x10];
5800};
5801
5802struct mlx5_ifc_arm_dct_out_bits {
5803 u8 status[0x8];
5804 u8 reserved_0[0x18];
5805
5806 u8 syndrome[0x20];
5807
5808 u8 reserved_1[0x40];
5809};
5810
5811struct mlx5_ifc_arm_dct_in_bits {
5812 u8 opcode[0x10];
5813 u8 reserved_0[0x10];
5814
5815 u8 reserved_1[0x10];
5816 u8 op_mod[0x10];
5817
5818 u8 reserved_2[0x8];
5819 u8 dct_number[0x18];
5820
5821 u8 reserved_3[0x20];
5822};
5823
5824struct mlx5_ifc_alloc_xrcd_out_bits {
5825 u8 status[0x8];
5826 u8 reserved_0[0x18];
5827
5828 u8 syndrome[0x20];
5829
5830 u8 reserved_1[0x8];
5831 u8 xrcd[0x18];
5832
5833 u8 reserved_2[0x20];
5834};
5835
5836struct mlx5_ifc_alloc_xrcd_in_bits {
5837 u8 opcode[0x10];
5838 u8 reserved_0[0x10];
5839
5840 u8 reserved_1[0x10];
5841 u8 op_mod[0x10];
5842
5843 u8 reserved_2[0x40];
5844};
5845
5846struct mlx5_ifc_alloc_uar_out_bits {
5847 u8 status[0x8];
5848 u8 reserved_0[0x18];
5849
5850 u8 syndrome[0x20];
5851
5852 u8 reserved_1[0x8];
5853 u8 uar[0x18];
5854
5855 u8 reserved_2[0x20];
5856};
5857
5858struct mlx5_ifc_alloc_uar_in_bits {
5859 u8 opcode[0x10];
5860 u8 reserved_0[0x10];
5861
5862 u8 reserved_1[0x10];
5863 u8 op_mod[0x10];
5864
5865 u8 reserved_2[0x40];
5866};
5867
5868struct mlx5_ifc_alloc_transport_domain_out_bits {
5869 u8 status[0x8];
5870 u8 reserved_0[0x18];
5871
5872 u8 syndrome[0x20];
5873
5874 u8 reserved_1[0x8];
5875 u8 transport_domain[0x18];
5876
5877 u8 reserved_2[0x20];
5878};
5879
5880struct mlx5_ifc_alloc_transport_domain_in_bits {
5881 u8 opcode[0x10];
5882 u8 reserved_0[0x10];
5883
5884 u8 reserved_1[0x10];
5885 u8 op_mod[0x10];
5886
5887 u8 reserved_2[0x40];
5888};
5889
5890struct mlx5_ifc_alloc_q_counter_out_bits {
5891 u8 status[0x8];
5892 u8 reserved_0[0x18];
5893
5894 u8 syndrome[0x20];
5895
5896 u8 reserved_1[0x18];
5897 u8 counter_set_id[0x8];
5898
5899 u8 reserved_2[0x20];
5900};
5901
5902struct mlx5_ifc_alloc_q_counter_in_bits {
5903 u8 opcode[0x10];
5904 u8 reserved_0[0x10];
5905
5906 u8 reserved_1[0x10];
5907 u8 op_mod[0x10];
5908
5909 u8 reserved_2[0x40];
5910};
5911
5912struct mlx5_ifc_alloc_pd_out_bits {
5913 u8 status[0x8];
5914 u8 reserved_0[0x18];
5915
5916 u8 syndrome[0x20];
5917
5918 u8 reserved_1[0x8];
5919 u8 pd[0x18];
5920
5921 u8 reserved_2[0x20];
5922};
5923
5924struct mlx5_ifc_alloc_pd_in_bits {
5925 u8 opcode[0x10];
5926 u8 reserved_0[0x10];
5927
5928 u8 reserved_1[0x10];
5929 u8 op_mod[0x10];
5930
5931 u8 reserved_2[0x40];
5932};
5933
5934struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5935 u8 status[0x8];
5936 u8 reserved_0[0x18];
5937
5938 u8 syndrome[0x20];
5939
5940 u8 reserved_1[0x40];
5941};
5942
5943struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5944 u8 opcode[0x10];
5945 u8 reserved_0[0x10];
5946
5947 u8 reserved_1[0x10];
5948 u8 op_mod[0x10];
5949
5950 u8 reserved_2[0x20];
5951
5952 u8 reserved_3[0x10];
5953 u8 vxlan_udp_port[0x10];
5954};
5955
5956struct mlx5_ifc_access_register_out_bits {
5957 u8 status[0x8];
5958 u8 reserved_0[0x18];
5959
5960 u8 syndrome[0x20];
5961
5962 u8 reserved_1[0x40];
5963
5964 u8 register_data[0][0x20];
5965};
5966
5967enum {
5968 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5969 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5970};
5971
5972struct mlx5_ifc_access_register_in_bits {
5973 u8 opcode[0x10];
5974 u8 reserved_0[0x10];
5975
5976 u8 reserved_1[0x10];
5977 u8 op_mod[0x10];
5978
5979 u8 reserved_2[0x10];
5980 u8 register_id[0x10];
5981
5982 u8 argument[0x20];
5983
5984 u8 register_data[0][0x20];
5985};
5986
5987struct mlx5_ifc_sltp_reg_bits {
5988 u8 status[0x4];
5989 u8 version[0x4];
5990 u8 local_port[0x8];
5991 u8 pnat[0x2];
5992 u8 reserved_0[0x2];
5993 u8 lane[0x4];
5994 u8 reserved_1[0x8];
5995
5996 u8 reserved_2[0x20];
5997
5998 u8 reserved_3[0x7];
5999 u8 polarity[0x1];
6000 u8 ob_tap0[0x8];
6001 u8 ob_tap1[0x8];
6002 u8 ob_tap2[0x8];
6003
6004 u8 reserved_4[0xc];
6005 u8 ob_preemp_mode[0x4];
6006 u8 ob_reg[0x8];
6007 u8 ob_bias[0x8];
6008
6009 u8 reserved_5[0x20];
6010};
6011
6012struct mlx5_ifc_slrg_reg_bits {
6013 u8 status[0x4];
6014 u8 version[0x4];
6015 u8 local_port[0x8];
6016 u8 pnat[0x2];
6017 u8 reserved_0[0x2];
6018 u8 lane[0x4];
6019 u8 reserved_1[0x8];
6020
6021 u8 time_to_link_up[0x10];
6022 u8 reserved_2[0xc];
6023 u8 grade_lane_speed[0x4];
6024
6025 u8 grade_version[0x8];
6026 u8 grade[0x18];
6027
6028 u8 reserved_3[0x4];
6029 u8 height_grade_type[0x4];
6030 u8 height_grade[0x18];
6031
6032 u8 height_dz[0x10];
6033 u8 height_dv[0x10];
6034
6035 u8 reserved_4[0x10];
6036 u8 height_sigma[0x10];
6037
6038 u8 reserved_5[0x20];
6039
6040 u8 reserved_6[0x4];
6041 u8 phase_grade_type[0x4];
6042 u8 phase_grade[0x18];
6043
6044 u8 reserved_7[0x8];
6045 u8 phase_eo_pos[0x8];
6046 u8 reserved_8[0x8];
6047 u8 phase_eo_neg[0x8];
6048
6049 u8 ffe_set_tested[0x10];
6050 u8 test_errors_per_lane[0x10];
6051};
6052
6053struct mlx5_ifc_pvlc_reg_bits {
6054 u8 reserved_0[0x8];
6055 u8 local_port[0x8];
6056 u8 reserved_1[0x10];
6057
6058 u8 reserved_2[0x1c];
6059 u8 vl_hw_cap[0x4];
6060
6061 u8 reserved_3[0x1c];
6062 u8 vl_admin[0x4];
6063
6064 u8 reserved_4[0x1c];
6065 u8 vl_operational[0x4];
6066};
6067
6068struct mlx5_ifc_pude_reg_bits {
6069 u8 swid[0x8];
6070 u8 local_port[0x8];
6071 u8 reserved_0[0x4];
6072 u8 admin_status[0x4];
6073 u8 reserved_1[0x4];
6074 u8 oper_status[0x4];
6075
6076 u8 reserved_2[0x60];
6077};
6078
6079struct mlx5_ifc_ptys_reg_bits {
6080 u8 reserved_0[0x8];
6081 u8 local_port[0x8];
6082 u8 reserved_1[0xd];
6083 u8 proto_mask[0x3];
6084
6085 u8 reserved_2[0x40];
6086
6087 u8 eth_proto_capability[0x20];
6088
6089 u8 ib_link_width_capability[0x10];
6090 u8 ib_proto_capability[0x10];
6091
6092 u8 reserved_3[0x20];
6093
6094 u8 eth_proto_admin[0x20];
6095
6096 u8 ib_link_width_admin[0x10];
6097 u8 ib_proto_admin[0x10];
6098
6099 u8 reserved_4[0x20];
6100
6101 u8 eth_proto_oper[0x20];
6102
6103 u8 ib_link_width_oper[0x10];
6104 u8 ib_proto_oper[0x10];
6105
6106 u8 reserved_5[0x20];
6107
6108 u8 eth_proto_lp_advertise[0x20];
6109
6110 u8 reserved_6[0x60];
6111};
6112
6113struct mlx5_ifc_ptas_reg_bits {
6114 u8 reserved_0[0x20];
6115
6116 u8 algorithm_options[0x10];
6117 u8 reserved_1[0x4];
6118 u8 repetitions_mode[0x4];
6119 u8 num_of_repetitions[0x8];
6120
6121 u8 grade_version[0x8];
6122 u8 height_grade_type[0x4];
6123 u8 phase_grade_type[0x4];
6124 u8 height_grade_weight[0x8];
6125 u8 phase_grade_weight[0x8];
6126
6127 u8 gisim_measure_bits[0x10];
6128 u8 adaptive_tap_measure_bits[0x10];
6129
6130 u8 ber_bath_high_error_threshold[0x10];
6131 u8 ber_bath_mid_error_threshold[0x10];
6132
6133 u8 ber_bath_low_error_threshold[0x10];
6134 u8 one_ratio_high_threshold[0x10];
6135
6136 u8 one_ratio_high_mid_threshold[0x10];
6137 u8 one_ratio_low_mid_threshold[0x10];
6138
6139 u8 one_ratio_low_threshold[0x10];
6140 u8 ndeo_error_threshold[0x10];
6141
6142 u8 mixer_offset_step_size[0x10];
6143 u8 reserved_2[0x8];
6144 u8 mix90_phase_for_voltage_bath[0x8];
6145
6146 u8 mixer_offset_start[0x10];
6147 u8 mixer_offset_end[0x10];
6148
6149 u8 reserved_3[0x15];
6150 u8 ber_test_time[0xb];
6151};
6152
6153struct mlx5_ifc_pspa_reg_bits {
6154 u8 swid[0x8];
6155 u8 local_port[0x8];
6156 u8 sub_port[0x8];
6157 u8 reserved_0[0x8];
6158
6159 u8 reserved_1[0x20];
6160};
6161
6162struct mlx5_ifc_pqdr_reg_bits {
6163 u8 reserved_0[0x8];
6164 u8 local_port[0x8];
6165 u8 reserved_1[0x5];
6166 u8 prio[0x3];
6167 u8 reserved_2[0x6];
6168 u8 mode[0x2];
6169
6170 u8 reserved_3[0x20];
6171
6172 u8 reserved_4[0x10];
6173 u8 min_threshold[0x10];
6174
6175 u8 reserved_5[0x10];
6176 u8 max_threshold[0x10];
6177
6178 u8 reserved_6[0x10];
6179 u8 mark_probability_denominator[0x10];
6180
6181 u8 reserved_7[0x60];
6182};
6183
6184struct mlx5_ifc_ppsc_reg_bits {
6185 u8 reserved_0[0x8];
6186 u8 local_port[0x8];
6187 u8 reserved_1[0x10];
6188
6189 u8 reserved_2[0x60];
6190
6191 u8 reserved_3[0x1c];
6192 u8 wrps_admin[0x4];
6193
6194 u8 reserved_4[0x1c];
6195 u8 wrps_status[0x4];
6196
6197 u8 reserved_5[0x8];
6198 u8 up_threshold[0x8];
6199 u8 reserved_6[0x8];
6200 u8 down_threshold[0x8];
6201
6202 u8 reserved_7[0x20];
6203
6204 u8 reserved_8[0x1c];
6205 u8 srps_admin[0x4];
6206
6207 u8 reserved_9[0x1c];
6208 u8 srps_status[0x4];
6209
6210 u8 reserved_10[0x40];
6211};
6212
6213struct mlx5_ifc_pplr_reg_bits {
6214 u8 reserved_0[0x8];
6215 u8 local_port[0x8];
6216 u8 reserved_1[0x10];
6217
6218 u8 reserved_2[0x8];
6219 u8 lb_cap[0x8];
6220 u8 reserved_3[0x8];
6221 u8 lb_en[0x8];
6222};
6223
6224struct mlx5_ifc_pplm_reg_bits {
6225 u8 reserved_0[0x8];
6226 u8 local_port[0x8];
6227 u8 reserved_1[0x10];
6228
6229 u8 reserved_2[0x20];
6230
6231 u8 port_profile_mode[0x8];
6232 u8 static_port_profile[0x8];
6233 u8 active_port_profile[0x8];
6234 u8 reserved_3[0x8];
6235
6236 u8 retransmission_active[0x8];
6237 u8 fec_mode_active[0x18];
6238
6239 u8 reserved_4[0x20];
6240};
6241
6242struct mlx5_ifc_ppcnt_reg_bits {
6243 u8 swid[0x8];
6244 u8 local_port[0x8];
6245 u8 pnat[0x2];
6246 u8 reserved_0[0x8];
6247 u8 grp[0x6];
6248
6249 u8 clr[0x1];
6250 u8 reserved_1[0x1c];
6251 u8 prio_tc[0x3];
6252
6253 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6254};
6255
6256struct mlx5_ifc_ppad_reg_bits {
6257 u8 reserved_0[0x3];
6258 u8 single_mac[0x1];
6259 u8 reserved_1[0x4];
6260 u8 local_port[0x8];
6261 u8 mac_47_32[0x10];
6262
6263 u8 mac_31_0[0x20];
6264
6265 u8 reserved_2[0x40];
6266};
6267
6268struct mlx5_ifc_pmtu_reg_bits {
6269 u8 reserved_0[0x8];
6270 u8 local_port[0x8];
6271 u8 reserved_1[0x10];
6272
6273 u8 max_mtu[0x10];
6274 u8 reserved_2[0x10];
6275
6276 u8 admin_mtu[0x10];
6277 u8 reserved_3[0x10];
6278
6279 u8 oper_mtu[0x10];
6280 u8 reserved_4[0x10];
6281};
6282
6283struct mlx5_ifc_pmpr_reg_bits {
6284 u8 reserved_0[0x8];
6285 u8 module[0x8];
6286 u8 reserved_1[0x10];
6287
6288 u8 reserved_2[0x18];
6289 u8 attenuation_5g[0x8];
6290
6291 u8 reserved_3[0x18];
6292 u8 attenuation_7g[0x8];
6293
6294 u8 reserved_4[0x18];
6295 u8 attenuation_12g[0x8];
6296};
6297
6298struct mlx5_ifc_pmpe_reg_bits {
6299 u8 reserved_0[0x8];
6300 u8 module[0x8];
6301 u8 reserved_1[0xc];
6302 u8 module_status[0x4];
6303
6304 u8 reserved_2[0x60];
6305};
6306
6307struct mlx5_ifc_pmpc_reg_bits {
6308 u8 module_state_updated[32][0x8];
6309};
6310
6311struct mlx5_ifc_pmlpn_reg_bits {
6312 u8 reserved_0[0x4];
6313 u8 mlpn_status[0x4];
6314 u8 local_port[0x8];
6315 u8 reserved_1[0x10];
6316
6317 u8 e[0x1];
6318 u8 reserved_2[0x1f];
6319};
6320
6321struct mlx5_ifc_pmlp_reg_bits {
6322 u8 rxtx[0x1];
6323 u8 reserved_0[0x7];
6324 u8 local_port[0x8];
6325 u8 reserved_1[0x8];
6326 u8 width[0x8];
6327
6328 u8 lane0_module_mapping[0x20];
6329
6330 u8 lane1_module_mapping[0x20];
6331
6332 u8 lane2_module_mapping[0x20];
6333
6334 u8 lane3_module_mapping[0x20];
6335
6336 u8 reserved_2[0x160];
6337};
6338
6339struct mlx5_ifc_pmaos_reg_bits {
6340 u8 reserved_0[0x8];
6341 u8 module[0x8];
6342 u8 reserved_1[0x4];
6343 u8 admin_status[0x4];
6344 u8 reserved_2[0x4];
6345 u8 oper_status[0x4];
6346
6347 u8 ase[0x1];
6348 u8 ee[0x1];
6349 u8 reserved_3[0x1c];
6350 u8 e[0x2];
6351
6352 u8 reserved_4[0x40];
6353};
6354
6355struct mlx5_ifc_plpc_reg_bits {
6356 u8 reserved_0[0x4];
6357 u8 profile_id[0xc];
6358 u8 reserved_1[0x4];
6359 u8 proto_mask[0x4];
6360 u8 reserved_2[0x8];
6361
6362 u8 reserved_3[0x10];
6363 u8 lane_speed[0x10];
6364
6365 u8 reserved_4[0x17];
6366 u8 lpbf[0x1];
6367 u8 fec_mode_policy[0x8];
6368
6369 u8 retransmission_capability[0x8];
6370 u8 fec_mode_capability[0x18];
6371
6372 u8 retransmission_support_admin[0x8];
6373 u8 fec_mode_support_admin[0x18];
6374
6375 u8 retransmission_request_admin[0x8];
6376 u8 fec_mode_request_admin[0x18];
6377
6378 u8 reserved_5[0x80];
6379};
6380
6381struct mlx5_ifc_plib_reg_bits {
6382 u8 reserved_0[0x8];
6383 u8 local_port[0x8];
6384 u8 reserved_1[0x8];
6385 u8 ib_port[0x8];
6386
6387 u8 reserved_2[0x60];
6388};
6389
6390struct mlx5_ifc_plbf_reg_bits {
6391 u8 reserved_0[0x8];
6392 u8 local_port[0x8];
6393 u8 reserved_1[0xd];
6394 u8 lbf_mode[0x3];
6395
6396 u8 reserved_2[0x20];
6397};
6398
6399struct mlx5_ifc_pipg_reg_bits {
6400 u8 reserved_0[0x8];
6401 u8 local_port[0x8];
6402 u8 reserved_1[0x10];
6403
6404 u8 dic[0x1];
6405 u8 reserved_2[0x19];
6406 u8 ipg[0x4];
6407 u8 reserved_3[0x2];
6408};
6409
6410struct mlx5_ifc_pifr_reg_bits {
6411 u8 reserved_0[0x8];
6412 u8 local_port[0x8];
6413 u8 reserved_1[0x10];
6414
6415 u8 reserved_2[0xe0];
6416
6417 u8 port_filter[8][0x20];
6418
6419 u8 port_filter_update_en[8][0x20];
6420};
6421
6422struct mlx5_ifc_pfcc_reg_bits {
6423 u8 reserved_0[0x8];
6424 u8 local_port[0x8];
6425 u8 reserved_1[0x10];
6426
6427 u8 ppan[0x4];
6428 u8 reserved_2[0x4];
6429 u8 prio_mask_tx[0x8];
6430 u8 reserved_3[0x8];
6431 u8 prio_mask_rx[0x8];
6432
6433 u8 pptx[0x1];
6434 u8 aptx[0x1];
6435 u8 reserved_4[0x6];
6436 u8 pfctx[0x8];
6437 u8 reserved_5[0x10];
6438
6439 u8 pprx[0x1];
6440 u8 aprx[0x1];
6441 u8 reserved_6[0x6];
6442 u8 pfcrx[0x8];
6443 u8 reserved_7[0x10];
6444
6445 u8 reserved_8[0x80];
6446};
6447
6448struct mlx5_ifc_pelc_reg_bits {
6449 u8 op[0x4];
6450 u8 reserved_0[0x4];
6451 u8 local_port[0x8];
6452 u8 reserved_1[0x10];
6453
6454 u8 op_admin[0x8];
6455 u8 op_capability[0x8];
6456 u8 op_request[0x8];
6457 u8 op_active[0x8];
6458
6459 u8 admin[0x40];
6460
6461 u8 capability[0x40];
6462
6463 u8 request[0x40];
6464
6465 u8 active[0x40];
6466
6467 u8 reserved_2[0x80];
6468};
6469
6470struct mlx5_ifc_peir_reg_bits {
6471 u8 reserved_0[0x8];
6472 u8 local_port[0x8];
6473 u8 reserved_1[0x10];
6474
6475 u8 reserved_2[0xc];
6476 u8 error_count[0x4];
6477 u8 reserved_3[0x10];
6478
6479 u8 reserved_4[0xc];
6480 u8 lane[0x4];
6481 u8 reserved_5[0x8];
6482 u8 error_type[0x8];
6483};
6484
6485struct mlx5_ifc_pcap_reg_bits {
6486 u8 reserved_0[0x8];
6487 u8 local_port[0x8];
6488 u8 reserved_1[0x10];
6489
6490 u8 port_capability_mask[4][0x20];
6491};
6492
6493struct mlx5_ifc_paos_reg_bits {
6494 u8 swid[0x8];
6495 u8 local_port[0x8];
6496 u8 reserved_0[0x4];
6497 u8 admin_status[0x4];
6498 u8 reserved_1[0x4];
6499 u8 oper_status[0x4];
6500
6501 u8 ase[0x1];
6502 u8 ee[0x1];
6503 u8 reserved_2[0x1c];
6504 u8 e[0x2];
6505
6506 u8 reserved_3[0x40];
6507};
6508
6509struct mlx5_ifc_pamp_reg_bits {
6510 u8 reserved_0[0x8];
6511 u8 opamp_group[0x8];
6512 u8 reserved_1[0xc];
6513 u8 opamp_group_type[0x4];
6514
6515 u8 start_index[0x10];
6516 u8 reserved_2[0x4];
6517 u8 num_of_indices[0xc];
6518
6519 u8 index_data[18][0x10];
6520};
6521
6522struct mlx5_ifc_lane_2_module_mapping_bits {
6523 u8 reserved_0[0x6];
6524 u8 rx_lane[0x2];
6525 u8 reserved_1[0x6];
6526 u8 tx_lane[0x2];
6527 u8 reserved_2[0x8];
6528 u8 module[0x8];
6529};
6530
6531struct mlx5_ifc_bufferx_reg_bits {
6532 u8 reserved_0[0x6];
6533 u8 lossy[0x1];
6534 u8 epsb[0x1];
6535 u8 reserved_1[0xc];
6536 u8 size[0xc];
6537
6538 u8 xoff_threshold[0x10];
6539 u8 xon_threshold[0x10];
6540};
6541
6542struct mlx5_ifc_set_node_in_bits {
6543 u8 node_description[64][0x8];
6544};
6545
6546struct mlx5_ifc_register_power_settings_bits {
6547 u8 reserved_0[0x18];
6548 u8 power_settings_level[0x8];
6549
6550 u8 reserved_1[0x60];
6551};
6552
6553struct mlx5_ifc_register_host_endianness_bits {
6554 u8 he[0x1];
6555 u8 reserved_0[0x1f];
6556
6557 u8 reserved_1[0x60];
6558};
6559
6560struct mlx5_ifc_umr_pointer_desc_argument_bits {
6561 u8 reserved_0[0x20];
6562
6563 u8 mkey[0x20];
6564
6565 u8 addressh_63_32[0x20];
6566
6567 u8 addressl_31_0[0x20];
6568};
6569
6570struct mlx5_ifc_ud_adrs_vector_bits {
6571 u8 dc_key[0x40];
6572
6573 u8 ext[0x1];
6574 u8 reserved_0[0x7];
6575 u8 destination_qp_dct[0x18];
6576
6577 u8 static_rate[0x4];
6578 u8 sl_eth_prio[0x4];
6579 u8 fl[0x1];
6580 u8 mlid[0x7];
6581 u8 rlid_udp_sport[0x10];
6582
6583 u8 reserved_1[0x20];
6584
6585 u8 rmac_47_16[0x20];
6586
6587 u8 rmac_15_0[0x10];
6588 u8 tclass[0x8];
6589 u8 hop_limit[0x8];
6590
6591 u8 reserved_2[0x1];
6592 u8 grh[0x1];
6593 u8 reserved_3[0x2];
6594 u8 src_addr_index[0x8];
6595 u8 flow_label[0x14];
6596
6597 u8 rgid_rip[16][0x8];
6598};
6599
6600struct mlx5_ifc_pages_req_event_bits {
6601 u8 reserved_0[0x10];
6602 u8 function_id[0x10];
6603
6604 u8 num_pages[0x20];
6605
6606 u8 reserved_1[0xa0];
6607};
6608
6609struct mlx5_ifc_eqe_bits {
6610 u8 reserved_0[0x8];
6611 u8 event_type[0x8];
6612 u8 reserved_1[0x8];
6613 u8 event_sub_type[0x8];
6614
6615 u8 reserved_2[0xe0];
6616
6617 union mlx5_ifc_event_auto_bits event_data;
6618
6619 u8 reserved_3[0x10];
6620 u8 signature[0x8];
6621 u8 reserved_4[0x7];
6622 u8 owner[0x1];
6623};
6624
6625enum {
6626 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6627};
6628
6629struct mlx5_ifc_cmd_queue_entry_bits {
6630 u8 type[0x8];
6631 u8 reserved_0[0x18];
6632
6633 u8 input_length[0x20];
6634
6635 u8 input_mailbox_pointer_63_32[0x20];
6636
6637 u8 input_mailbox_pointer_31_9[0x17];
6638 u8 reserved_1[0x9];
6639
6640 u8 command_input_inline_data[16][0x8];
6641
6642 u8 command_output_inline_data[16][0x8];
6643
6644 u8 output_mailbox_pointer_63_32[0x20];
6645
6646 u8 output_mailbox_pointer_31_9[0x17];
6647 u8 reserved_2[0x9];
6648
6649 u8 output_length[0x20];
6650
6651 u8 token[0x8];
6652 u8 signature[0x8];
6653 u8 reserved_3[0x8];
6654 u8 status[0x7];
6655 u8 ownership[0x1];
6656};
6657
6658struct mlx5_ifc_cmd_out_bits {
6659 u8 status[0x8];
6660 u8 reserved_0[0x18];
6661
6662 u8 syndrome[0x20];
6663
6664 u8 command_output[0x20];
6665};
6666
6667struct mlx5_ifc_cmd_in_bits {
6668 u8 opcode[0x10];
6669 u8 reserved_0[0x10];
6670
6671 u8 reserved_1[0x10];
6672 u8 op_mod[0x10];
6673
6674 u8 command[0][0x20];
6675};
6676
6677struct mlx5_ifc_cmd_if_box_bits {
6678 u8 mailbox_data[512][0x8];
6679
6680 u8 reserved_0[0x180];
6681
6682 u8 next_pointer_63_32[0x20];
6683
6684 u8 next_pointer_31_10[0x16];
6685 u8 reserved_1[0xa];
6686
6687 u8 block_number[0x20];
6688
6689 u8 reserved_2[0x8];
6690 u8 token[0x8];
6691 u8 ctrl_signature[0x8];
6692 u8 signature[0x8];
6693};
6694
6695struct mlx5_ifc_mtt_bits {
6696 u8 ptag_63_32[0x20];
6697
6698 u8 ptag_31_8[0x18];
6699 u8 reserved_0[0x6];
6700 u8 wr_en[0x1];
6701 u8 rd_en[0x1];
6702};
6703
6704enum {
6705 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6706 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6707 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6708};
6709
6710enum {
6711 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6712 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6713 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6714};
6715
6716enum {
6717 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6728};
6729
6730struct mlx5_ifc_initial_seg_bits {
6731 u8 fw_rev_minor[0x10];
6732 u8 fw_rev_major[0x10];
6733
6734 u8 cmd_interface_rev[0x10];
6735 u8 fw_rev_subminor[0x10];
6736
6737 u8 reserved_0[0x40];
6738
6739 u8 cmdq_phy_addr_63_32[0x20];
6740
6741 u8 cmdq_phy_addr_31_12[0x14];
6742 u8 reserved_1[0x2];
6743 u8 nic_interface[0x2];
6744 u8 log_cmdq_size[0x4];
6745 u8 log_cmdq_stride[0x4];
6746
6747 u8 command_doorbell_vector[0x20];
6748
6749 u8 reserved_2[0xf00];
6750
6751 u8 initializing[0x1];
6752 u8 reserved_3[0x4];
6753 u8 nic_interface_supported[0x3];
6754 u8 reserved_4[0x18];
6755
6756 struct mlx5_ifc_health_buffer_bits health_buffer;
6757
6758 u8 no_dram_nic_offset[0x20];
6759
6760 u8 reserved_5[0x6e40];
6761
6762 u8 reserved_6[0x1f];
6763 u8 clear_int[0x1];
6764
6765 u8 health_syndrome[0x8];
6766 u8 health_counter[0x18];
6767
6768 u8 reserved_7[0x17fc0];
6769};
6770
6771union mlx5_ifc_ports_control_registers_document_bits {
6772 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6773 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6774 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6775 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6776 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6777 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6778 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6779 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6780 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6781 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6782 struct mlx5_ifc_paos_reg_bits paos_reg;
6783 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6784 struct mlx5_ifc_peir_reg_bits peir_reg;
6785 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6786 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6787 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6788 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6789 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6790 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6791 struct mlx5_ifc_plib_reg_bits plib_reg;
6792 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6793 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6794 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6795 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6796 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6797 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6798 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6799 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6800 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6801 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6802 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6803 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6804 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6805 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6806 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6807 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6808 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6809 struct mlx5_ifc_pude_reg_bits pude_reg;
6810 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6811 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6812 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6813 u8 reserved_0[0x60e0];
6814};
6815
6816union mlx5_ifc_debug_enhancements_document_bits {
6817 struct mlx5_ifc_health_buffer_bits health_buffer;
6818 u8 reserved_0[0x200];
6819};
6820
6821union mlx5_ifc_uplink_pci_interface_document_bits {
6822 struct mlx5_ifc_initial_seg_bits initial_seg;
6823 u8 reserved_0[0x20060];
b775516b
EC		 6824};
6825
d29b796a 6826#endif /* MLX5_IFC_H */
Linux kernel - Deliverables
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