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IB/mlx5: Implement callbacks for manipulating VFs
[deliverable/linux.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
d29b796a
EC		 169 MLX5_CMD_OP_CREATE_TIR = 0x900,
170 MLX5_CMD_OP_MODIFY_TIR = 0x901,
171 MLX5_CMD_OP_DESTROY_TIR = 0x902,
172 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 173 MLX5_CMD_OP_CREATE_SQ = 0x904,
174 MLX5_CMD_OP_MODIFY_SQ = 0x905,
175 MLX5_CMD_OP_DESTROY_SQ = 0x906,
176 MLX5_CMD_OP_QUERY_SQ = 0x907,
177 MLX5_CMD_OP_CREATE_RQ = 0x908,
178 MLX5_CMD_OP_MODIFY_RQ = 0x909,
179 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
180 MLX5_CMD_OP_QUERY_RQ = 0x90b,
181 MLX5_CMD_OP_CREATE_RMP = 0x90c,
182 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
183 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
184 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 185 MLX5_CMD_OP_CREATE_TIS = 0x912,
186 MLX5_CMD_OP_MODIFY_TIS = 0x913,
187 MLX5_CMD_OP_DESTROY_TIS = 0x914,
188 MLX5_CMD_OP_QUERY_TIS = 0x915,
189 MLX5_CMD_OP_CREATE_RQT = 0x916,
190 MLX5_CMD_OP_MODIFY_RQT = 0x917,
191 MLX5_CMD_OP_DESTROY_RQT = 0x918,
192 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 193 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 194 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
195 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
196 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
197 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
198 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
199 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
200 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
201 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68
MG		 202 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
203 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
e281682b
SM		 204};
205
206struct mlx5_ifc_flow_table_fields_supported_bits {
207 u8 outer_dmac[0x1];
208 u8 outer_smac[0x1];
209 u8 outer_ether_type[0x1];
b4ff3a36 210 u8 reserved_at_3[0x1];
e281682b
SM		 211 u8 outer_first_prio[0x1];
212 u8 outer_first_cfi[0x1];
213 u8 outer_first_vid[0x1];
b4ff3a36 214 u8 reserved_at_7[0x1];
e281682b
SM		 215 u8 outer_second_prio[0x1];
216 u8 outer_second_cfi[0x1];
217 u8 outer_second_vid[0x1];
b4ff3a36 218 u8 reserved_at_b[0x1];
e281682b
SM		 219 u8 outer_sip[0x1];
220 u8 outer_dip[0x1];
221 u8 outer_frag[0x1];
222 u8 outer_ip_protocol[0x1];
223 u8 outer_ip_ecn[0x1];
224 u8 outer_ip_dscp[0x1];
225 u8 outer_udp_sport[0x1];
226 u8 outer_udp_dport[0x1];
227 u8 outer_tcp_sport[0x1];
228 u8 outer_tcp_dport[0x1];
229 u8 outer_tcp_flags[0x1];
230 u8 outer_gre_protocol[0x1];
231 u8 outer_gre_key[0x1];
232 u8 outer_vxlan_vni[0x1];
b4ff3a36 233 u8 reserved_at_1a[0x5];
e281682b
SM		 234 u8 source_eswitch_port[0x1];
235
236 u8 inner_dmac[0x1];
237 u8 inner_smac[0x1];
238 u8 inner_ether_type[0x1];
b4ff3a36 239 u8 reserved_at_23[0x1];
e281682b
SM		 240 u8 inner_first_prio[0x1];
241 u8 inner_first_cfi[0x1];
242 u8 inner_first_vid[0x1];
b4ff3a36 243 u8 reserved_at_27[0x1];
e281682b
SM		 244 u8 inner_second_prio[0x1];
245 u8 inner_second_cfi[0x1];
246 u8 inner_second_vid[0x1];
b4ff3a36 247 u8 reserved_at_2b[0x1];
e281682b
SM		 248 u8 inner_sip[0x1];
249 u8 inner_dip[0x1];
250 u8 inner_frag[0x1];
251 u8 inner_ip_protocol[0x1];
252 u8 inner_ip_ecn[0x1];
253 u8 inner_ip_dscp[0x1];
254 u8 inner_udp_sport[0x1];
255 u8 inner_udp_dport[0x1];
256 u8 inner_tcp_sport[0x1];
257 u8 inner_tcp_dport[0x1];
258 u8 inner_tcp_flags[0x1];
b4ff3a36 259 u8 reserved_at_37[0x9];
e281682b 260
b4ff3a36 261 u8 reserved_at_40[0x40];
e281682b
SM		 262};
263
264struct mlx5_ifc_flow_table_prop_layout_bits {
265 u8 ft_support[0x1];
b4ff3a36 266 u8 reserved_at_1[0x2];
26a81453 267 u8 flow_modify_en[0x1];
2cc43b49 268 u8 modify_root[0x1];
34a40e68
MG		 269 u8 identified_miss_table_mode[0x1];
270 u8 flow_table_modify[0x1];
b4ff3a36 271 u8 reserved_at_7[0x19];
e281682b 272
b4ff3a36 273 u8 reserved_at_20[0x2];
e281682b 274 u8 log_max_ft_size[0x6];
b4ff3a36 275 u8 reserved_at_28[0x10];
e281682b
SM		 276 u8 max_ft_level[0x8];
277
b4ff3a36 278 u8 reserved_at_40[0x20];
e281682b 279
b4ff3a36 280 u8 reserved_at_60[0x18];
e281682b
SM		 281 u8 log_max_ft_num[0x8];
282
b4ff3a36 283 u8 reserved_at_80[0x18];
e281682b
SM		 284 u8 log_max_destination[0x8];
285
b4ff3a36 286 u8 reserved_at_a0[0x18];
e281682b
SM		 287 u8 log_max_flow[0x8];
288
b4ff3a36 289 u8 reserved_at_c0[0x40];
e281682b
SM		 290
291 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
292
293 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
294};
295
296struct mlx5_ifc_odp_per_transport_service_cap_bits {
297 u8 send[0x1];
298 u8 receive[0x1];
299 u8 write[0x1];
300 u8 read[0x1];
b4ff3a36 301 u8 reserved_at_4[0x1];
e281682b 302 u8 srq_receive[0x1];
b4ff3a36 303 u8 reserved_at_6[0x1a];
e281682b
SM		 304};
305
b4d1f032 306struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 307 u8 reserved_at_0[0x60];
b4d1f032
MG		 308
309 u8 ipv4[0x20];
310};
311
312struct mlx5_ifc_ipv6_layout_bits {
313 u8 ipv6[16][0x8];
314};
315
316union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
317 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
318 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 319 u8 reserved_at_0[0x80];
b4d1f032
MG		 320};
321
e281682b
SM		 322struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
323 u8 smac_47_16[0x20];
324
325 u8 smac_15_0[0x10];
326 u8 ethertype[0x10];
327
328 u8 dmac_47_16[0x20];
329
330 u8 dmac_15_0[0x10];
331 u8 first_prio[0x3];
332 u8 first_cfi[0x1];
333 u8 first_vid[0xc];
334
335 u8 ip_protocol[0x8];
336 u8 ip_dscp[0x6];
337 u8 ip_ecn[0x2];
338 u8 vlan_tag[0x1];
b4ff3a36 339 u8 reserved_at_91[0x1];
e281682b 340 u8 frag[0x1];
b4ff3a36 341 u8 reserved_at_93[0x4];
e281682b
SM		 342 u8 tcp_flags[0x9];
343
344 u8 tcp_sport[0x10];
345 u8 tcp_dport[0x10];
346
b4ff3a36 347 u8 reserved_at_c0[0x20];
e281682b
SM		 348
349 u8 udp_sport[0x10];
350 u8 udp_dport[0x10];
351
b4d1f032 352 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 353
b4d1f032 354 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 355};
356
357struct mlx5_ifc_fte_match_set_misc_bits {
b4ff3a36 358 u8 reserved_at_0[0x20];
e281682b 359
b4ff3a36 360 u8 reserved_at_20[0x10];
e281682b
SM		 361 u8 source_port[0x10];
362
363 u8 outer_second_prio[0x3];
364 u8 outer_second_cfi[0x1];
365 u8 outer_second_vid[0xc];
366 u8 inner_second_prio[0x3];
367 u8 inner_second_cfi[0x1];
368 u8 inner_second_vid[0xc];
369
370 u8 outer_second_vlan_tag[0x1];
371 u8 inner_second_vlan_tag[0x1];
b4ff3a36 372 u8 reserved_at_62[0xe];
e281682b
SM		 373 u8 gre_protocol[0x10];
374
375 u8 gre_key_h[0x18];
376 u8 gre_key_l[0x8];
377
378 u8 vxlan_vni[0x18];
b4ff3a36 379 u8 reserved_at_b8[0x8];
e281682b 380
b4ff3a36 381 u8 reserved_at_c0[0x20];
e281682b 382
b4ff3a36 383 u8 reserved_at_e0[0xc];
e281682b
SM		 384 u8 outer_ipv6_flow_label[0x14];
385
b4ff3a36 386 u8 reserved_at_100[0xc];
e281682b
SM		 387 u8 inner_ipv6_flow_label[0x14];
388
b4ff3a36 389 u8 reserved_at_120[0xe0];
e281682b
SM		 390};
391
392struct mlx5_ifc_cmd_pas_bits {
393 u8 pa_h[0x20];
394
395 u8 pa_l[0x14];
b4ff3a36 396 u8 reserved_at_34[0xc];
e281682b
SM		 397};
398
399struct mlx5_ifc_uint64_bits {
400 u8 hi[0x20];
401
402 u8 lo[0x20];
403};
404
405enum {
406 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
407 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
408 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
409 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
410 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
411 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
412 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
413 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
414 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
415 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
416};
417
418struct mlx5_ifc_ads_bits {
419 u8 fl[0x1];
420 u8 free_ar[0x1];
b4ff3a36 421 u8 reserved_at_2[0xe];
e281682b
SM		 422 u8 pkey_index[0x10];
423
b4ff3a36 424 u8 reserved_at_20[0x8];
e281682b
SM		 425 u8 grh[0x1];
426 u8 mlid[0x7];
427 u8 rlid[0x10];
428
429 u8 ack_timeout[0x5];
b4ff3a36 430 u8 reserved_at_45[0x3];
e281682b 431 u8 src_addr_index[0x8];
b4ff3a36 432 u8 reserved_at_50[0x4];
e281682b
SM		 433 u8 stat_rate[0x4];
434 u8 hop_limit[0x8];
435
b4ff3a36 436 u8 reserved_at_60[0x4];
e281682b
SM		 437 u8 tclass[0x8];
438 u8 flow_label[0x14];
439
440 u8 rgid_rip[16][0x8];
441
b4ff3a36 442 u8 reserved_at_100[0x4];
e281682b
SM		 443 u8 f_dscp[0x1];
444 u8 f_ecn[0x1];
b4ff3a36 445 u8 reserved_at_106[0x1];
e281682b
SM		 446 u8 f_eth_prio[0x1];
447 u8 ecn[0x2];
448 u8 dscp[0x6];
449 u8 udp_sport[0x10];
450
451 u8 dei_cfi[0x1];
452 u8 eth_prio[0x3];
453 u8 sl[0x4];
454 u8 port[0x8];
455 u8 rmac_47_32[0x10];
456
457 u8 rmac_31_0[0x20];
458};
459
460struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a
MG		 461 u8 nic_rx_multi_path_tirs[0x1];
462 u8 reserved_at_1[0x1ff];
e281682b
SM		 463
464 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
465
b4ff3a36 466 u8 reserved_at_400[0x200];
e281682b
SM		 467
468 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
469
470 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
471
b4ff3a36 472 u8 reserved_at_a00[0x200];
e281682b
SM		 473
474 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
475
b4ff3a36 476 u8 reserved_at_e00[0x7200];
e281682b
SM		 477};
478
495716b1 479struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 480 u8 reserved_at_0[0x200];
495716b1
SM		 481
482 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
483
484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
485
486 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
487
b4ff3a36 488 u8 reserved_at_800[0x7800];
495716b1
SM		 489};
490
d6666753
SM		 491struct mlx5_ifc_e_switch_cap_bits {
492 u8 vport_svlan_strip[0x1];
493 u8 vport_cvlan_strip[0x1];
494 u8 vport_svlan_insert[0x1];
495 u8 vport_cvlan_insert_if_not_exist[0x1];
496 u8 vport_cvlan_insert_overwrite[0x1];
b4ff3a36 497 u8 reserved_at_5[0x1b];
d6666753 498
b4ff3a36 499 u8 reserved_at_20[0x7e0];
d6666753
SM		 500};
501
e281682b
SM		 502struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
503 u8 csum_cap[0x1];
504 u8 vlan_cap[0x1];
505 u8 lro_cap[0x1];
506 u8 lro_psh_flag[0x1];
507 u8 lro_time_stamp[0x1];
b4ff3a36 508 u8 reserved_at_5[0x3];
66189961 509 u8 self_lb_en_modifiable[0x1];
b4ff3a36 510 u8 reserved_at_9[0x2];
e281682b 511 u8 max_lso_cap[0x5];
b4ff3a36 512 u8 reserved_at_10[0x4];
e281682b 513 u8 rss_ind_tbl_cap[0x4];
b4ff3a36 514 u8 reserved_at_18[0x3];
e281682b 515 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 516 u8 reserved_at_1c[0x2];
e281682b
SM		 517 u8 tunnel_statless_gre[0x1];
518 u8 tunnel_stateless_vxlan[0x1];
519
b4ff3a36 520 u8 reserved_at_20[0x20];
e281682b 521
b4ff3a36 522 u8 reserved_at_40[0x10];
e281682b
SM		 523 u8 lro_min_mss_size[0x10];
524
b4ff3a36 525 u8 reserved_at_60[0x120];
e281682b
SM		 526
527 u8 lro_timer_supported_periods[4][0x20];
528
b4ff3a36 529 u8 reserved_at_200[0x600];
e281682b
SM		 530};
531
532struct mlx5_ifc_roce_cap_bits {
533 u8 roce_apm[0x1];
b4ff3a36 534 u8 reserved_at_1[0x1f];
e281682b 535
b4ff3a36 536 u8 reserved_at_20[0x60];
e281682b 537
b4ff3a36 538 u8 reserved_at_80[0xc];
e281682b 539 u8 l3_type[0x4];
b4ff3a36 540 u8 reserved_at_90[0x8];
e281682b
SM		 541 u8 roce_version[0x8];
542
b4ff3a36 543 u8 reserved_at_a0[0x10];
e281682b
SM		 544 u8 r_roce_dest_udp_port[0x10];
545
546 u8 r_roce_max_src_udp_port[0x10];
547 u8 r_roce_min_src_udp_port[0x10];
548
b4ff3a36 549 u8 reserved_at_e0[0x10];
e281682b
SM		 550 u8 roce_address_table_size[0x10];
551
b4ff3a36 552 u8 reserved_at_100[0x700];
e281682b
SM		 553};
554
555enum {
556 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
557 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
559 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
560 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
561 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
565};
566
567enum {
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
577};
578
579struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 580 u8 reserved_at_0[0x40];
e281682b 581
f91e6d89 582 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 583 u8 reserved_at_42[0x4];
f91e6d89 584 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 585
b4ff3a36 586 u8 reserved_at_47[0x19];
e281682b 587
b4ff3a36 588 u8 reserved_at_60[0x20];
e281682b 589
b4ff3a36 590 u8 reserved_at_80[0x10];
f91e6d89 591 u8 atomic_operations[0x10];
e281682b 592
b4ff3a36 593 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 594 u8 atomic_size_qp[0x10];
595
b4ff3a36 596 u8 reserved_at_c0[0x10];
e281682b
SM		 597 u8 atomic_size_dc[0x10];
598
b4ff3a36 599 u8 reserved_at_e0[0x720];
e281682b
SM		 600};
601
602struct mlx5_ifc_odp_cap_bits {
b4ff3a36 603 u8 reserved_at_0[0x40];
e281682b
SM		 604
605 u8 sig[0x1];
b4ff3a36 606 u8 reserved_at_41[0x1f];
e281682b 607
b4ff3a36 608 u8 reserved_at_60[0x20];
e281682b
SM		 609
610 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
611
612 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
613
614 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
615
b4ff3a36 616 u8 reserved_at_e0[0x720];
e281682b
SM		 617};
618
3f0393a5
SG		 619struct mlx5_ifc_calc_op {
620 u8 reserved_at_0[0x10];
621 u8 reserved_at_10[0x9];
622 u8 op_swap_endianness[0x1];
623 u8 op_min[0x1];
624 u8 op_xor[0x1];
625 u8 op_or[0x1];
626 u8 op_and[0x1];
627 u8 op_max[0x1];
628 u8 op_add[0x1];
629};
630
631struct mlx5_ifc_vector_calc_cap_bits {
632 u8 calc_matrix[0x1];
633 u8 reserved_at_1[0x1f];
634 u8 reserved_at_20[0x8];
635 u8 max_vec_count[0x8];
636 u8 reserved_at_30[0xd];
637 u8 max_chunk_size[0x3];
638 struct mlx5_ifc_calc_op calc0;
639 struct mlx5_ifc_calc_op calc1;
640 struct mlx5_ifc_calc_op calc2;
641 struct mlx5_ifc_calc_op calc3;
642
643 u8 reserved_at_e0[0x720];
644};
645
e281682b
SM		 646enum {
647 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
648 MLX5_WQ_TYPE_CYCLIC = 0x1,
649 MLX5_WQ_TYPE_STRQ = 0x2,
650};
651
652enum {
653 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
654 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
655};
656
657enum {
658 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
659 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
660 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
661 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
662 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
663};
664
665enum {
666 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
667 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
668 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
669 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
670 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
671 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
672};
673
674enum {
675 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
676 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
677};
678
679enum {
680 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
681 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
682 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
683};
684
685enum {
686 MLX5_CAP_PORT_TYPE_IB = 0x0,
687 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 688};
689
b775516b 690struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 691 u8 reserved_at_0[0x80];
b775516b
EC		 692
693 u8 log_max_srq_sz[0x8];
694 u8 log_max_qp_sz[0x8];
b4ff3a36 695 u8 reserved_at_90[0xb];
b775516b
EC		 696 u8 log_max_qp[0x5];
697
b4ff3a36 698 u8 reserved_at_a0[0xb];
e281682b 699 u8 log_max_srq[0x5];
b4ff3a36 700 u8 reserved_at_b0[0x10];
b775516b 701
b4ff3a36 702 u8 reserved_at_c0[0x8];
b775516b 703 u8 log_max_cq_sz[0x8];
b4ff3a36 704 u8 reserved_at_d0[0xb];
b775516b
EC		 705 u8 log_max_cq[0x5];
706
707 u8 log_max_eq_sz[0x8];
b4ff3a36 708 u8 reserved_at_e8[0x2];
b775516b 709 u8 log_max_mkey[0x6];
b4ff3a36 710 u8 reserved_at_f0[0xc];
b775516b
EC		 711 u8 log_max_eq[0x4];
712
713 u8 max_indirection[0x8];
b4ff3a36 714 u8 reserved_at_108[0x1];
b775516b 715 u8 log_max_mrw_sz[0x7];
b4ff3a36 716 u8 reserved_at_110[0x2];
b775516b 717 u8 log_max_bsf_list_size[0x6];
b4ff3a36 718 u8 reserved_at_118[0x2];
b775516b
EC		 719 u8 log_max_klm_list_size[0x6];
720
b4ff3a36 721 u8 reserved_at_120[0xa];
b775516b 722 u8 log_max_ra_req_dc[0x6];
b4ff3a36 723 u8 reserved_at_130[0xa];
b775516b
EC		 724 u8 log_max_ra_res_dc[0x6];
725
b4ff3a36 726 u8 reserved_at_140[0xa];
b775516b 727 u8 log_max_ra_req_qp[0x6];
b4ff3a36 728 u8 reserved_at_150[0xa];
b775516b
EC		 729 u8 log_max_ra_res_qp[0x6];
730
731 u8 pad_cap[0x1];
732 u8 cc_query_allowed[0x1];
733 u8 cc_modify_allowed[0x1];
b4ff3a36 734 u8 reserved_at_163[0xd];
e281682b 735 u8 gid_table_size[0x10];
b775516b 736
e281682b
SM		 737 u8 out_of_seq_cnt[0x1];
738 u8 vport_counters[0x1];
b4ff3a36 739 u8 reserved_at_182[0x4];
b775516b
EC		 740 u8 max_qp_cnt[0xa];
741 u8 pkey_table_size[0x10];
742
e281682b
SM		 743 u8 vport_group_manager[0x1];
744 u8 vhca_group_manager[0x1];
745 u8 ib_virt[0x1];
746 u8 eth_virt[0x1];
b4ff3a36 747 u8 reserved_at_1a4[0x1];
e281682b
SM		 748 u8 ets[0x1];
749 u8 nic_flow_table[0x1];
54f0a411 750 u8 eswitch_flow_table[0x1];
fc50db98 751 u8 early_vf_enable;
b4ff3a36 752 u8 reserved_at_1a8[0x2];
b775516b 753 u8 local_ca_ack_delay[0x5];
b4ff3a36 754 u8 reserved_at_1af[0x6];
e281682b 755 u8 port_type[0x2];
b775516b
EC		 756 u8 num_ports[0x8];
757
b4ff3a36 758 u8 reserved_at_1bf[0x3];
b775516b 759 u8 log_max_msg[0x5];
b4ff3a36 760 u8 reserved_at_1c7[0x18];
b775516b
EC		 761
762 u8 stat_rate_support[0x10];
b4ff3a36 763 u8 reserved_at_1ef[0xc];
e281682b 764 u8 cqe_version[0x4];
b775516b 765
e281682b 766 u8 compact_address_vector[0x1];
1015c2e8
ES		 767 u8 reserved_at_200[0x3];
768 u8 ipoib_basic_offloads[0x1];
769 u8 reserved_at_204[0xa];
e281682b 770 u8 drain_sigerr[0x1];
b775516b
EC		 771 u8 cmdif_checksum[0x2];
772 u8 sigerr_cqe[0x1];
b4ff3a36 773 u8 reserved_at_212[0x1];
b775516b
EC		 774 u8 wq_signature[0x1];
775 u8 sctr_data_cqe[0x1];
b4ff3a36 776 u8 reserved_at_215[0x1];
b775516b
EC		 777 u8 sho[0x1];
778 u8 tph[0x1];
779 u8 rf[0x1];
e281682b 780 u8 dct[0x1];
b4ff3a36 781 u8 reserved_at_21a[0x1];
e281682b 782 u8 eth_net_offloads[0x1];
b775516b
EC		 783 u8 roce[0x1];
784 u8 atomic[0x1];
b4ff3a36 785 u8 reserved_at_21e[0x1];
b775516b
EC		 786
787 u8 cq_oi[0x1];
788 u8 cq_resize[0x1];
789 u8 cq_moderation[0x1];
b4ff3a36 790 u8 reserved_at_222[0x3];
e281682b 791 u8 cq_eq_remap[0x1];
b775516b
EC		 792 u8 pg[0x1];
793 u8 block_lb_mc[0x1];
b4ff3a36 794 u8 reserved_at_228[0x1];
e281682b 795 u8 scqe_break_moderation[0x1];
b4ff3a36 796 u8 reserved_at_22a[0x1];
b775516b 797 u8 cd[0x1];
b4ff3a36 798 u8 reserved_at_22c[0x1];
b775516b 799 u8 apm[0x1];
3f0393a5
SG		 800 u8 vector_calc[0x1];
801 u8 reserved_at_22f[0x1];
d2370e0a
MB		 802 u8 imaicl[0x1];
803 u8 reserved_at_231[0x4];
b775516b
EC		 804 u8 qkv[0x1];
805 u8 pkv[0x1];
b11a4f9c
HE		 806 u8 set_deth_sqpn[0x1];
807 u8 reserved_at_239[0x3];
b775516b
EC		 808 u8 xrc[0x1];
809 u8 ud[0x1];
810 u8 uc[0x1];
811 u8 rc[0x1];
812
b4ff3a36 813 u8 reserved_at_23f[0xa];
b775516b 814 u8 uar_sz[0x6];
b4ff3a36 815 u8 reserved_at_24f[0x8];
b775516b
EC		 816 u8 log_pg_sz[0x8];
817
818 u8 bf[0x1];
b4ff3a36 819 u8 reserved_at_260[0x1];
e281682b 820 u8 pad_tx_eth_packet[0x1];
b4ff3a36 821 u8 reserved_at_262[0x8];
b775516b 822 u8 log_bf_reg_size[0x5];
b4ff3a36 823 u8 reserved_at_26f[0x10];
b775516b 824
b4ff3a36 825 u8 reserved_at_27f[0x10];
b775516b
EC		 826 u8 max_wqe_sz_sq[0x10];
827
b4ff3a36 828 u8 reserved_at_29f[0x10];
b775516b
EC		 829 u8 max_wqe_sz_rq[0x10];
830
b4ff3a36 831 u8 reserved_at_2bf[0x10];
b775516b
EC		 832 u8 max_wqe_sz_sq_dc[0x10];
833
b4ff3a36 834 u8 reserved_at_2df[0x7];
b775516b
EC		 835 u8 max_qp_mcg[0x19];
836
b4ff3a36 837 u8 reserved_at_2ff[0x18];
b775516b
EC		 838 u8 log_max_mcg[0x8];
839
b4ff3a36 840 u8 reserved_at_31f[0x3];
e281682b 841 u8 log_max_transport_domain[0x5];
b4ff3a36 842 u8 reserved_at_327[0x3];
b775516b 843 u8 log_max_pd[0x5];
b4ff3a36 844 u8 reserved_at_32f[0xb];
b775516b
EC		 845 u8 log_max_xrcd[0x5];
846
b4ff3a36 847 u8 reserved_at_33f[0x20];
b775516b 848
b4ff3a36 849 u8 reserved_at_35f[0x3];
b775516b 850 u8 log_max_rq[0x5];
b4ff3a36 851 u8 reserved_at_367[0x3];
b775516b 852 u8 log_max_sq[0x5];
b4ff3a36 853 u8 reserved_at_36f[0x3];
b775516b 854 u8 log_max_tir[0x5];
b4ff3a36 855 u8 reserved_at_377[0x3];
b775516b
EC		 856 u8 log_max_tis[0x5];
857
e281682b 858 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 859 u8 reserved_at_380[0x2];
e281682b 860 u8 log_max_rmp[0x5];
b4ff3a36 861 u8 reserved_at_387[0x3];
e281682b 862 u8 log_max_rqt[0x5];
b4ff3a36 863 u8 reserved_at_38f[0x3];
e281682b 864 u8 log_max_rqt_size[0x5];
b4ff3a36 865 u8 reserved_at_397[0x3];
b775516b
EC		 866 u8 log_max_tis_per_sq[0x5];
867
b4ff3a36 868 u8 reserved_at_39f[0x3];
e281682b 869 u8 log_max_stride_sz_rq[0x5];
b4ff3a36 870 u8 reserved_at_3a7[0x3];
e281682b 871 u8 log_min_stride_sz_rq[0x5];
b4ff3a36 872 u8 reserved_at_3af[0x3];
e281682b 873 u8 log_max_stride_sz_sq[0x5];
b4ff3a36 874 u8 reserved_at_3b7[0x3];
e281682b
SM		 875 u8 log_min_stride_sz_sq[0x5];
876
b4ff3a36 877 u8 reserved_at_3bf[0x1b];
e281682b
SM		 878 u8 log_max_wq_sz[0x5];
879
54f0a411 880 u8 nic_vport_change_event[0x1];
b4ff3a36 881 u8 reserved_at_3e0[0xa];
54f0a411 882 u8 log_max_vlan_list[0x5];
b4ff3a36 883 u8 reserved_at_3ef[0x3];
54f0a411 884 u8 log_max_current_mc_list[0x5];
b4ff3a36 885 u8 reserved_at_3f7[0x3];
54f0a411
SM		 886 u8 log_max_current_uc_list[0x5];
887
b4ff3a36 888 u8 reserved_at_3ff[0x80];
54f0a411 889
b4ff3a36 890 u8 reserved_at_47f[0x3];
e281682b 891 u8 log_max_l2_table[0x5];
b4ff3a36 892 u8 reserved_at_487[0x8];
b775516b
EC		 893 u8 log_uar_page_sz[0x10];
894
b4ff3a36 895 u8 reserved_at_49f[0x20];
048ccca8 896 u8 device_frequency_mhz[0x20];
b0844444 897 u8 device_frequency_khz[0x20];
b4ff3a36 898 u8 reserved_at_4ff[0x5f];
b775516b
EC		 899 u8 cqe_zip[0x1];
900
901 u8 cqe_zip_timeout[0x10];
902 u8 cqe_zip_max_num[0x10];
903
b4ff3a36 904 u8 reserved_at_57f[0x220];
b775516b
EC		 905};
906
81848731
SM		 907enum mlx5_flow_destination_type {
908 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
909 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
910 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
e281682b 911};
b775516b 912
e281682b
SM		 913struct mlx5_ifc_dest_format_struct_bits {
914 u8 destination_type[0x8];
915 u8 destination_id[0x18];
b775516b 916
b4ff3a36 917 u8 reserved_at_20[0x20];
e281682b
SM		 918};
919
920struct mlx5_ifc_fte_match_param_bits {
921 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
922
923 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
924
925 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 926
b4ff3a36 927 u8 reserved_at_600[0xa00];
b775516b
EC		 928};
929
e281682b
SM		 930enum {
931 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
932 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
933 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
934 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
935 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
936};
b775516b 937
e281682b
SM		 938struct mlx5_ifc_rx_hash_field_select_bits {
939 u8 l3_prot_type[0x1];
940 u8 l4_prot_type[0x1];
941 u8 selected_fields[0x1e];
942};
b775516b 943
e281682b
SM		 944enum {
945 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
946 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 947};
948
e281682b
SM		 949enum {
950 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
951 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
952};
953
954struct mlx5_ifc_wq_bits {
955 u8 wq_type[0x4];
956 u8 wq_signature[0x1];
957 u8 end_padding_mode[0x2];
958 u8 cd_slave[0x1];
b4ff3a36 959 u8 reserved_at_8[0x18];
b775516b 960
e281682b
SM		 961 u8 hds_skip_first_sge[0x1];
962 u8 log2_hds_buf_size[0x3];
b4ff3a36 963 u8 reserved_at_24[0x7];
e281682b
SM		 964 u8 page_offset[0x5];
965 u8 lwm[0x10];
b775516b 966
b4ff3a36 967 u8 reserved_at_40[0x8];
e281682b
SM		 968 u8 pd[0x18];
969
b4ff3a36 970 u8 reserved_at_60[0x8];
e281682b
SM		 971 u8 uar_page[0x18];
972
973 u8 dbr_addr[0x40];
974
975 u8 hw_counter[0x20];
976
977 u8 sw_counter[0x20];
978
b4ff3a36 979 u8 reserved_at_100[0xc];
e281682b 980 u8 log_wq_stride[0x4];
b4ff3a36 981 u8 reserved_at_110[0x3];
e281682b 982 u8 log_wq_pg_sz[0x5];
b4ff3a36 983 u8 reserved_at_118[0x3];
e281682b
SM		 984 u8 log_wq_sz[0x5];
985
b4ff3a36 986 u8 reserved_at_120[0x4e0];
b775516b 987
e281682b 988 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 989};
990
e281682b 991struct mlx5_ifc_rq_num_bits {
b4ff3a36 992 u8 reserved_at_0[0x8];
e281682b
SM		 993 u8 rq_num[0x18];
994};
b775516b 995
e281682b 996struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 997 u8 reserved_at_0[0x10];
e281682b 998 u8 mac_addr_47_32[0x10];
b775516b 999
e281682b
SM		 1000 u8 mac_addr_31_0[0x20];
1001};
1002
c0046cf7 1003struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1004 u8 reserved_at_0[0x14];
c0046cf7
SM		 1005 u8 vlan[0x0c];
1006
b4ff3a36 1007 u8 reserved_at_20[0x20];
c0046cf7
SM		 1008};
1009
e281682b 1010struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1011 u8 reserved_at_0[0xa0];
e281682b
SM		 1012
1013 u8 min_time_between_cnps[0x20];
1014
b4ff3a36 1015 u8 reserved_at_c0[0x12];
e281682b 1016 u8 cnp_dscp[0x6];
b4ff3a36 1017 u8 reserved_at_d8[0x5];
e281682b
SM		 1018 u8 cnp_802p_prio[0x3];
1019
b4ff3a36 1020 u8 reserved_at_e0[0x720];
e281682b
SM		 1021};
1022
1023struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1024 u8 reserved_at_0[0x60];
e281682b 1025
b4ff3a36 1026 u8 reserved_at_60[0x4];
e281682b 1027 u8 clamp_tgt_rate[0x1];
b4ff3a36 1028 u8 reserved_at_65[0x3];
e281682b 1029 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1030 u8 reserved_at_69[0x17];
e281682b 1031
b4ff3a36 1032 u8 reserved_at_80[0x20];
e281682b
SM		 1033
1034 u8 rpg_time_reset[0x20];
1035
1036 u8 rpg_byte_reset[0x20];
1037
1038 u8 rpg_threshold[0x20];
1039
1040 u8 rpg_max_rate[0x20];
1041
1042 u8 rpg_ai_rate[0x20];
1043
1044 u8 rpg_hai_rate[0x20];
1045
1046 u8 rpg_gd[0x20];
1047
1048 u8 rpg_min_dec_fac[0x20];
1049
1050 u8 rpg_min_rate[0x20];
1051
b4ff3a36 1052 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1053
1054 u8 rate_to_set_on_first_cnp[0x20];
1055
1056 u8 dce_tcp_g[0x20];
1057
1058 u8 dce_tcp_rtt[0x20];
1059
1060 u8 rate_reduce_monitor_period[0x20];
1061
b4ff3a36 1062 u8 reserved_at_320[0x20];
e281682b
SM		 1063
1064 u8 initial_alpha_value[0x20];
1065
b4ff3a36 1066 u8 reserved_at_360[0x4a0];
e281682b
SM		 1067};
1068
1069struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1070 u8 reserved_at_0[0x80];
e281682b
SM		 1071
1072 u8 rppp_max_rps[0x20];
1073
1074 u8 rpg_time_reset[0x20];
1075
1076 u8 rpg_byte_reset[0x20];
1077
1078 u8 rpg_threshold[0x20];
1079
1080 u8 rpg_max_rate[0x20];
1081
1082 u8 rpg_ai_rate[0x20];
1083
1084 u8 rpg_hai_rate[0x20];
1085
1086 u8 rpg_gd[0x20];
1087
1088 u8 rpg_min_dec_fac[0x20];
1089
1090 u8 rpg_min_rate[0x20];
1091
b4ff3a36 1092 u8 reserved_at_1c0[0x640];
e281682b
SM		 1093};
1094
1095enum {
1096 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1097 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1098 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1099};
1100
1101struct mlx5_ifc_resize_field_select_bits {
1102 u8 resize_field_select[0x20];
1103};
1104
1105enum {
1106 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1107 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1108 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1109 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1110};
1111
1112struct mlx5_ifc_modify_field_select_bits {
1113 u8 modify_field_select[0x20];
1114};
1115
1116struct mlx5_ifc_field_select_r_roce_np_bits {
1117 u8 field_select_r_roce_np[0x20];
1118};
1119
1120struct mlx5_ifc_field_select_r_roce_rp_bits {
1121 u8 field_select_r_roce_rp[0x20];
1122};
1123
1124enum {
1125 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1126 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1127 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1128 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1129 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1130 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1131 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1132 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1133 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1134 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1135};
1136
1137struct mlx5_ifc_field_select_802_1qau_rp_bits {
1138 u8 field_select_8021qaurp[0x20];
1139};
1140
1141struct mlx5_ifc_phys_layer_cntrs_bits {
1142 u8 time_since_last_clear_high[0x20];
1143
1144 u8 time_since_last_clear_low[0x20];
1145
1146 u8 symbol_errors_high[0x20];
1147
1148 u8 symbol_errors_low[0x20];
1149
1150 u8 sync_headers_errors_high[0x20];
1151
1152 u8 sync_headers_errors_low[0x20];
1153
1154 u8 edpl_bip_errors_lane0_high[0x20];
1155
1156 u8 edpl_bip_errors_lane0_low[0x20];
1157
1158 u8 edpl_bip_errors_lane1_high[0x20];
1159
1160 u8 edpl_bip_errors_lane1_low[0x20];
1161
1162 u8 edpl_bip_errors_lane2_high[0x20];
1163
1164 u8 edpl_bip_errors_lane2_low[0x20];
1165
1166 u8 edpl_bip_errors_lane3_high[0x20];
1167
1168 u8 edpl_bip_errors_lane3_low[0x20];
1169
1170 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1171
1172 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1173
1174 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1175
1176 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1177
1178 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1179
1180 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1181
1182 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1183
1184 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1185
1186 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1187
1188 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1189
1190 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1191
1192 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1193
1194 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1195
1196 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1197
1198 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1199
1200 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1201
1202 u8 rs_fec_corrected_blocks_high[0x20];
1203
1204 u8 rs_fec_corrected_blocks_low[0x20];
1205
1206 u8 rs_fec_uncorrectable_blocks_high[0x20];
1207
1208 u8 rs_fec_uncorrectable_blocks_low[0x20];
1209
1210 u8 rs_fec_no_errors_blocks_high[0x20];
1211
1212 u8 rs_fec_no_errors_blocks_low[0x20];
1213
1214 u8 rs_fec_single_error_blocks_high[0x20];
1215
1216 u8 rs_fec_single_error_blocks_low[0x20];
1217
1218 u8 rs_fec_corrected_symbols_total_high[0x20];
1219
1220 u8 rs_fec_corrected_symbols_total_low[0x20];
1221
1222 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1223
1224 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1225
1226 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1227
1228 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1229
1230 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1231
1232 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1233
1234 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1235
1236 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1237
1238 u8 link_down_events[0x20];
1239
1240 u8 successful_recovery_events[0x20];
1241
b4ff3a36 1242 u8 reserved_at_640[0x180];
e281682b
SM		 1243};
1244
1c64bf6f
MY		 1245struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1246 u8 symbol_error_counter[0x10];
1247
1248 u8 link_error_recovery_counter[0x8];
1249
1250 u8 link_downed_counter[0x8];
1251
1252 u8 port_rcv_errors[0x10];
1253
1254 u8 port_rcv_remote_physical_errors[0x10];
1255
1256 u8 port_rcv_switch_relay_errors[0x10];
1257
1258 u8 port_xmit_discards[0x10];
1259
1260 u8 port_xmit_constraint_errors[0x8];
1261
1262 u8 port_rcv_constraint_errors[0x8];
1263
1264 u8 reserved_at_70[0x8];
1265
1266 u8 link_overrun_errors[0x8];
1267
1268 u8 reserved_at_80[0x10];
1269
1270 u8 vl_15_dropped[0x10];
1271
1272 u8 reserved_at_a0[0xa0];
1273};
1274
e281682b
SM		 1275struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1276 u8 transmit_queue_high[0x20];
1277
1278 u8 transmit_queue_low[0x20];
1279
b4ff3a36 1280 u8 reserved_at_40[0x780];
e281682b
SM		 1281};
1282
1283struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1284 u8 rx_octets_high[0x20];
1285
1286 u8 rx_octets_low[0x20];
1287
b4ff3a36 1288 u8 reserved_at_40[0xc0];
e281682b
SM		 1289
1290 u8 rx_frames_high[0x20];
1291
1292 u8 rx_frames_low[0x20];
1293
1294 u8 tx_octets_high[0x20];
1295
1296 u8 tx_octets_low[0x20];
1297
b4ff3a36 1298 u8 reserved_at_180[0xc0];
e281682b
SM		 1299
1300 u8 tx_frames_high[0x20];
1301
1302 u8 tx_frames_low[0x20];
1303
1304 u8 rx_pause_high[0x20];
1305
1306 u8 rx_pause_low[0x20];
1307
1308 u8 rx_pause_duration_high[0x20];
1309
1310 u8 rx_pause_duration_low[0x20];
1311
1312 u8 tx_pause_high[0x20];
1313
1314 u8 tx_pause_low[0x20];
1315
1316 u8 tx_pause_duration_high[0x20];
1317
1318 u8 tx_pause_duration_low[0x20];
1319
1320 u8 rx_pause_transition_high[0x20];
1321
1322 u8 rx_pause_transition_low[0x20];
1323
b4ff3a36 1324 u8 reserved_at_3c0[0x400];
e281682b
SM		 1325};
1326
1327struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1328 u8 port_transmit_wait_high[0x20];
1329
1330 u8 port_transmit_wait_low[0x20];
1331
b4ff3a36 1332 u8 reserved_at_40[0x780];
e281682b
SM		 1333};
1334
1335struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1336 u8 dot3stats_alignment_errors_high[0x20];
1337
1338 u8 dot3stats_alignment_errors_low[0x20];
1339
1340 u8 dot3stats_fcs_errors_high[0x20];
1341
1342 u8 dot3stats_fcs_errors_low[0x20];
1343
1344 u8 dot3stats_single_collision_frames_high[0x20];
1345
1346 u8 dot3stats_single_collision_frames_low[0x20];
1347
1348 u8 dot3stats_multiple_collision_frames_high[0x20];
1349
1350 u8 dot3stats_multiple_collision_frames_low[0x20];
1351
1352 u8 dot3stats_sqe_test_errors_high[0x20];
1353
1354 u8 dot3stats_sqe_test_errors_low[0x20];
1355
1356 u8 dot3stats_deferred_transmissions_high[0x20];
1357
1358 u8 dot3stats_deferred_transmissions_low[0x20];
1359
1360 u8 dot3stats_late_collisions_high[0x20];
1361
1362 u8 dot3stats_late_collisions_low[0x20];
1363
1364 u8 dot3stats_excessive_collisions_high[0x20];
1365
1366 u8 dot3stats_excessive_collisions_low[0x20];
1367
1368 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1369
1370 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1371
1372 u8 dot3stats_carrier_sense_errors_high[0x20];
1373
1374 u8 dot3stats_carrier_sense_errors_low[0x20];
1375
1376 u8 dot3stats_frame_too_longs_high[0x20];
1377
1378 u8 dot3stats_frame_too_longs_low[0x20];
1379
1380 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1381
1382 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1383
1384 u8 dot3stats_symbol_errors_high[0x20];
1385
1386 u8 dot3stats_symbol_errors_low[0x20];
1387
1388 u8 dot3control_in_unknown_opcodes_high[0x20];
1389
1390 u8 dot3control_in_unknown_opcodes_low[0x20];
1391
1392 u8 dot3in_pause_frames_high[0x20];
1393
1394 u8 dot3in_pause_frames_low[0x20];
1395
1396 u8 dot3out_pause_frames_high[0x20];
1397
1398 u8 dot3out_pause_frames_low[0x20];
1399
b4ff3a36 1400 u8 reserved_at_400[0x3c0];
e281682b
SM		 1401};
1402
1403struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1404 u8 ether_stats_drop_events_high[0x20];
1405
1406 u8 ether_stats_drop_events_low[0x20];
1407
1408 u8 ether_stats_octets_high[0x20];
1409
1410 u8 ether_stats_octets_low[0x20];
1411
1412 u8 ether_stats_pkts_high[0x20];
1413
1414 u8 ether_stats_pkts_low[0x20];
1415
1416 u8 ether_stats_broadcast_pkts_high[0x20];
1417
1418 u8 ether_stats_broadcast_pkts_low[0x20];
1419
1420 u8 ether_stats_multicast_pkts_high[0x20];
1421
1422 u8 ether_stats_multicast_pkts_low[0x20];
1423
1424 u8 ether_stats_crc_align_errors_high[0x20];
1425
1426 u8 ether_stats_crc_align_errors_low[0x20];
1427
1428 u8 ether_stats_undersize_pkts_high[0x20];
1429
1430 u8 ether_stats_undersize_pkts_low[0x20];
1431
1432 u8 ether_stats_oversize_pkts_high[0x20];
1433
1434 u8 ether_stats_oversize_pkts_low[0x20];
1435
1436 u8 ether_stats_fragments_high[0x20];
1437
1438 u8 ether_stats_fragments_low[0x20];
1439
1440 u8 ether_stats_jabbers_high[0x20];
1441
1442 u8 ether_stats_jabbers_low[0x20];
1443
1444 u8 ether_stats_collisions_high[0x20];
1445
1446 u8 ether_stats_collisions_low[0x20];
1447
1448 u8 ether_stats_pkts64octets_high[0x20];
1449
1450 u8 ether_stats_pkts64octets_low[0x20];
1451
1452 u8 ether_stats_pkts65to127octets_high[0x20];
1453
1454 u8 ether_stats_pkts65to127octets_low[0x20];
1455
1456 u8 ether_stats_pkts128to255octets_high[0x20];
1457
1458 u8 ether_stats_pkts128to255octets_low[0x20];
1459
1460 u8 ether_stats_pkts256to511octets_high[0x20];
1461
1462 u8 ether_stats_pkts256to511octets_low[0x20];
1463
1464 u8 ether_stats_pkts512to1023octets_high[0x20];
1465
1466 u8 ether_stats_pkts512to1023octets_low[0x20];
1467
1468 u8 ether_stats_pkts1024to1518octets_high[0x20];
1469
1470 u8 ether_stats_pkts1024to1518octets_low[0x20];
1471
1472 u8 ether_stats_pkts1519to2047octets_high[0x20];
1473
1474 u8 ether_stats_pkts1519to2047octets_low[0x20];
1475
1476 u8 ether_stats_pkts2048to4095octets_high[0x20];
1477
1478 u8 ether_stats_pkts2048to4095octets_low[0x20];
1479
1480 u8 ether_stats_pkts4096to8191octets_high[0x20];
1481
1482 u8 ether_stats_pkts4096to8191octets_low[0x20];
1483
1484 u8 ether_stats_pkts8192to10239octets_high[0x20];
1485
1486 u8 ether_stats_pkts8192to10239octets_low[0x20];
1487
b4ff3a36 1488 u8 reserved_at_540[0x280];
e281682b
SM		 1489};
1490
1491struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1492 u8 if_in_octets_high[0x20];
1493
1494 u8 if_in_octets_low[0x20];
1495
1496 u8 if_in_ucast_pkts_high[0x20];
1497
1498 u8 if_in_ucast_pkts_low[0x20];
1499
1500 u8 if_in_discards_high[0x20];
1501
1502 u8 if_in_discards_low[0x20];
1503
1504 u8 if_in_errors_high[0x20];
1505
1506 u8 if_in_errors_low[0x20];
1507
1508 u8 if_in_unknown_protos_high[0x20];
1509
1510 u8 if_in_unknown_protos_low[0x20];
1511
1512 u8 if_out_octets_high[0x20];
1513
1514 u8 if_out_octets_low[0x20];
1515
1516 u8 if_out_ucast_pkts_high[0x20];
1517
1518 u8 if_out_ucast_pkts_low[0x20];
1519
1520 u8 if_out_discards_high[0x20];
1521
1522 u8 if_out_discards_low[0x20];
1523
1524 u8 if_out_errors_high[0x20];
1525
1526 u8 if_out_errors_low[0x20];
1527
1528 u8 if_in_multicast_pkts_high[0x20];
1529
1530 u8 if_in_multicast_pkts_low[0x20];
1531
1532 u8 if_in_broadcast_pkts_high[0x20];
1533
1534 u8 if_in_broadcast_pkts_low[0x20];
1535
1536 u8 if_out_multicast_pkts_high[0x20];
1537
1538 u8 if_out_multicast_pkts_low[0x20];
1539
1540 u8 if_out_broadcast_pkts_high[0x20];
1541
1542 u8 if_out_broadcast_pkts_low[0x20];
1543
b4ff3a36 1544 u8 reserved_at_340[0x480];
e281682b
SM		 1545};
1546
1547struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1548 u8 a_frames_transmitted_ok_high[0x20];
1549
1550 u8 a_frames_transmitted_ok_low[0x20];
1551
1552 u8 a_frames_received_ok_high[0x20];
1553
1554 u8 a_frames_received_ok_low[0x20];
1555
1556 u8 a_frame_check_sequence_errors_high[0x20];
1557
1558 u8 a_frame_check_sequence_errors_low[0x20];
1559
1560 u8 a_alignment_errors_high[0x20];
1561
1562 u8 a_alignment_errors_low[0x20];
1563
1564 u8 a_octets_transmitted_ok_high[0x20];
1565
1566 u8 a_octets_transmitted_ok_low[0x20];
1567
1568 u8 a_octets_received_ok_high[0x20];
1569
1570 u8 a_octets_received_ok_low[0x20];
1571
1572 u8 a_multicast_frames_xmitted_ok_high[0x20];
1573
1574 u8 a_multicast_frames_xmitted_ok_low[0x20];
1575
1576 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1577
1578 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1579
1580 u8 a_multicast_frames_received_ok_high[0x20];
1581
1582 u8 a_multicast_frames_received_ok_low[0x20];
1583
1584 u8 a_broadcast_frames_received_ok_high[0x20];
1585
1586 u8 a_broadcast_frames_received_ok_low[0x20];
1587
1588 u8 a_in_range_length_errors_high[0x20];
1589
1590 u8 a_in_range_length_errors_low[0x20];
1591
1592 u8 a_out_of_range_length_field_high[0x20];
1593
1594 u8 a_out_of_range_length_field_low[0x20];
1595
1596 u8 a_frame_too_long_errors_high[0x20];
1597
1598 u8 a_frame_too_long_errors_low[0x20];
1599
1600 u8 a_symbol_error_during_carrier_high[0x20];
1601
1602 u8 a_symbol_error_during_carrier_low[0x20];
1603
1604 u8 a_mac_control_frames_transmitted_high[0x20];
1605
1606 u8 a_mac_control_frames_transmitted_low[0x20];
1607
1608 u8 a_mac_control_frames_received_high[0x20];
1609
1610 u8 a_mac_control_frames_received_low[0x20];
1611
1612 u8 a_unsupported_opcodes_received_high[0x20];
1613
1614 u8 a_unsupported_opcodes_received_low[0x20];
1615
1616 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1617
1618 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1619
1620 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1621
1622 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1623
b4ff3a36 1624 u8 reserved_at_4c0[0x300];
e281682b
SM		 1625};
1626
1627struct mlx5_ifc_cmd_inter_comp_event_bits {
1628 u8 command_completion_vector[0x20];
1629
b4ff3a36 1630 u8 reserved_at_20[0xc0];
e281682b
SM		 1631};
1632
1633struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1634 u8 reserved_at_0[0x18];
e281682b 1635 u8 port_num[0x1];
b4ff3a36 1636 u8 reserved_at_19[0x3];
e281682b
SM		 1637 u8 vl[0x4];
1638
b4ff3a36 1639 u8 reserved_at_20[0xa0];
e281682b
SM		 1640};
1641
1642struct mlx5_ifc_db_bf_congestion_event_bits {
1643 u8 event_subtype[0x8];
b4ff3a36 1644 u8 reserved_at_8[0x8];
e281682b 1645 u8 congestion_level[0x8];
b4ff3a36 1646 u8 reserved_at_18[0x8];
e281682b 1647
b4ff3a36 1648 u8 reserved_at_20[0xa0];
e281682b
SM		 1649};
1650
1651struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1652 u8 reserved_at_0[0x60];
e281682b
SM		 1653
1654 u8 gpio_event_hi[0x20];
1655
1656 u8 gpio_event_lo[0x20];
1657
b4ff3a36 1658 u8 reserved_at_a0[0x40];
e281682b
SM		 1659};
1660
1661struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1662 u8 reserved_at_0[0x40];
e281682b
SM		 1663
1664 u8 port_num[0x4];
b4ff3a36 1665 u8 reserved_at_44[0x1c];
e281682b 1666
b4ff3a36 1667 u8 reserved_at_60[0x80];
e281682b
SM		 1668};
1669
1670struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1671 u8 reserved_at_0[0xe0];
e281682b
SM		 1672};
1673
1674enum {
1675 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1676 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1677};
1678
1679struct mlx5_ifc_cq_error_bits {
b4ff3a36 1680 u8 reserved_at_0[0x8];
e281682b
SM		 1681 u8 cqn[0x18];
1682
b4ff3a36 1683 u8 reserved_at_20[0x20];
e281682b 1684
b4ff3a36 1685 u8 reserved_at_40[0x18];
e281682b
SM		 1686 u8 syndrome[0x8];
1687
b4ff3a36 1688 u8 reserved_at_60[0x80];
e281682b
SM		 1689};
1690
1691struct mlx5_ifc_rdma_page_fault_event_bits {
1692 u8 bytes_committed[0x20];
1693
1694 u8 r_key[0x20];
1695
b4ff3a36 1696 u8 reserved_at_40[0x10];
e281682b
SM		 1697 u8 packet_len[0x10];
1698
1699 u8 rdma_op_len[0x20];
1700
1701 u8 rdma_va[0x40];
1702
b4ff3a36 1703 u8 reserved_at_c0[0x5];
e281682b
SM		 1704 u8 rdma[0x1];
1705 u8 write[0x1];
1706 u8 requestor[0x1];
1707 u8 qp_number[0x18];
1708};
1709
1710struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1711 u8 bytes_committed[0x20];
1712
b4ff3a36 1713 u8 reserved_at_20[0x10];
e281682b
SM		 1714 u8 wqe_index[0x10];
1715
b4ff3a36 1716 u8 reserved_at_40[0x10];
e281682b
SM		 1717 u8 len[0x10];
1718
b4ff3a36 1719 u8 reserved_at_60[0x60];
e281682b 1720
b4ff3a36 1721 u8 reserved_at_c0[0x5];
e281682b
SM		 1722 u8 rdma[0x1];
1723 u8 write_read[0x1];
1724 u8 requestor[0x1];
1725 u8 qpn[0x18];
1726};
1727
1728struct mlx5_ifc_qp_events_bits {
b4ff3a36 1729 u8 reserved_at_0[0xa0];
e281682b
SM		 1730
1731 u8 type[0x8];
b4ff3a36 1732 u8 reserved_at_a8[0x18];
e281682b 1733
b4ff3a36 1734 u8 reserved_at_c0[0x8];
e281682b
SM		 1735 u8 qpn_rqn_sqn[0x18];
1736};
1737
1738struct mlx5_ifc_dct_events_bits {
b4ff3a36 1739 u8 reserved_at_0[0xc0];
e281682b 1740
b4ff3a36 1741 u8 reserved_at_c0[0x8];
e281682b
SM		 1742 u8 dct_number[0x18];
1743};
1744
1745struct mlx5_ifc_comp_event_bits {
b4ff3a36 1746 u8 reserved_at_0[0xc0];
e281682b 1747
b4ff3a36 1748 u8 reserved_at_c0[0x8];
e281682b
SM		 1749 u8 cq_number[0x18];
1750};
1751
1752enum {
1753 MLX5_QPC_STATE_RST = 0x0,
1754 MLX5_QPC_STATE_INIT = 0x1,
1755 MLX5_QPC_STATE_RTR = 0x2,
1756 MLX5_QPC_STATE_RTS = 0x3,
1757 MLX5_QPC_STATE_SQER = 0x4,
1758 MLX5_QPC_STATE_ERR = 0x6,
1759 MLX5_QPC_STATE_SQD = 0x7,
1760 MLX5_QPC_STATE_SUSPENDED = 0x9,
1761};
1762
1763enum {
1764 MLX5_QPC_ST_RC = 0x0,
1765 MLX5_QPC_ST_UC = 0x1,
1766 MLX5_QPC_ST_UD = 0x2,
1767 MLX5_QPC_ST_XRC = 0x3,
1768 MLX5_QPC_ST_DCI = 0x5,
1769 MLX5_QPC_ST_QP0 = 0x7,
1770 MLX5_QPC_ST_QP1 = 0x8,
1771 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1772 MLX5_QPC_ST_REG_UMR = 0xc,
1773};
1774
1775enum {
1776 MLX5_QPC_PM_STATE_ARMED = 0x0,
1777 MLX5_QPC_PM_STATE_REARM = 0x1,
1778 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1779 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1780};
1781
1782enum {
1783 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1784 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1785};
1786
1787enum {
1788 MLX5_QPC_MTU_256_BYTES = 0x1,
1789 MLX5_QPC_MTU_512_BYTES = 0x2,
1790 MLX5_QPC_MTU_1K_BYTES = 0x3,
1791 MLX5_QPC_MTU_2K_BYTES = 0x4,
1792 MLX5_QPC_MTU_4K_BYTES = 0x5,
1793 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1794};
1795
1796enum {
1797 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1798 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1799 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1800 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1801 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1802 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1803 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1804 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1805};
1806
1807enum {
1808 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1809 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1810 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1811};
1812
1813enum {
1814 MLX5_QPC_CS_RES_DISABLE = 0x0,
1815 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1816 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1817};
1818
1819struct mlx5_ifc_qpc_bits {
1820 u8 state[0x4];
b4ff3a36 1821 u8 reserved_at_4[0x4];
e281682b 1822 u8 st[0x8];
b4ff3a36 1823 u8 reserved_at_10[0x3];
e281682b 1824 u8 pm_state[0x2];
b4ff3a36 1825 u8 reserved_at_15[0x7];
e281682b 1826 u8 end_padding_mode[0x2];
b4ff3a36 1827 u8 reserved_at_1e[0x2];
e281682b
SM		 1828
1829 u8 wq_signature[0x1];
1830 u8 block_lb_mc[0x1];
1831 u8 atomic_like_write_en[0x1];
1832 u8 latency_sensitive[0x1];
b4ff3a36 1833 u8 reserved_at_24[0x1];
e281682b 1834 u8 drain_sigerr[0x1];
b4ff3a36 1835 u8 reserved_at_26[0x2];
e281682b
SM		 1836 u8 pd[0x18];
1837
1838 u8 mtu[0x3];
1839 u8 log_msg_max[0x5];
b4ff3a36 1840 u8 reserved_at_48[0x1];
e281682b
SM		 1841 u8 log_rq_size[0x4];
1842 u8 log_rq_stride[0x3];
1843 u8 no_sq[0x1];
1844 u8 log_sq_size[0x4];
b4ff3a36 1845 u8 reserved_at_55[0x6];
e281682b 1846 u8 rlky[0x1];
1015c2e8 1847 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 1848
1849 u8 counter_set_id[0x8];
1850 u8 uar_page[0x18];
1851
b4ff3a36 1852 u8 reserved_at_80[0x8];
e281682b
SM		 1853 u8 user_index[0x18];
1854
b4ff3a36 1855 u8 reserved_at_a0[0x3];
e281682b
SM		 1856 u8 log_page_size[0x5];
1857 u8 remote_qpn[0x18];
1858
1859 struct mlx5_ifc_ads_bits primary_address_path;
1860
1861 struct mlx5_ifc_ads_bits secondary_address_path;
1862
1863 u8 log_ack_req_freq[0x4];
b4ff3a36 1864 u8 reserved_at_384[0x4];
e281682b 1865 u8 log_sra_max[0x3];
b4ff3a36 1866 u8 reserved_at_38b[0x2];
e281682b
SM		 1867 u8 retry_count[0x3];
1868 u8 rnr_retry[0x3];
b4ff3a36 1869 u8 reserved_at_393[0x1];
e281682b
SM		 1870 u8 fre[0x1];
1871 u8 cur_rnr_retry[0x3];
1872 u8 cur_retry_count[0x3];
b4ff3a36 1873 u8 reserved_at_39b[0x5];
e281682b 1874
b4ff3a36 1875 u8 reserved_at_3a0[0x20];
e281682b 1876
b4ff3a36 1877 u8 reserved_at_3c0[0x8];
e281682b
SM		 1878 u8 next_send_psn[0x18];
1879
b4ff3a36 1880 u8 reserved_at_3e0[0x8];
e281682b
SM		 1881 u8 cqn_snd[0x18];
1882
b4ff3a36 1883 u8 reserved_at_400[0x40];
e281682b 1884
b4ff3a36 1885 u8 reserved_at_440[0x8];
e281682b
SM		 1886 u8 last_acked_psn[0x18];
1887
b4ff3a36 1888 u8 reserved_at_460[0x8];
e281682b
SM		 1889 u8 ssn[0x18];
1890
b4ff3a36 1891 u8 reserved_at_480[0x8];
e281682b 1892 u8 log_rra_max[0x3];
b4ff3a36 1893 u8 reserved_at_48b[0x1];
e281682b
SM		 1894 u8 atomic_mode[0x4];
1895 u8 rre[0x1];
1896 u8 rwe[0x1];
1897 u8 rae[0x1];
b4ff3a36 1898 u8 reserved_at_493[0x1];
e281682b 1899 u8 page_offset[0x6];
b4ff3a36 1900 u8 reserved_at_49a[0x3];
e281682b
SM		 1901 u8 cd_slave_receive[0x1];
1902 u8 cd_slave_send[0x1];
1903 u8 cd_master[0x1];
1904
b4ff3a36 1905 u8 reserved_at_4a0[0x3];
e281682b
SM		 1906 u8 min_rnr_nak[0x5];
1907 u8 next_rcv_psn[0x18];
1908
b4ff3a36 1909 u8 reserved_at_4c0[0x8];
e281682b
SM		 1910 u8 xrcd[0x18];
1911
b4ff3a36 1912 u8 reserved_at_4e0[0x8];
e281682b
SM		 1913 u8 cqn_rcv[0x18];
1914
1915 u8 dbr_addr[0x40];
1916
1917 u8 q_key[0x20];
1918
b4ff3a36 1919 u8 reserved_at_560[0x5];
e281682b
SM		 1920 u8 rq_type[0x3];
1921 u8 srqn_rmpn[0x18];
1922
b4ff3a36 1923 u8 reserved_at_580[0x8];
e281682b
SM		 1924 u8 rmsn[0x18];
1925
1926 u8 hw_sq_wqebb_counter[0x10];
1927 u8 sw_sq_wqebb_counter[0x10];
1928
1929 u8 hw_rq_counter[0x20];
1930
1931 u8 sw_rq_counter[0x20];
1932
b4ff3a36 1933 u8 reserved_at_600[0x20];
e281682b 1934
b4ff3a36 1935 u8 reserved_at_620[0xf];
e281682b
SM		 1936 u8 cgs[0x1];
1937 u8 cs_req[0x8];
1938 u8 cs_res[0x8];
1939
1940 u8 dc_access_key[0x40];
1941
b4ff3a36 1942 u8 reserved_at_680[0xc0];
e281682b
SM		 1943};
1944
1945struct mlx5_ifc_roce_addr_layout_bits {
1946 u8 source_l3_address[16][0x8];
1947
b4ff3a36 1948 u8 reserved_at_80[0x3];
e281682b
SM		 1949 u8 vlan_valid[0x1];
1950 u8 vlan_id[0xc];
1951 u8 source_mac_47_32[0x10];
1952
1953 u8 source_mac_31_0[0x20];
1954
b4ff3a36 1955 u8 reserved_at_c0[0x14];
e281682b
SM		 1956 u8 roce_l3_type[0x4];
1957 u8 roce_version[0x8];
1958
b4ff3a36 1959 u8 reserved_at_e0[0x20];
e281682b
SM		 1960};
1961
1962union mlx5_ifc_hca_cap_union_bits {
1963 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1964 struct mlx5_ifc_odp_cap_bits odp_cap;
1965 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1966 struct mlx5_ifc_roce_cap_bits roce_cap;
1967 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1968 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 1969 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 1970 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 1971 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
b4ff3a36 1972 u8 reserved_at_0[0x8000];
e281682b
SM		 1973};
1974
1975enum {
1976 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1977 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1978 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1979};
1980
1981struct mlx5_ifc_flow_context_bits {
b4ff3a36 1982 u8 reserved_at_0[0x20];
e281682b
SM		 1983
1984 u8 group_id[0x20];
1985
b4ff3a36 1986 u8 reserved_at_40[0x8];
e281682b
SM		 1987 u8 flow_tag[0x18];
1988
b4ff3a36 1989 u8 reserved_at_60[0x10];
e281682b
SM		 1990 u8 action[0x10];
1991
b4ff3a36 1992 u8 reserved_at_80[0x8];
e281682b
SM		 1993 u8 destination_list_size[0x18];
1994
b4ff3a36 1995 u8 reserved_at_a0[0x160];
e281682b
SM		 1996
1997 struct mlx5_ifc_fte_match_param_bits match_value;
1998
b4ff3a36 1999 u8 reserved_at_1200[0x600];
e281682b
SM		 2000
2001 struct mlx5_ifc_dest_format_struct_bits destination[0];
2002};
2003
2004enum {
2005 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2006 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2007};
2008
2009struct mlx5_ifc_xrc_srqc_bits {
2010 u8 state[0x4];
2011 u8 log_xrc_srq_size[0x4];
b4ff3a36 2012 u8 reserved_at_8[0x18];
e281682b
SM		 2013
2014 u8 wq_signature[0x1];
2015 u8 cont_srq[0x1];
b4ff3a36 2016 u8 reserved_at_22[0x1];
e281682b
SM		 2017 u8 rlky[0x1];
2018 u8 basic_cyclic_rcv_wqe[0x1];
2019 u8 log_rq_stride[0x3];
2020 u8 xrcd[0x18];
2021
2022 u8 page_offset[0x6];
b4ff3a36 2023 u8 reserved_at_46[0x2];
e281682b
SM		 2024 u8 cqn[0x18];
2025
b4ff3a36 2026 u8 reserved_at_60[0x20];
e281682b
SM		 2027
2028 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2029 u8 reserved_at_81[0x1];
e281682b
SM		 2030 u8 log_page_size[0x6];
2031 u8 user_index[0x18];
2032
b4ff3a36 2033 u8 reserved_at_a0[0x20];
e281682b 2034
b4ff3a36 2035 u8 reserved_at_c0[0x8];
e281682b
SM		 2036 u8 pd[0x18];
2037
2038 u8 lwm[0x10];
2039 u8 wqe_cnt[0x10];
2040
b4ff3a36 2041 u8 reserved_at_100[0x40];
e281682b
SM		 2042
2043 u8 db_record_addr_h[0x20];
2044
2045 u8 db_record_addr_l[0x1e];
b4ff3a36 2046 u8 reserved_at_17e[0x2];
e281682b 2047
b4ff3a36 2048 u8 reserved_at_180[0x80];
e281682b
SM		 2049};
2050
2051struct mlx5_ifc_traffic_counter_bits {
2052 u8 packets[0x40];
2053
2054 u8 octets[0x40];
2055};
2056
2057struct mlx5_ifc_tisc_bits {
b4ff3a36 2058 u8 reserved_at_0[0xc];
e281682b 2059 u8 prio[0x4];
b4ff3a36 2060 u8 reserved_at_10[0x10];
e281682b 2061
b4ff3a36 2062 u8 reserved_at_20[0x100];
e281682b 2063
b4ff3a36 2064 u8 reserved_at_120[0x8];
e281682b
SM		 2065 u8 transport_domain[0x18];
2066
b4ff3a36 2067 u8 reserved_at_140[0x3c0];
e281682b
SM		 2068};
2069
2070enum {
2071 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2072 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2073};
2074
2075enum {
2076 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2077 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2078};
2079
2080enum {
2be6967c
SM		 2081 MLX5_RX_HASH_FN_NONE = 0x0,
2082 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2083 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2084};
2085
2086enum {
2087 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2088 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2089};
2090
2091struct mlx5_ifc_tirc_bits {
b4ff3a36 2092 u8 reserved_at_0[0x20];
e281682b
SM		 2093
2094 u8 disp_type[0x4];
b4ff3a36 2095 u8 reserved_at_24[0x1c];
e281682b 2096
b4ff3a36 2097 u8 reserved_at_40[0x40];
e281682b 2098
b4ff3a36 2099 u8 reserved_at_80[0x4];
e281682b
SM		 2100 u8 lro_timeout_period_usecs[0x10];
2101 u8 lro_enable_mask[0x4];
2102 u8 lro_max_ip_payload_size[0x8];
2103
b4ff3a36 2104 u8 reserved_at_a0[0x40];
e281682b 2105
b4ff3a36 2106 u8 reserved_at_e0[0x8];
e281682b
SM		 2107 u8 inline_rqn[0x18];
2108
2109 u8 rx_hash_symmetric[0x1];
b4ff3a36 2110 u8 reserved_at_101[0x1];
e281682b 2111 u8 tunneled_offload_en[0x1];
b4ff3a36 2112 u8 reserved_at_103[0x5];
e281682b
SM		 2113 u8 indirect_table[0x18];
2114
2115 u8 rx_hash_fn[0x4];
b4ff3a36 2116 u8 reserved_at_124[0x2];
e281682b
SM		 2117 u8 self_lb_block[0x2];
2118 u8 transport_domain[0x18];
2119
2120 u8 rx_hash_toeplitz_key[10][0x20];
2121
2122 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2123
2124 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2125
b4ff3a36 2126 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2127};
2128
2129enum {
2130 MLX5_SRQC_STATE_GOOD = 0x0,
2131 MLX5_SRQC_STATE_ERROR = 0x1,
2132};
2133
2134struct mlx5_ifc_srqc_bits {
2135 u8 state[0x4];
2136 u8 log_srq_size[0x4];
b4ff3a36 2137 u8 reserved_at_8[0x18];
e281682b
SM		 2138
2139 u8 wq_signature[0x1];
2140 u8 cont_srq[0x1];
b4ff3a36 2141 u8 reserved_at_22[0x1];
e281682b 2142 u8 rlky[0x1];
b4ff3a36 2143 u8 reserved_at_24[0x1];
e281682b
SM		 2144 u8 log_rq_stride[0x3];
2145 u8 xrcd[0x18];
2146
2147 u8 page_offset[0x6];
b4ff3a36 2148 u8 reserved_at_46[0x2];
e281682b
SM		 2149 u8 cqn[0x18];
2150
b4ff3a36 2151 u8 reserved_at_60[0x20];
e281682b 2152
b4ff3a36 2153 u8 reserved_at_80[0x2];
e281682b 2154 u8 log_page_size[0x6];
b4ff3a36 2155 u8 reserved_at_88[0x18];
e281682b 2156
b4ff3a36 2157 u8 reserved_at_a0[0x20];
e281682b 2158
b4ff3a36 2159 u8 reserved_at_c0[0x8];
e281682b
SM		 2160 u8 pd[0x18];
2161
2162 u8 lwm[0x10];
2163 u8 wqe_cnt[0x10];
2164
b4ff3a36 2165 u8 reserved_at_100[0x40];
e281682b 2166
01949d01 2167 u8 dbr_addr[0x40];
e281682b 2168
b4ff3a36 2169 u8 reserved_at_180[0x80];
e281682b
SM		 2170};
2171
2172enum {
2173 MLX5_SQC_STATE_RST = 0x0,
2174 MLX5_SQC_STATE_RDY = 0x1,
2175 MLX5_SQC_STATE_ERR = 0x3,
2176};
2177
2178struct mlx5_ifc_sqc_bits {
2179 u8 rlky[0x1];
2180 u8 cd_master[0x1];
2181 u8 fre[0x1];
2182 u8 flush_in_error_en[0x1];
b4ff3a36 2183 u8 reserved_at_4[0x4];
e281682b 2184 u8 state[0x4];
b4ff3a36 2185 u8 reserved_at_c[0x14];
e281682b 2186
b4ff3a36 2187 u8 reserved_at_20[0x8];
e281682b
SM		 2188 u8 user_index[0x18];
2189
b4ff3a36 2190 u8 reserved_at_40[0x8];
e281682b
SM		 2191 u8 cqn[0x18];
2192
b4ff3a36 2193 u8 reserved_at_60[0xa0];
e281682b
SM		 2194
2195 u8 tis_lst_sz[0x10];
b4ff3a36 2196 u8 reserved_at_110[0x10];
e281682b 2197
b4ff3a36 2198 u8 reserved_at_120[0x40];
e281682b 2199
b4ff3a36 2200 u8 reserved_at_160[0x8];
e281682b
SM		 2201 u8 tis_num_0[0x18];
2202
2203 struct mlx5_ifc_wq_bits wq;
2204};
2205
2206struct mlx5_ifc_rqtc_bits {
b4ff3a36 2207 u8 reserved_at_0[0xa0];
e281682b 2208
b4ff3a36 2209 u8 reserved_at_a0[0x10];
e281682b
SM		 2210 u8 rqt_max_size[0x10];
2211
b4ff3a36 2212 u8 reserved_at_c0[0x10];
e281682b
SM		 2213 u8 rqt_actual_size[0x10];
2214
b4ff3a36 2215 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2216
2217 struct mlx5_ifc_rq_num_bits rq_num[0];
2218};
2219
2220enum {
2221 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2222 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2223};
2224
2225enum {
2226 MLX5_RQC_STATE_RST = 0x0,
2227 MLX5_RQC_STATE_RDY = 0x1,
2228 MLX5_RQC_STATE_ERR = 0x3,
2229};
2230
2231struct mlx5_ifc_rqc_bits {
2232 u8 rlky[0x1];
b4ff3a36 2233 u8 reserved_at_1[0x2];
e281682b
SM		 2234 u8 vsd[0x1];
2235 u8 mem_rq_type[0x4];
2236 u8 state[0x4];
b4ff3a36 2237 u8 reserved_at_c[0x1];
e281682b 2238 u8 flush_in_error_en[0x1];
b4ff3a36 2239 u8 reserved_at_e[0x12];
e281682b 2240
b4ff3a36 2241 u8 reserved_at_20[0x8];
e281682b
SM		 2242 u8 user_index[0x18];
2243
b4ff3a36 2244 u8 reserved_at_40[0x8];
e281682b
SM		 2245 u8 cqn[0x18];
2246
2247 u8 counter_set_id[0x8];
b4ff3a36 2248 u8 reserved_at_68[0x18];
e281682b 2249
b4ff3a36 2250 u8 reserved_at_80[0x8];
e281682b
SM		 2251 u8 rmpn[0x18];
2252
b4ff3a36 2253 u8 reserved_at_a0[0xe0];
e281682b
SM		 2254
2255 struct mlx5_ifc_wq_bits wq;
2256};
2257
2258enum {
2259 MLX5_RMPC_STATE_RDY = 0x1,
2260 MLX5_RMPC_STATE_ERR = 0x3,
2261};
2262
2263struct mlx5_ifc_rmpc_bits {
b4ff3a36 2264 u8 reserved_at_0[0x8];
e281682b 2265 u8 state[0x4];
b4ff3a36 2266 u8 reserved_at_c[0x14];
e281682b
SM		 2267
2268 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2269 u8 reserved_at_21[0x1f];
e281682b 2270
b4ff3a36 2271 u8 reserved_at_40[0x140];
e281682b
SM		 2272
2273 struct mlx5_ifc_wq_bits wq;
2274};
2275
e281682b 2276struct mlx5_ifc_nic_vport_context_bits {
b4ff3a36 2277 u8 reserved_at_0[0x1f];
e281682b
SM		 2278 u8 roce_en[0x1];
2279
d82b7318 2280 u8 arm_change_event[0x1];
b4ff3a36 2281 u8 reserved_at_21[0x1a];
d82b7318
SM		 2282 u8 event_on_mtu[0x1];
2283 u8 event_on_promisc_change[0x1];
2284 u8 event_on_vlan_change[0x1];
2285 u8 event_on_mc_address_change[0x1];
2286 u8 event_on_uc_address_change[0x1];
e281682b 2287
b4ff3a36 2288 u8 reserved_at_40[0xf0];
d82b7318
SM		 2289
2290 u8 mtu[0x10];
2291
9efa7525
AS		 2292 u8 system_image_guid[0x40];
2293 u8 port_guid[0x40];
2294 u8 node_guid[0x40];
2295
b4ff3a36 2296 u8 reserved_at_200[0x140];
9efa7525 2297 u8 qkey_violation_counter[0x10];
b4ff3a36 2298 u8 reserved_at_350[0x430];
d82b7318
SM		 2299
2300 u8 promisc_uc[0x1];
2301 u8 promisc_mc[0x1];
2302 u8 promisc_all[0x1];
b4ff3a36 2303 u8 reserved_at_783[0x2];
e281682b 2304 u8 allowed_list_type[0x3];
b4ff3a36 2305 u8 reserved_at_788[0xc];
e281682b
SM		 2306 u8 allowed_list_size[0xc];
2307
2308 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2309
b4ff3a36 2310 u8 reserved_at_7e0[0x20];
e281682b
SM		 2311
2312 u8 current_uc_mac_address[0][0x40];
2313};
2314
2315enum {
2316 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2317 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2318 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2319};
2320
2321struct mlx5_ifc_mkc_bits {
b4ff3a36 2322 u8 reserved_at_0[0x1];
e281682b 2323 u8 free[0x1];
b4ff3a36 2324 u8 reserved_at_2[0xd];
e281682b
SM		 2325 u8 small_fence_on_rdma_read_response[0x1];
2326 u8 umr_en[0x1];
2327 u8 a[0x1];
2328 u8 rw[0x1];
2329 u8 rr[0x1];
2330 u8 lw[0x1];
2331 u8 lr[0x1];
2332 u8 access_mode[0x2];
b4ff3a36 2333 u8 reserved_at_18[0x8];
e281682b
SM		 2334
2335 u8 qpn[0x18];
2336 u8 mkey_7_0[0x8];
2337
b4ff3a36 2338 u8 reserved_at_40[0x20];
e281682b
SM		 2339
2340 u8 length64[0x1];
2341 u8 bsf_en[0x1];
2342 u8 sync_umr[0x1];
b4ff3a36 2343 u8 reserved_at_63[0x2];
e281682b 2344 u8 expected_sigerr_count[0x1];
b4ff3a36 2345 u8 reserved_at_66[0x1];
e281682b
SM		 2346 u8 en_rinval[0x1];
2347 u8 pd[0x18];
2348
2349 u8 start_addr[0x40];
2350
2351 u8 len[0x40];
2352
2353 u8 bsf_octword_size[0x20];
2354
b4ff3a36 2355 u8 reserved_at_120[0x80];
e281682b
SM		 2356
2357 u8 translations_octword_size[0x20];
2358
b4ff3a36 2359 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2360 u8 log_page_size[0x5];
2361
b4ff3a36 2362 u8 reserved_at_1e0[0x20];
e281682b
SM		 2363};
2364
2365struct mlx5_ifc_pkey_bits {
b4ff3a36 2366 u8 reserved_at_0[0x10];
e281682b
SM		 2367 u8 pkey[0x10];
2368};
2369
2370struct mlx5_ifc_array128_auto_bits {
2371 u8 array128_auto[16][0x8];
2372};
2373
2374struct mlx5_ifc_hca_vport_context_bits {
2375 u8 field_select[0x20];
2376
b4ff3a36 2377 u8 reserved_at_20[0xe0];
e281682b
SM		 2378
2379 u8 sm_virt_aware[0x1];
2380 u8 has_smi[0x1];
2381 u8 has_raw[0x1];
2382 u8 grh_required[0x1];
b4ff3a36 2383 u8 reserved_at_104[0xc];
707c4602
MD		 2384 u8 port_physical_state[0x4];
2385 u8 vport_state_policy[0x4];
2386 u8 port_state[0x4];
e281682b
SM		 2387 u8 vport_state[0x4];
2388
b4ff3a36 2389 u8 reserved_at_120[0x20];
707c4602
MD		 2390
2391 u8 system_image_guid[0x40];
e281682b
SM		 2392
2393 u8 port_guid[0x40];
2394
2395 u8 node_guid[0x40];
2396
2397 u8 cap_mask1[0x20];
2398
2399 u8 cap_mask1_field_select[0x20];
2400
2401 u8 cap_mask2[0x20];
2402
2403 u8 cap_mask2_field_select[0x20];
2404
b4ff3a36 2405 u8 reserved_at_280[0x80];
e281682b
SM		 2406
2407 u8 lid[0x10];
b4ff3a36 2408 u8 reserved_at_310[0x4];
e281682b
SM		 2409 u8 init_type_reply[0x4];
2410 u8 lmc[0x3];
2411 u8 subnet_timeout[0x5];
2412
2413 u8 sm_lid[0x10];
2414 u8 sm_sl[0x4];
b4ff3a36 2415 u8 reserved_at_334[0xc];
e281682b
SM		 2416
2417 u8 qkey_violation_counter[0x10];
2418 u8 pkey_violation_counter[0x10];
2419
b4ff3a36 2420 u8 reserved_at_360[0xca0];
e281682b
SM		 2421};
2422
d6666753 2423struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2424 u8 reserved_at_0[0x3];
d6666753
SM		 2425 u8 vport_svlan_strip[0x1];
2426 u8 vport_cvlan_strip[0x1];
2427 u8 vport_svlan_insert[0x1];
2428 u8 vport_cvlan_insert[0x2];
b4ff3a36 2429 u8 reserved_at_8[0x18];
d6666753 2430
b4ff3a36 2431 u8 reserved_at_20[0x20];
d6666753
SM		 2432
2433 u8 svlan_cfi[0x1];
2434 u8 svlan_pcp[0x3];
2435 u8 svlan_id[0xc];
2436 u8 cvlan_cfi[0x1];
2437 u8 cvlan_pcp[0x3];
2438 u8 cvlan_id[0xc];
2439
b4ff3a36 2440 u8 reserved_at_60[0x7a0];
d6666753
SM		 2441};
2442
e281682b
SM		 2443enum {
2444 MLX5_EQC_STATUS_OK = 0x0,
2445 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2446};
2447
2448enum {
2449 MLX5_EQC_ST_ARMED = 0x9,
2450 MLX5_EQC_ST_FIRED = 0xa,
2451};
2452
2453struct mlx5_ifc_eqc_bits {
2454 u8 status[0x4];
b4ff3a36 2455 u8 reserved_at_4[0x9];
e281682b
SM		 2456 u8 ec[0x1];
2457 u8 oi[0x1];
b4ff3a36 2458 u8 reserved_at_f[0x5];
e281682b 2459 u8 st[0x4];
b4ff3a36 2460 u8 reserved_at_18[0x8];
e281682b 2461
b4ff3a36 2462 u8 reserved_at_20[0x20];
e281682b 2463
b4ff3a36 2464 u8 reserved_at_40[0x14];
e281682b 2465 u8 page_offset[0x6];
b4ff3a36 2466 u8 reserved_at_5a[0x6];
e281682b 2467
b4ff3a36 2468 u8 reserved_at_60[0x3];
e281682b
SM		 2469 u8 log_eq_size[0x5];
2470 u8 uar_page[0x18];
2471
b4ff3a36 2472 u8 reserved_at_80[0x20];
e281682b 2473
b4ff3a36 2474 u8 reserved_at_a0[0x18];
e281682b
SM		 2475 u8 intr[0x8];
2476
b4ff3a36 2477 u8 reserved_at_c0[0x3];
e281682b 2478 u8 log_page_size[0x5];
b4ff3a36 2479 u8 reserved_at_c8[0x18];
e281682b 2480
b4ff3a36 2481 u8 reserved_at_e0[0x60];
e281682b 2482
b4ff3a36 2483 u8 reserved_at_140[0x8];
e281682b
SM		 2484 u8 consumer_counter[0x18];
2485
b4ff3a36 2486 u8 reserved_at_160[0x8];
e281682b
SM		 2487 u8 producer_counter[0x18];
2488
b4ff3a36 2489 u8 reserved_at_180[0x80];
e281682b
SM		 2490};
2491
2492enum {
2493 MLX5_DCTC_STATE_ACTIVE = 0x0,
2494 MLX5_DCTC_STATE_DRAINING = 0x1,
2495 MLX5_DCTC_STATE_DRAINED = 0x2,
2496};
2497
2498enum {
2499 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2500 MLX5_DCTC_CS_RES_NA = 0x1,
2501 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2502};
2503
2504enum {
2505 MLX5_DCTC_MTU_256_BYTES = 0x1,
2506 MLX5_DCTC_MTU_512_BYTES = 0x2,
2507 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2508 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2509 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2510};
2511
2512struct mlx5_ifc_dctc_bits {
b4ff3a36 2513 u8 reserved_at_0[0x4];
e281682b 2514 u8 state[0x4];
b4ff3a36 2515 u8 reserved_at_8[0x18];
e281682b 2516
b4ff3a36 2517 u8 reserved_at_20[0x8];
e281682b
SM		 2518 u8 user_index[0x18];
2519
b4ff3a36 2520 u8 reserved_at_40[0x8];
e281682b
SM		 2521 u8 cqn[0x18];
2522
2523 u8 counter_set_id[0x8];
2524 u8 atomic_mode[0x4];
2525 u8 rre[0x1];
2526 u8 rwe[0x1];
2527 u8 rae[0x1];
2528 u8 atomic_like_write_en[0x1];
2529 u8 latency_sensitive[0x1];
2530 u8 rlky[0x1];
2531 u8 free_ar[0x1];
b4ff3a36 2532 u8 reserved_at_73[0xd];
e281682b 2533
b4ff3a36 2534 u8 reserved_at_80[0x8];
e281682b 2535 u8 cs_res[0x8];
b4ff3a36 2536 u8 reserved_at_90[0x3];
e281682b 2537 u8 min_rnr_nak[0x5];
b4ff3a36 2538 u8 reserved_at_98[0x8];
e281682b 2539
b4ff3a36 2540 u8 reserved_at_a0[0x8];
e281682b
SM		 2541 u8 srqn[0x18];
2542
b4ff3a36 2543 u8 reserved_at_c0[0x8];
e281682b
SM		 2544 u8 pd[0x18];
2545
2546 u8 tclass[0x8];
b4ff3a36 2547 u8 reserved_at_e8[0x4];
e281682b
SM		 2548 u8 flow_label[0x14];
2549
2550 u8 dc_access_key[0x40];
2551
b4ff3a36 2552 u8 reserved_at_140[0x5];
e281682b
SM		 2553 u8 mtu[0x3];
2554 u8 port[0x8];
2555 u8 pkey_index[0x10];
2556
b4ff3a36 2557 u8 reserved_at_160[0x8];
e281682b 2558 u8 my_addr_index[0x8];
b4ff3a36 2559 u8 reserved_at_170[0x8];
e281682b
SM		 2560 u8 hop_limit[0x8];
2561
2562 u8 dc_access_key_violation_count[0x20];
2563
b4ff3a36 2564 u8 reserved_at_1a0[0x14];
e281682b
SM		 2565 u8 dei_cfi[0x1];
2566 u8 eth_prio[0x3];
2567 u8 ecn[0x2];
2568 u8 dscp[0x6];
2569
b4ff3a36 2570 u8 reserved_at_1c0[0x40];
e281682b
SM		 2571};
2572
2573enum {
2574 MLX5_CQC_STATUS_OK = 0x0,
2575 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2576 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2577};
2578
2579enum {
2580 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2581 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2582};
2583
2584enum {
2585 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2586 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2587 MLX5_CQC_ST_FIRED = 0xa,
2588};
2589
2590struct mlx5_ifc_cqc_bits {
2591 u8 status[0x4];
b4ff3a36 2592 u8 reserved_at_4[0x4];
e281682b
SM		 2593 u8 cqe_sz[0x3];
2594 u8 cc[0x1];
b4ff3a36 2595 u8 reserved_at_c[0x1];
e281682b
SM		 2596 u8 scqe_break_moderation_en[0x1];
2597 u8 oi[0x1];
b4ff3a36 2598 u8 reserved_at_f[0x2];
e281682b
SM		 2599 u8 cqe_zip_en[0x1];
2600 u8 mini_cqe_res_format[0x2];
2601 u8 st[0x4];
b4ff3a36 2602 u8 reserved_at_18[0x8];
e281682b 2603
b4ff3a36 2604 u8 reserved_at_20[0x20];
e281682b 2605
b4ff3a36 2606 u8 reserved_at_40[0x14];
e281682b 2607 u8 page_offset[0x6];
b4ff3a36 2608 u8 reserved_at_5a[0x6];
e281682b 2609
b4ff3a36 2610 u8 reserved_at_60[0x3];
e281682b
SM		 2611 u8 log_cq_size[0x5];
2612 u8 uar_page[0x18];
2613
b4ff3a36 2614 u8 reserved_at_80[0x4];
e281682b
SM		 2615 u8 cq_period[0xc];
2616 u8 cq_max_count[0x10];
2617
b4ff3a36 2618 u8 reserved_at_a0[0x18];
e281682b
SM		 2619 u8 c_eqn[0x8];
2620
b4ff3a36 2621 u8 reserved_at_c0[0x3];
e281682b 2622 u8 log_page_size[0x5];
b4ff3a36 2623 u8 reserved_at_c8[0x18];
e281682b 2624
b4ff3a36 2625 u8 reserved_at_e0[0x20];
e281682b 2626
b4ff3a36 2627 u8 reserved_at_100[0x8];
e281682b
SM		 2628 u8 last_notified_index[0x18];
2629
b4ff3a36 2630 u8 reserved_at_120[0x8];
e281682b
SM		 2631 u8 last_solicit_index[0x18];
2632
b4ff3a36 2633 u8 reserved_at_140[0x8];
e281682b
SM		 2634 u8 consumer_counter[0x18];
2635
b4ff3a36 2636 u8 reserved_at_160[0x8];
e281682b
SM		 2637 u8 producer_counter[0x18];
2638
b4ff3a36 2639 u8 reserved_at_180[0x40];
e281682b
SM		 2640
2641 u8 dbr_addr[0x40];
2642};
2643
2644union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2645 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2646 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2647 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2648 u8 reserved_at_0[0x800];
e281682b
SM		 2649};
2650
2651struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2652 u8 reserved_at_0[0xc0];
e281682b 2653
b4ff3a36 2654 u8 reserved_at_c0[0x8];
211e6c80
MD		 2655 u8 ieee_vendor_id[0x18];
2656
b4ff3a36 2657 u8 reserved_at_e0[0x10];
e281682b
SM		 2658 u8 vsd_vendor_id[0x10];
2659
2660 u8 vsd[208][0x8];
2661
2662 u8 vsd_contd_psid[16][0x8];
2663};
2664
2665union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2666 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2667 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2668 u8 reserved_at_0[0x20];
e281682b
SM		 2669};
2670
2671union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2672 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2673 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2674 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2675 u8 reserved_at_0[0x20];
e281682b
SM		 2676};
2677
2678union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2679 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2680 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2681 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2682 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2683 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2684 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2685 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2686 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2687 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2688 u8 reserved_at_0[0x7c0];
e281682b
SM		 2689};
2690
2691union mlx5_ifc_event_auto_bits {
2692 struct mlx5_ifc_comp_event_bits comp_event;
2693 struct mlx5_ifc_dct_events_bits dct_events;
2694 struct mlx5_ifc_qp_events_bits qp_events;
2695 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2696 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2697 struct mlx5_ifc_cq_error_bits cq_error;
2698 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2699 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2700 struct mlx5_ifc_gpio_event_bits gpio_event;
2701 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2702 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2703 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2704 u8 reserved_at_0[0xe0];
e281682b
SM		 2705};
2706
2707struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2708 u8 reserved_at_0[0x100];
e281682b
SM		 2709
2710 u8 assert_existptr[0x20];
2711
2712 u8 assert_callra[0x20];
2713
b4ff3a36 2714 u8 reserved_at_140[0x40];
e281682b
SM		 2715
2716 u8 fw_version[0x20];
2717
2718 u8 hw_id[0x20];
2719
b4ff3a36 2720 u8 reserved_at_1c0[0x20];
e281682b
SM		 2721
2722 u8 irisc_index[0x8];
2723 u8 synd[0x8];
2724 u8 ext_synd[0x10];
2725};
2726
2727struct mlx5_ifc_register_loopback_control_bits {
2728 u8 no_lb[0x1];
b4ff3a36 2729 u8 reserved_at_1[0x7];
e281682b 2730 u8 port[0x8];
b4ff3a36 2731 u8 reserved_at_10[0x10];
e281682b 2732
b4ff3a36 2733 u8 reserved_at_20[0x60];
e281682b
SM		 2734};
2735
2736struct mlx5_ifc_teardown_hca_out_bits {
2737 u8 status[0x8];
b4ff3a36 2738 u8 reserved_at_8[0x18];
e281682b
SM		 2739
2740 u8 syndrome[0x20];
2741
b4ff3a36 2742 u8 reserved_at_40[0x40];
e281682b
SM		 2743};
2744
2745enum {
2746 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2747 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2748};
2749
2750struct mlx5_ifc_teardown_hca_in_bits {
2751 u8 opcode[0x10];
b4ff3a36 2752 u8 reserved_at_10[0x10];
e281682b 2753
b4ff3a36 2754 u8 reserved_at_20[0x10];
e281682b
SM		 2755 u8 op_mod[0x10];
2756
b4ff3a36 2757 u8 reserved_at_40[0x10];
e281682b
SM		 2758 u8 profile[0x10];
2759
b4ff3a36 2760 u8 reserved_at_60[0x20];
e281682b
SM		 2761};
2762
2763struct mlx5_ifc_sqerr2rts_qp_out_bits {
2764 u8 status[0x8];
b4ff3a36 2765 u8 reserved_at_8[0x18];
e281682b
SM		 2766
2767 u8 syndrome[0x20];
2768
b4ff3a36 2769 u8 reserved_at_40[0x40];
e281682b
SM		 2770};
2771
2772struct mlx5_ifc_sqerr2rts_qp_in_bits {
2773 u8 opcode[0x10];
b4ff3a36 2774 u8 reserved_at_10[0x10];
e281682b 2775
b4ff3a36 2776 u8 reserved_at_20[0x10];
e281682b
SM		 2777 u8 op_mod[0x10];
2778
b4ff3a36 2779 u8 reserved_at_40[0x8];
e281682b
SM		 2780 u8 qpn[0x18];
2781
b4ff3a36 2782 u8 reserved_at_60[0x20];
e281682b
SM		 2783
2784 u8 opt_param_mask[0x20];
2785
b4ff3a36 2786 u8 reserved_at_a0[0x20];
e281682b
SM		 2787
2788 struct mlx5_ifc_qpc_bits qpc;
2789
b4ff3a36 2790 u8 reserved_at_800[0x80];
e281682b
SM		 2791};
2792
2793struct mlx5_ifc_sqd2rts_qp_out_bits {
2794 u8 status[0x8];
b4ff3a36 2795 u8 reserved_at_8[0x18];
e281682b
SM		 2796
2797 u8 syndrome[0x20];
2798
b4ff3a36 2799 u8 reserved_at_40[0x40];
e281682b
SM		 2800};
2801
2802struct mlx5_ifc_sqd2rts_qp_in_bits {
2803 u8 opcode[0x10];
b4ff3a36 2804 u8 reserved_at_10[0x10];
e281682b 2805
b4ff3a36 2806 u8 reserved_at_20[0x10];
e281682b
SM		 2807 u8 op_mod[0x10];
2808
b4ff3a36 2809 u8 reserved_at_40[0x8];
e281682b
SM		 2810 u8 qpn[0x18];
2811
b4ff3a36 2812 u8 reserved_at_60[0x20];
e281682b
SM		 2813
2814 u8 opt_param_mask[0x20];
2815
b4ff3a36 2816 u8 reserved_at_a0[0x20];
e281682b
SM		 2817
2818 struct mlx5_ifc_qpc_bits qpc;
2819
b4ff3a36 2820 u8 reserved_at_800[0x80];
e281682b
SM		 2821};
2822
2823struct mlx5_ifc_set_roce_address_out_bits {
2824 u8 status[0x8];
b4ff3a36 2825 u8 reserved_at_8[0x18];
e281682b
SM		 2826
2827 u8 syndrome[0x20];
2828
b4ff3a36 2829 u8 reserved_at_40[0x40];
e281682b
SM		 2830};
2831
2832struct mlx5_ifc_set_roce_address_in_bits {
2833 u8 opcode[0x10];
b4ff3a36 2834 u8 reserved_at_10[0x10];
e281682b 2835
b4ff3a36 2836 u8 reserved_at_20[0x10];
e281682b
SM		 2837 u8 op_mod[0x10];
2838
2839 u8 roce_address_index[0x10];
b4ff3a36 2840 u8 reserved_at_50[0x10];
e281682b 2841
b4ff3a36 2842 u8 reserved_at_60[0x20];
e281682b
SM		 2843
2844 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2845};
2846
2847struct mlx5_ifc_set_mad_demux_out_bits {
2848 u8 status[0x8];
b4ff3a36 2849 u8 reserved_at_8[0x18];
e281682b
SM		 2850
2851 u8 syndrome[0x20];
2852
b4ff3a36 2853 u8 reserved_at_40[0x40];
e281682b
SM		 2854};
2855
2856enum {
2857 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2858 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2859};
2860
2861struct mlx5_ifc_set_mad_demux_in_bits {
2862 u8 opcode[0x10];
b4ff3a36 2863 u8 reserved_at_10[0x10];
e281682b 2864
b4ff3a36 2865 u8 reserved_at_20[0x10];
e281682b
SM		 2866 u8 op_mod[0x10];
2867
b4ff3a36 2868 u8 reserved_at_40[0x20];
e281682b 2869
b4ff3a36 2870 u8 reserved_at_60[0x6];
e281682b 2871 u8 demux_mode[0x2];
b4ff3a36 2872 u8 reserved_at_68[0x18];
e281682b
SM		 2873};
2874
2875struct mlx5_ifc_set_l2_table_entry_out_bits {
2876 u8 status[0x8];
b4ff3a36 2877 u8 reserved_at_8[0x18];
e281682b
SM		 2878
2879 u8 syndrome[0x20];
2880
b4ff3a36 2881 u8 reserved_at_40[0x40];
e281682b
SM		 2882};
2883
2884struct mlx5_ifc_set_l2_table_entry_in_bits {
2885 u8 opcode[0x10];
b4ff3a36 2886 u8 reserved_at_10[0x10];
e281682b 2887
b4ff3a36 2888 u8 reserved_at_20[0x10];
e281682b
SM		 2889 u8 op_mod[0x10];
2890
b4ff3a36 2891 u8 reserved_at_40[0x60];
e281682b 2892
b4ff3a36 2893 u8 reserved_at_a0[0x8];
e281682b
SM		 2894 u8 table_index[0x18];
2895
b4ff3a36 2896 u8 reserved_at_c0[0x20];
e281682b 2897
b4ff3a36 2898 u8 reserved_at_e0[0x13];
e281682b
SM		 2899 u8 vlan_valid[0x1];
2900 u8 vlan[0xc];
2901
2902 struct mlx5_ifc_mac_address_layout_bits mac_address;
2903
b4ff3a36 2904 u8 reserved_at_140[0xc0];
e281682b
SM		 2905};
2906
2907struct mlx5_ifc_set_issi_out_bits {
2908 u8 status[0x8];
b4ff3a36 2909 u8 reserved_at_8[0x18];
e281682b
SM		 2910
2911 u8 syndrome[0x20];
2912
b4ff3a36 2913 u8 reserved_at_40[0x40];
e281682b
SM		 2914};
2915
2916struct mlx5_ifc_set_issi_in_bits {
2917 u8 opcode[0x10];
b4ff3a36 2918 u8 reserved_at_10[0x10];
e281682b 2919
b4ff3a36 2920 u8 reserved_at_20[0x10];
e281682b
SM		 2921 u8 op_mod[0x10];
2922
b4ff3a36 2923 u8 reserved_at_40[0x10];
e281682b
SM		 2924 u8 current_issi[0x10];
2925
b4ff3a36 2926 u8 reserved_at_60[0x20];
e281682b
SM		 2927};
2928
2929struct mlx5_ifc_set_hca_cap_out_bits {
2930 u8 status[0x8];
b4ff3a36 2931 u8 reserved_at_8[0x18];
e281682b
SM		 2932
2933 u8 syndrome[0x20];
2934
b4ff3a36 2935 u8 reserved_at_40[0x40];
e281682b
SM		 2936};
2937
2938struct mlx5_ifc_set_hca_cap_in_bits {
2939 u8 opcode[0x10];
b4ff3a36 2940 u8 reserved_at_10[0x10];
e281682b 2941
b4ff3a36 2942 u8 reserved_at_20[0x10];
e281682b
SM		 2943 u8 op_mod[0x10];
2944
b4ff3a36 2945 u8 reserved_at_40[0x40];
e281682b
SM		 2946
2947 union mlx5_ifc_hca_cap_union_bits capability;
2948};
2949
26a81453
MG		 2950enum {
2951 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
2952 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
2953 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2954 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
2955};
2956
e281682b
SM		 2957struct mlx5_ifc_set_fte_out_bits {
2958 u8 status[0x8];
b4ff3a36 2959 u8 reserved_at_8[0x18];
e281682b
SM		 2960
2961 u8 syndrome[0x20];
2962
b4ff3a36 2963 u8 reserved_at_40[0x40];
e281682b
SM		 2964};
2965
2966struct mlx5_ifc_set_fte_in_bits {
2967 u8 opcode[0x10];
b4ff3a36 2968 u8 reserved_at_10[0x10];
e281682b 2969
b4ff3a36 2970 u8 reserved_at_20[0x10];
e281682b
SM		 2971 u8 op_mod[0x10];
2972
b4ff3a36 2973 u8 reserved_at_40[0x40];
e281682b
SM		 2974
2975 u8 table_type[0x8];
b4ff3a36 2976 u8 reserved_at_88[0x18];
e281682b 2977
b4ff3a36 2978 u8 reserved_at_a0[0x8];
e281682b
SM		 2979 u8 table_id[0x18];
2980
b4ff3a36 2981 u8 reserved_at_c0[0x18];
26a81453
MG		 2982 u8 modify_enable_mask[0x8];
2983
b4ff3a36 2984 u8 reserved_at_e0[0x20];
e281682b
SM		 2985
2986 u8 flow_index[0x20];
2987
b4ff3a36 2988 u8 reserved_at_120[0xe0];
e281682b
SM		 2989
2990 struct mlx5_ifc_flow_context_bits flow_context;
2991};
2992
2993struct mlx5_ifc_rts2rts_qp_out_bits {
2994 u8 status[0x8];
b4ff3a36 2995 u8 reserved_at_8[0x18];
e281682b
SM		 2996
2997 u8 syndrome[0x20];
2998
b4ff3a36 2999 u8 reserved_at_40[0x40];
e281682b
SM		 3000};
3001
3002struct mlx5_ifc_rts2rts_qp_in_bits {
3003 u8 opcode[0x10];
b4ff3a36 3004 u8 reserved_at_10[0x10];
e281682b 3005
b4ff3a36 3006 u8 reserved_at_20[0x10];
e281682b
SM		 3007 u8 op_mod[0x10];
3008
b4ff3a36 3009 u8 reserved_at_40[0x8];
e281682b
SM		 3010 u8 qpn[0x18];
3011
b4ff3a36 3012 u8 reserved_at_60[0x20];
e281682b
SM		 3013
3014 u8 opt_param_mask[0x20];
3015
b4ff3a36 3016 u8 reserved_at_a0[0x20];
e281682b
SM		 3017
3018 struct mlx5_ifc_qpc_bits qpc;
3019
b4ff3a36 3020 u8 reserved_at_800[0x80];
e281682b
SM		 3021};
3022
3023struct mlx5_ifc_rtr2rts_qp_out_bits {
3024 u8 status[0x8];
b4ff3a36 3025 u8 reserved_at_8[0x18];
e281682b
SM		 3026
3027 u8 syndrome[0x20];
3028
b4ff3a36 3029 u8 reserved_at_40[0x40];
e281682b
SM		 3030};
3031
3032struct mlx5_ifc_rtr2rts_qp_in_bits {
3033 u8 opcode[0x10];
b4ff3a36 3034 u8 reserved_at_10[0x10];
e281682b 3035
b4ff3a36 3036 u8 reserved_at_20[0x10];
e281682b
SM		 3037 u8 op_mod[0x10];
3038
b4ff3a36 3039 u8 reserved_at_40[0x8];
e281682b
SM		 3040 u8 qpn[0x18];
3041
b4ff3a36 3042 u8 reserved_at_60[0x20];
e281682b
SM		 3043
3044 u8 opt_param_mask[0x20];
3045
b4ff3a36 3046 u8 reserved_at_a0[0x20];
e281682b
SM		 3047
3048 struct mlx5_ifc_qpc_bits qpc;
3049
b4ff3a36 3050 u8 reserved_at_800[0x80];
e281682b
SM		 3051};
3052
3053struct mlx5_ifc_rst2init_qp_out_bits {
3054 u8 status[0x8];
b4ff3a36 3055 u8 reserved_at_8[0x18];
e281682b
SM		 3056
3057 u8 syndrome[0x20];
3058
b4ff3a36 3059 u8 reserved_at_40[0x40];
e281682b
SM		 3060};
3061
3062struct mlx5_ifc_rst2init_qp_in_bits {
3063 u8 opcode[0x10];
b4ff3a36 3064 u8 reserved_at_10[0x10];
e281682b 3065
b4ff3a36 3066 u8 reserved_at_20[0x10];
e281682b
SM		 3067 u8 op_mod[0x10];
3068
b4ff3a36 3069 u8 reserved_at_40[0x8];
e281682b
SM		 3070 u8 qpn[0x18];
3071
b4ff3a36 3072 u8 reserved_at_60[0x20];
e281682b
SM		 3073
3074 u8 opt_param_mask[0x20];
3075
b4ff3a36 3076 u8 reserved_at_a0[0x20];
e281682b
SM		 3077
3078 struct mlx5_ifc_qpc_bits qpc;
3079
b4ff3a36 3080 u8 reserved_at_800[0x80];
e281682b
SM		 3081};
3082
3083struct mlx5_ifc_query_xrc_srq_out_bits {
3084 u8 status[0x8];
b4ff3a36 3085 u8 reserved_at_8[0x18];
e281682b
SM		 3086
3087 u8 syndrome[0x20];
3088
b4ff3a36 3089 u8 reserved_at_40[0x40];
e281682b
SM		 3090
3091 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3092
b4ff3a36 3093 u8 reserved_at_280[0x600];
e281682b
SM		 3094
3095 u8 pas[0][0x40];
3096};
3097
3098struct mlx5_ifc_query_xrc_srq_in_bits {
3099 u8 opcode[0x10];
b4ff3a36 3100 u8 reserved_at_10[0x10];
e281682b 3101
b4ff3a36 3102 u8 reserved_at_20[0x10];
e281682b
SM		 3103 u8 op_mod[0x10];
3104
b4ff3a36 3105 u8 reserved_at_40[0x8];
e281682b
SM		 3106 u8 xrc_srqn[0x18];
3107
b4ff3a36 3108 u8 reserved_at_60[0x20];
e281682b
SM		 3109};
3110
3111enum {
3112 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3113 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3114};
3115
3116struct mlx5_ifc_query_vport_state_out_bits {
3117 u8 status[0x8];
b4ff3a36 3118 u8 reserved_at_8[0x18];
e281682b
SM		 3119
3120 u8 syndrome[0x20];
3121
b4ff3a36 3122 u8 reserved_at_40[0x20];
e281682b 3123
b4ff3a36 3124 u8 reserved_at_60[0x18];
e281682b
SM		 3125 u8 admin_state[0x4];
3126 u8 state[0x4];
3127};
3128
3129enum {
3130 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3131 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3132};
3133
3134struct mlx5_ifc_query_vport_state_in_bits {
3135 u8 opcode[0x10];
b4ff3a36 3136 u8 reserved_at_10[0x10];
e281682b 3137
b4ff3a36 3138 u8 reserved_at_20[0x10];
e281682b
SM		 3139 u8 op_mod[0x10];
3140
3141 u8 other_vport[0x1];
b4ff3a36 3142 u8 reserved_at_41[0xf];
e281682b
SM		 3143 u8 vport_number[0x10];
3144
b4ff3a36 3145 u8 reserved_at_60[0x20];
e281682b
SM		 3146};
3147
3148struct mlx5_ifc_query_vport_counter_out_bits {
3149 u8 status[0x8];
b4ff3a36 3150 u8 reserved_at_8[0x18];
e281682b
SM		 3151
3152 u8 syndrome[0x20];
3153
b4ff3a36 3154 u8 reserved_at_40[0x40];
e281682b
SM		 3155
3156 struct mlx5_ifc_traffic_counter_bits received_errors;
3157
3158 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3159
3160 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3161
3162 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3163
3164 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3165
3166 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3167
3168 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3169
3170 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3171
3172 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3173
3174 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3175
3176 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3177
3178 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3179
b4ff3a36 3180 u8 reserved_at_680[0xa00];
e281682b
SM		 3181};
3182
3183enum {
3184 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3185};
3186
3187struct mlx5_ifc_query_vport_counter_in_bits {
3188 u8 opcode[0x10];
b4ff3a36 3189 u8 reserved_at_10[0x10];
e281682b 3190
b4ff3a36 3191 u8 reserved_at_20[0x10];
e281682b
SM		 3192 u8 op_mod[0x10];
3193
3194 u8 other_vport[0x1];
b54ba277
MY		 3195 u8 reserved_at_41[0xb];
3196 u8 port_num[0x4];
e281682b
SM		 3197 u8 vport_number[0x10];
3198
b4ff3a36 3199 u8 reserved_at_60[0x60];
e281682b
SM		 3200
3201 u8 clear[0x1];
b4ff3a36 3202 u8 reserved_at_c1[0x1f];
e281682b 3203
b4ff3a36 3204 u8 reserved_at_e0[0x20];
e281682b
SM		 3205};
3206
3207struct mlx5_ifc_query_tis_out_bits {
3208 u8 status[0x8];
b4ff3a36 3209 u8 reserved_at_8[0x18];
e281682b
SM		 3210
3211 u8 syndrome[0x20];
3212
b4ff3a36 3213 u8 reserved_at_40[0x40];
e281682b
SM		 3214
3215 struct mlx5_ifc_tisc_bits tis_context;
3216};
3217
3218struct mlx5_ifc_query_tis_in_bits {
3219 u8 opcode[0x10];
b4ff3a36 3220 u8 reserved_at_10[0x10];
e281682b 3221
b4ff3a36 3222 u8 reserved_at_20[0x10];
e281682b
SM		 3223 u8 op_mod[0x10];
3224
b4ff3a36 3225 u8 reserved_at_40[0x8];
e281682b
SM		 3226 u8 tisn[0x18];
3227
b4ff3a36 3228 u8 reserved_at_60[0x20];
e281682b
SM		 3229};
3230
3231struct mlx5_ifc_query_tir_out_bits {
3232 u8 status[0x8];
b4ff3a36 3233 u8 reserved_at_8[0x18];
e281682b
SM		 3234
3235 u8 syndrome[0x20];
3236
b4ff3a36 3237 u8 reserved_at_40[0xc0];
e281682b
SM		 3238
3239 struct mlx5_ifc_tirc_bits tir_context;
3240};
3241
3242struct mlx5_ifc_query_tir_in_bits {
3243 u8 opcode[0x10];
b4ff3a36 3244 u8 reserved_at_10[0x10];
e281682b 3245
b4ff3a36 3246 u8 reserved_at_20[0x10];
e281682b
SM		 3247 u8 op_mod[0x10];
3248
b4ff3a36 3249 u8 reserved_at_40[0x8];
e281682b
SM		 3250 u8 tirn[0x18];
3251
b4ff3a36 3252 u8 reserved_at_60[0x20];
e281682b
SM		 3253};
3254
3255struct mlx5_ifc_query_srq_out_bits {
3256 u8 status[0x8];
b4ff3a36 3257 u8 reserved_at_8[0x18];
e281682b
SM		 3258
3259 u8 syndrome[0x20];
3260
b4ff3a36 3261 u8 reserved_at_40[0x40];
e281682b
SM		 3262
3263 struct mlx5_ifc_srqc_bits srq_context_entry;
3264
b4ff3a36 3265 u8 reserved_at_280[0x600];
e281682b
SM		 3266
3267 u8 pas[0][0x40];
3268};
3269
3270struct mlx5_ifc_query_srq_in_bits {
3271 u8 opcode[0x10];
b4ff3a36 3272 u8 reserved_at_10[0x10];
e281682b 3273
b4ff3a36 3274 u8 reserved_at_20[0x10];
e281682b
SM		 3275 u8 op_mod[0x10];
3276
b4ff3a36 3277 u8 reserved_at_40[0x8];
e281682b
SM		 3278 u8 srqn[0x18];
3279
b4ff3a36 3280 u8 reserved_at_60[0x20];
e281682b
SM		 3281};
3282
3283struct mlx5_ifc_query_sq_out_bits {
3284 u8 status[0x8];
b4ff3a36 3285 u8 reserved_at_8[0x18];
e281682b
SM		 3286
3287 u8 syndrome[0x20];
3288
b4ff3a36 3289 u8 reserved_at_40[0xc0];
e281682b
SM		 3290
3291 struct mlx5_ifc_sqc_bits sq_context;
3292};
3293
3294struct mlx5_ifc_query_sq_in_bits {
3295 u8 opcode[0x10];
b4ff3a36 3296 u8 reserved_at_10[0x10];
e281682b 3297
b4ff3a36 3298 u8 reserved_at_20[0x10];
e281682b
SM		 3299 u8 op_mod[0x10];
3300
b4ff3a36 3301 u8 reserved_at_40[0x8];
e281682b
SM		 3302 u8 sqn[0x18];
3303
b4ff3a36 3304 u8 reserved_at_60[0x20];
e281682b
SM		 3305};
3306
3307struct mlx5_ifc_query_special_contexts_out_bits {
3308 u8 status[0x8];
b4ff3a36 3309 u8 reserved_at_8[0x18];
e281682b
SM		 3310
3311 u8 syndrome[0x20];
3312
b4ff3a36 3313 u8 reserved_at_40[0x20];
e281682b
SM		 3314
3315 u8 resd_lkey[0x20];
3316};
3317
3318struct mlx5_ifc_query_special_contexts_in_bits {
3319 u8 opcode[0x10];
b4ff3a36 3320 u8 reserved_at_10[0x10];
e281682b 3321
b4ff3a36 3322 u8 reserved_at_20[0x10];
e281682b
SM		 3323 u8 op_mod[0x10];
3324
b4ff3a36 3325 u8 reserved_at_40[0x40];
e281682b
SM		 3326};
3327
3328struct mlx5_ifc_query_rqt_out_bits {
3329 u8 status[0x8];
b4ff3a36 3330 u8 reserved_at_8[0x18];
e281682b
SM		 3331
3332 u8 syndrome[0x20];
3333
b4ff3a36 3334 u8 reserved_at_40[0xc0];
e281682b
SM		 3335
3336 struct mlx5_ifc_rqtc_bits rqt_context;
3337};
3338
3339struct mlx5_ifc_query_rqt_in_bits {
3340 u8 opcode[0x10];
b4ff3a36 3341 u8 reserved_at_10[0x10];
e281682b 3342
b4ff3a36 3343 u8 reserved_at_20[0x10];
e281682b
SM		 3344 u8 op_mod[0x10];
3345
b4ff3a36 3346 u8 reserved_at_40[0x8];
e281682b
SM		 3347 u8 rqtn[0x18];
3348
b4ff3a36 3349 u8 reserved_at_60[0x20];
e281682b
SM		 3350};
3351
3352struct mlx5_ifc_query_rq_out_bits {
3353 u8 status[0x8];
b4ff3a36 3354 u8 reserved_at_8[0x18];
e281682b
SM		 3355
3356 u8 syndrome[0x20];
3357
b4ff3a36 3358 u8 reserved_at_40[0xc0];
e281682b
SM		 3359
3360 struct mlx5_ifc_rqc_bits rq_context;
3361};
3362
3363struct mlx5_ifc_query_rq_in_bits {
3364 u8 opcode[0x10];
b4ff3a36 3365 u8 reserved_at_10[0x10];
e281682b 3366
b4ff3a36 3367 u8 reserved_at_20[0x10];
e281682b
SM		 3368 u8 op_mod[0x10];
3369
b4ff3a36 3370 u8 reserved_at_40[0x8];
e281682b
SM		 3371 u8 rqn[0x18];
3372
b4ff3a36 3373 u8 reserved_at_60[0x20];
e281682b
SM		 3374};
3375
3376struct mlx5_ifc_query_roce_address_out_bits {
3377 u8 status[0x8];
b4ff3a36 3378 u8 reserved_at_8[0x18];
e281682b
SM		 3379
3380 u8 syndrome[0x20];
3381
b4ff3a36 3382 u8 reserved_at_40[0x40];
e281682b
SM		 3383
3384 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3385};
3386
3387struct mlx5_ifc_query_roce_address_in_bits {
3388 u8 opcode[0x10];
b4ff3a36 3389 u8 reserved_at_10[0x10];
e281682b 3390
b4ff3a36 3391 u8 reserved_at_20[0x10];
e281682b
SM		 3392 u8 op_mod[0x10];
3393
3394 u8 roce_address_index[0x10];
b4ff3a36 3395 u8 reserved_at_50[0x10];
e281682b 3396
b4ff3a36 3397 u8 reserved_at_60[0x20];
e281682b
SM		 3398};
3399
3400struct mlx5_ifc_query_rmp_out_bits {
3401 u8 status[0x8];
b4ff3a36 3402 u8 reserved_at_8[0x18];
e281682b
SM		 3403
3404 u8 syndrome[0x20];
3405
b4ff3a36 3406 u8 reserved_at_40[0xc0];
e281682b
SM		 3407
3408 struct mlx5_ifc_rmpc_bits rmp_context;
3409};
3410
3411struct mlx5_ifc_query_rmp_in_bits {
3412 u8 opcode[0x10];
b4ff3a36 3413 u8 reserved_at_10[0x10];
e281682b 3414
b4ff3a36 3415 u8 reserved_at_20[0x10];
e281682b
SM		 3416 u8 op_mod[0x10];
3417
b4ff3a36 3418 u8 reserved_at_40[0x8];
e281682b
SM		 3419 u8 rmpn[0x18];
3420
b4ff3a36 3421 u8 reserved_at_60[0x20];
e281682b
SM		 3422};
3423
3424struct mlx5_ifc_query_qp_out_bits {
3425 u8 status[0x8];
b4ff3a36 3426 u8 reserved_at_8[0x18];
e281682b
SM		 3427
3428 u8 syndrome[0x20];
3429
b4ff3a36 3430 u8 reserved_at_40[0x40];
e281682b
SM		 3431
3432 u8 opt_param_mask[0x20];
3433
b4ff3a36 3434 u8 reserved_at_a0[0x20];
e281682b
SM		 3435
3436 struct mlx5_ifc_qpc_bits qpc;
3437
b4ff3a36 3438 u8 reserved_at_800[0x80];
e281682b
SM		 3439
3440 u8 pas[0][0x40];
3441};
3442
3443struct mlx5_ifc_query_qp_in_bits {
3444 u8 opcode[0x10];
b4ff3a36 3445 u8 reserved_at_10[0x10];
e281682b 3446
b4ff3a36 3447 u8 reserved_at_20[0x10];
e281682b
SM		 3448 u8 op_mod[0x10];
3449
b4ff3a36 3450 u8 reserved_at_40[0x8];
e281682b
SM		 3451 u8 qpn[0x18];
3452
b4ff3a36 3453 u8 reserved_at_60[0x20];
e281682b
SM		 3454};
3455
3456struct mlx5_ifc_query_q_counter_out_bits {
3457 u8 status[0x8];
b4ff3a36 3458 u8 reserved_at_8[0x18];
e281682b
SM		 3459
3460 u8 syndrome[0x20];
3461
b4ff3a36 3462 u8 reserved_at_40[0x40];
e281682b
SM		 3463
3464 u8 rx_write_requests[0x20];
3465
b4ff3a36 3466 u8 reserved_at_a0[0x20];
e281682b
SM		 3467
3468 u8 rx_read_requests[0x20];
3469
b4ff3a36 3470 u8 reserved_at_e0[0x20];
e281682b
SM		 3471
3472 u8 rx_atomic_requests[0x20];
3473
b4ff3a36 3474 u8 reserved_at_120[0x20];
e281682b
SM		 3475
3476 u8 rx_dct_connect[0x20];
3477
b4ff3a36 3478 u8 reserved_at_160[0x20];
e281682b
SM		 3479
3480 u8 out_of_buffer[0x20];
3481
b4ff3a36 3482 u8 reserved_at_1a0[0x20];
e281682b
SM		 3483
3484 u8 out_of_sequence[0x20];
3485
b4ff3a36 3486 u8 reserved_at_1e0[0x620];
e281682b
SM		 3487};
3488
3489struct mlx5_ifc_query_q_counter_in_bits {
3490 u8 opcode[0x10];
b4ff3a36 3491 u8 reserved_at_10[0x10];
e281682b 3492
b4ff3a36 3493 u8 reserved_at_20[0x10];
e281682b
SM		 3494 u8 op_mod[0x10];
3495
b4ff3a36 3496 u8 reserved_at_40[0x80];
e281682b
SM		 3497
3498 u8 clear[0x1];
b4ff3a36 3499 u8 reserved_at_c1[0x1f];
e281682b 3500
b4ff3a36 3501 u8 reserved_at_e0[0x18];
e281682b
SM		 3502 u8 counter_set_id[0x8];
3503};
3504
3505struct mlx5_ifc_query_pages_out_bits {
3506 u8 status[0x8];
b4ff3a36 3507 u8 reserved_at_8[0x18];
e281682b
SM		 3508
3509 u8 syndrome[0x20];
3510
b4ff3a36 3511 u8 reserved_at_40[0x10];
e281682b
SM		 3512 u8 function_id[0x10];
3513
3514 u8 num_pages[0x20];
3515};
3516
3517enum {
3518 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3519 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3520 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3521};
3522
3523struct mlx5_ifc_query_pages_in_bits {
3524 u8 opcode[0x10];
b4ff3a36 3525 u8 reserved_at_10[0x10];
e281682b 3526
b4ff3a36 3527 u8 reserved_at_20[0x10];
e281682b
SM		 3528 u8 op_mod[0x10];
3529
b4ff3a36 3530 u8 reserved_at_40[0x10];
e281682b
SM		 3531 u8 function_id[0x10];
3532
b4ff3a36 3533 u8 reserved_at_60[0x20];
e281682b
SM		 3534};
3535
3536struct mlx5_ifc_query_nic_vport_context_out_bits {
3537 u8 status[0x8];
b4ff3a36 3538 u8 reserved_at_8[0x18];
e281682b
SM		 3539
3540 u8 syndrome[0x20];
3541
b4ff3a36 3542 u8 reserved_at_40[0x40];
e281682b
SM		 3543
3544 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3545};
3546
3547struct mlx5_ifc_query_nic_vport_context_in_bits {
3548 u8 opcode[0x10];
b4ff3a36 3549 u8 reserved_at_10[0x10];
e281682b 3550
b4ff3a36 3551 u8 reserved_at_20[0x10];
e281682b
SM		 3552 u8 op_mod[0x10];
3553
3554 u8 other_vport[0x1];
b4ff3a36 3555 u8 reserved_at_41[0xf];
e281682b
SM		 3556 u8 vport_number[0x10];
3557
b4ff3a36 3558 u8 reserved_at_60[0x5];
e281682b 3559 u8 allowed_list_type[0x3];
b4ff3a36 3560 u8 reserved_at_68[0x18];
e281682b
SM		 3561};
3562
3563struct mlx5_ifc_query_mkey_out_bits {
3564 u8 status[0x8];
b4ff3a36 3565 u8 reserved_at_8[0x18];
e281682b
SM		 3566
3567 u8 syndrome[0x20];
3568
b4ff3a36 3569 u8 reserved_at_40[0x40];
e281682b
SM		 3570
3571 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3572
b4ff3a36 3573 u8 reserved_at_280[0x600];
e281682b
SM		 3574
3575 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3576
3577 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3578};
3579
3580struct mlx5_ifc_query_mkey_in_bits {
3581 u8 opcode[0x10];
b4ff3a36 3582 u8 reserved_at_10[0x10];
e281682b 3583
b4ff3a36 3584 u8 reserved_at_20[0x10];
e281682b
SM		 3585 u8 op_mod[0x10];
3586
b4ff3a36 3587 u8 reserved_at_40[0x8];
e281682b
SM		 3588 u8 mkey_index[0x18];
3589
3590 u8 pg_access[0x1];
b4ff3a36 3591 u8 reserved_at_61[0x1f];
e281682b
SM		 3592};
3593
3594struct mlx5_ifc_query_mad_demux_out_bits {
3595 u8 status[0x8];
b4ff3a36 3596 u8 reserved_at_8[0x18];
e281682b
SM		 3597
3598 u8 syndrome[0x20];
3599
b4ff3a36 3600 u8 reserved_at_40[0x40];
e281682b
SM		 3601
3602 u8 mad_dumux_parameters_block[0x20];
3603};
3604
3605struct mlx5_ifc_query_mad_demux_in_bits {
3606 u8 opcode[0x10];
b4ff3a36 3607 u8 reserved_at_10[0x10];
e281682b 3608
b4ff3a36 3609 u8 reserved_at_20[0x10];
e281682b
SM		 3610 u8 op_mod[0x10];
3611
b4ff3a36 3612 u8 reserved_at_40[0x40];
e281682b
SM		 3613};
3614
3615struct mlx5_ifc_query_l2_table_entry_out_bits {
3616 u8 status[0x8];
b4ff3a36 3617 u8 reserved_at_8[0x18];
e281682b
SM		 3618
3619 u8 syndrome[0x20];
3620
b4ff3a36 3621 u8 reserved_at_40[0xa0];
e281682b 3622
b4ff3a36 3623 u8 reserved_at_e0[0x13];
e281682b
SM		 3624 u8 vlan_valid[0x1];
3625 u8 vlan[0xc];
3626
3627 struct mlx5_ifc_mac_address_layout_bits mac_address;
3628
b4ff3a36 3629 u8 reserved_at_140[0xc0];
e281682b
SM		 3630};
3631
3632struct mlx5_ifc_query_l2_table_entry_in_bits {
3633 u8 opcode[0x10];
b4ff3a36 3634 u8 reserved_at_10[0x10];
e281682b 3635
b4ff3a36 3636 u8 reserved_at_20[0x10];
e281682b
SM		 3637 u8 op_mod[0x10];
3638
b4ff3a36 3639 u8 reserved_at_40[0x60];
e281682b 3640
b4ff3a36 3641 u8 reserved_at_a0[0x8];
e281682b
SM		 3642 u8 table_index[0x18];
3643
b4ff3a36 3644 u8 reserved_at_c0[0x140];
e281682b
SM		 3645};
3646
3647struct mlx5_ifc_query_issi_out_bits {
3648 u8 status[0x8];
b4ff3a36 3649 u8 reserved_at_8[0x18];
e281682b
SM		 3650
3651 u8 syndrome[0x20];
3652
b4ff3a36 3653 u8 reserved_at_40[0x10];
e281682b
SM		 3654 u8 current_issi[0x10];
3655
b4ff3a36 3656 u8 reserved_at_60[0xa0];
e281682b 3657
b4ff3a36 3658 u8 reserved_at_100[76][0x8];
e281682b
SM		 3659 u8 supported_issi_dw0[0x20];
3660};
3661
3662struct mlx5_ifc_query_issi_in_bits {
3663 u8 opcode[0x10];
b4ff3a36 3664 u8 reserved_at_10[0x10];
e281682b 3665
b4ff3a36 3666 u8 reserved_at_20[0x10];
e281682b
SM		 3667 u8 op_mod[0x10];
3668
b4ff3a36 3669 u8 reserved_at_40[0x40];
e281682b
SM		 3670};
3671
3672struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3673 u8 status[0x8];
b4ff3a36 3674 u8 reserved_at_8[0x18];
e281682b
SM		 3675
3676 u8 syndrome[0x20];
3677
b4ff3a36 3678 u8 reserved_at_40[0x40];
e281682b
SM		 3679
3680 struct mlx5_ifc_pkey_bits pkey[0];
3681};
3682
3683struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3684 u8 opcode[0x10];
b4ff3a36 3685 u8 reserved_at_10[0x10];
e281682b 3686
b4ff3a36 3687 u8 reserved_at_20[0x10];
e281682b
SM		 3688 u8 op_mod[0x10];
3689
3690 u8 other_vport[0x1];
b4ff3a36 3691 u8 reserved_at_41[0xb];
707c4602 3692 u8 port_num[0x4];
e281682b
SM		 3693 u8 vport_number[0x10];
3694
b4ff3a36 3695 u8 reserved_at_60[0x10];
e281682b
SM		 3696 u8 pkey_index[0x10];
3697};
3698
eff901d3
EC		 3699enum {
3700 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3701 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3702 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3703};
3704
e281682b
SM		 3705struct mlx5_ifc_query_hca_vport_gid_out_bits {
3706 u8 status[0x8];
b4ff3a36 3707 u8 reserved_at_8[0x18];
e281682b
SM		 3708
3709 u8 syndrome[0x20];
3710
b4ff3a36 3711 u8 reserved_at_40[0x20];
e281682b
SM		 3712
3713 u8 gids_num[0x10];
b4ff3a36 3714 u8 reserved_at_70[0x10];
e281682b
SM		 3715
3716 struct mlx5_ifc_array128_auto_bits gid[0];
3717};
3718
3719struct mlx5_ifc_query_hca_vport_gid_in_bits {
3720 u8 opcode[0x10];
b4ff3a36 3721 u8 reserved_at_10[0x10];
e281682b 3722
b4ff3a36 3723 u8 reserved_at_20[0x10];
e281682b
SM		 3724 u8 op_mod[0x10];
3725
3726 u8 other_vport[0x1];
b4ff3a36 3727 u8 reserved_at_41[0xb];
707c4602 3728 u8 port_num[0x4];
e281682b
SM		 3729 u8 vport_number[0x10];
3730
b4ff3a36 3731 u8 reserved_at_60[0x10];
e281682b
SM		 3732 u8 gid_index[0x10];
3733};
3734
3735struct mlx5_ifc_query_hca_vport_context_out_bits {
3736 u8 status[0x8];
b4ff3a36 3737 u8 reserved_at_8[0x18];
e281682b
SM		 3738
3739 u8 syndrome[0x20];
3740
b4ff3a36 3741 u8 reserved_at_40[0x40];
e281682b
SM		 3742
3743 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3744};
3745
3746struct mlx5_ifc_query_hca_vport_context_in_bits {
3747 u8 opcode[0x10];
b4ff3a36 3748 u8 reserved_at_10[0x10];
e281682b 3749
b4ff3a36 3750 u8 reserved_at_20[0x10];
e281682b
SM		 3751 u8 op_mod[0x10];
3752
3753 u8 other_vport[0x1];
b4ff3a36 3754 u8 reserved_at_41[0xb];
707c4602 3755 u8 port_num[0x4];
e281682b
SM		 3756 u8 vport_number[0x10];
3757
b4ff3a36 3758 u8 reserved_at_60[0x20];
e281682b
SM		 3759};
3760
3761struct mlx5_ifc_query_hca_cap_out_bits {
3762 u8 status[0x8];
b4ff3a36 3763 u8 reserved_at_8[0x18];
e281682b
SM		 3764
3765 u8 syndrome[0x20];
3766
b4ff3a36 3767 u8 reserved_at_40[0x40];
e281682b
SM		 3768
3769 union mlx5_ifc_hca_cap_union_bits capability;
3770};
3771
3772struct mlx5_ifc_query_hca_cap_in_bits {
3773 u8 opcode[0x10];
b4ff3a36 3774 u8 reserved_at_10[0x10];
e281682b 3775
b4ff3a36 3776 u8 reserved_at_20[0x10];
e281682b
SM		 3777 u8 op_mod[0x10];
3778
b4ff3a36 3779 u8 reserved_at_40[0x40];
e281682b
SM		 3780};
3781
3782struct mlx5_ifc_query_flow_table_out_bits {
3783 u8 status[0x8];
b4ff3a36 3784 u8 reserved_at_8[0x18];
e281682b
SM		 3785
3786 u8 syndrome[0x20];
3787
b4ff3a36 3788 u8 reserved_at_40[0x80];
e281682b 3789
b4ff3a36 3790 u8 reserved_at_c0[0x8];
e281682b 3791 u8 level[0x8];
b4ff3a36 3792 u8 reserved_at_d0[0x8];
e281682b
SM		 3793 u8 log_size[0x8];
3794
b4ff3a36 3795 u8 reserved_at_e0[0x120];
e281682b
SM		 3796};
3797
3798struct mlx5_ifc_query_flow_table_in_bits {
3799 u8 opcode[0x10];
b4ff3a36 3800 u8 reserved_at_10[0x10];
e281682b 3801
b4ff3a36 3802 u8 reserved_at_20[0x10];
e281682b
SM		 3803 u8 op_mod[0x10];
3804
b4ff3a36 3805 u8 reserved_at_40[0x40];
e281682b
SM		 3806
3807 u8 table_type[0x8];
b4ff3a36 3808 u8 reserved_at_88[0x18];
e281682b 3809
b4ff3a36 3810 u8 reserved_at_a0[0x8];
e281682b
SM		 3811 u8 table_id[0x18];
3812
b4ff3a36 3813 u8 reserved_at_c0[0x140];
e281682b
SM		 3814};
3815
3816struct mlx5_ifc_query_fte_out_bits {
3817 u8 status[0x8];
b4ff3a36 3818 u8 reserved_at_8[0x18];
e281682b
SM		 3819
3820 u8 syndrome[0x20];
3821
b4ff3a36 3822 u8 reserved_at_40[0x1c0];
e281682b
SM		 3823
3824 struct mlx5_ifc_flow_context_bits flow_context;
3825};
3826
3827struct mlx5_ifc_query_fte_in_bits {
3828 u8 opcode[0x10];
b4ff3a36 3829 u8 reserved_at_10[0x10];
e281682b 3830
b4ff3a36 3831 u8 reserved_at_20[0x10];
e281682b
SM		 3832 u8 op_mod[0x10];
3833
b4ff3a36 3834 u8 reserved_at_40[0x40];
e281682b
SM		 3835
3836 u8 table_type[0x8];
b4ff3a36 3837 u8 reserved_at_88[0x18];
e281682b 3838
b4ff3a36 3839 u8 reserved_at_a0[0x8];
e281682b
SM		 3840 u8 table_id[0x18];
3841
b4ff3a36 3842 u8 reserved_at_c0[0x40];
e281682b
SM		 3843
3844 u8 flow_index[0x20];
3845
b4ff3a36 3846 u8 reserved_at_120[0xe0];
e281682b
SM		 3847};
3848
3849enum {
3850 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3851 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3852 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3853};
3854
3855struct mlx5_ifc_query_flow_group_out_bits {
3856 u8 status[0x8];
b4ff3a36 3857 u8 reserved_at_8[0x18];
e281682b
SM		 3858
3859 u8 syndrome[0x20];
3860
b4ff3a36 3861 u8 reserved_at_40[0xa0];
e281682b
SM		 3862
3863 u8 start_flow_index[0x20];
3864
b4ff3a36 3865 u8 reserved_at_100[0x20];
e281682b
SM		 3866
3867 u8 end_flow_index[0x20];
3868
b4ff3a36 3869 u8 reserved_at_140[0xa0];
e281682b 3870
b4ff3a36 3871 u8 reserved_at_1e0[0x18];
e281682b
SM		 3872 u8 match_criteria_enable[0x8];
3873
3874 struct mlx5_ifc_fte_match_param_bits match_criteria;
3875
b4ff3a36 3876 u8 reserved_at_1200[0xe00];
e281682b
SM		 3877};
3878
3879struct mlx5_ifc_query_flow_group_in_bits {
3880 u8 opcode[0x10];
b4ff3a36 3881 u8 reserved_at_10[0x10];
e281682b 3882
b4ff3a36 3883 u8 reserved_at_20[0x10];
e281682b
SM		 3884 u8 op_mod[0x10];
3885
b4ff3a36 3886 u8 reserved_at_40[0x40];
e281682b
SM		 3887
3888 u8 table_type[0x8];
b4ff3a36 3889 u8 reserved_at_88[0x18];
e281682b 3890
b4ff3a36 3891 u8 reserved_at_a0[0x8];
e281682b
SM		 3892 u8 table_id[0x18];
3893
3894 u8 group_id[0x20];
3895
b4ff3a36 3896 u8 reserved_at_e0[0x120];
e281682b
SM		 3897};
3898
d6666753
SM		 3899struct mlx5_ifc_query_esw_vport_context_out_bits {
3900 u8 status[0x8];
b4ff3a36 3901 u8 reserved_at_8[0x18];
d6666753
SM		 3902
3903 u8 syndrome[0x20];
3904
b4ff3a36 3905 u8 reserved_at_40[0x40];
d6666753
SM		 3906
3907 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3908};
3909
3910struct mlx5_ifc_query_esw_vport_context_in_bits {
3911 u8 opcode[0x10];
b4ff3a36 3912 u8 reserved_at_10[0x10];
d6666753 3913
b4ff3a36 3914 u8 reserved_at_20[0x10];
d6666753
SM		 3915 u8 op_mod[0x10];
3916
3917 u8 other_vport[0x1];
b4ff3a36 3918 u8 reserved_at_41[0xf];
d6666753
SM		 3919 u8 vport_number[0x10];
3920
b4ff3a36 3921 u8 reserved_at_60[0x20];
d6666753
SM		 3922};
3923
3924struct mlx5_ifc_modify_esw_vport_context_out_bits {
3925 u8 status[0x8];
b4ff3a36 3926 u8 reserved_at_8[0x18];
d6666753
SM		 3927
3928 u8 syndrome[0x20];
3929
b4ff3a36 3930 u8 reserved_at_40[0x40];
d6666753
SM		 3931};
3932
3933struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 3934 u8 reserved_at_0[0x1c];
d6666753
SM		 3935 u8 vport_cvlan_insert[0x1];
3936 u8 vport_svlan_insert[0x1];
3937 u8 vport_cvlan_strip[0x1];
3938 u8 vport_svlan_strip[0x1];
3939};
3940
3941struct mlx5_ifc_modify_esw_vport_context_in_bits {
3942 u8 opcode[0x10];
b4ff3a36 3943 u8 reserved_at_10[0x10];
d6666753 3944
b4ff3a36 3945 u8 reserved_at_20[0x10];
d6666753
SM		 3946 u8 op_mod[0x10];
3947
3948 u8 other_vport[0x1];
b4ff3a36 3949 u8 reserved_at_41[0xf];
d6666753
SM		 3950 u8 vport_number[0x10];
3951
3952 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3953
3954 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3955};
3956
e281682b
SM		 3957struct mlx5_ifc_query_eq_out_bits {
3958 u8 status[0x8];
b4ff3a36 3959 u8 reserved_at_8[0x18];
e281682b
SM		 3960
3961 u8 syndrome[0x20];
3962
b4ff3a36 3963 u8 reserved_at_40[0x40];
e281682b
SM		 3964
3965 struct mlx5_ifc_eqc_bits eq_context_entry;
3966
b4ff3a36 3967 u8 reserved_at_280[0x40];
e281682b
SM		 3968
3969 u8 event_bitmask[0x40];
3970
b4ff3a36 3971 u8 reserved_at_300[0x580];
e281682b
SM		 3972
3973 u8 pas[0][0x40];
3974};
3975
3976struct mlx5_ifc_query_eq_in_bits {
3977 u8 opcode[0x10];
b4ff3a36 3978 u8 reserved_at_10[0x10];
e281682b 3979
b4ff3a36 3980 u8 reserved_at_20[0x10];
e281682b
SM		 3981 u8 op_mod[0x10];
3982
b4ff3a36 3983 u8 reserved_at_40[0x18];
e281682b
SM		 3984 u8 eq_number[0x8];
3985
b4ff3a36 3986 u8 reserved_at_60[0x20];
e281682b
SM		 3987};
3988
3989struct mlx5_ifc_query_dct_out_bits {
3990 u8 status[0x8];
b4ff3a36 3991 u8 reserved_at_8[0x18];
e281682b
SM		 3992
3993 u8 syndrome[0x20];
3994
b4ff3a36 3995 u8 reserved_at_40[0x40];
e281682b
SM		 3996
3997 struct mlx5_ifc_dctc_bits dct_context_entry;
3998
b4ff3a36 3999 u8 reserved_at_280[0x180];
e281682b
SM		 4000};
4001
4002struct mlx5_ifc_query_dct_in_bits {
4003 u8 opcode[0x10];
b4ff3a36 4004 u8 reserved_at_10[0x10];
e281682b 4005
b4ff3a36 4006 u8 reserved_at_20[0x10];
e281682b
SM		 4007 u8 op_mod[0x10];
4008
b4ff3a36 4009 u8 reserved_at_40[0x8];
e281682b
SM		 4010 u8 dctn[0x18];
4011
b4ff3a36 4012 u8 reserved_at_60[0x20];
e281682b
SM		 4013};
4014
4015struct mlx5_ifc_query_cq_out_bits {
4016 u8 status[0x8];
b4ff3a36 4017 u8 reserved_at_8[0x18];
e281682b
SM		 4018
4019 u8 syndrome[0x20];
4020
b4ff3a36 4021 u8 reserved_at_40[0x40];
e281682b
SM		 4022
4023 struct mlx5_ifc_cqc_bits cq_context;
4024
b4ff3a36 4025 u8 reserved_at_280[0x600];
e281682b
SM		 4026
4027 u8 pas[0][0x40];
4028};
4029
4030struct mlx5_ifc_query_cq_in_bits {
4031 u8 opcode[0x10];
b4ff3a36 4032 u8 reserved_at_10[0x10];
e281682b 4033
b4ff3a36 4034 u8 reserved_at_20[0x10];
e281682b
SM		 4035 u8 op_mod[0x10];
4036
b4ff3a36 4037 u8 reserved_at_40[0x8];
e281682b
SM		 4038 u8 cqn[0x18];
4039
b4ff3a36 4040 u8 reserved_at_60[0x20];
e281682b
SM		 4041};
4042
4043struct mlx5_ifc_query_cong_status_out_bits {
4044 u8 status[0x8];
b4ff3a36 4045 u8 reserved_at_8[0x18];
e281682b
SM		 4046
4047 u8 syndrome[0x20];
4048
b4ff3a36 4049 u8 reserved_at_40[0x20];
e281682b
SM		 4050
4051 u8 enable[0x1];
4052 u8 tag_enable[0x1];
b4ff3a36 4053 u8 reserved_at_62[0x1e];
e281682b
SM		 4054};
4055
4056struct mlx5_ifc_query_cong_status_in_bits {
4057 u8 opcode[0x10];
b4ff3a36 4058 u8 reserved_at_10[0x10];
e281682b 4059
b4ff3a36 4060 u8 reserved_at_20[0x10];
e281682b
SM		 4061 u8 op_mod[0x10];
4062
b4ff3a36 4063 u8 reserved_at_40[0x18];
e281682b
SM		 4064 u8 priority[0x4];
4065 u8 cong_protocol[0x4];
4066
b4ff3a36 4067 u8 reserved_at_60[0x20];
e281682b
SM		 4068};
4069
4070struct mlx5_ifc_query_cong_statistics_out_bits {
4071 u8 status[0x8];
b4ff3a36 4072 u8 reserved_at_8[0x18];
e281682b
SM		 4073
4074 u8 syndrome[0x20];
4075
b4ff3a36 4076 u8 reserved_at_40[0x40];
e281682b
SM		 4077
4078 u8 cur_flows[0x20];
4079
4080 u8 sum_flows[0x20];
4081
4082 u8 cnp_ignored_high[0x20];
4083
4084 u8 cnp_ignored_low[0x20];
4085
4086 u8 cnp_handled_high[0x20];
4087
4088 u8 cnp_handled_low[0x20];
4089
b4ff3a36 4090 u8 reserved_at_140[0x100];
e281682b
SM		 4091
4092 u8 time_stamp_high[0x20];
4093
4094 u8 time_stamp_low[0x20];
4095
4096 u8 accumulators_period[0x20];
4097
4098 u8 ecn_marked_roce_packets_high[0x20];
4099
4100 u8 ecn_marked_roce_packets_low[0x20];
4101
4102 u8 cnps_sent_high[0x20];
4103
4104 u8 cnps_sent_low[0x20];
4105
b4ff3a36 4106 u8 reserved_at_320[0x560];
e281682b
SM		 4107};
4108
4109struct mlx5_ifc_query_cong_statistics_in_bits {
4110 u8 opcode[0x10];
b4ff3a36 4111 u8 reserved_at_10[0x10];
e281682b 4112
b4ff3a36 4113 u8 reserved_at_20[0x10];
e281682b
SM		 4114 u8 op_mod[0x10];
4115
4116 u8 clear[0x1];
b4ff3a36 4117 u8 reserved_at_41[0x1f];
e281682b 4118
b4ff3a36 4119 u8 reserved_at_60[0x20];
e281682b
SM		 4120};
4121
4122struct mlx5_ifc_query_cong_params_out_bits {
4123 u8 status[0x8];
b4ff3a36 4124 u8 reserved_at_8[0x18];
e281682b
SM		 4125
4126 u8 syndrome[0x20];
4127
b4ff3a36 4128 u8 reserved_at_40[0x40];
e281682b
SM		 4129
4130 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4131};
4132
4133struct mlx5_ifc_query_cong_params_in_bits {
4134 u8 opcode[0x10];
b4ff3a36 4135 u8 reserved_at_10[0x10];
e281682b 4136
b4ff3a36 4137 u8 reserved_at_20[0x10];
e281682b
SM		 4138 u8 op_mod[0x10];
4139
b4ff3a36 4140 u8 reserved_at_40[0x1c];
e281682b
SM		 4141 u8 cong_protocol[0x4];
4142
b4ff3a36 4143 u8 reserved_at_60[0x20];
e281682b
SM		 4144};
4145
4146struct mlx5_ifc_query_adapter_out_bits {
4147 u8 status[0x8];
b4ff3a36 4148 u8 reserved_at_8[0x18];
e281682b
SM		 4149
4150 u8 syndrome[0x20];
4151
b4ff3a36 4152 u8 reserved_at_40[0x40];
e281682b
SM		 4153
4154 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4155};
4156
4157struct mlx5_ifc_query_adapter_in_bits {
4158 u8 opcode[0x10];
b4ff3a36 4159 u8 reserved_at_10[0x10];
e281682b 4160
b4ff3a36 4161 u8 reserved_at_20[0x10];
e281682b
SM		 4162 u8 op_mod[0x10];
4163
b4ff3a36 4164 u8 reserved_at_40[0x40];
e281682b
SM		 4165};
4166
4167struct mlx5_ifc_qp_2rst_out_bits {
4168 u8 status[0x8];
b4ff3a36 4169 u8 reserved_at_8[0x18];
e281682b
SM		 4170
4171 u8 syndrome[0x20];
4172
b4ff3a36 4173 u8 reserved_at_40[0x40];
e281682b
SM		 4174};
4175
4176struct mlx5_ifc_qp_2rst_in_bits {
4177 u8 opcode[0x10];
b4ff3a36 4178 u8 reserved_at_10[0x10];
e281682b 4179
b4ff3a36 4180 u8 reserved_at_20[0x10];
e281682b
SM		 4181 u8 op_mod[0x10];
4182
b4ff3a36 4183 u8 reserved_at_40[0x8];
e281682b
SM		 4184 u8 qpn[0x18];
4185
b4ff3a36 4186 u8 reserved_at_60[0x20];
e281682b
SM		 4187};
4188
4189struct mlx5_ifc_qp_2err_out_bits {
4190 u8 status[0x8];
b4ff3a36 4191 u8 reserved_at_8[0x18];
e281682b
SM		 4192
4193 u8 syndrome[0x20];
4194
b4ff3a36 4195 u8 reserved_at_40[0x40];
e281682b
SM		 4196};
4197
4198struct mlx5_ifc_qp_2err_in_bits {
4199 u8 opcode[0x10];
b4ff3a36 4200 u8 reserved_at_10[0x10];
e281682b 4201
b4ff3a36 4202 u8 reserved_at_20[0x10];
e281682b
SM		 4203 u8 op_mod[0x10];
4204
b4ff3a36 4205 u8 reserved_at_40[0x8];
e281682b
SM		 4206 u8 qpn[0x18];
4207
b4ff3a36 4208 u8 reserved_at_60[0x20];
e281682b
SM		 4209};
4210
4211struct mlx5_ifc_page_fault_resume_out_bits {
4212 u8 status[0x8];
b4ff3a36 4213 u8 reserved_at_8[0x18];
e281682b
SM		 4214
4215 u8 syndrome[0x20];
4216
b4ff3a36 4217 u8 reserved_at_40[0x40];
e281682b
SM		 4218};
4219
4220struct mlx5_ifc_page_fault_resume_in_bits {
4221 u8 opcode[0x10];
b4ff3a36 4222 u8 reserved_at_10[0x10];
e281682b 4223
b4ff3a36 4224 u8 reserved_at_20[0x10];
e281682b
SM		 4225 u8 op_mod[0x10];
4226
4227 u8 error[0x1];
b4ff3a36 4228 u8 reserved_at_41[0x4];
e281682b
SM		 4229 u8 rdma[0x1];
4230 u8 read_write[0x1];
4231 u8 req_res[0x1];
4232 u8 qpn[0x18];
4233
b4ff3a36 4234 u8 reserved_at_60[0x20];
e281682b
SM		 4235};
4236
4237struct mlx5_ifc_nop_out_bits {
4238 u8 status[0x8];
b4ff3a36 4239 u8 reserved_at_8[0x18];
e281682b
SM		 4240
4241 u8 syndrome[0x20];
4242
b4ff3a36 4243 u8 reserved_at_40[0x40];
e281682b
SM		 4244};
4245
4246struct mlx5_ifc_nop_in_bits {
4247 u8 opcode[0x10];
b4ff3a36 4248 u8 reserved_at_10[0x10];
e281682b 4249
b4ff3a36 4250 u8 reserved_at_20[0x10];
e281682b
SM		 4251 u8 op_mod[0x10];
4252
b4ff3a36 4253 u8 reserved_at_40[0x40];
e281682b
SM		 4254};
4255
4256struct mlx5_ifc_modify_vport_state_out_bits {
4257 u8 status[0x8];
b4ff3a36 4258 u8 reserved_at_8[0x18];
e281682b
SM		 4259
4260 u8 syndrome[0x20];
4261
b4ff3a36 4262 u8 reserved_at_40[0x40];
e281682b
SM		 4263};
4264
4265struct mlx5_ifc_modify_vport_state_in_bits {
4266 u8 opcode[0x10];
b4ff3a36 4267 u8 reserved_at_10[0x10];
e281682b 4268
b4ff3a36 4269 u8 reserved_at_20[0x10];
e281682b
SM		 4270 u8 op_mod[0x10];
4271
4272 u8 other_vport[0x1];
b4ff3a36 4273 u8 reserved_at_41[0xf];
e281682b
SM		 4274 u8 vport_number[0x10];
4275
b4ff3a36 4276 u8 reserved_at_60[0x18];
e281682b 4277 u8 admin_state[0x4];
b4ff3a36 4278 u8 reserved_at_7c[0x4];
e281682b
SM		 4279};
4280
4281struct mlx5_ifc_modify_tis_out_bits {
4282 u8 status[0x8];
b4ff3a36 4283 u8 reserved_at_8[0x18];
e281682b
SM		 4284
4285 u8 syndrome[0x20];
4286
b4ff3a36 4287 u8 reserved_at_40[0x40];
e281682b
SM		 4288};
4289
75850d0b 4290struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4291 u8 reserved_at_0[0x20];
75850d0b 4292
b4ff3a36 4293 u8 reserved_at_20[0x1f];
75850d0b 4294 u8 prio[0x1];
4295};
4296
e281682b
SM		 4297struct mlx5_ifc_modify_tis_in_bits {
4298 u8 opcode[0x10];
b4ff3a36 4299 u8 reserved_at_10[0x10];
e281682b 4300
b4ff3a36 4301 u8 reserved_at_20[0x10];
e281682b
SM		 4302 u8 op_mod[0x10];
4303
b4ff3a36 4304 u8 reserved_at_40[0x8];
e281682b
SM		 4305 u8 tisn[0x18];
4306
b4ff3a36 4307 u8 reserved_at_60[0x20];
e281682b 4308
75850d0b 4309 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4310
b4ff3a36 4311 u8 reserved_at_c0[0x40];
e281682b
SM		 4312
4313 struct mlx5_ifc_tisc_bits ctx;
4314};
4315
d9eea403 4316struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4317 u8 reserved_at_0[0x20];
d9eea403 4318
b4ff3a36 4319 u8 reserved_at_20[0x1b];
66189961 4320 u8 self_lb_en[0x1];
b4ff3a36 4321 u8 reserved_at_3c[0x3];
d9eea403
AS		 4322 u8 lro[0x1];
4323};
4324
e281682b
SM		 4325struct mlx5_ifc_modify_tir_out_bits {
4326 u8 status[0x8];
b4ff3a36 4327 u8 reserved_at_8[0x18];
e281682b
SM		 4328
4329 u8 syndrome[0x20];
4330
b4ff3a36 4331 u8 reserved_at_40[0x40];
e281682b
SM		 4332};
4333
4334struct mlx5_ifc_modify_tir_in_bits {
4335 u8 opcode[0x10];
b4ff3a36 4336 u8 reserved_at_10[0x10];
e281682b 4337
b4ff3a36 4338 u8 reserved_at_20[0x10];
e281682b
SM		 4339 u8 op_mod[0x10];
4340
b4ff3a36 4341 u8 reserved_at_40[0x8];
e281682b
SM		 4342 u8 tirn[0x18];
4343
b4ff3a36 4344 u8 reserved_at_60[0x20];
e281682b 4345
d9eea403 4346 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4347
b4ff3a36 4348 u8 reserved_at_c0[0x40];
e281682b
SM		 4349
4350 struct mlx5_ifc_tirc_bits ctx;
4351};
4352
4353struct mlx5_ifc_modify_sq_out_bits {
4354 u8 status[0x8];
b4ff3a36 4355 u8 reserved_at_8[0x18];
e281682b
SM		 4356
4357 u8 syndrome[0x20];
4358
b4ff3a36 4359 u8 reserved_at_40[0x40];
e281682b
SM		 4360};
4361
4362struct mlx5_ifc_modify_sq_in_bits {
4363 u8 opcode[0x10];
b4ff3a36 4364 u8 reserved_at_10[0x10];
e281682b 4365
b4ff3a36 4366 u8 reserved_at_20[0x10];
e281682b
SM		 4367 u8 op_mod[0x10];
4368
4369 u8 sq_state[0x4];
b4ff3a36 4370 u8 reserved_at_44[0x4];
e281682b
SM		 4371 u8 sqn[0x18];
4372
b4ff3a36 4373 u8 reserved_at_60[0x20];
e281682b
SM		 4374
4375 u8 modify_bitmask[0x40];
4376
b4ff3a36 4377 u8 reserved_at_c0[0x40];
e281682b
SM		 4378
4379 struct mlx5_ifc_sqc_bits ctx;
4380};
4381
4382struct mlx5_ifc_modify_rqt_out_bits {
4383 u8 status[0x8];
b4ff3a36 4384 u8 reserved_at_8[0x18];
e281682b
SM		 4385
4386 u8 syndrome[0x20];
4387
b4ff3a36 4388 u8 reserved_at_40[0x40];
e281682b
SM		 4389};
4390
5c50368f 4391struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4392 u8 reserved_at_0[0x20];
5c50368f 4393
b4ff3a36 4394 u8 reserved_at_20[0x1f];
5c50368f
AS		 4395 u8 rqn_list[0x1];
4396};
4397
e281682b
SM		 4398struct mlx5_ifc_modify_rqt_in_bits {
4399 u8 opcode[0x10];
b4ff3a36 4400 u8 reserved_at_10[0x10];
e281682b 4401
b4ff3a36 4402 u8 reserved_at_20[0x10];
e281682b
SM		 4403 u8 op_mod[0x10];
4404
b4ff3a36 4405 u8 reserved_at_40[0x8];
e281682b
SM		 4406 u8 rqtn[0x18];
4407
b4ff3a36 4408 u8 reserved_at_60[0x20];
e281682b 4409
5c50368f 4410 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4411
b4ff3a36 4412 u8 reserved_at_c0[0x40];
e281682b
SM		 4413
4414 struct mlx5_ifc_rqtc_bits ctx;
4415};
4416
4417struct mlx5_ifc_modify_rq_out_bits {
4418 u8 status[0x8];
b4ff3a36 4419 u8 reserved_at_8[0x18];
e281682b
SM		 4420
4421 u8 syndrome[0x20];
4422
b4ff3a36 4423 u8 reserved_at_40[0x40];
e281682b
SM		 4424};
4425
4426struct mlx5_ifc_modify_rq_in_bits {
4427 u8 opcode[0x10];
b4ff3a36 4428 u8 reserved_at_10[0x10];
e281682b 4429
b4ff3a36 4430 u8 reserved_at_20[0x10];
e281682b
SM		 4431 u8 op_mod[0x10];
4432
4433 u8 rq_state[0x4];
b4ff3a36 4434 u8 reserved_at_44[0x4];
e281682b
SM		 4435 u8 rqn[0x18];
4436
b4ff3a36 4437 u8 reserved_at_60[0x20];
e281682b
SM		 4438
4439 u8 modify_bitmask[0x40];
4440
b4ff3a36 4441 u8 reserved_at_c0[0x40];
e281682b
SM		 4442
4443 struct mlx5_ifc_rqc_bits ctx;
4444};
4445
4446struct mlx5_ifc_modify_rmp_out_bits {
4447 u8 status[0x8];
b4ff3a36 4448 u8 reserved_at_8[0x18];
e281682b
SM		 4449
4450 u8 syndrome[0x20];
4451
b4ff3a36 4452 u8 reserved_at_40[0x40];
e281682b
SM		 4453};
4454
01949d01 4455struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 4456 u8 reserved_at_0[0x20];
01949d01 4457
b4ff3a36 4458 u8 reserved_at_20[0x1f];
01949d01
HA		 4459 u8 lwm[0x1];
4460};
4461
e281682b
SM		 4462struct mlx5_ifc_modify_rmp_in_bits {
4463 u8 opcode[0x10];
b4ff3a36 4464 u8 reserved_at_10[0x10];
e281682b 4465
b4ff3a36 4466 u8 reserved_at_20[0x10];
e281682b
SM		 4467 u8 op_mod[0x10];
4468
4469 u8 rmp_state[0x4];
b4ff3a36 4470 u8 reserved_at_44[0x4];
e281682b
SM		 4471 u8 rmpn[0x18];
4472
b4ff3a36 4473 u8 reserved_at_60[0x20];
e281682b 4474
01949d01 4475 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 4476
b4ff3a36 4477 u8 reserved_at_c0[0x40];
e281682b
SM		 4478
4479 struct mlx5_ifc_rmpc_bits ctx;
4480};
4481
4482struct mlx5_ifc_modify_nic_vport_context_out_bits {
4483 u8 status[0x8];
b4ff3a36 4484 u8 reserved_at_8[0x18];
e281682b
SM		 4485
4486 u8 syndrome[0x20];
4487
b4ff3a36 4488 u8 reserved_at_40[0x40];
e281682b
SM		 4489};
4490
4491struct mlx5_ifc_modify_nic_vport_field_select_bits {
b4ff3a36 4492 u8 reserved_at_0[0x19];
d82b7318
SM		 4493 u8 mtu[0x1];
4494 u8 change_event[0x1];
4495 u8 promisc[0x1];
e281682b
SM		 4496 u8 permanent_address[0x1];
4497 u8 addresses_list[0x1];
4498 u8 roce_en[0x1];
b4ff3a36 4499 u8 reserved_at_1f[0x1];
e281682b
SM		 4500};
4501
4502struct mlx5_ifc_modify_nic_vport_context_in_bits {
4503 u8 opcode[0x10];
b4ff3a36 4504 u8 reserved_at_10[0x10];
e281682b 4505
b4ff3a36 4506 u8 reserved_at_20[0x10];
e281682b
SM		 4507 u8 op_mod[0x10];
4508
4509 u8 other_vport[0x1];
b4ff3a36 4510 u8 reserved_at_41[0xf];
e281682b
SM		 4511 u8 vport_number[0x10];
4512
4513 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4514
b4ff3a36 4515 u8 reserved_at_80[0x780];
e281682b
SM		 4516
4517 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4518};
4519
4520struct mlx5_ifc_modify_hca_vport_context_out_bits {
4521 u8 status[0x8];
b4ff3a36 4522 u8 reserved_at_8[0x18];
e281682b
SM		 4523
4524 u8 syndrome[0x20];
4525
b4ff3a36 4526 u8 reserved_at_40[0x40];
e281682b
SM		 4527};
4528
4529struct mlx5_ifc_modify_hca_vport_context_in_bits {
4530 u8 opcode[0x10];
b4ff3a36 4531 u8 reserved_at_10[0x10];
e281682b 4532
b4ff3a36 4533 u8 reserved_at_20[0x10];
e281682b
SM		 4534 u8 op_mod[0x10];
4535
4536 u8 other_vport[0x1];
b4ff3a36 4537 u8 reserved_at_41[0xb];
707c4602 4538 u8 port_num[0x4];
e281682b
SM		 4539 u8 vport_number[0x10];
4540
b4ff3a36 4541 u8 reserved_at_60[0x20];
e281682b
SM		 4542
4543 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4544};
4545
4546struct mlx5_ifc_modify_cq_out_bits {
4547 u8 status[0x8];
b4ff3a36 4548 u8 reserved_at_8[0x18];
e281682b
SM		 4549
4550 u8 syndrome[0x20];
4551
b4ff3a36 4552 u8 reserved_at_40[0x40];
e281682b
SM		 4553};
4554
4555enum {
4556 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4557 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4558};
4559
4560struct mlx5_ifc_modify_cq_in_bits {
4561 u8 opcode[0x10];
b4ff3a36 4562 u8 reserved_at_10[0x10];
e281682b 4563
b4ff3a36 4564 u8 reserved_at_20[0x10];
e281682b
SM		 4565 u8 op_mod[0x10];
4566
b4ff3a36 4567 u8 reserved_at_40[0x8];
e281682b
SM		 4568 u8 cqn[0x18];
4569
4570 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4571
4572 struct mlx5_ifc_cqc_bits cq_context;
4573
b4ff3a36 4574 u8 reserved_at_280[0x600];
e281682b
SM		 4575
4576 u8 pas[0][0x40];
4577};
4578
4579struct mlx5_ifc_modify_cong_status_out_bits {
4580 u8 status[0x8];
b4ff3a36 4581 u8 reserved_at_8[0x18];
e281682b
SM		 4582
4583 u8 syndrome[0x20];
4584
b4ff3a36 4585 u8 reserved_at_40[0x40];
e281682b
SM		 4586};
4587
4588struct mlx5_ifc_modify_cong_status_in_bits {
4589 u8 opcode[0x10];
b4ff3a36 4590 u8 reserved_at_10[0x10];
e281682b 4591
b4ff3a36 4592 u8 reserved_at_20[0x10];
e281682b
SM		 4593 u8 op_mod[0x10];
4594
b4ff3a36 4595 u8 reserved_at_40[0x18];
e281682b
SM		 4596 u8 priority[0x4];
4597 u8 cong_protocol[0x4];
4598
4599 u8 enable[0x1];
4600 u8 tag_enable[0x1];
b4ff3a36 4601 u8 reserved_at_62[0x1e];
e281682b
SM		 4602};
4603
4604struct mlx5_ifc_modify_cong_params_out_bits {
4605 u8 status[0x8];
b4ff3a36 4606 u8 reserved_at_8[0x18];
e281682b
SM		 4607
4608 u8 syndrome[0x20];
4609
b4ff3a36 4610 u8 reserved_at_40[0x40];
e281682b
SM		 4611};
4612
4613struct mlx5_ifc_modify_cong_params_in_bits {
4614 u8 opcode[0x10];
b4ff3a36 4615 u8 reserved_at_10[0x10];
e281682b 4616
b4ff3a36 4617 u8 reserved_at_20[0x10];
e281682b
SM		 4618 u8 op_mod[0x10];
4619
b4ff3a36 4620 u8 reserved_at_40[0x1c];
e281682b
SM		 4621 u8 cong_protocol[0x4];
4622
4623 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4624
b4ff3a36 4625 u8 reserved_at_80[0x80];
e281682b
SM		 4626
4627 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4628};
4629
4630struct mlx5_ifc_manage_pages_out_bits {
4631 u8 status[0x8];
b4ff3a36 4632 u8 reserved_at_8[0x18];
e281682b
SM		 4633
4634 u8 syndrome[0x20];
4635
4636 u8 output_num_entries[0x20];
4637
b4ff3a36 4638 u8 reserved_at_60[0x20];
e281682b
SM		 4639
4640 u8 pas[0][0x40];
4641};
4642
4643enum {
4644 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4645 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4646 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4647};
4648
4649struct mlx5_ifc_manage_pages_in_bits {
4650 u8 opcode[0x10];
b4ff3a36 4651 u8 reserved_at_10[0x10];
e281682b 4652
b4ff3a36 4653 u8 reserved_at_20[0x10];
e281682b
SM		 4654 u8 op_mod[0x10];
4655
b4ff3a36 4656 u8 reserved_at_40[0x10];
e281682b
SM		 4657 u8 function_id[0x10];
4658
4659 u8 input_num_entries[0x20];
4660
4661 u8 pas[0][0x40];
4662};
4663
4664struct mlx5_ifc_mad_ifc_out_bits {
4665 u8 status[0x8];
b4ff3a36 4666 u8 reserved_at_8[0x18];
e281682b
SM		 4667
4668 u8 syndrome[0x20];
4669
b4ff3a36 4670 u8 reserved_at_40[0x40];
e281682b
SM		 4671
4672 u8 response_mad_packet[256][0x8];
4673};
4674
4675struct mlx5_ifc_mad_ifc_in_bits {
4676 u8 opcode[0x10];
b4ff3a36 4677 u8 reserved_at_10[0x10];
e281682b 4678
b4ff3a36 4679 u8 reserved_at_20[0x10];
e281682b
SM		 4680 u8 op_mod[0x10];
4681
4682 u8 remote_lid[0x10];
b4ff3a36 4683 u8 reserved_at_50[0x8];
e281682b
SM		 4684 u8 port[0x8];
4685
b4ff3a36 4686 u8 reserved_at_60[0x20];
e281682b
SM		 4687
4688 u8 mad[256][0x8];
4689};
4690
4691struct mlx5_ifc_init_hca_out_bits {
4692 u8 status[0x8];
b4ff3a36 4693 u8 reserved_at_8[0x18];
e281682b
SM		 4694
4695 u8 syndrome[0x20];
4696
b4ff3a36 4697 u8 reserved_at_40[0x40];
e281682b
SM		 4698};
4699
4700struct mlx5_ifc_init_hca_in_bits {
4701 u8 opcode[0x10];
b4ff3a36 4702 u8 reserved_at_10[0x10];
e281682b 4703
b4ff3a36 4704 u8 reserved_at_20[0x10];
e281682b
SM		 4705 u8 op_mod[0x10];
4706
b4ff3a36 4707 u8 reserved_at_40[0x40];
e281682b
SM		 4708};
4709
4710struct mlx5_ifc_init2rtr_qp_out_bits {
4711 u8 status[0x8];
b4ff3a36 4712 u8 reserved_at_8[0x18];
e281682b
SM		 4713
4714 u8 syndrome[0x20];
4715
b4ff3a36 4716 u8 reserved_at_40[0x40];
e281682b
SM		 4717};
4718
4719struct mlx5_ifc_init2rtr_qp_in_bits {
4720 u8 opcode[0x10];
b4ff3a36 4721 u8 reserved_at_10[0x10];
e281682b 4722
b4ff3a36 4723 u8 reserved_at_20[0x10];
e281682b
SM		 4724 u8 op_mod[0x10];
4725
b4ff3a36 4726 u8 reserved_at_40[0x8];
e281682b
SM		 4727 u8 qpn[0x18];
4728
b4ff3a36 4729 u8 reserved_at_60[0x20];
e281682b
SM		 4730
4731 u8 opt_param_mask[0x20];
4732
b4ff3a36 4733 u8 reserved_at_a0[0x20];
e281682b
SM		 4734
4735 struct mlx5_ifc_qpc_bits qpc;
4736
b4ff3a36 4737 u8 reserved_at_800[0x80];
e281682b
SM		 4738};
4739
4740struct mlx5_ifc_init2init_qp_out_bits {
4741 u8 status[0x8];
b4ff3a36 4742 u8 reserved_at_8[0x18];
e281682b
SM		 4743
4744 u8 syndrome[0x20];
4745
b4ff3a36 4746 u8 reserved_at_40[0x40];
e281682b
SM		 4747};
4748
4749struct mlx5_ifc_init2init_qp_in_bits {
4750 u8 opcode[0x10];
b4ff3a36 4751 u8 reserved_at_10[0x10];
e281682b 4752
b4ff3a36 4753 u8 reserved_at_20[0x10];
e281682b
SM		 4754 u8 op_mod[0x10];
4755
b4ff3a36 4756 u8 reserved_at_40[0x8];
e281682b
SM		 4757 u8 qpn[0x18];
4758
b4ff3a36 4759 u8 reserved_at_60[0x20];
e281682b
SM		 4760
4761 u8 opt_param_mask[0x20];
4762
b4ff3a36 4763 u8 reserved_at_a0[0x20];
e281682b
SM		 4764
4765 struct mlx5_ifc_qpc_bits qpc;
4766
b4ff3a36 4767 u8 reserved_at_800[0x80];
e281682b
SM		 4768};
4769
4770struct mlx5_ifc_get_dropped_packet_log_out_bits {
4771 u8 status[0x8];
b4ff3a36 4772 u8 reserved_at_8[0x18];
e281682b
SM		 4773
4774 u8 syndrome[0x20];
4775
b4ff3a36 4776 u8 reserved_at_40[0x40];
e281682b
SM		 4777
4778 u8 packet_headers_log[128][0x8];
4779
4780 u8 packet_syndrome[64][0x8];
4781};
4782
4783struct mlx5_ifc_get_dropped_packet_log_in_bits {
4784 u8 opcode[0x10];
b4ff3a36 4785 u8 reserved_at_10[0x10];
e281682b 4786
b4ff3a36 4787 u8 reserved_at_20[0x10];
e281682b
SM		 4788 u8 op_mod[0x10];
4789
b4ff3a36 4790 u8 reserved_at_40[0x40];
e281682b
SM		 4791};
4792
4793struct mlx5_ifc_gen_eqe_in_bits {
4794 u8 opcode[0x10];
b4ff3a36 4795 u8 reserved_at_10[0x10];
e281682b 4796
b4ff3a36 4797 u8 reserved_at_20[0x10];
e281682b
SM		 4798 u8 op_mod[0x10];
4799
b4ff3a36 4800 u8 reserved_at_40[0x18];
e281682b
SM		 4801 u8 eq_number[0x8];
4802
b4ff3a36 4803 u8 reserved_at_60[0x20];
e281682b
SM		 4804
4805 u8 eqe[64][0x8];
4806};
4807
4808struct mlx5_ifc_gen_eq_out_bits {
4809 u8 status[0x8];
b4ff3a36 4810 u8 reserved_at_8[0x18];
e281682b
SM		 4811
4812 u8 syndrome[0x20];
4813
b4ff3a36 4814 u8 reserved_at_40[0x40];
e281682b
SM		 4815};
4816
4817struct mlx5_ifc_enable_hca_out_bits {
4818 u8 status[0x8];
b4ff3a36 4819 u8 reserved_at_8[0x18];
e281682b
SM		 4820
4821 u8 syndrome[0x20];
4822
b4ff3a36 4823 u8 reserved_at_40[0x20];
e281682b
SM		 4824};
4825
4826struct mlx5_ifc_enable_hca_in_bits {
4827 u8 opcode[0x10];
b4ff3a36 4828 u8 reserved_at_10[0x10];
e281682b 4829
b4ff3a36 4830 u8 reserved_at_20[0x10];
e281682b
SM		 4831 u8 op_mod[0x10];
4832
b4ff3a36 4833 u8 reserved_at_40[0x10];
e281682b
SM		 4834 u8 function_id[0x10];
4835
b4ff3a36 4836 u8 reserved_at_60[0x20];
e281682b
SM		 4837};
4838
4839struct mlx5_ifc_drain_dct_out_bits {
4840 u8 status[0x8];
b4ff3a36 4841 u8 reserved_at_8[0x18];
e281682b
SM		 4842
4843 u8 syndrome[0x20];
4844
b4ff3a36 4845 u8 reserved_at_40[0x40];
e281682b
SM		 4846};
4847
4848struct mlx5_ifc_drain_dct_in_bits {
4849 u8 opcode[0x10];
b4ff3a36 4850 u8 reserved_at_10[0x10];
e281682b 4851
b4ff3a36 4852 u8 reserved_at_20[0x10];
e281682b
SM		 4853 u8 op_mod[0x10];
4854
b4ff3a36 4855 u8 reserved_at_40[0x8];
e281682b
SM		 4856 u8 dctn[0x18];
4857
b4ff3a36 4858 u8 reserved_at_60[0x20];
e281682b
SM		 4859};
4860
4861struct mlx5_ifc_disable_hca_out_bits {
4862 u8 status[0x8];
b4ff3a36 4863 u8 reserved_at_8[0x18];
e281682b
SM		 4864
4865 u8 syndrome[0x20];
4866
b4ff3a36 4867 u8 reserved_at_40[0x20];
e281682b
SM		 4868};
4869
4870struct mlx5_ifc_disable_hca_in_bits {
4871 u8 opcode[0x10];
b4ff3a36 4872 u8 reserved_at_10[0x10];
e281682b 4873
b4ff3a36 4874 u8 reserved_at_20[0x10];
e281682b
SM		 4875 u8 op_mod[0x10];
4876
b4ff3a36 4877 u8 reserved_at_40[0x10];
e281682b
SM		 4878 u8 function_id[0x10];
4879
b4ff3a36 4880 u8 reserved_at_60[0x20];
e281682b
SM		 4881};
4882
4883struct mlx5_ifc_detach_from_mcg_out_bits {
4884 u8 status[0x8];
b4ff3a36 4885 u8 reserved_at_8[0x18];
e281682b
SM		 4886
4887 u8 syndrome[0x20];
4888
b4ff3a36 4889 u8 reserved_at_40[0x40];
e281682b
SM		 4890};
4891
4892struct mlx5_ifc_detach_from_mcg_in_bits {
4893 u8 opcode[0x10];
b4ff3a36 4894 u8 reserved_at_10[0x10];
e281682b 4895
b4ff3a36 4896 u8 reserved_at_20[0x10];
e281682b
SM		 4897 u8 op_mod[0x10];
4898
b4ff3a36 4899 u8 reserved_at_40[0x8];
e281682b
SM		 4900 u8 qpn[0x18];
4901
b4ff3a36 4902 u8 reserved_at_60[0x20];
e281682b
SM		 4903
4904 u8 multicast_gid[16][0x8];
4905};
4906
4907struct mlx5_ifc_destroy_xrc_srq_out_bits {
4908 u8 status[0x8];
b4ff3a36 4909 u8 reserved_at_8[0x18];
e281682b
SM		 4910
4911 u8 syndrome[0x20];
4912
b4ff3a36 4913 u8 reserved_at_40[0x40];
e281682b
SM		 4914};
4915
4916struct mlx5_ifc_destroy_xrc_srq_in_bits {
4917 u8 opcode[0x10];
b4ff3a36 4918 u8 reserved_at_10[0x10];
e281682b 4919
b4ff3a36 4920 u8 reserved_at_20[0x10];
e281682b
SM		 4921 u8 op_mod[0x10];
4922
b4ff3a36 4923 u8 reserved_at_40[0x8];
e281682b
SM		 4924 u8 xrc_srqn[0x18];
4925
b4ff3a36 4926 u8 reserved_at_60[0x20];
e281682b
SM		 4927};
4928
4929struct mlx5_ifc_destroy_tis_out_bits {
4930 u8 status[0x8];
b4ff3a36 4931 u8 reserved_at_8[0x18];
e281682b
SM		 4932
4933 u8 syndrome[0x20];
4934
b4ff3a36 4935 u8 reserved_at_40[0x40];
e281682b
SM		 4936};
4937
4938struct mlx5_ifc_destroy_tis_in_bits {
4939 u8 opcode[0x10];
b4ff3a36 4940 u8 reserved_at_10[0x10];
e281682b 4941
b4ff3a36 4942 u8 reserved_at_20[0x10];
e281682b
SM		 4943 u8 op_mod[0x10];
4944
b4ff3a36 4945 u8 reserved_at_40[0x8];
e281682b
SM		 4946 u8 tisn[0x18];
4947
b4ff3a36 4948 u8 reserved_at_60[0x20];
e281682b
SM		 4949};
4950
4951struct mlx5_ifc_destroy_tir_out_bits {
4952 u8 status[0x8];
b4ff3a36 4953 u8 reserved_at_8[0x18];
e281682b
SM		 4954
4955 u8 syndrome[0x20];
4956
b4ff3a36 4957 u8 reserved_at_40[0x40];
e281682b
SM		 4958};
4959
4960struct mlx5_ifc_destroy_tir_in_bits {
4961 u8 opcode[0x10];
b4ff3a36 4962 u8 reserved_at_10[0x10];
e281682b 4963
b4ff3a36 4964 u8 reserved_at_20[0x10];
e281682b
SM		 4965 u8 op_mod[0x10];
4966
b4ff3a36 4967 u8 reserved_at_40[0x8];
e281682b
SM		 4968 u8 tirn[0x18];
4969
b4ff3a36 4970 u8 reserved_at_60[0x20];
e281682b
SM		 4971};
4972
4973struct mlx5_ifc_destroy_srq_out_bits {
4974 u8 status[0x8];
b4ff3a36 4975 u8 reserved_at_8[0x18];
e281682b
SM		 4976
4977 u8 syndrome[0x20];
4978
b4ff3a36 4979 u8 reserved_at_40[0x40];
e281682b
SM		 4980};
4981
4982struct mlx5_ifc_destroy_srq_in_bits {
4983 u8 opcode[0x10];
b4ff3a36 4984 u8 reserved_at_10[0x10];
e281682b 4985
b4ff3a36 4986 u8 reserved_at_20[0x10];
e281682b
SM		 4987 u8 op_mod[0x10];
4988
b4ff3a36 4989 u8 reserved_at_40[0x8];
e281682b
SM		 4990 u8 srqn[0x18];
4991
b4ff3a36 4992 u8 reserved_at_60[0x20];
e281682b
SM		 4993};
4994
4995struct mlx5_ifc_destroy_sq_out_bits {
4996 u8 status[0x8];
b4ff3a36 4997 u8 reserved_at_8[0x18];
e281682b
SM		 4998
4999 u8 syndrome[0x20];
5000
b4ff3a36 5001 u8 reserved_at_40[0x40];
e281682b
SM		 5002};
5003
5004struct mlx5_ifc_destroy_sq_in_bits {
5005 u8 opcode[0x10];
b4ff3a36 5006 u8 reserved_at_10[0x10];
e281682b 5007
b4ff3a36 5008 u8 reserved_at_20[0x10];
e281682b
SM		 5009 u8 op_mod[0x10];
5010
b4ff3a36 5011 u8 reserved_at_40[0x8];
e281682b
SM		 5012 u8 sqn[0x18];
5013
b4ff3a36 5014 u8 reserved_at_60[0x20];
e281682b
SM		 5015};
5016
5017struct mlx5_ifc_destroy_rqt_out_bits {
5018 u8 status[0x8];
b4ff3a36 5019 u8 reserved_at_8[0x18];
e281682b
SM		 5020
5021 u8 syndrome[0x20];
5022
b4ff3a36 5023 u8 reserved_at_40[0x40];
e281682b
SM		 5024};
5025
5026struct mlx5_ifc_destroy_rqt_in_bits {
5027 u8 opcode[0x10];
b4ff3a36 5028 u8 reserved_at_10[0x10];
e281682b 5029
b4ff3a36 5030 u8 reserved_at_20[0x10];
e281682b
SM		 5031 u8 op_mod[0x10];
5032
b4ff3a36 5033 u8 reserved_at_40[0x8];
e281682b
SM		 5034 u8 rqtn[0x18];
5035
b4ff3a36 5036 u8 reserved_at_60[0x20];
e281682b
SM		 5037};
5038
5039struct mlx5_ifc_destroy_rq_out_bits {
5040 u8 status[0x8];
b4ff3a36 5041 u8 reserved_at_8[0x18];
e281682b
SM		 5042
5043 u8 syndrome[0x20];
5044
b4ff3a36 5045 u8 reserved_at_40[0x40];
e281682b
SM		 5046};
5047
5048struct mlx5_ifc_destroy_rq_in_bits {
5049 u8 opcode[0x10];
b4ff3a36 5050 u8 reserved_at_10[0x10];
e281682b 5051
b4ff3a36 5052 u8 reserved_at_20[0x10];
e281682b
SM		 5053 u8 op_mod[0x10];
5054
b4ff3a36 5055 u8 reserved_at_40[0x8];
e281682b
SM		 5056 u8 rqn[0x18];
5057
b4ff3a36 5058 u8 reserved_at_60[0x20];
e281682b
SM		 5059};
5060
5061struct mlx5_ifc_destroy_rmp_out_bits {
5062 u8 status[0x8];
b4ff3a36 5063 u8 reserved_at_8[0x18];
e281682b
SM		 5064
5065 u8 syndrome[0x20];
5066
b4ff3a36 5067 u8 reserved_at_40[0x40];
e281682b
SM		 5068};
5069
5070struct mlx5_ifc_destroy_rmp_in_bits {
5071 u8 opcode[0x10];
b4ff3a36 5072 u8 reserved_at_10[0x10];
e281682b 5073
b4ff3a36 5074 u8 reserved_at_20[0x10];
e281682b
SM		 5075 u8 op_mod[0x10];
5076
b4ff3a36 5077 u8 reserved_at_40[0x8];
e281682b
SM		 5078 u8 rmpn[0x18];
5079
b4ff3a36 5080 u8 reserved_at_60[0x20];
e281682b
SM		 5081};
5082
5083struct mlx5_ifc_destroy_qp_out_bits {
5084 u8 status[0x8];
b4ff3a36 5085 u8 reserved_at_8[0x18];
e281682b
SM		 5086
5087 u8 syndrome[0x20];
5088
b4ff3a36 5089 u8 reserved_at_40[0x40];
e281682b
SM		 5090};
5091
5092struct mlx5_ifc_destroy_qp_in_bits {
5093 u8 opcode[0x10];
b4ff3a36 5094 u8 reserved_at_10[0x10];
e281682b 5095
b4ff3a36 5096 u8 reserved_at_20[0x10];
e281682b
SM		 5097 u8 op_mod[0x10];
5098
b4ff3a36 5099 u8 reserved_at_40[0x8];
e281682b
SM		 5100 u8 qpn[0x18];
5101
b4ff3a36 5102 u8 reserved_at_60[0x20];
e281682b
SM		 5103};
5104
5105struct mlx5_ifc_destroy_psv_out_bits {
5106 u8 status[0x8];
b4ff3a36 5107 u8 reserved_at_8[0x18];
e281682b
SM		 5108
5109 u8 syndrome[0x20];
5110
b4ff3a36 5111 u8 reserved_at_40[0x40];
e281682b
SM		 5112};
5113
5114struct mlx5_ifc_destroy_psv_in_bits {
5115 u8 opcode[0x10];
b4ff3a36 5116 u8 reserved_at_10[0x10];
e281682b 5117
b4ff3a36 5118 u8 reserved_at_20[0x10];
e281682b
SM		 5119 u8 op_mod[0x10];
5120
b4ff3a36 5121 u8 reserved_at_40[0x8];
e281682b
SM		 5122 u8 psvn[0x18];
5123
b4ff3a36 5124 u8 reserved_at_60[0x20];
e281682b
SM		 5125};
5126
5127struct mlx5_ifc_destroy_mkey_out_bits {
5128 u8 status[0x8];
b4ff3a36 5129 u8 reserved_at_8[0x18];
e281682b
SM		 5130
5131 u8 syndrome[0x20];
5132
b4ff3a36 5133 u8 reserved_at_40[0x40];
e281682b
SM		 5134};
5135
5136struct mlx5_ifc_destroy_mkey_in_bits {
5137 u8 opcode[0x10];
b4ff3a36 5138 u8 reserved_at_10[0x10];
e281682b 5139
b4ff3a36 5140 u8 reserved_at_20[0x10];
e281682b
SM		 5141 u8 op_mod[0x10];
5142
b4ff3a36 5143 u8 reserved_at_40[0x8];
e281682b
SM		 5144 u8 mkey_index[0x18];
5145
b4ff3a36 5146 u8 reserved_at_60[0x20];
e281682b
SM		 5147};
5148
5149struct mlx5_ifc_destroy_flow_table_out_bits {
5150 u8 status[0x8];
b4ff3a36 5151 u8 reserved_at_8[0x18];
e281682b
SM		 5152
5153 u8 syndrome[0x20];
5154
b4ff3a36 5155 u8 reserved_at_40[0x40];
e281682b
SM		 5156};
5157
5158struct mlx5_ifc_destroy_flow_table_in_bits {
5159 u8 opcode[0x10];
b4ff3a36 5160 u8 reserved_at_10[0x10];
e281682b 5161
b4ff3a36 5162 u8 reserved_at_20[0x10];
e281682b
SM		 5163 u8 op_mod[0x10];
5164
b4ff3a36 5165 u8 reserved_at_40[0x40];
e281682b
SM		 5166
5167 u8 table_type[0x8];
b4ff3a36 5168 u8 reserved_at_88[0x18];
e281682b 5169
b4ff3a36 5170 u8 reserved_at_a0[0x8];
e281682b
SM		 5171 u8 table_id[0x18];
5172
b4ff3a36 5173 u8 reserved_at_c0[0x140];
e281682b
SM		 5174};
5175
5176struct mlx5_ifc_destroy_flow_group_out_bits {
5177 u8 status[0x8];
b4ff3a36 5178 u8 reserved_at_8[0x18];
e281682b
SM		 5179
5180 u8 syndrome[0x20];
5181
b4ff3a36 5182 u8 reserved_at_40[0x40];
e281682b
SM		 5183};
5184
5185struct mlx5_ifc_destroy_flow_group_in_bits {
5186 u8 opcode[0x10];
b4ff3a36 5187 u8 reserved_at_10[0x10];
e281682b 5188
b4ff3a36 5189 u8 reserved_at_20[0x10];
e281682b
SM		 5190 u8 op_mod[0x10];
5191
b4ff3a36 5192 u8 reserved_at_40[0x40];
e281682b
SM		 5193
5194 u8 table_type[0x8];
b4ff3a36 5195 u8 reserved_at_88[0x18];
e281682b 5196
b4ff3a36 5197 u8 reserved_at_a0[0x8];
e281682b
SM		 5198 u8 table_id[0x18];
5199
5200 u8 group_id[0x20];
5201
b4ff3a36 5202 u8 reserved_at_e0[0x120];
e281682b
SM		 5203};
5204
5205struct mlx5_ifc_destroy_eq_out_bits {
5206 u8 status[0x8];
b4ff3a36 5207 u8 reserved_at_8[0x18];
e281682b
SM		 5208
5209 u8 syndrome[0x20];
5210
b4ff3a36 5211 u8 reserved_at_40[0x40];
e281682b
SM		 5212};
5213
5214struct mlx5_ifc_destroy_eq_in_bits {
5215 u8 opcode[0x10];
b4ff3a36 5216 u8 reserved_at_10[0x10];
e281682b 5217
b4ff3a36 5218 u8 reserved_at_20[0x10];
e281682b
SM		 5219 u8 op_mod[0x10];
5220
b4ff3a36 5221 u8 reserved_at_40[0x18];
e281682b
SM		 5222 u8 eq_number[0x8];
5223
b4ff3a36 5224 u8 reserved_at_60[0x20];
e281682b
SM		 5225};
5226
5227struct mlx5_ifc_destroy_dct_out_bits {
5228 u8 status[0x8];
b4ff3a36 5229 u8 reserved_at_8[0x18];
e281682b
SM		 5230
5231 u8 syndrome[0x20];
5232
b4ff3a36 5233 u8 reserved_at_40[0x40];
e281682b
SM		 5234};
5235
5236struct mlx5_ifc_destroy_dct_in_bits {
5237 u8 opcode[0x10];
b4ff3a36 5238 u8 reserved_at_10[0x10];
e281682b 5239
b4ff3a36 5240 u8 reserved_at_20[0x10];
e281682b
SM		 5241 u8 op_mod[0x10];
5242
b4ff3a36 5243 u8 reserved_at_40[0x8];
e281682b
SM		 5244 u8 dctn[0x18];
5245
b4ff3a36 5246 u8 reserved_at_60[0x20];
e281682b
SM		 5247};
5248
5249struct mlx5_ifc_destroy_cq_out_bits {
5250 u8 status[0x8];
b4ff3a36 5251 u8 reserved_at_8[0x18];
e281682b
SM		 5252
5253 u8 syndrome[0x20];
5254
b4ff3a36 5255 u8 reserved_at_40[0x40];
e281682b
SM		 5256};
5257
5258struct mlx5_ifc_destroy_cq_in_bits {
5259 u8 opcode[0x10];
b4ff3a36 5260 u8 reserved_at_10[0x10];
e281682b 5261
b4ff3a36 5262 u8 reserved_at_20[0x10];
e281682b
SM		 5263 u8 op_mod[0x10];
5264
b4ff3a36 5265 u8 reserved_at_40[0x8];
e281682b
SM		 5266 u8 cqn[0x18];
5267
b4ff3a36 5268 u8 reserved_at_60[0x20];
e281682b
SM		 5269};
5270
5271struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5272 u8 status[0x8];
b4ff3a36 5273 u8 reserved_at_8[0x18];
e281682b
SM		 5274
5275 u8 syndrome[0x20];
5276
b4ff3a36 5277 u8 reserved_at_40[0x40];
e281682b
SM		 5278};
5279
5280struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5281 u8 opcode[0x10];
b4ff3a36 5282 u8 reserved_at_10[0x10];
e281682b 5283
b4ff3a36 5284 u8 reserved_at_20[0x10];
e281682b
SM		 5285 u8 op_mod[0x10];
5286
b4ff3a36 5287 u8 reserved_at_40[0x20];
e281682b 5288
b4ff3a36 5289 u8 reserved_at_60[0x10];
e281682b
SM		 5290 u8 vxlan_udp_port[0x10];
5291};
5292
5293struct mlx5_ifc_delete_l2_table_entry_out_bits {
5294 u8 status[0x8];
b4ff3a36 5295 u8 reserved_at_8[0x18];
e281682b
SM		 5296
5297 u8 syndrome[0x20];
5298
b4ff3a36 5299 u8 reserved_at_40[0x40];
e281682b
SM		 5300};
5301
5302struct mlx5_ifc_delete_l2_table_entry_in_bits {
5303 u8 opcode[0x10];
b4ff3a36 5304 u8 reserved_at_10[0x10];
e281682b 5305
b4ff3a36 5306 u8 reserved_at_20[0x10];
e281682b
SM		 5307 u8 op_mod[0x10];
5308
b4ff3a36 5309 u8 reserved_at_40[0x60];
e281682b 5310
b4ff3a36 5311 u8 reserved_at_a0[0x8];
e281682b
SM		 5312 u8 table_index[0x18];
5313
b4ff3a36 5314 u8 reserved_at_c0[0x140];
e281682b
SM		 5315};
5316
5317struct mlx5_ifc_delete_fte_out_bits {
5318 u8 status[0x8];
b4ff3a36 5319 u8 reserved_at_8[0x18];
e281682b
SM		 5320
5321 u8 syndrome[0x20];
5322
b4ff3a36 5323 u8 reserved_at_40[0x40];
e281682b
SM		 5324};
5325
5326struct mlx5_ifc_delete_fte_in_bits {
5327 u8 opcode[0x10];
b4ff3a36 5328 u8 reserved_at_10[0x10];
e281682b 5329
b4ff3a36 5330 u8 reserved_at_20[0x10];
e281682b
SM		 5331 u8 op_mod[0x10];
5332
b4ff3a36 5333 u8 reserved_at_40[0x40];
e281682b
SM		 5334
5335 u8 table_type[0x8];
b4ff3a36 5336 u8 reserved_at_88[0x18];
e281682b 5337
b4ff3a36 5338 u8 reserved_at_a0[0x8];
e281682b
SM		 5339 u8 table_id[0x18];
5340
b4ff3a36 5341 u8 reserved_at_c0[0x40];
e281682b
SM		 5342
5343 u8 flow_index[0x20];
5344
b4ff3a36 5345 u8 reserved_at_120[0xe0];
e281682b
SM		 5346};
5347
5348struct mlx5_ifc_dealloc_xrcd_out_bits {
5349 u8 status[0x8];
b4ff3a36 5350 u8 reserved_at_8[0x18];
e281682b
SM		 5351
5352 u8 syndrome[0x20];
5353
b4ff3a36 5354 u8 reserved_at_40[0x40];
e281682b
SM		 5355};
5356
5357struct mlx5_ifc_dealloc_xrcd_in_bits {
5358 u8 opcode[0x10];
b4ff3a36 5359 u8 reserved_at_10[0x10];
e281682b 5360
b4ff3a36 5361 u8 reserved_at_20[0x10];
e281682b
SM		 5362 u8 op_mod[0x10];
5363
b4ff3a36 5364 u8 reserved_at_40[0x8];
e281682b
SM		 5365 u8 xrcd[0x18];
5366
b4ff3a36 5367 u8 reserved_at_60[0x20];
e281682b
SM		 5368};
5369
5370struct mlx5_ifc_dealloc_uar_out_bits {
5371 u8 status[0x8];
b4ff3a36 5372 u8 reserved_at_8[0x18];
e281682b
SM		 5373
5374 u8 syndrome[0x20];
5375
b4ff3a36 5376 u8 reserved_at_40[0x40];
e281682b
SM		 5377};
5378
5379struct mlx5_ifc_dealloc_uar_in_bits {
5380 u8 opcode[0x10];
b4ff3a36 5381 u8 reserved_at_10[0x10];
e281682b 5382
b4ff3a36 5383 u8 reserved_at_20[0x10];
e281682b
SM		 5384 u8 op_mod[0x10];
5385
b4ff3a36 5386 u8 reserved_at_40[0x8];
e281682b
SM		 5387 u8 uar[0x18];
5388
b4ff3a36 5389 u8 reserved_at_60[0x20];
e281682b
SM		 5390};
5391
5392struct mlx5_ifc_dealloc_transport_domain_out_bits {
5393 u8 status[0x8];
b4ff3a36 5394 u8 reserved_at_8[0x18];
e281682b
SM		 5395
5396 u8 syndrome[0x20];
5397
b4ff3a36 5398 u8 reserved_at_40[0x40];
e281682b
SM		 5399};
5400
5401struct mlx5_ifc_dealloc_transport_domain_in_bits {
5402 u8 opcode[0x10];
b4ff3a36 5403 u8 reserved_at_10[0x10];
e281682b 5404
b4ff3a36 5405 u8 reserved_at_20[0x10];
e281682b
SM		 5406 u8 op_mod[0x10];
5407
b4ff3a36 5408 u8 reserved_at_40[0x8];
e281682b
SM		 5409 u8 transport_domain[0x18];
5410
b4ff3a36 5411 u8 reserved_at_60[0x20];
e281682b
SM		 5412};
5413
5414struct mlx5_ifc_dealloc_q_counter_out_bits {
5415 u8 status[0x8];
b4ff3a36 5416 u8 reserved_at_8[0x18];
e281682b
SM		 5417
5418 u8 syndrome[0x20];
5419
b4ff3a36 5420 u8 reserved_at_40[0x40];
e281682b
SM		 5421};
5422
5423struct mlx5_ifc_dealloc_q_counter_in_bits {
5424 u8 opcode[0x10];
b4ff3a36 5425 u8 reserved_at_10[0x10];
e281682b 5426
b4ff3a36 5427 u8 reserved_at_20[0x10];
e281682b
SM		 5428 u8 op_mod[0x10];
5429
b4ff3a36 5430 u8 reserved_at_40[0x18];
e281682b
SM		 5431 u8 counter_set_id[0x8];
5432
b4ff3a36 5433 u8 reserved_at_60[0x20];
e281682b
SM		 5434};
5435
5436struct mlx5_ifc_dealloc_pd_out_bits {
5437 u8 status[0x8];
b4ff3a36 5438 u8 reserved_at_8[0x18];
e281682b
SM		 5439
5440 u8 syndrome[0x20];
5441
b4ff3a36 5442 u8 reserved_at_40[0x40];
e281682b
SM		 5443};
5444
5445struct mlx5_ifc_dealloc_pd_in_bits {
5446 u8 opcode[0x10];
b4ff3a36 5447 u8 reserved_at_10[0x10];
e281682b 5448
b4ff3a36 5449 u8 reserved_at_20[0x10];
e281682b
SM		 5450 u8 op_mod[0x10];
5451
b4ff3a36 5452 u8 reserved_at_40[0x8];
e281682b
SM		 5453 u8 pd[0x18];
5454
b4ff3a36 5455 u8 reserved_at_60[0x20];
e281682b
SM		 5456};
5457
5458struct mlx5_ifc_create_xrc_srq_out_bits {
5459 u8 status[0x8];
b4ff3a36 5460 u8 reserved_at_8[0x18];
e281682b
SM		 5461
5462 u8 syndrome[0x20];
5463
b4ff3a36 5464 u8 reserved_at_40[0x8];
e281682b
SM		 5465 u8 xrc_srqn[0x18];
5466
b4ff3a36 5467 u8 reserved_at_60[0x20];
e281682b
SM		 5468};
5469
5470struct mlx5_ifc_create_xrc_srq_in_bits {
5471 u8 opcode[0x10];
b4ff3a36 5472 u8 reserved_at_10[0x10];
e281682b 5473
b4ff3a36 5474 u8 reserved_at_20[0x10];
e281682b
SM		 5475 u8 op_mod[0x10];
5476
b4ff3a36 5477 u8 reserved_at_40[0x40];
e281682b
SM		 5478
5479 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5480
b4ff3a36 5481 u8 reserved_at_280[0x600];
e281682b
SM		 5482
5483 u8 pas[0][0x40];
5484};
5485
5486struct mlx5_ifc_create_tis_out_bits {
5487 u8 status[0x8];
b4ff3a36 5488 u8 reserved_at_8[0x18];
e281682b
SM		 5489
5490 u8 syndrome[0x20];
5491
b4ff3a36 5492 u8 reserved_at_40[0x8];
e281682b
SM		 5493 u8 tisn[0x18];
5494
b4ff3a36 5495 u8 reserved_at_60[0x20];
e281682b
SM		 5496};
5497
5498struct mlx5_ifc_create_tis_in_bits {
5499 u8 opcode[0x10];
b4ff3a36 5500 u8 reserved_at_10[0x10];
e281682b 5501
b4ff3a36 5502 u8 reserved_at_20[0x10];
e281682b
SM		 5503 u8 op_mod[0x10];
5504
b4ff3a36 5505 u8 reserved_at_40[0xc0];
e281682b
SM		 5506
5507 struct mlx5_ifc_tisc_bits ctx;
5508};
5509
5510struct mlx5_ifc_create_tir_out_bits {
5511 u8 status[0x8];
b4ff3a36 5512 u8 reserved_at_8[0x18];
e281682b
SM		 5513
5514 u8 syndrome[0x20];
5515
b4ff3a36 5516 u8 reserved_at_40[0x8];
e281682b
SM		 5517 u8 tirn[0x18];
5518
b4ff3a36 5519 u8 reserved_at_60[0x20];
e281682b
SM		 5520};
5521
5522struct mlx5_ifc_create_tir_in_bits {
5523 u8 opcode[0x10];
b4ff3a36 5524 u8 reserved_at_10[0x10];
e281682b 5525
b4ff3a36 5526 u8 reserved_at_20[0x10];
e281682b
SM		 5527 u8 op_mod[0x10];
5528
b4ff3a36 5529 u8 reserved_at_40[0xc0];
e281682b
SM		 5530
5531 struct mlx5_ifc_tirc_bits ctx;
5532};
5533
5534struct mlx5_ifc_create_srq_out_bits {
5535 u8 status[0x8];
b4ff3a36 5536 u8 reserved_at_8[0x18];
e281682b
SM		 5537
5538 u8 syndrome[0x20];
5539
b4ff3a36 5540 u8 reserved_at_40[0x8];
e281682b
SM		 5541 u8 srqn[0x18];
5542
b4ff3a36 5543 u8 reserved_at_60[0x20];
e281682b
SM		 5544};
5545
5546struct mlx5_ifc_create_srq_in_bits {
5547 u8 opcode[0x10];
b4ff3a36 5548 u8 reserved_at_10[0x10];
e281682b 5549
b4ff3a36 5550 u8 reserved_at_20[0x10];
e281682b
SM		 5551 u8 op_mod[0x10];
5552
b4ff3a36 5553 u8 reserved_at_40[0x40];
e281682b
SM		 5554
5555 struct mlx5_ifc_srqc_bits srq_context_entry;
5556
b4ff3a36 5557 u8 reserved_at_280[0x600];
e281682b
SM		 5558
5559 u8 pas[0][0x40];
5560};
5561
5562struct mlx5_ifc_create_sq_out_bits {
5563 u8 status[0x8];
b4ff3a36 5564 u8 reserved_at_8[0x18];
e281682b
SM		 5565
5566 u8 syndrome[0x20];
5567
b4ff3a36 5568 u8 reserved_at_40[0x8];
e281682b
SM		 5569 u8 sqn[0x18];
5570
b4ff3a36 5571 u8 reserved_at_60[0x20];
e281682b
SM		 5572};
5573
5574struct mlx5_ifc_create_sq_in_bits {
5575 u8 opcode[0x10];
b4ff3a36 5576 u8 reserved_at_10[0x10];
e281682b 5577
b4ff3a36 5578 u8 reserved_at_20[0x10];
e281682b
SM		 5579 u8 op_mod[0x10];
5580
b4ff3a36 5581 u8 reserved_at_40[0xc0];
e281682b
SM		 5582
5583 struct mlx5_ifc_sqc_bits ctx;
5584};
5585
5586struct mlx5_ifc_create_rqt_out_bits {
5587 u8 status[0x8];
b4ff3a36 5588 u8 reserved_at_8[0x18];
e281682b
SM		 5589
5590 u8 syndrome[0x20];
5591
b4ff3a36 5592 u8 reserved_at_40[0x8];
e281682b
SM		 5593 u8 rqtn[0x18];
5594
b4ff3a36 5595 u8 reserved_at_60[0x20];
e281682b
SM		 5596};
5597
5598struct mlx5_ifc_create_rqt_in_bits {
5599 u8 opcode[0x10];
b4ff3a36 5600 u8 reserved_at_10[0x10];
e281682b 5601
b4ff3a36 5602 u8 reserved_at_20[0x10];
e281682b
SM		 5603 u8 op_mod[0x10];
5604
b4ff3a36 5605 u8 reserved_at_40[0xc0];
e281682b
SM		 5606
5607 struct mlx5_ifc_rqtc_bits rqt_context;
5608};
5609
5610struct mlx5_ifc_create_rq_out_bits {
5611 u8 status[0x8];
b4ff3a36 5612 u8 reserved_at_8[0x18];
e281682b
SM		 5613
5614 u8 syndrome[0x20];
5615
b4ff3a36 5616 u8 reserved_at_40[0x8];
e281682b
SM		 5617 u8 rqn[0x18];
5618
b4ff3a36 5619 u8 reserved_at_60[0x20];
e281682b
SM		 5620};
5621
5622struct mlx5_ifc_create_rq_in_bits {
5623 u8 opcode[0x10];
b4ff3a36 5624 u8 reserved_at_10[0x10];
e281682b 5625
b4ff3a36 5626 u8 reserved_at_20[0x10];
e281682b
SM		 5627 u8 op_mod[0x10];
5628
b4ff3a36 5629 u8 reserved_at_40[0xc0];
e281682b
SM		 5630
5631 struct mlx5_ifc_rqc_bits ctx;
5632};
5633
5634struct mlx5_ifc_create_rmp_out_bits {
5635 u8 status[0x8];
b4ff3a36 5636 u8 reserved_at_8[0x18];
e281682b
SM		 5637
5638 u8 syndrome[0x20];
5639
b4ff3a36 5640 u8 reserved_at_40[0x8];
e281682b
SM		 5641 u8 rmpn[0x18];
5642
b4ff3a36 5643 u8 reserved_at_60[0x20];
e281682b
SM		 5644};
5645
5646struct mlx5_ifc_create_rmp_in_bits {
5647 u8 opcode[0x10];
b4ff3a36 5648 u8 reserved_at_10[0x10];
e281682b 5649
b4ff3a36 5650 u8 reserved_at_20[0x10];
e281682b
SM		 5651 u8 op_mod[0x10];
5652
b4ff3a36 5653 u8 reserved_at_40[0xc0];
e281682b
SM		 5654
5655 struct mlx5_ifc_rmpc_bits ctx;
5656};
5657
5658struct mlx5_ifc_create_qp_out_bits {
5659 u8 status[0x8];
b4ff3a36 5660 u8 reserved_at_8[0x18];
e281682b
SM		 5661
5662 u8 syndrome[0x20];
5663
b4ff3a36 5664 u8 reserved_at_40[0x8];
e281682b
SM		 5665 u8 qpn[0x18];
5666
b4ff3a36 5667 u8 reserved_at_60[0x20];
e281682b
SM		 5668};
5669
5670struct mlx5_ifc_create_qp_in_bits {
5671 u8 opcode[0x10];
b4ff3a36 5672 u8 reserved_at_10[0x10];
e281682b 5673
b4ff3a36 5674 u8 reserved_at_20[0x10];
e281682b
SM		 5675 u8 op_mod[0x10];
5676
b4ff3a36 5677 u8 reserved_at_40[0x40];
e281682b
SM		 5678
5679 u8 opt_param_mask[0x20];
5680
b4ff3a36 5681 u8 reserved_at_a0[0x20];
e281682b
SM		 5682
5683 struct mlx5_ifc_qpc_bits qpc;
5684
b4ff3a36 5685 u8 reserved_at_800[0x80];
e281682b
SM		 5686
5687 u8 pas[0][0x40];
5688};
5689
5690struct mlx5_ifc_create_psv_out_bits {
5691 u8 status[0x8];
b4ff3a36 5692 u8 reserved_at_8[0x18];
e281682b
SM		 5693
5694 u8 syndrome[0x20];
5695
b4ff3a36 5696 u8 reserved_at_40[0x40];
e281682b 5697
b4ff3a36 5698 u8 reserved_at_80[0x8];
e281682b
SM		 5699 u8 psv0_index[0x18];
5700
b4ff3a36 5701 u8 reserved_at_a0[0x8];
e281682b
SM		 5702 u8 psv1_index[0x18];
5703
b4ff3a36 5704 u8 reserved_at_c0[0x8];
e281682b
SM		 5705 u8 psv2_index[0x18];
5706
b4ff3a36 5707 u8 reserved_at_e0[0x8];
e281682b
SM		 5708 u8 psv3_index[0x18];
5709};
5710
5711struct mlx5_ifc_create_psv_in_bits {
5712 u8 opcode[0x10];
b4ff3a36 5713 u8 reserved_at_10[0x10];
e281682b 5714
b4ff3a36 5715 u8 reserved_at_20[0x10];
e281682b
SM		 5716 u8 op_mod[0x10];
5717
5718 u8 num_psv[0x4];
b4ff3a36 5719 u8 reserved_at_44[0x4];
e281682b
SM		 5720 u8 pd[0x18];
5721
b4ff3a36 5722 u8 reserved_at_60[0x20];
e281682b
SM		 5723};
5724
5725struct mlx5_ifc_create_mkey_out_bits {
5726 u8 status[0x8];
b4ff3a36 5727 u8 reserved_at_8[0x18];
e281682b
SM		 5728
5729 u8 syndrome[0x20];
5730
b4ff3a36 5731 u8 reserved_at_40[0x8];
e281682b
SM		 5732 u8 mkey_index[0x18];
5733
b4ff3a36 5734 u8 reserved_at_60[0x20];
e281682b
SM		 5735};
5736
5737struct mlx5_ifc_create_mkey_in_bits {
5738 u8 opcode[0x10];
b4ff3a36 5739 u8 reserved_at_10[0x10];
e281682b 5740
b4ff3a36 5741 u8 reserved_at_20[0x10];
e281682b
SM		 5742 u8 op_mod[0x10];
5743
b4ff3a36 5744 u8 reserved_at_40[0x20];
e281682b
SM		 5745
5746 u8 pg_access[0x1];
b4ff3a36 5747 u8 reserved_at_61[0x1f];
e281682b
SM		 5748
5749 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5750
b4ff3a36 5751 u8 reserved_at_280[0x80];
e281682b
SM		 5752
5753 u8 translations_octword_actual_size[0x20];
5754
b4ff3a36 5755 u8 reserved_at_320[0x560];
e281682b
SM		 5756
5757 u8 klm_pas_mtt[0][0x20];
5758};
5759
5760struct mlx5_ifc_create_flow_table_out_bits {
5761 u8 status[0x8];
b4ff3a36 5762 u8 reserved_at_8[0x18];
e281682b
SM		 5763
5764 u8 syndrome[0x20];
5765
b4ff3a36 5766 u8 reserved_at_40[0x8];
e281682b
SM		 5767 u8 table_id[0x18];
5768
b4ff3a36 5769 u8 reserved_at_60[0x20];
e281682b
SM		 5770};
5771
5772struct mlx5_ifc_create_flow_table_in_bits {
5773 u8 opcode[0x10];
b4ff3a36 5774 u8 reserved_at_10[0x10];
e281682b 5775
b4ff3a36 5776 u8 reserved_at_20[0x10];
e281682b
SM		 5777 u8 op_mod[0x10];
5778
b4ff3a36 5779 u8 reserved_at_40[0x40];
e281682b
SM		 5780
5781 u8 table_type[0x8];
b4ff3a36 5782 u8 reserved_at_88[0x18];
e281682b 5783
b4ff3a36 5784 u8 reserved_at_a0[0x20];
e281682b 5785
b4ff3a36 5786 u8 reserved_at_c0[0x4];
34a40e68 5787 u8 table_miss_mode[0x4];
e281682b 5788 u8 level[0x8];
b4ff3a36 5789 u8 reserved_at_d0[0x8];
e281682b
SM		 5790 u8 log_size[0x8];
5791
b4ff3a36 5792 u8 reserved_at_e0[0x8];
34a40e68
MG		 5793 u8 table_miss_id[0x18];
5794
b4ff3a36 5795 u8 reserved_at_100[0x100];
e281682b
SM		 5796};
5797
5798struct mlx5_ifc_create_flow_group_out_bits {
5799 u8 status[0x8];
b4ff3a36 5800 u8 reserved_at_8[0x18];
e281682b
SM		 5801
5802 u8 syndrome[0x20];
5803
b4ff3a36 5804 u8 reserved_at_40[0x8];
e281682b
SM		 5805 u8 group_id[0x18];
5806
b4ff3a36 5807 u8 reserved_at_60[0x20];
e281682b
SM		 5808};
5809
5810enum {
5811 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5812 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5813 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5814};
5815
5816struct mlx5_ifc_create_flow_group_in_bits {
5817 u8 opcode[0x10];
b4ff3a36 5818 u8 reserved_at_10[0x10];
e281682b 5819
b4ff3a36 5820 u8 reserved_at_20[0x10];
e281682b
SM		 5821 u8 op_mod[0x10];
5822
b4ff3a36 5823 u8 reserved_at_40[0x40];
e281682b
SM		 5824
5825 u8 table_type[0x8];
b4ff3a36 5826 u8 reserved_at_88[0x18];
e281682b 5827
b4ff3a36 5828 u8 reserved_at_a0[0x8];
e281682b
SM		 5829 u8 table_id[0x18];
5830
b4ff3a36 5831 u8 reserved_at_c0[0x20];
e281682b
SM		 5832
5833 u8 start_flow_index[0x20];
5834
b4ff3a36 5835 u8 reserved_at_100[0x20];
e281682b
SM		 5836
5837 u8 end_flow_index[0x20];
5838
b4ff3a36 5839 u8 reserved_at_140[0xa0];
e281682b 5840
b4ff3a36 5841 u8 reserved_at_1e0[0x18];
e281682b
SM		 5842 u8 match_criteria_enable[0x8];
5843
5844 struct mlx5_ifc_fte_match_param_bits match_criteria;
5845
b4ff3a36 5846 u8 reserved_at_1200[0xe00];
e281682b
SM		 5847};
5848
5849struct mlx5_ifc_create_eq_out_bits {
5850 u8 status[0x8];
b4ff3a36 5851 u8 reserved_at_8[0x18];
e281682b
SM		 5852
5853 u8 syndrome[0x20];
5854
b4ff3a36 5855 u8 reserved_at_40[0x18];
e281682b
SM		 5856 u8 eq_number[0x8];
5857
b4ff3a36 5858 u8 reserved_at_60[0x20];
e281682b
SM		 5859};
5860
5861struct mlx5_ifc_create_eq_in_bits {
5862 u8 opcode[0x10];
b4ff3a36 5863 u8 reserved_at_10[0x10];
e281682b 5864
b4ff3a36 5865 u8 reserved_at_20[0x10];
e281682b
SM		 5866 u8 op_mod[0x10];
5867
b4ff3a36 5868 u8 reserved_at_40[0x40];
e281682b
SM		 5869
5870 struct mlx5_ifc_eqc_bits eq_context_entry;
5871
b4ff3a36 5872 u8 reserved_at_280[0x40];
e281682b
SM		 5873
5874 u8 event_bitmask[0x40];
5875
b4ff3a36 5876 u8 reserved_at_300[0x580];
e281682b
SM		 5877
5878 u8 pas[0][0x40];
5879};
5880
5881struct mlx5_ifc_create_dct_out_bits {
5882 u8 status[0x8];
b4ff3a36 5883 u8 reserved_at_8[0x18];
e281682b
SM		 5884
5885 u8 syndrome[0x20];
5886
b4ff3a36 5887 u8 reserved_at_40[0x8];
e281682b
SM		 5888 u8 dctn[0x18];
5889
b4ff3a36 5890 u8 reserved_at_60[0x20];
e281682b
SM		 5891};
5892
5893struct mlx5_ifc_create_dct_in_bits {
5894 u8 opcode[0x10];
b4ff3a36 5895 u8 reserved_at_10[0x10];
e281682b 5896
b4ff3a36 5897 u8 reserved_at_20[0x10];
e281682b
SM		 5898 u8 op_mod[0x10];
5899
b4ff3a36 5900 u8 reserved_at_40[0x40];
e281682b
SM		 5901
5902 struct mlx5_ifc_dctc_bits dct_context_entry;
5903
b4ff3a36 5904 u8 reserved_at_280[0x180];
e281682b
SM		 5905};
5906
5907struct mlx5_ifc_create_cq_out_bits {
5908 u8 status[0x8];
b4ff3a36 5909 u8 reserved_at_8[0x18];
e281682b
SM		 5910
5911 u8 syndrome[0x20];
5912
b4ff3a36 5913 u8 reserved_at_40[0x8];
e281682b
SM		 5914 u8 cqn[0x18];
5915
b4ff3a36 5916 u8 reserved_at_60[0x20];
e281682b
SM		 5917};
5918
5919struct mlx5_ifc_create_cq_in_bits {
5920 u8 opcode[0x10];
b4ff3a36 5921 u8 reserved_at_10[0x10];
e281682b 5922
b4ff3a36 5923 u8 reserved_at_20[0x10];
e281682b
SM		 5924 u8 op_mod[0x10];
5925
b4ff3a36 5926 u8 reserved_at_40[0x40];
e281682b
SM		 5927
5928 struct mlx5_ifc_cqc_bits cq_context;
5929
b4ff3a36 5930 u8 reserved_at_280[0x600];
e281682b
SM		 5931
5932 u8 pas[0][0x40];
5933};
5934
5935struct mlx5_ifc_config_int_moderation_out_bits {
5936 u8 status[0x8];
b4ff3a36 5937 u8 reserved_at_8[0x18];
e281682b
SM		 5938
5939 u8 syndrome[0x20];
5940
b4ff3a36 5941 u8 reserved_at_40[0x4];
e281682b
SM		 5942 u8 min_delay[0xc];
5943 u8 int_vector[0x10];
5944
b4ff3a36 5945 u8 reserved_at_60[0x20];
e281682b
SM		 5946};
5947
5948enum {
5949 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5950 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5951};
5952
5953struct mlx5_ifc_config_int_moderation_in_bits {
5954 u8 opcode[0x10];
b4ff3a36 5955 u8 reserved_at_10[0x10];
e281682b 5956
b4ff3a36 5957 u8 reserved_at_20[0x10];
e281682b
SM		 5958 u8 op_mod[0x10];
5959
b4ff3a36 5960 u8 reserved_at_40[0x4];
e281682b
SM		 5961 u8 min_delay[0xc];
5962 u8 int_vector[0x10];
5963
b4ff3a36 5964 u8 reserved_at_60[0x20];
e281682b
SM		 5965};
5966
5967struct mlx5_ifc_attach_to_mcg_out_bits {
5968 u8 status[0x8];
b4ff3a36 5969 u8 reserved_at_8[0x18];
e281682b
SM		 5970
5971 u8 syndrome[0x20];
5972
b4ff3a36 5973 u8 reserved_at_40[0x40];
e281682b
SM		 5974};
5975
5976struct mlx5_ifc_attach_to_mcg_in_bits {
5977 u8 opcode[0x10];
b4ff3a36 5978 u8 reserved_at_10[0x10];
e281682b 5979
b4ff3a36 5980 u8 reserved_at_20[0x10];
e281682b
SM		 5981 u8 op_mod[0x10];
5982
b4ff3a36 5983 u8 reserved_at_40[0x8];
e281682b
SM		 5984 u8 qpn[0x18];
5985
b4ff3a36 5986 u8 reserved_at_60[0x20];
e281682b
SM		 5987
5988 u8 multicast_gid[16][0x8];
5989};
5990
5991struct mlx5_ifc_arm_xrc_srq_out_bits {
5992 u8 status[0x8];
b4ff3a36 5993 u8 reserved_at_8[0x18];
e281682b
SM		 5994
5995 u8 syndrome[0x20];
5996
b4ff3a36 5997 u8 reserved_at_40[0x40];
e281682b
SM		 5998};
5999
6000enum {
6001 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6002};
6003
6004struct mlx5_ifc_arm_xrc_srq_in_bits {
6005 u8 opcode[0x10];
b4ff3a36 6006 u8 reserved_at_10[0x10];
e281682b 6007
b4ff3a36 6008 u8 reserved_at_20[0x10];
e281682b
SM		 6009 u8 op_mod[0x10];
6010
b4ff3a36 6011 u8 reserved_at_40[0x8];
e281682b
SM		 6012 u8 xrc_srqn[0x18];
6013
b4ff3a36 6014 u8 reserved_at_60[0x10];
e281682b
SM		 6015 u8 lwm[0x10];
6016};
6017
6018struct mlx5_ifc_arm_rq_out_bits {
6019 u8 status[0x8];
b4ff3a36 6020 u8 reserved_at_8[0x18];
e281682b
SM		 6021
6022 u8 syndrome[0x20];
6023
b4ff3a36 6024 u8 reserved_at_40[0x40];
e281682b
SM		 6025};
6026
6027enum {
6028 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
6029};
6030
6031struct mlx5_ifc_arm_rq_in_bits {
6032 u8 opcode[0x10];
b4ff3a36 6033 u8 reserved_at_10[0x10];
e281682b 6034
b4ff3a36 6035 u8 reserved_at_20[0x10];
e281682b
SM		 6036 u8 op_mod[0x10];
6037
b4ff3a36 6038 u8 reserved_at_40[0x8];
e281682b
SM		 6039 u8 srq_number[0x18];
6040
b4ff3a36 6041 u8 reserved_at_60[0x10];
e281682b
SM		 6042 u8 lwm[0x10];
6043};
6044
6045struct mlx5_ifc_arm_dct_out_bits {
6046 u8 status[0x8];
b4ff3a36 6047 u8 reserved_at_8[0x18];
e281682b
SM		 6048
6049 u8 syndrome[0x20];
6050
b4ff3a36 6051 u8 reserved_at_40[0x40];
e281682b
SM		 6052};
6053
6054struct mlx5_ifc_arm_dct_in_bits {
6055 u8 opcode[0x10];
b4ff3a36 6056 u8 reserved_at_10[0x10];
e281682b 6057
b4ff3a36 6058 u8 reserved_at_20[0x10];
e281682b
SM		 6059 u8 op_mod[0x10];
6060
b4ff3a36 6061 u8 reserved_at_40[0x8];
e281682b
SM		 6062 u8 dct_number[0x18];
6063
b4ff3a36 6064 u8 reserved_at_60[0x20];
e281682b
SM		 6065};
6066
6067struct mlx5_ifc_alloc_xrcd_out_bits {
6068 u8 status[0x8];
b4ff3a36 6069 u8 reserved_at_8[0x18];
e281682b
SM		 6070
6071 u8 syndrome[0x20];
6072
b4ff3a36 6073 u8 reserved_at_40[0x8];
e281682b
SM		 6074 u8 xrcd[0x18];
6075
b4ff3a36 6076 u8 reserved_at_60[0x20];
e281682b
SM		 6077};
6078
6079struct mlx5_ifc_alloc_xrcd_in_bits {
6080 u8 opcode[0x10];
b4ff3a36 6081 u8 reserved_at_10[0x10];
e281682b 6082
b4ff3a36 6083 u8 reserved_at_20[0x10];
e281682b
SM		 6084 u8 op_mod[0x10];
6085
b4ff3a36 6086 u8 reserved_at_40[0x40];
e281682b
SM		 6087};
6088
6089struct mlx5_ifc_alloc_uar_out_bits {
6090 u8 status[0x8];
b4ff3a36 6091 u8 reserved_at_8[0x18];
e281682b
SM		 6092
6093 u8 syndrome[0x20];
6094
b4ff3a36 6095 u8 reserved_at_40[0x8];
e281682b
SM		 6096 u8 uar[0x18];
6097
b4ff3a36 6098 u8 reserved_at_60[0x20];
e281682b
SM		 6099};
6100
6101struct mlx5_ifc_alloc_uar_in_bits {
6102 u8 opcode[0x10];
b4ff3a36 6103 u8 reserved_at_10[0x10];
e281682b 6104
b4ff3a36 6105 u8 reserved_at_20[0x10];
e281682b
SM		 6106 u8 op_mod[0x10];
6107
b4ff3a36 6108 u8 reserved_at_40[0x40];
e281682b
SM		 6109};
6110
6111struct mlx5_ifc_alloc_transport_domain_out_bits {
6112 u8 status[0x8];
b4ff3a36 6113 u8 reserved_at_8[0x18];
e281682b
SM		 6114
6115 u8 syndrome[0x20];
6116
b4ff3a36 6117 u8 reserved_at_40[0x8];
e281682b
SM		 6118 u8 transport_domain[0x18];
6119
b4ff3a36 6120 u8 reserved_at_60[0x20];
e281682b
SM		 6121};
6122
6123struct mlx5_ifc_alloc_transport_domain_in_bits {
6124 u8 opcode[0x10];
b4ff3a36 6125 u8 reserved_at_10[0x10];
e281682b 6126
b4ff3a36 6127 u8 reserved_at_20[0x10];
e281682b
SM		 6128 u8 op_mod[0x10];
6129
b4ff3a36 6130 u8 reserved_at_40[0x40];
e281682b
SM		 6131};
6132
6133struct mlx5_ifc_alloc_q_counter_out_bits {
6134 u8 status[0x8];
b4ff3a36 6135 u8 reserved_at_8[0x18];
e281682b
SM		 6136
6137 u8 syndrome[0x20];
6138
b4ff3a36 6139 u8 reserved_at_40[0x18];
e281682b
SM		 6140 u8 counter_set_id[0x8];
6141
b4ff3a36 6142 u8 reserved_at_60[0x20];
e281682b
SM		 6143};
6144
6145struct mlx5_ifc_alloc_q_counter_in_bits {
6146 u8 opcode[0x10];
b4ff3a36 6147 u8 reserved_at_10[0x10];
e281682b 6148
b4ff3a36 6149 u8 reserved_at_20[0x10];
e281682b
SM		 6150 u8 op_mod[0x10];
6151
b4ff3a36 6152 u8 reserved_at_40[0x40];
e281682b
SM		 6153};
6154
6155struct mlx5_ifc_alloc_pd_out_bits {
6156 u8 status[0x8];
b4ff3a36 6157 u8 reserved_at_8[0x18];
e281682b
SM		 6158
6159 u8 syndrome[0x20];
6160
b4ff3a36 6161 u8 reserved_at_40[0x8];
e281682b
SM		 6162 u8 pd[0x18];
6163
b4ff3a36 6164 u8 reserved_at_60[0x20];
e281682b
SM		 6165};
6166
6167struct mlx5_ifc_alloc_pd_in_bits {
6168 u8 opcode[0x10];
b4ff3a36 6169 u8 reserved_at_10[0x10];
e281682b 6170
b4ff3a36 6171 u8 reserved_at_20[0x10];
e281682b
SM		 6172 u8 op_mod[0x10];
6173
b4ff3a36 6174 u8 reserved_at_40[0x40];
e281682b
SM		 6175};
6176
6177struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6178 u8 status[0x8];
b4ff3a36 6179 u8 reserved_at_8[0x18];
e281682b
SM		 6180
6181 u8 syndrome[0x20];
6182
b4ff3a36 6183 u8 reserved_at_40[0x40];
e281682b
SM		 6184};
6185
6186struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6187 u8 opcode[0x10];
b4ff3a36 6188 u8 reserved_at_10[0x10];
e281682b 6189
b4ff3a36 6190 u8 reserved_at_20[0x10];
e281682b
SM		 6191 u8 op_mod[0x10];
6192
b4ff3a36 6193 u8 reserved_at_40[0x20];
e281682b 6194
b4ff3a36 6195 u8 reserved_at_60[0x10];
e281682b
SM		 6196 u8 vxlan_udp_port[0x10];
6197};
6198
6199struct mlx5_ifc_access_register_out_bits {
6200 u8 status[0x8];
b4ff3a36 6201 u8 reserved_at_8[0x18];
e281682b
SM		 6202
6203 u8 syndrome[0x20];
6204
b4ff3a36 6205 u8 reserved_at_40[0x40];
e281682b
SM		 6206
6207 u8 register_data[0][0x20];
6208};
6209
6210enum {
6211 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6212 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6213};
6214
6215struct mlx5_ifc_access_register_in_bits {
6216 u8 opcode[0x10];
b4ff3a36 6217 u8 reserved_at_10[0x10];
e281682b 6218
b4ff3a36 6219 u8 reserved_at_20[0x10];
e281682b
SM		 6220 u8 op_mod[0x10];
6221
b4ff3a36 6222 u8 reserved_at_40[0x10];
e281682b
SM		 6223 u8 register_id[0x10];
6224
6225 u8 argument[0x20];
6226
6227 u8 register_data[0][0x20];
6228};
6229
6230struct mlx5_ifc_sltp_reg_bits {
6231 u8 status[0x4];
6232 u8 version[0x4];
6233 u8 local_port[0x8];
6234 u8 pnat[0x2];
b4ff3a36 6235 u8 reserved_at_12[0x2];
e281682b 6236 u8 lane[0x4];
b4ff3a36 6237 u8 reserved_at_18[0x8];
e281682b 6238
b4ff3a36 6239 u8 reserved_at_20[0x20];
e281682b 6240
b4ff3a36 6241 u8 reserved_at_40[0x7];
e281682b
SM		 6242 u8 polarity[0x1];
6243 u8 ob_tap0[0x8];
6244 u8 ob_tap1[0x8];
6245 u8 ob_tap2[0x8];
6246
b4ff3a36 6247 u8 reserved_at_60[0xc];
e281682b
SM		 6248 u8 ob_preemp_mode[0x4];
6249 u8 ob_reg[0x8];
6250 u8 ob_bias[0x8];
6251
b4ff3a36 6252 u8 reserved_at_80[0x20];
e281682b
SM		 6253};
6254
6255struct mlx5_ifc_slrg_reg_bits {
6256 u8 status[0x4];
6257 u8 version[0x4];
6258 u8 local_port[0x8];
6259 u8 pnat[0x2];
b4ff3a36 6260 u8 reserved_at_12[0x2];
e281682b 6261 u8 lane[0x4];
b4ff3a36 6262 u8 reserved_at_18[0x8];
e281682b
SM		 6263
6264 u8 time_to_link_up[0x10];
b4ff3a36 6265 u8 reserved_at_30[0xc];
e281682b
SM		 6266 u8 grade_lane_speed[0x4];
6267
6268 u8 grade_version[0x8];
6269 u8 grade[0x18];
6270
b4ff3a36 6271 u8 reserved_at_60[0x4];
e281682b
SM		 6272 u8 height_grade_type[0x4];
6273 u8 height_grade[0x18];
6274
6275 u8 height_dz[0x10];
6276 u8 height_dv[0x10];
6277
b4ff3a36 6278 u8 reserved_at_a0[0x10];
e281682b
SM		 6279 u8 height_sigma[0x10];
6280
b4ff3a36 6281 u8 reserved_at_c0[0x20];
e281682b 6282
b4ff3a36 6283 u8 reserved_at_e0[0x4];
e281682b
SM		 6284 u8 phase_grade_type[0x4];
6285 u8 phase_grade[0x18];
6286
b4ff3a36 6287 u8 reserved_at_100[0x8];
e281682b 6288 u8 phase_eo_pos[0x8];
b4ff3a36 6289 u8 reserved_at_110[0x8];
e281682b
SM		 6290 u8 phase_eo_neg[0x8];
6291
6292 u8 ffe_set_tested[0x10];
6293 u8 test_errors_per_lane[0x10];
6294};
6295
6296struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 6297 u8 reserved_at_0[0x8];
e281682b 6298 u8 local_port[0x8];
b4ff3a36 6299 u8 reserved_at_10[0x10];
e281682b 6300
b4ff3a36 6301 u8 reserved_at_20[0x1c];
e281682b
SM		 6302 u8 vl_hw_cap[0x4];
6303
b4ff3a36 6304 u8 reserved_at_40[0x1c];
e281682b
SM		 6305 u8 vl_admin[0x4];
6306
b4ff3a36 6307 u8 reserved_at_60[0x1c];
e281682b
SM		 6308 u8 vl_operational[0x4];
6309};
6310
6311struct mlx5_ifc_pude_reg_bits {
6312 u8 swid[0x8];
6313 u8 local_port[0x8];
b4ff3a36 6314 u8 reserved_at_10[0x4];
e281682b 6315 u8 admin_status[0x4];
b4ff3a36 6316 u8 reserved_at_18[0x4];
e281682b
SM		 6317 u8 oper_status[0x4];
6318
b4ff3a36 6319 u8 reserved_at_20[0x60];
e281682b
SM		 6320};
6321
6322struct mlx5_ifc_ptys_reg_bits {
b4ff3a36 6323 u8 reserved_at_0[0x8];
e281682b 6324 u8 local_port[0x8];
b4ff3a36 6325 u8 reserved_at_10[0xd];
e281682b
SM		 6326 u8 proto_mask[0x3];
6327
b4ff3a36 6328 u8 reserved_at_20[0x40];
e281682b
SM		 6329
6330 u8 eth_proto_capability[0x20];
6331
6332 u8 ib_link_width_capability[0x10];
6333 u8 ib_proto_capability[0x10];
6334
b4ff3a36 6335 u8 reserved_at_a0[0x20];
e281682b
SM		 6336
6337 u8 eth_proto_admin[0x20];
6338
6339 u8 ib_link_width_admin[0x10];
6340 u8 ib_proto_admin[0x10];
6341
b4ff3a36 6342 u8 reserved_at_100[0x20];
e281682b
SM		 6343
6344 u8 eth_proto_oper[0x20];
6345
6346 u8 ib_link_width_oper[0x10];
6347 u8 ib_proto_oper[0x10];
6348
b4ff3a36 6349 u8 reserved_at_160[0x20];
e281682b
SM		 6350
6351 u8 eth_proto_lp_advertise[0x20];
6352
b4ff3a36 6353 u8 reserved_at_1a0[0x60];
e281682b
SM		 6354};
6355
6356struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 6357 u8 reserved_at_0[0x20];
e281682b
SM		 6358
6359 u8 algorithm_options[0x10];
b4ff3a36 6360 u8 reserved_at_30[0x4];
e281682b
SM		 6361 u8 repetitions_mode[0x4];
6362 u8 num_of_repetitions[0x8];
6363
6364 u8 grade_version[0x8];
6365 u8 height_grade_type[0x4];
6366 u8 phase_grade_type[0x4];
6367 u8 height_grade_weight[0x8];
6368 u8 phase_grade_weight[0x8];
6369
6370 u8 gisim_measure_bits[0x10];
6371 u8 adaptive_tap_measure_bits[0x10];
6372
6373 u8 ber_bath_high_error_threshold[0x10];
6374 u8 ber_bath_mid_error_threshold[0x10];
6375
6376 u8 ber_bath_low_error_threshold[0x10];
6377 u8 one_ratio_high_threshold[0x10];
6378
6379 u8 one_ratio_high_mid_threshold[0x10];
6380 u8 one_ratio_low_mid_threshold[0x10];
6381
6382 u8 one_ratio_low_threshold[0x10];
6383 u8 ndeo_error_threshold[0x10];
6384
6385 u8 mixer_offset_step_size[0x10];
b4ff3a36 6386 u8 reserved_at_110[0x8];
e281682b
SM		 6387 u8 mix90_phase_for_voltage_bath[0x8];
6388
6389 u8 mixer_offset_start[0x10];
6390 u8 mixer_offset_end[0x10];
6391
b4ff3a36 6392 u8 reserved_at_140[0x15];
e281682b
SM		 6393 u8 ber_test_time[0xb];
6394};
6395
6396struct mlx5_ifc_pspa_reg_bits {
6397 u8 swid[0x8];
6398 u8 local_port[0x8];
6399 u8 sub_port[0x8];
b4ff3a36 6400 u8 reserved_at_18[0x8];
e281682b 6401
b4ff3a36 6402 u8 reserved_at_20[0x20];
e281682b
SM		 6403};
6404
6405struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 6406 u8 reserved_at_0[0x8];
e281682b 6407 u8 local_port[0x8];
b4ff3a36 6408 u8 reserved_at_10[0x5];
e281682b 6409 u8 prio[0x3];
b4ff3a36 6410 u8 reserved_at_18[0x6];
e281682b
SM		 6411 u8 mode[0x2];
6412
b4ff3a36 6413 u8 reserved_at_20[0x20];
e281682b 6414
b4ff3a36 6415 u8 reserved_at_40[0x10];
e281682b
SM		 6416 u8 min_threshold[0x10];
6417
b4ff3a36 6418 u8 reserved_at_60[0x10];
e281682b
SM		 6419 u8 max_threshold[0x10];
6420
b4ff3a36 6421 u8 reserved_at_80[0x10];
e281682b
SM		 6422 u8 mark_probability_denominator[0x10];
6423
b4ff3a36 6424 u8 reserved_at_a0[0x60];
e281682b
SM		 6425};
6426
6427struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 6428 u8 reserved_at_0[0x8];
e281682b 6429 u8 local_port[0x8];
b4ff3a36 6430 u8 reserved_at_10[0x10];
e281682b 6431
b4ff3a36 6432 u8 reserved_at_20[0x60];
e281682b 6433
b4ff3a36 6434 u8 reserved_at_80[0x1c];
e281682b
SM		 6435 u8 wrps_admin[0x4];
6436
b4ff3a36 6437 u8 reserved_at_a0[0x1c];
e281682b
SM		 6438 u8 wrps_status[0x4];
6439
b4ff3a36 6440 u8 reserved_at_c0[0x8];
e281682b 6441 u8 up_threshold[0x8];
b4ff3a36 6442 u8 reserved_at_d0[0x8];
e281682b
SM		 6443 u8 down_threshold[0x8];
6444
b4ff3a36 6445 u8 reserved_at_e0[0x20];
e281682b 6446
b4ff3a36 6447 u8 reserved_at_100[0x1c];
e281682b
SM		 6448 u8 srps_admin[0x4];
6449
b4ff3a36 6450 u8 reserved_at_120[0x1c];
e281682b
SM		 6451 u8 srps_status[0x4];
6452
b4ff3a36 6453 u8 reserved_at_140[0x40];
e281682b
SM		 6454};
6455
6456struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 6457 u8 reserved_at_0[0x8];
e281682b 6458 u8 local_port[0x8];
b4ff3a36 6459 u8 reserved_at_10[0x10];
e281682b 6460
b4ff3a36 6461 u8 reserved_at_20[0x8];
e281682b 6462 u8 lb_cap[0x8];
b4ff3a36 6463 u8 reserved_at_30[0x8];
e281682b
SM		 6464 u8 lb_en[0x8];
6465};
6466
6467struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 6468 u8 reserved_at_0[0x8];
e281682b 6469 u8 local_port[0x8];
b4ff3a36 6470 u8 reserved_at_10[0x10];
e281682b 6471
b4ff3a36 6472 u8 reserved_at_20[0x20];
e281682b
SM		 6473
6474 u8 port_profile_mode[0x8];
6475 u8 static_port_profile[0x8];
6476 u8 active_port_profile[0x8];
b4ff3a36 6477 u8 reserved_at_58[0x8];
e281682b
SM		 6478
6479 u8 retransmission_active[0x8];
6480 u8 fec_mode_active[0x18];
6481
b4ff3a36 6482 u8 reserved_at_80[0x20];
e281682b
SM		 6483};
6484
6485struct mlx5_ifc_ppcnt_reg_bits {
6486 u8 swid[0x8];
6487 u8 local_port[0x8];
6488 u8 pnat[0x2];
b4ff3a36 6489 u8 reserved_at_12[0x8];
e281682b
SM		 6490 u8 grp[0x6];
6491
6492 u8 clr[0x1];
b4ff3a36 6493 u8 reserved_at_21[0x1c];
e281682b
SM		 6494 u8 prio_tc[0x3];
6495
6496 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6497};
6498
6499struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 6500 u8 reserved_at_0[0x3];
e281682b 6501 u8 single_mac[0x1];
b4ff3a36 6502 u8 reserved_at_4[0x4];
e281682b
SM		 6503 u8 local_port[0x8];
6504 u8 mac_47_32[0x10];
6505
6506 u8 mac_31_0[0x20];
6507
b4ff3a36 6508 u8 reserved_at_40[0x40];
e281682b
SM		 6509};
6510
6511struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 6512 u8 reserved_at_0[0x8];
e281682b 6513 u8 local_port[0x8];
b4ff3a36 6514 u8 reserved_at_10[0x10];
e281682b
SM		 6515
6516 u8 max_mtu[0x10];
b4ff3a36 6517 u8 reserved_at_30[0x10];
e281682b
SM		 6518
6519 u8 admin_mtu[0x10];
b4ff3a36 6520 u8 reserved_at_50[0x10];
e281682b
SM		 6521
6522 u8 oper_mtu[0x10];
b4ff3a36 6523 u8 reserved_at_70[0x10];
e281682b
SM		 6524};
6525
6526struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 6527 u8 reserved_at_0[0x8];
e281682b 6528 u8 module[0x8];
b4ff3a36 6529 u8 reserved_at_10[0x10];
e281682b 6530
b4ff3a36 6531 u8 reserved_at_20[0x18];
e281682b
SM		 6532 u8 attenuation_5g[0x8];
6533
b4ff3a36 6534 u8 reserved_at_40[0x18];
e281682b
SM		 6535 u8 attenuation_7g[0x8];
6536
b4ff3a36 6537 u8 reserved_at_60[0x18];
e281682b
SM		 6538 u8 attenuation_12g[0x8];
6539};
6540
6541struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 6542 u8 reserved_at_0[0x8];
e281682b 6543 u8 module[0x8];
b4ff3a36 6544 u8 reserved_at_10[0xc];
e281682b
SM		 6545 u8 module_status[0x4];
6546
b4ff3a36 6547 u8 reserved_at_20[0x60];
e281682b
SM		 6548};
6549
6550struct mlx5_ifc_pmpc_reg_bits {
6551 u8 module_state_updated[32][0x8];
6552};
6553
6554struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 6555 u8 reserved_at_0[0x4];
e281682b
SM		 6556 u8 mlpn_status[0x4];
6557 u8 local_port[0x8];
b4ff3a36 6558 u8 reserved_at_10[0x10];
e281682b
SM		 6559
6560 u8 e[0x1];
b4ff3a36 6561 u8 reserved_at_21[0x1f];
e281682b
SM		 6562};
6563
6564struct mlx5_ifc_pmlp_reg_bits {
6565 u8 rxtx[0x1];
b4ff3a36 6566 u8 reserved_at_1[0x7];
e281682b 6567 u8 local_port[0x8];
b4ff3a36 6568 u8 reserved_at_10[0x8];
e281682b
SM		 6569 u8 width[0x8];
6570
6571 u8 lane0_module_mapping[0x20];
6572
6573 u8 lane1_module_mapping[0x20];
6574
6575 u8 lane2_module_mapping[0x20];
6576
6577 u8 lane3_module_mapping[0x20];
6578
b4ff3a36 6579 u8 reserved_at_a0[0x160];
e281682b
SM		 6580};
6581
6582struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 6583 u8 reserved_at_0[0x8];
e281682b 6584 u8 module[0x8];
b4ff3a36 6585 u8 reserved_at_10[0x4];
e281682b 6586 u8 admin_status[0x4];
b4ff3a36 6587 u8 reserved_at_18[0x4];
e281682b
SM		 6588 u8 oper_status[0x4];
6589
6590 u8 ase[0x1];
6591 u8 ee[0x1];
b4ff3a36 6592 u8 reserved_at_22[0x1c];
e281682b
SM		 6593 u8 e[0x2];
6594
b4ff3a36 6595 u8 reserved_at_40[0x40];
e281682b
SM		 6596};
6597
6598struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 6599 u8 reserved_at_0[0x4];
e281682b 6600 u8 profile_id[0xc];
b4ff3a36 6601 u8 reserved_at_10[0x4];
e281682b 6602 u8 proto_mask[0x4];
b4ff3a36 6603 u8 reserved_at_18[0x8];
e281682b 6604
b4ff3a36 6605 u8 reserved_at_20[0x10];
e281682b
SM		 6606 u8 lane_speed[0x10];
6607
b4ff3a36 6608 u8 reserved_at_40[0x17];
e281682b
SM		 6609 u8 lpbf[0x1];
6610 u8 fec_mode_policy[0x8];
6611
6612 u8 retransmission_capability[0x8];
6613 u8 fec_mode_capability[0x18];
6614
6615 u8 retransmission_support_admin[0x8];
6616 u8 fec_mode_support_admin[0x18];
6617
6618 u8 retransmission_request_admin[0x8];
6619 u8 fec_mode_request_admin[0x18];
6620
b4ff3a36 6621 u8 reserved_at_c0[0x80];
e281682b
SM		 6622};
6623
6624struct mlx5_ifc_plib_reg_bits {
b4ff3a36 6625 u8 reserved_at_0[0x8];
e281682b 6626 u8 local_port[0x8];
b4ff3a36 6627 u8 reserved_at_10[0x8];
e281682b
SM		 6628 u8 ib_port[0x8];
6629
b4ff3a36 6630 u8 reserved_at_20[0x60];
e281682b
SM		 6631};
6632
6633struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 6634 u8 reserved_at_0[0x8];
e281682b 6635 u8 local_port[0x8];
b4ff3a36 6636 u8 reserved_at_10[0xd];
e281682b
SM		 6637 u8 lbf_mode[0x3];
6638
b4ff3a36 6639 u8 reserved_at_20[0x20];
e281682b
SM		 6640};
6641
6642struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 6643 u8 reserved_at_0[0x8];
e281682b 6644 u8 local_port[0x8];
b4ff3a36 6645 u8 reserved_at_10[0x10];
e281682b
SM		 6646
6647 u8 dic[0x1];
b4ff3a36 6648 u8 reserved_at_21[0x19];
e281682b 6649 u8 ipg[0x4];
b4ff3a36 6650 u8 reserved_at_3e[0x2];
e281682b
SM		 6651};
6652
6653struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 6654 u8 reserved_at_0[0x8];
e281682b 6655 u8 local_port[0x8];
b4ff3a36 6656 u8 reserved_at_10[0x10];
e281682b 6657
b4ff3a36 6658 u8 reserved_at_20[0xe0];
e281682b
SM		 6659
6660 u8 port_filter[8][0x20];
6661
6662 u8 port_filter_update_en[8][0x20];
6663};
6664
6665struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 6666 u8 reserved_at_0[0x8];
e281682b 6667 u8 local_port[0x8];
b4ff3a36 6668 u8 reserved_at_10[0x10];
e281682b
SM		 6669
6670 u8 ppan[0x4];
b4ff3a36 6671 u8 reserved_at_24[0x4];
e281682b 6672 u8 prio_mask_tx[0x8];
b4ff3a36 6673 u8 reserved_at_30[0x8];
e281682b
SM		 6674 u8 prio_mask_rx[0x8];
6675
6676 u8 pptx[0x1];
6677 u8 aptx[0x1];
b4ff3a36 6678 u8 reserved_at_42[0x6];
e281682b 6679 u8 pfctx[0x8];
b4ff3a36 6680 u8 reserved_at_50[0x10];
e281682b
SM		 6681
6682 u8 pprx[0x1];
6683 u8 aprx[0x1];
b4ff3a36 6684 u8 reserved_at_62[0x6];
e281682b 6685 u8 pfcrx[0x8];
b4ff3a36 6686 u8 reserved_at_70[0x10];
e281682b 6687
b4ff3a36 6688 u8 reserved_at_80[0x80];
e281682b
SM		 6689};
6690
6691struct mlx5_ifc_pelc_reg_bits {
6692 u8 op[0x4];
b4ff3a36 6693 u8 reserved_at_4[0x4];
e281682b 6694 u8 local_port[0x8];
b4ff3a36 6695 u8 reserved_at_10[0x10];
e281682b
SM		 6696
6697 u8 op_admin[0x8];
6698 u8 op_capability[0x8];
6699 u8 op_request[0x8];
6700 u8 op_active[0x8];
6701
6702 u8 admin[0x40];
6703
6704 u8 capability[0x40];
6705
6706 u8 request[0x40];
6707
6708 u8 active[0x40];
6709
b4ff3a36 6710 u8 reserved_at_140[0x80];
e281682b
SM		 6711};
6712
6713struct mlx5_ifc_peir_reg_bits {
b4ff3a36 6714 u8 reserved_at_0[0x8];
e281682b 6715 u8 local_port[0x8];
b4ff3a36 6716 u8 reserved_at_10[0x10];
e281682b 6717
b4ff3a36 6718 u8 reserved_at_20[0xc];
e281682b 6719 u8 error_count[0x4];
b4ff3a36 6720 u8 reserved_at_30[0x10];
e281682b 6721
b4ff3a36 6722 u8 reserved_at_40[0xc];
e281682b 6723 u8 lane[0x4];
b4ff3a36 6724 u8 reserved_at_50[0x8];
e281682b
SM		 6725 u8 error_type[0x8];
6726};
6727
6728struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 6729 u8 reserved_at_0[0x8];
e281682b 6730 u8 local_port[0x8];
b4ff3a36 6731 u8 reserved_at_10[0x10];
e281682b
SM		 6732
6733 u8 port_capability_mask[4][0x20];
6734};
6735
6736struct mlx5_ifc_paos_reg_bits {
6737 u8 swid[0x8];
6738 u8 local_port[0x8];
b4ff3a36 6739 u8 reserved_at_10[0x4];
e281682b 6740 u8 admin_status[0x4];
b4ff3a36 6741 u8 reserved_at_18[0x4];
e281682b
SM		 6742 u8 oper_status[0x4];
6743
6744 u8 ase[0x1];
6745 u8 ee[0x1];
b4ff3a36 6746 u8 reserved_at_22[0x1c];
e281682b
SM		 6747 u8 e[0x2];
6748
b4ff3a36 6749 u8 reserved_at_40[0x40];
e281682b
SM		 6750};
6751
6752struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 6753 u8 reserved_at_0[0x8];
e281682b 6754 u8 opamp_group[0x8];
b4ff3a36 6755 u8 reserved_at_10[0xc];
e281682b
SM		 6756 u8 opamp_group_type[0x4];
6757
6758 u8 start_index[0x10];
b4ff3a36 6759 u8 reserved_at_30[0x4];
e281682b
SM		 6760 u8 num_of_indices[0xc];
6761
6762 u8 index_data[18][0x10];
6763};
6764
6765struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 6766 u8 reserved_at_0[0x6];
e281682b 6767 u8 rx_lane[0x2];
b4ff3a36 6768 u8 reserved_at_8[0x6];
e281682b 6769 u8 tx_lane[0x2];
b4ff3a36 6770 u8 reserved_at_10[0x8];
e281682b
SM		 6771 u8 module[0x8];
6772};
6773
6774struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 6775 u8 reserved_at_0[0x6];
e281682b
SM		 6776 u8 lossy[0x1];
6777 u8 epsb[0x1];
b4ff3a36 6778 u8 reserved_at_8[0xc];
e281682b
SM		 6779 u8 size[0xc];
6780
6781 u8 xoff_threshold[0x10];
6782 u8 xon_threshold[0x10];
6783};
6784
6785struct mlx5_ifc_set_node_in_bits {
6786 u8 node_description[64][0x8];
6787};
6788
6789struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 6790 u8 reserved_at_0[0x18];
e281682b
SM		 6791 u8 power_settings_level[0x8];
6792
b4ff3a36 6793 u8 reserved_at_20[0x60];
e281682b
SM		 6794};
6795
6796struct mlx5_ifc_register_host_endianness_bits {
6797 u8 he[0x1];
b4ff3a36 6798 u8 reserved_at_1[0x1f];
e281682b 6799
b4ff3a36 6800 u8 reserved_at_20[0x60];
e281682b
SM		 6801};
6802
6803struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 6804 u8 reserved_at_0[0x20];
e281682b
SM		 6805
6806 u8 mkey[0x20];
6807
6808 u8 addressh_63_32[0x20];
6809
6810 u8 addressl_31_0[0x20];
6811};
6812
6813struct mlx5_ifc_ud_adrs_vector_bits {
6814 u8 dc_key[0x40];
6815
6816 u8 ext[0x1];
b4ff3a36 6817 u8 reserved_at_41[0x7];
e281682b
SM		 6818 u8 destination_qp_dct[0x18];
6819
6820 u8 static_rate[0x4];
6821 u8 sl_eth_prio[0x4];
6822 u8 fl[0x1];
6823 u8 mlid[0x7];
6824 u8 rlid_udp_sport[0x10];
6825
b4ff3a36 6826 u8 reserved_at_80[0x20];
e281682b
SM		 6827
6828 u8 rmac_47_16[0x20];
6829
6830 u8 rmac_15_0[0x10];
6831 u8 tclass[0x8];
6832 u8 hop_limit[0x8];
6833
b4ff3a36 6834 u8 reserved_at_e0[0x1];
e281682b 6835 u8 grh[0x1];
b4ff3a36 6836 u8 reserved_at_e2[0x2];
e281682b
SM		 6837 u8 src_addr_index[0x8];
6838 u8 flow_label[0x14];
6839
6840 u8 rgid_rip[16][0x8];
6841};
6842
6843struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 6844 u8 reserved_at_0[0x10];
e281682b
SM		 6845 u8 function_id[0x10];
6846
6847 u8 num_pages[0x20];
6848
b4ff3a36 6849 u8 reserved_at_40[0xa0];
e281682b
SM		 6850};
6851
6852struct mlx5_ifc_eqe_bits {
b4ff3a36 6853 u8 reserved_at_0[0x8];
e281682b 6854 u8 event_type[0x8];
b4ff3a36 6855 u8 reserved_at_10[0x8];
e281682b
SM		 6856 u8 event_sub_type[0x8];
6857
b4ff3a36 6858 u8 reserved_at_20[0xe0];
e281682b
SM		 6859
6860 union mlx5_ifc_event_auto_bits event_data;
6861
b4ff3a36 6862 u8 reserved_at_1e0[0x10];
e281682b 6863 u8 signature[0x8];
b4ff3a36 6864 u8 reserved_at_1f8[0x7];
e281682b
SM		 6865 u8 owner[0x1];
6866};
6867
6868enum {
6869 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6870};
6871
6872struct mlx5_ifc_cmd_queue_entry_bits {
6873 u8 type[0x8];
b4ff3a36 6874 u8 reserved_at_8[0x18];
e281682b
SM		 6875
6876 u8 input_length[0x20];
6877
6878 u8 input_mailbox_pointer_63_32[0x20];
6879
6880 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 6881 u8 reserved_at_77[0x9];
e281682b
SM		 6882
6883 u8 command_input_inline_data[16][0x8];
6884
6885 u8 command_output_inline_data[16][0x8];
6886
6887 u8 output_mailbox_pointer_63_32[0x20];
6888
6889 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 6890 u8 reserved_at_1b7[0x9];
e281682b
SM		 6891
6892 u8 output_length[0x20];
6893
6894 u8 token[0x8];
6895 u8 signature[0x8];
b4ff3a36 6896 u8 reserved_at_1f0[0x8];
e281682b
SM		 6897 u8 status[0x7];
6898 u8 ownership[0x1];
6899};
6900
6901struct mlx5_ifc_cmd_out_bits {
6902 u8 status[0x8];
b4ff3a36 6903 u8 reserved_at_8[0x18];
e281682b
SM		 6904
6905 u8 syndrome[0x20];
6906
6907 u8 command_output[0x20];
6908};
6909
6910struct mlx5_ifc_cmd_in_bits {
6911 u8 opcode[0x10];
b4ff3a36 6912 u8 reserved_at_10[0x10];
e281682b 6913
b4ff3a36 6914 u8 reserved_at_20[0x10];
e281682b
SM		 6915 u8 op_mod[0x10];
6916
6917 u8 command[0][0x20];
6918};
6919
6920struct mlx5_ifc_cmd_if_box_bits {
6921 u8 mailbox_data[512][0x8];
6922
b4ff3a36 6923 u8 reserved_at_1000[0x180];
e281682b
SM		 6924
6925 u8 next_pointer_63_32[0x20];
6926
6927 u8 next_pointer_31_10[0x16];
b4ff3a36 6928 u8 reserved_at_11b6[0xa];
e281682b
SM		 6929
6930 u8 block_number[0x20];
6931
b4ff3a36 6932 u8 reserved_at_11e0[0x8];
e281682b
SM		 6933 u8 token[0x8];
6934 u8 ctrl_signature[0x8];
6935 u8 signature[0x8];
6936};
6937
6938struct mlx5_ifc_mtt_bits {
6939 u8 ptag_63_32[0x20];
6940
6941 u8 ptag_31_8[0x18];
b4ff3a36 6942 u8 reserved_at_38[0x6];
e281682b
SM		 6943 u8 wr_en[0x1];
6944 u8 rd_en[0x1];
6945};
6946
6947enum {
6948 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6949 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6950 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6951};
6952
6953enum {
6954 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6955 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6956 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6957};
6958
6959enum {
6960 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6961 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6962 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6963 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6964 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6965 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6966 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6967 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6968 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6969 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6970 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6971};
6972
6973struct mlx5_ifc_initial_seg_bits {
6974 u8 fw_rev_minor[0x10];
6975 u8 fw_rev_major[0x10];
6976
6977 u8 cmd_interface_rev[0x10];
6978 u8 fw_rev_subminor[0x10];
6979
b4ff3a36 6980 u8 reserved_at_40[0x40];
e281682b
SM		 6981
6982 u8 cmdq_phy_addr_63_32[0x20];
6983
6984 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 6985 u8 reserved_at_b4[0x2];
e281682b
SM		 6986 u8 nic_interface[0x2];
6987 u8 log_cmdq_size[0x4];
6988 u8 log_cmdq_stride[0x4];
6989
6990 u8 command_doorbell_vector[0x20];
6991
b4ff3a36 6992 u8 reserved_at_e0[0xf00];
e281682b
SM		 6993
6994 u8 initializing[0x1];
b4ff3a36 6995 u8 reserved_at_fe1[0x4];
e281682b 6996 u8 nic_interface_supported[0x3];
b4ff3a36 6997 u8 reserved_at_fe8[0x18];
e281682b
SM		 6998
6999 struct mlx5_ifc_health_buffer_bits health_buffer;
7000
7001 u8 no_dram_nic_offset[0x20];
7002
b4ff3a36 7003 u8 reserved_at_1220[0x6e40];
e281682b 7004
b4ff3a36 7005 u8 reserved_at_8060[0x1f];
e281682b
SM		 7006 u8 clear_int[0x1];
7007
7008 u8 health_syndrome[0x8];
7009 u8 health_counter[0x18];
7010
b4ff3a36 7011 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7012};
7013
7014union mlx5_ifc_ports_control_registers_document_bits {
7015 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7016 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7017 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7018 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7019 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7020 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7021 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7022 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7023 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7024 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7025 struct mlx5_ifc_paos_reg_bits paos_reg;
7026 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7027 struct mlx5_ifc_peir_reg_bits peir_reg;
7028 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7029 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7030 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7031 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7032 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7033 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7034 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7035 struct mlx5_ifc_plib_reg_bits plib_reg;
7036 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7037 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7038 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7039 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7040 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7041 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7042 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7043 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7044 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7045 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7046 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7047 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7048 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7049 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7050 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7051 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7052 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7053 struct mlx5_ifc_pude_reg_bits pude_reg;
7054 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7055 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7056 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7057 u8 reserved_at_0[0x60e0];
e281682b
SM		 7058};
7059
7060union mlx5_ifc_debug_enhancements_document_bits {
7061 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7062 u8 reserved_at_0[0x200];
e281682b
SM		 7063};
7064
7065union mlx5_ifc_uplink_pci_interface_document_bits {
7066 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7067 u8 reserved_at_0[0x20060];
b775516b
EC		 7068};
7069
2cc43b49
MG		 7070struct mlx5_ifc_set_flow_table_root_out_bits {
7071 u8 status[0x8];
b4ff3a36 7072 u8 reserved_at_8[0x18];
2cc43b49
MG		 7073
7074 u8 syndrome[0x20];
7075
b4ff3a36 7076 u8 reserved_at_40[0x40];
2cc43b49
MG		 7077};
7078
7079struct mlx5_ifc_set_flow_table_root_in_bits {
7080 u8 opcode[0x10];
b4ff3a36 7081 u8 reserved_at_10[0x10];
2cc43b49 7082
b4ff3a36 7083 u8 reserved_at_20[0x10];
2cc43b49
MG		 7084 u8 op_mod[0x10];
7085
b4ff3a36 7086 u8 reserved_at_40[0x40];
2cc43b49
MG		 7087
7088 u8 table_type[0x8];
b4ff3a36 7089 u8 reserved_at_88[0x18];
2cc43b49 7090
b4ff3a36 7091 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7092 u8 table_id[0x18];
7093
b4ff3a36 7094 u8 reserved_at_c0[0x140];
2cc43b49
MG		 7095};
7096
34a40e68
MG		 7097enum {
7098 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7099};
7100
7101struct mlx5_ifc_modify_flow_table_out_bits {
7102 u8 status[0x8];
b4ff3a36 7103 u8 reserved_at_8[0x18];
34a40e68
MG		 7104
7105 u8 syndrome[0x20];
7106
b4ff3a36 7107 u8 reserved_at_40[0x40];
34a40e68
MG		 7108};
7109
7110struct mlx5_ifc_modify_flow_table_in_bits {
7111 u8 opcode[0x10];
b4ff3a36 7112 u8 reserved_at_10[0x10];
34a40e68 7113
b4ff3a36 7114 u8 reserved_at_20[0x10];
34a40e68
MG		 7115 u8 op_mod[0x10];
7116
b4ff3a36 7117 u8 reserved_at_40[0x20];
34a40e68 7118
b4ff3a36 7119 u8 reserved_at_60[0x10];
34a40e68
MG		 7120 u8 modify_field_select[0x10];
7121
7122 u8 table_type[0x8];
b4ff3a36 7123 u8 reserved_at_88[0x18];
34a40e68 7124
b4ff3a36 7125 u8 reserved_at_a0[0x8];
34a40e68
MG		 7126 u8 table_id[0x18];
7127
b4ff3a36 7128 u8 reserved_at_c0[0x4];
34a40e68 7129 u8 table_miss_mode[0x4];
b4ff3a36 7130 u8 reserved_at_c8[0x18];
34a40e68 7131
b4ff3a36 7132 u8 reserved_at_e0[0x8];
34a40e68
MG		 7133 u8 table_miss_id[0x18];
7134
b4ff3a36 7135 u8 reserved_at_100[0x100];
34a40e68
MG		 7136};
7137
d29b796a 7138#endif /* MLX5_IFC_H */
Linux kernel - Deliverables
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