[deliverable/linux.git] / include / linux / mmc / dw_mmc.h

/*
 * Synopsys DesignWare Multimedia Card Interface driver
 *  (Based on NXP driver for lpc 31xx)
 *
 * Copyright (C) 2009 NXP Semiconductors
 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef LINUX_MMC_DW_MMC_H
#define LINUX_MMC_DW_MMC_H

#include <linux/scatterlist.h>

#define MAX_MCI_SLOTS	2

enum dw_mci_state {
	STATE_IDLE = 0,
	STATE_SENDING_CMD,
	STATE_SENDING_DATA,
	STATE_DATA_BUSY,
	STATE_SENDING_STOP,
	STATE_DATA_ERROR,
};

enum {
	EVENT_CMD_COMPLETE = 0,
	EVENT_XFER_COMPLETE,
	EVENT_DATA_COMPLETE,
	EVENT_DATA_ERROR,
	EVENT_XFER_ERROR
};

struct mmc_data;

/**
 * struct dw_mci - MMC controller state shared between all slots
 * @lock: Spinlock protecting the queue and associated data.
 * @regs: Pointer to MMIO registers.
 * @sg: Scatterlist entry currently being processed by PIO code, if any.
 * @sg_miter: PIO mapping scatterlist iterator.
 * @cur_slot: The slot which is currently using the controller.
 * @mrq: The request currently being processed on @cur_slot,
 *	or NULL if the controller is idle.
 * @cmd: The command currently being sent to the card, or NULL.
 * @data: The data currently being transferred, or NULL if no data
 *	transfer is in progress.
 * @use_dma: Whether DMA channel is initialized or not.
 * @using_dma: Whether DMA is in use for the current transfer.
 * @sg_dma: Bus address of DMA buffer.
 * @sg_cpu: Virtual address of DMA buffer.
 * @dma_ops: Pointer to platform-specific DMA callbacks.
 * @cmd_status: Snapshot of SR taken upon completion of the current
 *	command. Only valid when EVENT_CMD_COMPLETE is pending.
 * @data_status: Snapshot of SR taken upon completion of the current
 *	data transfer. Only valid when EVENT_DATA_COMPLETE or
 *	EVENT_DATA_ERROR is pending.
 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 *	to be sent.
 * @dir_status: Direction of current transfer.
 * @tasklet: Tasklet running the request state machine.
 * @card_tasklet: Tasklet handling card detect.
 * @pending_events: Bitmask of events flagged by the interrupt handler
 *	to be processed by the tasklet.
 * @completed_events: Bitmask of events which the state machine has
 *	processed.
 * @state: Tasklet state.
 * @queue: List of slots waiting for access to the controller.
 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 *	rate and timeout calculations.
 * @current_speed: Configured rate of the controller.
 * @num_slots: Number of slots available.
 * @verid: Denote Version ID.
 * @data_offset: Set the offset of DATA register according to VERID.
 * @dev: Device associated with the MMC controller.
 * @pdata: Platform data associated with the MMC controller.
 * @drv_data: Driver specific data for identified variant of the controller
 * @priv: Implementation defined private data.
 * @biu_clk: Pointer to bus interface unit clock instance.
 * @ciu_clk: Pointer to card interface unit clock instance.
 * @slot: Slots sharing this MMC controller.
 * @fifo_depth: depth of FIFO.
 * @data_shift: log2 of FIFO item size.
 * @part_buf_start: Start index in part_buf.
 * @part_buf_count: Bytes of partial data in part_buf.
 * @part_buf: Simple buffer for partial fifo reads/writes.
 * @push_data: Pointer to FIFO push function.
 * @pull_data: Pointer to FIFO pull function.
 * @quirks: Set of quirks that apply to specific versions of the IP.
 * @irq_flags: The flags to be passed to request_irq.
 * @irq: The irq value to be passed to request_irq.
 *
 * Locking
 * =======
 *
 * @lock is a softirq-safe spinlock protecting @queue as well as
 * @cur_slot, @mrq and @state. These must always be updated
 * at the same time while holding @lock.
 *
 * The @mrq field of struct dw_mci_slot is also protected by @lock,
 * and must always be written at the same time as the slot is added to
 * @queue.
 *
 * @pending_events and @completed_events are accessed using atomic bit
 * operations, so they don't need any locking.
 *
 * None of the fields touched by the interrupt handler need any
 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 * interrupts must be disabled and @data_status updated with a
 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 * CMDRDY interrupt must be disabled and @cmd_status updated with a
 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 * bytes_xfered field of @data must be written. This is ensured by
 * using barriers.
 */
struct dw_mci {
	spinlock_t		lock;
	void __iomem		*regs;

	struct scatterlist	*sg;
	struct sg_mapping_iter	sg_miter;

	struct dw_mci_slot	*cur_slot;
	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
	struct workqueue_struct	*card_workqueue;

	/* DMA interface members*/
	int			use_dma;
	int			using_dma;

	dma_addr_t		sg_dma;
	void			*sg_cpu;
	const struct dw_mci_dma_ops	*dma_ops;
#ifdef CONFIG_MMC_DW_IDMAC
	unsigned int		ring_size;
#else
	struct dw_mci_dma_data	*dma_data;
#endif
	u32			cmd_status;
	u32			data_status;
	u32			stop_cmdr;
	u32			dir_status;
	struct tasklet_struct	tasklet;
	struct work_struct	card_work;
	unsigned long		pending_events;
	unsigned long		completed_events;
	enum dw_mci_state	state;
	struct list_head	queue;

	u32			bus_hz;
	u32			current_speed;
	u32			num_slots;
	u32			fifoth_val;
	u16			verid;
	u16			data_offset;
	struct device		*dev;
	struct dw_mci_board	*pdata;
	const struct dw_mci_drv_data	*drv_data;
	void			*priv;
	struct clk		*biu_clk;
	struct clk		*ciu_clk;
	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

	/* FIFO push and pull */
	int			fifo_depth;
	int			data_shift;
	u8			part_buf_start;
	u8			part_buf_count;
	union {
		u16		part_buf16;
		u32		part_buf32;
		u64		part_buf;
	};
	void (*push_data)(struct dw_mci *host, void *buf, int cnt);
	void (*pull_data)(struct dw_mci *host, void *buf, int cnt);

	/* Workaround flags */
	u32			quirks;

	struct regulator	*vmmc;	/* Power regulator */
	unsigned long		irq_flags; /* IRQ flags */
	int			irq;
};

/* DMA ops for Internal/External DMAC interface */
struct dw_mci_dma_ops {
	/* DMA Ops */
	int (*init)(struct dw_mci *host);
	void (*start)(struct dw_mci *host, unsigned int sg_len);
	void (*complete)(struct dw_mci *host);
	void (*stop)(struct dw_mci *host);
	void (*cleanup)(struct dw_mci *host);
	void (*exit)(struct dw_mci *host);
};

/* IP Quirks/flags. */
/* DTO fix for command transmission with IDMAC configured */
#define DW_MCI_QUIRK_IDMAC_DTO			BIT(0)
/* delay needed between retries on some 2.11a implementations */
#define DW_MCI_QUIRK_RETRY_DELAY		BIT(1)
/* High Speed Capable - Supports HS cards (up to 50MHz) */
#define DW_MCI_QUIRK_HIGHSPEED			BIT(2)
/* Unreliable card detection */
#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION	BIT(3)

/* Write Protect detection not available */
/*
 * NOTE: DW_MCI_QUIRK_NO_WRITE_PROTECT will be removed in a future
 * patch in the series once reference to it is removed.
 */
#define DW_MCI_QUIRK_NO_WRITE_PROTECT		BIT(4)

/* Slot level quirks */
/* This slot has no write protect */
#define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT	BIT(0)

struct dma_pdata;

struct block_settings {
	unsigned short	max_segs;	/* see blk_queue_max_segments */
	unsigned int	max_blk_size;	/* maximum size of one mmc block */
	unsigned int	max_blk_count;	/* maximum number of blocks in one req*/
	unsigned int	max_req_size;	/* maximum number of bytes in one req*/
	unsigned int	max_seg_size;	/* see blk_queue_max_segment_size */
};

/* Board platform data */
struct dw_mci_board {
	u32 num_slots;

	u32 quirks; /* Workaround / Quirk flags */
	unsigned int bus_hz; /* Clock speed at the cclk_in pad */

	u32 caps;	/* Capabilities */
	u32 caps2;	/* More capabilities */
	u32 pm_caps;	/* PM capabilities */
	/*
	 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
	 * but note that this may not be reliable after a bootloader has used
	 * it.
	 */
	unsigned int fifo_depth;

	/* delay in mS before detecting cards after interrupt */
	u32 detect_delay_ms;

	int (*init)(u32 slot_id, irq_handler_t , void *);
	int (*get_ro)(u32 slot_id);
	int (*get_cd)(u32 slot_id);
	int (*get_ocr)(u32 slot_id);
	int (*get_bus_wd)(u32 slot_id);
	/*
	 * Enable power to selected slot and set voltage to desired level.
	 * Voltage levels are specified using MMC_VDD_xxx defines defined
	 * in linux/mmc/host.h file.
	 */
	void (*setpower)(u32 slot_id, u32 volt);
	void (*exit)(u32 slot_id);
	void (*select_slot)(u32 slot_id);

	struct dw_mci_dma_ops *dma_ops;
	struct dma_pdata *data;
	struct block_settings *blk_settings;
};

#endif /* LINUX_MMC_DW_MMC_H */
Commit	Line	Data
f95f3850 WN	1	/*
	2	* Synopsys DesignWare Multimedia Card Interface driver
	3	* (Based on NXP driver for lpc 31xx)
	4	*
	5	* Copyright (C) 2009 NXP Semiconductors
	6	* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
100e9186 RD	14	#ifndef LINUX_MMC_DW_MMC_H
100e9186 RD	15	#define LINUX_MMC_DW_MMC_H
f95f3850	16
f9c2a0dc SJ	17	#include <linux/scatterlist.h>
f9c2a0dc SJ	18
f95f3850 WN	19	#define MAX_MCI_SLOTS 2
	20
	21	enum dw_mci_state {
	22	STATE_IDLE = 0,
	23	STATE_SENDING_CMD,
	24	STATE_SENDING_DATA,
	25	STATE_DATA_BUSY,
	26	STATE_SENDING_STOP,
	27	STATE_DATA_ERROR,
	28	};
	29
	30	enum {
	31	EVENT_CMD_COMPLETE = 0,
	32	EVENT_XFER_COMPLETE,
	33	EVENT_DATA_COMPLETE,
	34	EVENT_DATA_ERROR,
	35	EVENT_XFER_ERROR
	36	};
	37
	38	struct mmc_data;
	39
	40	/**
	41	* struct dw_mci - MMC controller state shared between all slots
	42	* @lock: Spinlock protecting the queue and associated data.
	43	* @regs: Pointer to MMIO registers.
	44	* @sg: Scatterlist entry currently being processed by PIO code, if any.
f9c2a0dc	45	* @sg_miter: PIO mapping scatterlist iterator.
f95f3850 WN	46	* @cur_slot: The slot which is currently using the controller.
	47	* @mrq: The request currently being processed on @cur_slot,
	48	* or NULL if the controller is idle.
	49	* @cmd: The command currently being sent to the card, or NULL.
	50	* @data: The data currently being transferred, or NULL if no data
	51	* transfer is in progress.
	52	* @use_dma: Whether DMA channel is initialized or not.
03e8cb53	53	* @using_dma: Whether DMA is in use for the current transfer.
f95f3850 WN	54	* @sg_dma: Bus address of DMA buffer.
	55	* @sg_cpu: Virtual address of DMA buffer.
	56	* @dma_ops: Pointer to platform-specific DMA callbacks.
	57	* @cmd_status: Snapshot of SR taken upon completion of the current
	58	* command. Only valid when EVENT_CMD_COMPLETE is pending.
	59	* @data_status: Snapshot of SR taken upon completion of the current
	60	* data transfer. Only valid when EVENT_DATA_COMPLETE or
	61	* EVENT_DATA_ERROR is pending.
	62	* @stop_cmdr: Value to be loaded into CMDR when the stop command is
	63	* to be sent.
	64	* @dir_status: Direction of current transfer.
	65	* @tasklet: Tasklet running the request state machine.
	66	* @card_tasklet: Tasklet handling card detect.
	67	* @pending_events: Bitmask of events flagged by the interrupt handler
	68	* to be processed by the tasklet.
	69	* @completed_events: Bitmask of events which the state machine has
	70	* processed.
	71	* @state: Tasklet state.
	72	* @queue: List of slots waiting for access to the controller.
	73	* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
	74	* rate and timeout calculations.
	75	* @current_speed: Configured rate of the controller.
	76	* @num_slots: Number of slots available.
4e0a5adf JC	77	* @verid: Denote Version ID.
4e0a5adf JC	78	* @data_offset: Set the offset of DATA register according to VERID.
62ca8034	79	* @dev: Device associated with the MMC controller.
f95f3850	80	* @pdata: Platform data associated with the MMC controller.
800d78bf TA	81	* @drv_data: Driver specific data for identified variant of the controller
800d78bf TA	82	* @priv: Implementation defined private data.
f90a0612 TA	83	* @biu_clk: Pointer to bus interface unit clock instance.
f90a0612 TA	84	* @ciu_clk: Pointer to card interface unit clock instance.
f95f3850	85	* @slot: Slots sharing this MMC controller.
b86d8253	86	* @fifo_depth: depth of FIFO.
f95f3850	87	* @data_shift: log2 of FIFO item size.
34b664a2 JH	88	* @part_buf_start: Start index in part_buf.
	89	* @part_buf_count: Bytes of partial data in part_buf.
	90	* @part_buf: Simple buffer for partial fifo reads/writes.
f95f3850 WN	91	* @push_data: Pointer to FIFO push function.
	92	* @pull_data: Pointer to FIFO pull function.
	93	* @quirks: Set of quirks that apply to specific versions of the IP.
62ca8034 SH	94	* @irq_flags: The flags to be passed to request_irq.
62ca8034 SH	95	* @irq: The irq value to be passed to request_irq.
f95f3850 WN	96	*
	97	* Locking
	98	* =======
	99	*
	100	* @lock is a softirq-safe spinlock protecting @queue as well as
	101	* @cur_slot, @mrq and @state. These must always be updated
	102	* at the same time while holding @lock.
	103	*
	104	* The @mrq field of struct dw_mci_slot is also protected by @lock,
	105	* and must always be written at the same time as the slot is added to
	106	* @queue.
	107	*
	108	* @pending_events and @completed_events are accessed using atomic bit
	109	* operations, so they don't need any locking.
	110	*
	111	* None of the fields touched by the interrupt handler need any
	112	* locking. However, ordering is important: Before EVENT_DATA_ERROR or
	113	* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
	114	* interrupts must be disabled and @data_status updated with a
	115	* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
25985edc	116	* CMDRDY interrupt must be disabled and @cmd_status updated with a
f95f3850 WN	117	* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
	118	* bytes_xfered field of @data must be written. This is ensured by
	119	* using barriers.
	120	*/
	121	struct dw_mci {
	122	spinlock_t lock;
	123	void __iomem *regs;
	124
	125	struct scatterlist *sg;
f9c2a0dc	126	struct sg_mapping_iter sg_miter;
f95f3850 WN	127
	128	struct dw_mci_slot *cur_slot;
	129	struct mmc_request *mrq;
	130	struct mmc_command *cmd;
	131	struct mmc_data *data;
95dcc2cb	132	struct workqueue_struct *card_workqueue;
f95f3850 WN	133
	134	/* DMA interface members*/
	135	int use_dma;
03e8cb53	136	int using_dma;
f95f3850 WN	137
	138	dma_addr_t sg_dma;
	139	void *sg_cpu;
8e2b36ea	140	const struct dw_mci_dma_ops *dma_ops;
f95f3850 WN	141	#ifdef CONFIG_MMC_DW_IDMAC
	142	unsigned int ring_size;
	143	#else
	144	struct dw_mci_dma_data *dma_data;
	145	#endif
	146	u32 cmd_status;
	147	u32 data_status;
	148	u32 stop_cmdr;
	149	u32 dir_status;
	150	struct tasklet_struct tasklet;
1791b13e	151	struct work_struct card_work;
f95f3850 WN	152	unsigned long pending_events;
	153	unsigned long completed_events;
	154	enum dw_mci_state state;
	155	struct list_head queue;
	156
	157	u32 bus_hz;
	158	u32 current_speed;
	159	u32 num_slots;
e61cf118	160	u32 fifoth_val;
4e0a5adf JC	161	u16 verid;
4e0a5adf JC	162	u16 data_offset;
4a90920c	163	struct device *dev;
f95f3850	164	struct dw_mci_board *pdata;
8e2b36ea	165	const struct dw_mci_drv_data *drv_data;
800d78bf	166	void *priv;
f90a0612 TA	167	struct clk *biu_clk;
f90a0612 TA	168	struct clk *ciu_clk;
f95f3850 WN	169	struct dw_mci_slot *slot[MAX_MCI_SLOTS];
	170
	171	/* FIFO push and pull */
b86d8253	172	int fifo_depth;
f95f3850	173	int data_shift;
34b664a2 JH	174	u8 part_buf_start;
	175	u8 part_buf_count;
	176	union {
	177	u16 part_buf16;
	178	u32 part_buf32;
	179	u64 part_buf;
	180	};
f95f3850 WN	181	void (push_data)(struct dw_mci host, void *buf, int cnt);
	182	void (pull_data)(struct dw_mci host, void *buf, int cnt);
	183
	184	/* Workaround flags */
	185	u32 quirks;
c07946a3 JC	186
c07946a3 JC	187	struct regulator vmmc; / Power regulator */
62ca8034	188	unsigned long irq_flags; /* IRQ flags */
d676188e	189	int irq;
f95f3850 WN	190	};
	191
	192	/* DMA ops for Internal/External DMAC interface */
	193	struct dw_mci_dma_ops {
	194	/* DMA Ops */
	195	int (init)(struct dw_mci host);
	196	void (start)(struct dw_mci host, unsigned int sg_len);
	197	void (complete)(struct dw_mci host);
	198	void (stop)(struct dw_mci host);
	199	void (cleanup)(struct dw_mci host);
	200	void (exit)(struct dw_mci host);
	201	};
	202
	203	/* IP Quirks/flags. */
f95f3850	204	/* DTO fix for command transmission with IDMAC configured */
fc3d7720	205	#define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
f95f3850	206	/* delay needed between retries on some 2.11a implementations */
fc3d7720	207	#define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
25985edc	208	/* High Speed Capable - Supports HS cards (up to 50MHz) */
fc3d7720 JC	209	#define DW_MCI_QUIRK_HIGHSPEED BIT(2)
	210	/* Unreliable card detection */
	211	#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
a70aaa64	212
b4967aa5	213	/* Write Protect detection not available */
a70aaa64 DA	214	/*
	215	* NOTE: DW_MCI_QUIRK_NO_WRITE_PROTECT will be removed in a future
	216	* patch in the series once reference to it is removed.
	217	*/
b4967aa5	218	#define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(4)
f95f3850	219
a70aaa64 DA	220	/* Slot level quirks */
	221	/* This slot has no write protect */
	222	#define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0)
	223
f95f3850 WN	224	struct dma_pdata;
	225
	226	struct block_settings {
	227	unsigned short max_segs; /* see blk_queue_max_segments */
	228	unsigned int max_blk_size; /* maximum size of one mmc block */
	229	unsigned int max_blk_count; /* maximum number of blocks in one req*/
	230	unsigned int max_req_size; /* maximum number of bytes in one req*/
	231	unsigned int max_seg_size; /* see blk_queue_max_segment_size */
	232	};
	233
	234	/* Board platform data */
	235	struct dw_mci_board {
	236	u32 num_slots;
	237
	238	u32 quirks; /* Workaround / Quirk flags */
c3665006	239	unsigned int bus_hz; /* Clock speed at the cclk_in pad */
f95f3850	240
5f1a4dd0 LJ	241	u32 caps; /* Capabilities */
5f1a4dd0 LJ	242	u32 caps2; /* More capabilities */
ab269128	243	u32 pm_caps; /* PM capabilities */
b86d8253 JH	244	/*
	245	* Override fifo depth. If 0, autodetect it from the FIFOTH register,
	246	* but note that this may not be reliable after a bootloader has used
	247	* it.
	248	*/
	249	unsigned int fifo_depth;
fc3d7720	250
f95f3850 WN	251	/* delay in mS before detecting cards after interrupt */
	252	u32 detect_delay_ms;
	253
	254	int (init)(u32 slot_id, irq_handler_t , void );
	255	int (*get_ro)(u32 slot_id);
	256	int (*get_cd)(u32 slot_id);
	257	int (*get_ocr)(u32 slot_id);
	258	int (*get_bus_wd)(u32 slot_id);
	259	/*
	260	* Enable power to selected slot and set voltage to desired level.
	261	* Voltage levels are specified using MMC_VDD_xxx defines defined
	262	* in linux/mmc/host.h file.
	263	*/
	264	void (*setpower)(u32 slot_id, u32 volt);
	265	void (*exit)(u32 slot_id);
	266	void (*select_slot)(u32 slot_id);
	267
	268	struct dw_mci_dma_ops *dma_ops;
	269	struct dma_pdata *data;
	270	struct block_settings *blk_settings;
	271	};
	272
100e9186	273	#endif /* LINUX_MMC_DW_MMC_H */