Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mmc/host.h | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Host driver specific definitions. | |
9 | */ | |
10 | #ifndef LINUX_MMC_HOST_H | |
11 | #define LINUX_MMC_HOST_H | |
12 | ||
af8350c7 | 13 | #include <linux/leds.h> |
a7d1a1eb | 14 | #include <linux/mutex.h> |
dfa13ebb | 15 | #include <linux/timer.h> |
d43c36dc | 16 | #include <linux/sched.h> |
313162d0 | 17 | #include <linux/device.h> |
1b676f70 | 18 | #include <linux/fault-inject.h> |
af8350c7 | 19 | |
aaac1b47 | 20 | #include <linux/mmc/core.h> |
cdc99179 | 21 | #include <linux/mmc/card.h> |
da68c4eb | 22 | #include <linux/mmc/pm.h> |
1da177e4 LT |
23 | |
24 | struct mmc_ios { | |
25 | unsigned int clock; /* clock rate */ | |
26 | unsigned short vdd; | |
27 | ||
4be34c99 | 28 | /* vdd stores the bit number of the selected voltage range from below. */ |
1da177e4 LT |
29 | |
30 | unsigned char bus_mode; /* command output mode */ | |
31 | ||
32 | #define MMC_BUSMODE_OPENDRAIN 1 | |
33 | #define MMC_BUSMODE_PUSHPULL 2 | |
34 | ||
865e9f13 PO |
35 | unsigned char chip_select; /* SPI chip select */ |
36 | ||
37 | #define MMC_CS_DONTCARE 0 | |
38 | #define MMC_CS_HIGH 1 | |
39 | #define MMC_CS_LOW 2 | |
40 | ||
1da177e4 LT |
41 | unsigned char power_mode; /* power supply mode */ |
42 | ||
43 | #define MMC_POWER_OFF 0 | |
44 | #define MMC_POWER_UP 1 | |
45 | #define MMC_POWER_ON 2 | |
8af465db | 46 | #define MMC_POWER_UNDEFINED 3 |
f218278a PO |
47 | |
48 | unsigned char bus_width; /* data bus width */ | |
49 | ||
50 | #define MMC_BUS_WIDTH_1 0 | |
51 | #define MMC_BUS_WIDTH_4 2 | |
b30f8af3 | 52 | #define MMC_BUS_WIDTH_8 3 |
cd9277c0 PO |
53 | |
54 | unsigned char timing; /* timing specification used */ | |
55 | ||
56 | #define MMC_TIMING_LEGACY 0 | |
57 | #define MMC_TIMING_MMC_HS 1 | |
58 | #define MMC_TIMING_SD_HS 2 | |
ed9dbb6e KL |
59 | #define MMC_TIMING_UHS_SDR12 3 |
60 | #define MMC_TIMING_UHS_SDR25 4 | |
61 | #define MMC_TIMING_UHS_SDR50 5 | |
62 | #define MMC_TIMING_UHS_SDR104 6 | |
63 | #define MMC_TIMING_UHS_DDR50 7 | |
79f7ae7c SJ |
64 | #define MMC_TIMING_MMC_DDR52 8 |
65 | #define MMC_TIMING_MMC_HS200 9 | |
0a5b6438 | 66 | #define MMC_TIMING_MMC_HS400 10 |
0f8d8ea6 | 67 | |
f2119df6 AN |
68 | unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ |
69 | ||
70 | #define MMC_SIGNAL_VOLTAGE_330 0 | |
71 | #define MMC_SIGNAL_VOLTAGE_180 1 | |
4c4cb171 | 72 | #define MMC_SIGNAL_VOLTAGE_120 2 |
d6d50a15 AN |
73 | |
74 | unsigned char drv_type; /* driver type (A, B, C, D) */ | |
75 | ||
76 | #define MMC_SET_DRIVER_TYPE_B 0 | |
77 | #define MMC_SET_DRIVER_TYPE_A 1 | |
78 | #define MMC_SET_DRIVER_TYPE_C 2 | |
79 | #define MMC_SET_DRIVER_TYPE_D 3 | |
1da177e4 LT |
80 | }; |
81 | ||
82 | struct mmc_host_ops { | |
aa8b683a PF |
83 | /* |
84 | * It is optional for the host to implement pre_req and post_req in | |
85 | * order to support double buffering of requests (prepare one | |
86 | * request while another request is active). | |
7c8a2829 PF |
87 | * pre_req() must always be followed by a post_req(). |
88 | * To undo a call made to pre_req(), call post_req() with | |
89 | * a nonzero err condition. | |
aa8b683a PF |
90 | */ |
91 | void (*post_req)(struct mmc_host *host, struct mmc_request *req, | |
92 | int err); | |
93 | void (*pre_req)(struct mmc_host *host, struct mmc_request *req, | |
94 | bool is_first_req); | |
1da177e4 | 95 | void (*request)(struct mmc_host *host, struct mmc_request *req); |
28f52482 AV |
96 | /* |
97 | * Avoid calling these three functions too often or in a "fast path", | |
98 | * since underlaying controller might implement them in an expensive | |
99 | * and/or slow way. | |
100 | * | |
101 | * Also note that these functions might sleep, so don't call them | |
102 | * in the atomic contexts! | |
08f80bb5 AV |
103 | * |
104 | * Return values for the get_ro callback should be: | |
105 | * 0 for a read/write card | |
106 | * 1 for a read-only card | |
107 | * -ENOSYS when not supported (equal to NULL callback) | |
108 | * or a negative errno value when something bad happened | |
109 | * | |
ee63a7d2 | 110 | * Return values for the get_cd callback should be: |
08f80bb5 AV |
111 | * 0 for a absent card |
112 | * 1 for a present card | |
113 | * -ENOSYS when not supported (equal to NULL callback) | |
114 | * or a negative errno value when something bad happened | |
28f52482 | 115 | */ |
1da177e4 | 116 | void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); |
a00fc090 | 117 | int (*get_ro)(struct mmc_host *host); |
28f52482 AV |
118 | int (*get_cd)(struct mmc_host *host); |
119 | ||
17b759af | 120 | void (*enable_sdio_irq)(struct mmc_host *host, int enable); |
3fcb027d DM |
121 | |
122 | /* optional callback for HC quirks */ | |
123 | void (*init_card)(struct mmc_host *host, struct mmc_card *card); | |
f2119df6 AN |
124 | |
125 | int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios); | |
a4924c71 | 126 | |
d887874e JR |
127 | /* Check if the card is pulling dat[0:3] low */ |
128 | int (*card_busy)(struct mmc_host *host); | |
129 | ||
a4924c71 G |
130 | /* The tuning command opcode value is different for SD and eMMC cards */ |
131 | int (*execute_tuning)(struct mmc_host *host, u32 opcode); | |
0a5b6438 SJ |
132 | |
133 | /* Prepare HS400 target operating frequency depending host driver */ | |
134 | int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); | |
ca8e99b3 | 135 | int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv); |
b2499518 | 136 | void (*hw_reset)(struct mmc_host *host); |
9f1fb60a | 137 | void (*card_event)(struct mmc_host *host); |
2e47e842 KM |
138 | |
139 | /* | |
140 | * Optional callback to support controllers with HW issues for multiple | |
141 | * I/O. Returns the number of supported blocks for the request. | |
142 | */ | |
143 | int (*multi_io_quirk)(struct mmc_card *card, | |
144 | unsigned int direction, int blk_size); | |
1da177e4 LT |
145 | }; |
146 | ||
147 | struct mmc_card; | |
148 | struct device; | |
149 | ||
aa8b683a PF |
150 | struct mmc_async_req { |
151 | /* active mmc request */ | |
152 | struct mmc_request *mrq; | |
153 | /* | |
154 | * Check error status of completed mmc request. | |
155 | * Returns 0 if success otherwise non zero. | |
156 | */ | |
157 | int (*err_check) (struct mmc_card *, struct mmc_async_req *); | |
158 | }; | |
159 | ||
27410ee7 GL |
160 | /** |
161 | * struct mmc_slot - MMC slot functions | |
162 | * | |
163 | * @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL | |
164 | * @handler_priv: MMC/SD-card slot context | |
165 | * | |
166 | * Some MMC/SD host controllers implement slot-functions like card and | |
167 | * write-protect detection natively. However, a large number of controllers | |
168 | * leave these functions to the CPU. This struct provides a hook to attach | |
169 | * such slot-function drivers. | |
170 | */ | |
171 | struct mmc_slot { | |
172 | int cd_irq; | |
b67e1980 GL |
173 | void *handler_priv; |
174 | }; | |
175 | ||
2220eedf KD |
176 | /** |
177 | * mmc_context_info - synchronization details for mmc context | |
178 | * @is_done_rcv wake up reason was done request | |
179 | * @is_new_req wake up reason was new request | |
180 | * @is_waiting_last_req mmc context waiting for single running request | |
181 | * @wait wait queue | |
182 | * @lock lock to protect data fields | |
183 | */ | |
184 | struct mmc_context_info { | |
185 | bool is_done_rcv; | |
186 | bool is_new_req; | |
187 | bool is_waiting_last_req; | |
188 | wait_queue_head_t wait; | |
189 | spinlock_t lock; | |
190 | }; | |
191 | ||
e137788d | 192 | struct regulator; |
3aa8793f | 193 | struct mmc_pwrseq; |
e137788d GL |
194 | |
195 | struct mmc_supply { | |
196 | struct regulator *vmmc; /* Card power supply */ | |
197 | struct regulator *vqmmc; /* Optional Vccq supply */ | |
198 | }; | |
199 | ||
1da177e4 | 200 | struct mmc_host { |
fcaf71fd GKH |
201 | struct device *parent; |
202 | struct device class_dev; | |
dce77377 | 203 | int index; |
f57b225e | 204 | const struct mmc_host_ops *ops; |
3aa8793f | 205 | struct mmc_pwrseq *pwrseq; |
1da177e4 LT |
206 | unsigned int f_min; |
207 | unsigned int f_max; | |
88ae8b86 | 208 | unsigned int f_init; |
1da177e4 | 209 | u32 ocr_avail; |
8f230f45 TI |
210 | u32 ocr_avail_sdio; /* SDIO-specific OCR */ |
211 | u32 ocr_avail_sd; /* SD-specific OCR */ | |
212 | u32 ocr_avail_mmc; /* MMC-specific OCR */ | |
4c2ef25f | 213 | struct notifier_block pm_notify; |
55c4665e AL |
214 | u32 max_current_330; |
215 | u32 max_current_300; | |
216 | u32 max_current_180; | |
1da177e4 | 217 | |
55556da0 | 218 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
f74d132c PO |
219 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ |
220 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ | |
221 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ | |
222 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ | |
223 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ | |
224 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ | |
225 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ | |
226 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ | |
227 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ | |
228 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ | |
229 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ | |
230 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ | |
231 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ | |
232 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ | |
233 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ | |
234 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ | |
235 | ||
5f1a4dd0 | 236 | u32 caps; /* Host capabilities */ |
f218278a PO |
237 | |
238 | #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ | |
23af6039 PO |
239 | #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ |
240 | #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ | |
241 | #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ | |
242 | #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ | |
243 | #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ | |
b30f8af3 | 244 | #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ |
c4d770d7 | 245 | #define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ |
9feae246 | 246 | #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ |
b1ebe384 | 247 | #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ |
dfe86cba | 248 | #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ |
dfc13e84 HP |
249 | #define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ |
250 | /* DDR mode at 1.8V */ | |
251 | #define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ | |
252 | /* DDR mode at 1.2V */ | |
ed919b01 | 253 | #define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ |
22113efd | 254 | #define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ |
f2119df6 AN |
255 | #define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ |
256 | #define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ | |
257 | #define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ | |
258 | #define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ | |
259 | #define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ | |
4d223782 | 260 | #define MMC_CAP_RUNTIME_RESUME (1 << 20) /* Resume at runtime_resume. */ |
d6d50a15 AN |
261 | #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ |
262 | #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ | |
263 | #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ | |
d0c97cfb | 264 | #define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ |
b2499518 | 265 | #define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ |
f218278a | 266 | |
5f1a4dd0 | 267 | u32 caps2; /* More host capabilities */ |
f7c56ef2 AH |
268 | |
269 | #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ | |
53275c21 | 270 | #define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ |
a4924c71 G |
271 | #define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ |
272 | #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ | |
273 | #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ | |
274 | MMC_CAP2_HS200_1_2V_SDR) | |
83bb24aa | 275 | #define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ |
5c08d7fa GL |
276 | #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ |
277 | #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ | |
abd9ac14 SJ |
278 | #define MMC_CAP2_PACKED_RD (1 << 12) /* Allow packed read */ |
279 | #define MMC_CAP2_PACKED_WR (1 << 13) /* Allow packed write */ | |
280 | #define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \ | |
281 | MMC_CAP2_PACKED_WR) | |
0d3e3350 | 282 | #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ |
0a5b6438 SJ |
283 | #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ |
284 | #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ | |
285 | #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ | |
286 | MMC_CAP2_HS400_1_2V) | |
549c0b18 | 287 | #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) |
bf3b5ec6 | 288 | #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) |
f7c56ef2 | 289 | |
da68c4eb NP |
290 | mmc_pm_flag_t pm_caps; /* supported pm features */ |
291 | ||
04566831 LW |
292 | #ifdef CONFIG_MMC_CLKGATE |
293 | int clk_requests; /* internal reference counter */ | |
294 | unsigned int clk_delay; /* number of MCI clk hold cycles */ | |
295 | bool clk_gated; /* clock gated */ | |
597dd9d7 | 296 | struct delayed_work clk_gate_work; /* delayed clock gate */ |
04566831 LW |
297 | unsigned int clk_old; /* old clock value cache */ |
298 | spinlock_t clk_lock; /* lock for clk fields */ | |
86f315bb | 299 | struct mutex clk_gate_mutex; /* mutex for clock gating */ |
597dd9d7 SRT |
300 | struct device_attribute clkgate_delay_attr; |
301 | unsigned long clkgate_delay; | |
04566831 LW |
302 | #endif |
303 | ||
1da177e4 LT |
304 | /* host specific block data */ |
305 | unsigned int max_seg_size; /* see blk_queue_max_segment_size */ | |
a36274e0 | 306 | unsigned short max_segs; /* see blk_queue_max_segments */ |
1da177e4 | 307 | unsigned short unused; |
55db890a | 308 | unsigned int max_req_size; /* maximum number of bytes in one req */ |
fe4a3c7a | 309 | unsigned int max_blk_size; /* maximum size of one mmc block */ |
55db890a | 310 | unsigned int max_blk_count; /* maximum number of blocks in one req */ |
68eb80e0 | 311 | unsigned int max_busy_timeout; /* max busy timeout in ms */ |
1da177e4 LT |
312 | |
313 | /* private data */ | |
7ea239d9 PO |
314 | spinlock_t lock; /* lock for claim and bus ops */ |
315 | ||
1da177e4 | 316 | struct mmc_ios ios; /* current io bus settings */ |
1da177e4 | 317 | |
97018580 DB |
318 | /* group bitfields together to minimize padding */ |
319 | unsigned int use_spi_crc:1; | |
320 | unsigned int claimed:1; /* host exclusively claimed */ | |
321 | unsigned int bus_dead:1; /* bus has been released */ | |
322 | #ifdef CONFIG_MMC_DEBUG | |
323 | unsigned int removed:1; /* host is being removed */ | |
324 | #endif | |
dfa13ebb AH |
325 | unsigned int can_retune:1; /* re-tuning can be used */ |
326 | unsigned int doing_retune:1; /* re-tuning in progress */ | |
327 | unsigned int retune_now:1; /* do re-tuning at next req */ | |
97018580 | 328 | |
4c2ef25f | 329 | int rescan_disable; /* disable card detection */ |
3339d1e3 | 330 | int rescan_entered; /* used with nonremovable devices */ |
8ea926b2 | 331 | |
dfa13ebb AH |
332 | int need_retune; /* re-tuning is needed */ |
333 | int hold_retune; /* hold off re-tuning */ | |
334 | unsigned int retune_period; /* re-tuning period in secs */ | |
335 | struct timer_list retune_timer; /* for periodic re-tuning */ | |
336 | ||
fa372a51 MM |
337 | bool trigger_card_event; /* card_event necessary */ |
338 | ||
b855885e | 339 | struct mmc_card *card; /* device attached to this host */ |
1da177e4 LT |
340 | |
341 | wait_queue_head_t wq; | |
319a3f14 AH |
342 | struct task_struct *claimer; /* task that has host claimed */ |
343 | int claim_cnt; /* "claim" nesting count */ | |
f22ee4ed | 344 | |
c4028958 | 345 | struct delayed_work detect; |
d3049504 | 346 | int detect_change; /* card detect flag */ |
27410ee7 | 347 | struct mmc_slot slot; |
01357dca | 348 | |
7ea239d9 PO |
349 | const struct mmc_bus_ops *bus_ops; /* current bus driver */ |
350 | unsigned int bus_refs; /* reference counter */ | |
7ea239d9 | 351 | |
d1496c39 NP |
352 | unsigned int sdio_irqs; |
353 | struct task_struct *sdio_irq_thread; | |
bbbc4c4d | 354 | bool sdio_irq_pending; |
d1496c39 NP |
355 | atomic_t sdio_irq_thread_abort; |
356 | ||
da68c4eb NP |
357 | mmc_pm_flag_t pm_flags; /* requested pm features */ |
358 | ||
af8350c7 | 359 | struct led_trigger *led; /* activity led */ |
af8350c7 | 360 | |
99fc5131 LW |
361 | #ifdef CONFIG_REGULATOR |
362 | bool regulator_enabled; /* regulator state */ | |
363 | #endif | |
e137788d | 364 | struct mmc_supply supply; |
99fc5131 | 365 | |
6edd8ee6 HS |
366 | struct dentry *debugfs_root; |
367 | ||
aa8b683a | 368 | struct mmc_async_req *areq; /* active async req */ |
2220eedf | 369 | struct mmc_context_info context_info; /* async synchronization info */ |
aa8b683a | 370 | |
1b676f70 PF |
371 | #ifdef CONFIG_FAIL_MMC_REQUEST |
372 | struct fault_attr fail_mmc_request; | |
373 | #endif | |
374 | ||
df16219f GC |
375 | unsigned int actual_clock; /* Actual HC clock rate */ |
376 | ||
eed222ac AL |
377 | unsigned int slotno; /* used for sdio acpi binding */ |
378 | ||
3d705d14 SH |
379 | int dsr_req; /* DSR value is valid */ |
380 | u32 dsr; /* optional driver stage (DSR) value */ | |
381 | ||
01357dca | 382 | unsigned long private[0] ____cacheline_aligned; |
1da177e4 LT |
383 | }; |
384 | ||
8c9beb11 GL |
385 | struct mmc_host *mmc_alloc_host(int extra, struct device *); |
386 | int mmc_add_host(struct mmc_host *); | |
387 | void mmc_remove_host(struct mmc_host *); | |
388 | void mmc_free_host(struct mmc_host *); | |
ec0a7517 | 389 | int mmc_of_parse(struct mmc_host *host); |
1da177e4 | 390 | |
01357dca RK |
391 | static inline void *mmc_priv(struct mmc_host *host) |
392 | { | |
393 | return (void *)host->private; | |
394 | } | |
395 | ||
97018580 DB |
396 | #define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) |
397 | ||
fcaf71fd | 398 | #define mmc_dev(x) ((x)->parent) |
11354d03 | 399 | #define mmc_classdev(x) (&(x)->class_dev) |
d1b26863 | 400 | #define mmc_hostname(x) (dev_name(&(x)->class_dev)) |
1da177e4 | 401 | |
8c9beb11 GL |
402 | int mmc_power_save_host(struct mmc_host *host); |
403 | int mmc_power_restore_host(struct mmc_host *host); | |
eae1aeee | 404 | |
8c9beb11 GL |
405 | void mmc_detect_change(struct mmc_host *, unsigned long delay); |
406 | void mmc_request_done(struct mmc_host *, struct mmc_request *); | |
1da177e4 | 407 | |
17b759af NP |
408 | static inline void mmc_signal_sdio_irq(struct mmc_host *host) |
409 | { | |
410 | host->ops->enable_sdio_irq(host, 0); | |
bbbc4c4d | 411 | host->sdio_irq_pending = true; |
17b759af NP |
412 | wake_up_process(host->sdio_irq_thread); |
413 | } | |
414 | ||
bf3b5ec6 RK |
415 | void sdio_run_irqs(struct mmc_host *host); |
416 | ||
99fc5131 | 417 | #ifdef CONFIG_REGULATOR |
5c13941a | 418 | int mmc_regulator_get_ocrmask(struct regulator *supply); |
99fc5131 LW |
419 | int mmc_regulator_set_ocr(struct mmc_host *mmc, |
420 | struct regulator *supply, | |
421 | unsigned short vdd_bit); | |
422 | #else | |
423 | static inline int mmc_regulator_get_ocrmask(struct regulator *supply) | |
424 | { | |
425 | return 0; | |
426 | } | |
427 | ||
428 | static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, | |
429 | struct regulator *supply, | |
430 | unsigned short vdd_bit) | |
431 | { | |
432 | return 0; | |
433 | } | |
434 | #endif | |
5c13941a | 435 | |
4d1f52f9 TK |
436 | int mmc_regulator_get_supply(struct mmc_host *mmc); |
437 | ||
4c2ef25f | 438 | int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *); |
8ea926b2 | 439 | |
71d7d3d1 MF |
440 | static inline int mmc_card_is_removable(struct mmc_host *host) |
441 | { | |
2501c917 | 442 | return !(host->caps & MMC_CAP_NONREMOVABLE); |
71d7d3d1 MF |
443 | } |
444 | ||
a5e9425d | 445 | static inline int mmc_card_keep_power(struct mmc_host *host) |
080bc977 OBC |
446 | { |
447 | return host->pm_flags & MMC_PM_KEEP_POWER; | |
448 | } | |
449 | ||
6b93d01f OBC |
450 | static inline int mmc_card_wake_sdio_irq(struct mmc_host *host) |
451 | { | |
452 | return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; | |
453 | } | |
d0c97cfb AW |
454 | |
455 | static inline int mmc_host_cmd23(struct mmc_host *host) | |
456 | { | |
457 | return host->caps & MMC_CAP_CMD23; | |
458 | } | |
f7c56ef2 AH |
459 | |
460 | static inline int mmc_boot_partition_access(struct mmc_host *host) | |
461 | { | |
462 | return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC); | |
463 | } | |
464 | ||
41875e38 SRT |
465 | static inline int mmc_host_uhs(struct mmc_host *host) |
466 | { | |
467 | return host->caps & | |
468 | (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | | |
469 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | | |
470 | MMC_CAP_UHS_DDR50); | |
471 | } | |
472 | ||
ce39f9d1 SJ |
473 | static inline int mmc_host_packed_wr(struct mmc_host *host) |
474 | { | |
475 | return host->caps2 & MMC_CAP2_PACKED_WR; | |
476 | } | |
477 | ||
2c4967f7 SRT |
478 | #ifdef CONFIG_MMC_CLKGATE |
479 | void mmc_host_clk_hold(struct mmc_host *host); | |
480 | void mmc_host_clk_release(struct mmc_host *host); | |
481 | unsigned int mmc_host_clk_rate(struct mmc_host *host); | |
482 | ||
483 | #else | |
484 | static inline void mmc_host_clk_hold(struct mmc_host *host) | |
485 | { | |
486 | } | |
487 | ||
488 | static inline void mmc_host_clk_release(struct mmc_host *host) | |
489 | { | |
490 | } | |
491 | ||
492 | static inline unsigned int mmc_host_clk_rate(struct mmc_host *host) | |
493 | { | |
494 | return host->ios.clock; | |
495 | } | |
496 | #endif | |
cdc99179 SJ |
497 | |
498 | static inline int mmc_card_hs(struct mmc_card *card) | |
499 | { | |
500 | return card->host->ios.timing == MMC_TIMING_SD_HS || | |
501 | card->host->ios.timing == MMC_TIMING_MMC_HS; | |
502 | } | |
503 | ||
504 | static inline int mmc_card_uhs(struct mmc_card *card) | |
505 | { | |
506 | return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && | |
507 | card->host->ios.timing <= MMC_TIMING_UHS_DDR50; | |
508 | } | |
509 | ||
510 | static inline bool mmc_card_hs200(struct mmc_card *card) | |
511 | { | |
512 | return card->host->ios.timing == MMC_TIMING_MMC_HS200; | |
513 | } | |
514 | ||
515 | static inline bool mmc_card_ddr52(struct mmc_card *card) | |
516 | { | |
517 | return card->host->ios.timing == MMC_TIMING_MMC_DDR52; | |
518 | } | |
0a5b6438 SJ |
519 | |
520 | static inline bool mmc_card_hs400(struct mmc_card *card) | |
521 | { | |
522 | return card->host->ios.timing == MMC_TIMING_MMC_HS400; | |
523 | } | |
524 | ||
dfa13ebb AH |
525 | void mmc_retune_timer_stop(struct mmc_host *host); |
526 | ||
527 | static inline void mmc_retune_needed(struct mmc_host *host) | |
528 | { | |
529 | if (host->can_retune) | |
530 | host->need_retune = 1; | |
531 | } | |
532 | ||
533 | static inline void mmc_retune_recheck(struct mmc_host *host) | |
534 | { | |
535 | if (host->hold_retune <= 1) | |
536 | host->retune_now = 1; | |
537 | } | |
538 | ||
100e9186 | 539 | #endif /* LINUX_MMC_HOST_H */ |