[deliverable/linux.git] / include / linux / mmc / sh_mmcif.h

/*
 * include/linux/mmc/sh_mmcif.h
 *
 * platform data for eMMC driver
 *
 * Copyright (C) 2010 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 */

#ifndef __SH_MMCIF_H__
#define __SH_MMCIF_H__

#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/sh_dma.h>

/*
 * MMCIF : CE_CLK_CTRL [19:16]
 * 1000 : Peripheral clock / 512
 * 0111 : Peripheral clock / 256
 * 0110 : Peripheral clock / 128
 * 0101 : Peripheral clock / 64
 * 0100 : Peripheral clock / 32
 * 0011 : Peripheral clock / 16
 * 0010 : Peripheral clock / 8
 * 0001 : Peripheral clock / 4
 * 0000 : Peripheral clock / 2
 * 1111 : Peripheral clock (sup_pclk set '1')
 */

struct sh_mmcif_dma {
	struct sh_dmae_slave chan_priv_tx;
	struct sh_dmae_slave chan_priv_rx;
};

struct sh_mmcif_plat_data {
	void (*set_pwr)(struct platform_device *pdev, int state);
	void (*down_pwr)(struct platform_device *pdev);
	int (*get_cd)(struct platform_device *pdef);
	struct sh_mmcif_dma	*dma;
	u8			sup_pclk;	/* 1 :SH7757, 0: SH7724/SH7372 */
	unsigned long		caps;
	u32			ocr;
};

#define MMCIF_CE_CMD_SET	0x00000000
#define MMCIF_CE_ARG		0x00000008
#define MMCIF_CE_ARG_CMD12	0x0000000C
#define MMCIF_CE_CMD_CTRL	0x00000010
#define MMCIF_CE_BLOCK_SET	0x00000014
#define MMCIF_CE_CLK_CTRL	0x00000018
#define MMCIF_CE_BUF_ACC	0x0000001C
#define MMCIF_CE_RESP3		0x00000020
#define MMCIF_CE_RESP2		0x00000024
#define MMCIF_CE_RESP1		0x00000028
#define MMCIF_CE_RESP0		0x0000002C
#define MMCIF_CE_RESP_CMD12	0x00000030
#define MMCIF_CE_DATA		0x00000034
#define MMCIF_CE_INT		0x00000040
#define MMCIF_CE_INT_MASK	0x00000044
#define MMCIF_CE_HOST_STS1	0x00000048
#define MMCIF_CE_HOST_STS2	0x0000004C
#define MMCIF_CE_VERSION	0x0000007C

/* CE_BUF_ACC */
#define BUF_ACC_DMAWEN		(1 << 25)
#define BUF_ACC_DMAREN		(1 << 24)
#define BUF_ACC_BUSW_32		(0 << 17)
#define BUF_ACC_BUSW_16		(1 << 17)
#define BUF_ACC_ATYP		(1 << 16)

/* CE_CLK_CTRL */
#define CLK_ENABLE		(1 << 24) /* 1: output mmc clock */
#define CLK_CLEAR		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLK_SUP_PCLK		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLKDIV_4		(1<<16) /* mmc clock frequency.
					 * n: bus clock/(2^(n+1)) */
#define CLKDIV_256		(7<<16) /* mmc clock frequency. (see above) */
#define SRSPTO_256		((1 << 13) | (0 << 12)) /* resp timeout */
#define SRBSYTO_29		((1 << 11) | (1 << 10) |	\
				 (1 << 9) | (1 << 8)) /* resp busy timeout */
#define SRWDTO_29		((1 << 7) | (1 << 6) |		\
				 (1 << 5) | (1 << 4)) /* read/write timeout */
#define SCCSTO_29		((1 << 3) | (1 << 2) |		\
				 (1 << 1) | (1 << 0)) /* ccs timeout */

/* CE_VERSION */
#define SOFT_RST_ON		(1 << 31)
#define SOFT_RST_OFF		0

static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
{
	return __raw_readl(addr + reg);
}

static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
{
	__raw_writel(val, addr + reg);
}

#define SH_MMCIF_BBS 512 /* boot block size */

enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
       MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };

static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
					  unsigned long cmd, unsigned long arg)
{
	sh_mmcif_writel(base, MMCIF_CE_INT, 0);
	sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
	sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
}

static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
{
	unsigned long tmp;
	int cnt;

	for (cnt = 0; cnt < 1000000; cnt++) {
		tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
		if (tmp & mask) {
			sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
			return 0;
		}
	}

	return -1;
}

static inline int sh_mmcif_boot_cmd(void __iomem *base,
				    unsigned long cmd, unsigned long arg)
{
	sh_mmcif_boot_cmd_send(base, cmd, arg);
	return sh_mmcif_boot_cmd_poll(base, 0x00010000);
}

static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
					       unsigned int block_nr,
					       unsigned long *buf)
{
	int k;

	/* CMD13 - Status */
	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);

	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
		return -1;

	/* CMD17 - Read */
	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
		return -1;

	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
		buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);

	return 0;
}

static inline int sh_mmcif_boot_do_read(void __iomem *base,
					unsigned long first_block,
					unsigned long nr_blocks,
					void *buf)
{
	unsigned long k;
	int ret = 0;

	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
			CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);

	/* CMD9 - Get CSD */
	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);

	/* CMD7 - Select the card */
	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);

	/* CMD16 - Set the block size */
	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);

	for (k = 0; !ret && k < nr_blocks; k++)
		ret = sh_mmcif_boot_do_read_single(base, first_block + k,
						   buf + (k * SH_MMCIF_BBS));

	return ret;
}

static inline void sh_mmcif_boot_init(void __iomem *base)
{
	/* reset */
	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);

	/* byte swap */
	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);

	/* Set block size in MMCIF hardware */
	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);

	/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
			CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);

	/* CMD0 */
	sh_mmcif_boot_cmd(base, 0x00000040, 0);

	/* CMD1 - Get OCR */
	do {
		sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
		 != 0x80000000);

	/* CMD2 - Get CID */
	sh_mmcif_boot_cmd(base, 0x02806040, 0);

	/* CMD3 - Set card relative address */
	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
}

#endif /* __SH_MMCIF_H__ */
Commit	Line	Data
fdc50a94 YG	1	/*
	2	* include/linux/mmc/sh_mmcif.h
	3	*
	4	* platform data for eMMC driver
	5	*
	6	* Copyright (C) 2010 Renesas Solutions Corp.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License.
	11	*
	12	*/
	13
	14	#ifndef __SH_MMCIF_H__
	15	#define __SH_MMCIF_H__
	16
487d9fc5	17	#include <linux/io.h>
a782d688 GL	18	#include <linux/platform_device.h>
a782d688 GL	19	#include <linux/sh_dma.h>
487d9fc5	20
fdc50a94 YG	21	/*
	22	* MMCIF : CE_CLK_CTRL [19:16]
	23	* 1000 : Peripheral clock / 512
	24	* 0111 : Peripheral clock / 256
	25	* 0110 : Peripheral clock / 128
	26	* 0101 : Peripheral clock / 64
	27	* 0100 : Peripheral clock / 32
	28	* 0011 : Peripheral clock / 16
	29	* 0010 : Peripheral clock / 8
	30	* 0001 : Peripheral clock / 4
	31	* 0000 : Peripheral clock / 2
	32	* 1111 : Peripheral clock (sup_pclk set '1')
	33	*/
	34
a782d688 GL	35	struct sh_mmcif_dma {
	36	struct sh_dmae_slave chan_priv_tx;
	37	struct sh_dmae_slave chan_priv_rx;
	38	};
	39
fdc50a94 YG	40	struct sh_mmcif_plat_data {
	41	void (set_pwr)(struct platform_device pdev, int state);
	42	void (down_pwr)(struct platform_device pdev);
777271d0	43	int (get_cd)(struct platform_device pdef);
a782d688 GL	44	struct sh_mmcif_dma *dma;
	45	u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
	46	unsigned long caps;
	47	u32 ocr;
fdc50a94 YG	48	};
fdc50a94 YG	49
487d9fc5 MD	50	#define MMCIF_CE_CMD_SET 0x00000000
	51	#define MMCIF_CE_ARG 0x00000008
	52	#define MMCIF_CE_ARG_CMD12 0x0000000C
	53	#define MMCIF_CE_CMD_CTRL 0x00000010
	54	#define MMCIF_CE_BLOCK_SET 0x00000014
	55	#define MMCIF_CE_CLK_CTRL 0x00000018
	56	#define MMCIF_CE_BUF_ACC 0x0000001C
	57	#define MMCIF_CE_RESP3 0x00000020
	58	#define MMCIF_CE_RESP2 0x00000024
	59	#define MMCIF_CE_RESP1 0x00000028
	60	#define MMCIF_CE_RESP0 0x0000002C
	61	#define MMCIF_CE_RESP_CMD12 0x00000030
	62	#define MMCIF_CE_DATA 0x00000034
	63	#define MMCIF_CE_INT 0x00000040
	64	#define MMCIF_CE_INT_MASK 0x00000044
	65	#define MMCIF_CE_HOST_STS1 0x00000048
	66	#define MMCIF_CE_HOST_STS2 0x0000004C
	67	#define MMCIF_CE_VERSION 0x0000007C
	68
da1d39e3 SH	69	/* CE_BUF_ACC */
	70	#define BUF_ACC_DMAWEN (1 << 25)
	71	#define BUF_ACC_DMAREN (1 << 24)
	72	#define BUF_ACC_BUSW_32 (0 << 17)
	73	#define BUF_ACC_BUSW_16 (1 << 17)
	74	#define BUF_ACC_ATYP (1 << 16)
	75
	76	/* CE_CLK_CTRL */
	77	#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
	78	#define CLK_CLEAR ((1 << 19) \| (1 << 18) \| (1 << 17) \| (1 << 16))
	79	#define CLK_SUP_PCLK ((1 << 19) \| (1 << 18) \| (1 << 17) \| (1 << 16))
22efa0fe SH	80	#define CLKDIV_4 (1<<16) /* mmc clock frequency.
	81	* n: bus clock/(2^(n+1)) */
	82	#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
da1d39e3 SH	83	#define SRSPTO_256 ((1 << 13) \| (0 << 12)) /* resp timeout */
	84	#define SRBSYTO_29 ((1 << 11) \| (1 << 10) \| \
	85	(1 << 9) \| (1 << 8)) /* resp busy timeout */
	86	#define SRWDTO_29 ((1 << 7) \| (1 << 6) \| \
	87	(1 << 5) \| (1 << 4)) /* read/write timeout */
	88	#define SCCSTO_29 ((1 << 3) \| (1 << 2) \| \
	89	(1 << 1) \| (1 << 0)) /* ccs timeout */
	90
	91	/* CE_VERSION */
	92	#define SOFT_RST_ON (1 << 31)
1ae0affe	93	#define SOFT_RST_OFF 0
da1d39e3	94
2f6ba579	95	static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
487d9fc5	96	{
bba95878	97	return __raw_readl(addr + reg);
487d9fc5 MD	98	}
487d9fc5 MD	99
2f6ba579	100	static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
487d9fc5	101	{
bba95878	102	__raw_writel(val, addr + reg);
487d9fc5 MD	103	}
487d9fc5 MD	104
8a768952 MD	105	#define SH_MMCIF_BBS 512 /* boot block size */
8a768952 MD	106
9f843706 SH	107	enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
	108	MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };
	109
2f6ba579	110	static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
8a768952 MD	111	unsigned long cmd, unsigned long arg)
	112	{
	113	sh_mmcif_writel(base, MMCIF_CE_INT, 0);
	114	sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
	115	sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
	116	}
	117
2f6ba579	118	static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
8a768952 MD	119	{
	120	unsigned long tmp;
	121	int cnt;
	122
	123	for (cnt = 0; cnt < 1000000; cnt++) {
	124	tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
	125	if (tmp & mask) {
	126	sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
	127	return 0;
	128	}
	129	}
	130
	131	return -1;
	132	}
	133
2f6ba579	134	static inline int sh_mmcif_boot_cmd(void __iomem *base,
8a768952 MD	135	unsigned long cmd, unsigned long arg)
	136	{
	137	sh_mmcif_boot_cmd_send(base, cmd, arg);
	138	return sh_mmcif_boot_cmd_poll(base, 0x00010000);
	139	}
	140
2f6ba579	141	static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
8a768952 MD	142	unsigned int block_nr,
	143	unsigned long *buf)
	144	{
	145	int k;
	146
	147	/* CMD13 - Status */
	148	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
	149
	150	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
	151	return -1;
	152
	153	/* CMD17 - Read */
	154	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
	155	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
	156	return -1;
	157
	158	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
	159	buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
	160
	161	return 0;
	162	}
	163
2f6ba579	164	static inline int sh_mmcif_boot_do_read(void __iomem *base,
8a768952 MD	165	unsigned long first_block,
	166	unsigned long nr_blocks,
	167	void *buf)
	168	{
	169	unsigned long k;
	170	int ret = 0;
	171
54b38463 SH	172	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
	173	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
	174	CLK_ENABLE \| CLKDIV_4 \| SRSPTO_256 \|
	175	SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29);
	176
	177	/* CMD9 - Get CSD */
	178	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
	179
	180	/* CMD7 - Select the card */
	181	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
	182
8a768952 MD	183	/* CMD16 - Set the block size */
	184	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
	185
	186	for (k = 0; !ret && k < nr_blocks; k++)
	187	ret = sh_mmcif_boot_do_read_single(base, first_block + k,
	188	buf + (k * SH_MMCIF_BBS));
	189
	190	return ret;
	191	}
	192
2f6ba579	193	static inline void sh_mmcif_boot_init(void __iomem *base)
8a768952	194	{
8a768952	195	/* reset */
1ae0affe SH	196	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
1ae0affe SH	197	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
8a768952 MD	198
8a768952 MD	199	/* byte swap */
da1d39e3	200	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
8a768952 MD	201
	202	/* Set block size in MMCIF hardware */
	203	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
	204
22efa0fe	205	/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
da1d39e3	206	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
22efa0fe SH	207	CLK_ENABLE \| CLKDIV_256 \| SRSPTO_256 \|
22efa0fe SH	208	SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29);
8a768952 MD	209
	210	/* CMD0 */
	211	sh_mmcif_boot_cmd(base, 0x00000040, 0);
	212
	213	/* CMD1 - Get OCR */
	214	do {
	215	sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
	216	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
	217	!= 0x80000000);
	218
	219	/* CMD2 - Get CID */
	220	sh_mmcif_boot_cmd(base, 0x02806040, 0);
	221
	222	/* CMD3 - Set card relative address */
	223	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
	224	}
	225
fdc50a94	226	#endif /* __SH_MMCIF_H__ */