[deliverable/linux.git] / include / linux / mtd / spi-nor.h

/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __LINUX_MTD_SPI_NOR_H
#define __LINUX_MTD_SPI_NOR_H

#include <linux/bitops.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/mtd.h>

/*
 * Manufacturer IDs
 *
 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
 */
#define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
#define SNOR_MFR_INTEL		CFI_MFR_INTEL
#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron */
#define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
#define SNOR_MFR_SPANSION	CFI_MFR_AMD
#define SNOR_MFR_SST		CFI_MFR_SST
#define SNOR_MFR_WINBOND	0xef /* Also used by some Spansion */

/*
 * Note on opcode nomenclature: some opcodes have a format like
 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
 * of I/O lines used for the opcode, address, and data (respectively). The
 * FUNCTION has an optional suffix of '4', to represent an opcode which
 * requires a 4-byte (32-bit) address.
 */

/* Flash opcodes. */
#define SPINOR_OP_WREN		0x06	/* Write enable */
#define SPINOR_OP_RDSR		0x05	/* Read status register */
#define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
#define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST	0x0b	/* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual SPI) */
#define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad SPI) */
#define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
#define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
#define SPINOR_OP_CHIP_ERASE	0xc7	/* Erase whole flash chip */
#define SPINOR_OP_SE		0xd8	/* Sector erase (usually 64KiB) */
#define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
#define SPINOR_OP_RDCR		0x35	/* Read configuration register */
#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */

/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define SPINOR_OP_READ4		0x13	/* Read data bytes (low frequency) */
#define SPINOR_OP_READ4_FAST	0x0c	/* Read data bytes (high frequency) */
#define SPINOR_OP_READ4_1_1_2	0x3c	/* Read data bytes (Dual SPI) */
#define SPINOR_OP_READ4_1_1_4	0x6c	/* Read data bytes (Quad SPI) */
#define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
#define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */

/* Used for SST flashes only. */
#define SPINOR_OP_BP		0x02	/* Byte program */
#define SPINOR_OP_WRDI		0x04	/* Write disable */
#define SPINOR_OP_AAI_WP	0xad	/* Auto address increment word program */

/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */

/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR		0x17	/* Bank register write */

/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */

/* Status Register bits. */
#define SR_WIP			BIT(0)	/* Write in progress */
#define SR_WEL			BIT(1)	/* Write enable latch */
/* meaning of other SR_* bits may differ between vendors */
#define SR_BP0			BIT(2)	/* Block protect 0 */
#define SR_BP1			BIT(3)	/* Block protect 1 */
#define SR_BP2			BIT(4)	/* Block protect 2 */
#define SR_TB			BIT(5)	/* Top/Bottom protect */
#define SR_SRWD			BIT(7)	/* SR write protect */

#define SR_QUAD_EN_MX		BIT(6)	/* Macronix Quad I/O */

/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON	BIT(7)	/* Micron Quad I/O */

/* Flag Status Register bits */
#define FSR_READY		BIT(7)

/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN		BIT(1)	/* Spansion Quad I/O */

enum read_mode {
	SPI_NOR_NORMAL = 0,
	SPI_NOR_FAST,
	SPI_NOR_DUAL,
	SPI_NOR_QUAD,
};

#define SPI_NOR_MAX_CMD_SIZE	8
enum spi_nor_ops {
	SPI_NOR_OPS_READ = 0,
	SPI_NOR_OPS_WRITE,
	SPI_NOR_OPS_ERASE,
	SPI_NOR_OPS_LOCK,
	SPI_NOR_OPS_UNLOCK,
};

enum spi_nor_option_flags {
	SNOR_F_USE_FSR		= BIT(0),
	SNOR_F_HAS_SR_TB	= BIT(1),
};

/**
 * struct spi_nor - Structure for defining a the SPI NOR layer
 * @mtd:		point to a mtd_info structure
 * @lock:		the lock for the read/write/erase/lock/unlock operations
 * @dev:		point to a spi device, or a spi nor controller device.
 * @page_size:		the page size of the SPI NOR
 * @addr_width:		number of address bytes
 * @erase_opcode:	the opcode for erasing a sector
 * @read_opcode:	the read opcode
 * @read_dummy:		the dummy needed by the read operation
 * @program_opcode:	the program opcode
 * @flash_read:		the mode of the read
 * @sst_write_second:	used by the SST write operation
 * @flags:		flag options for the current SPI-NOR (SNOR_F_*)
 * @cmd_buf:		used by the write_reg
 * @prepare:		[OPTIONAL] do some preparations for the
 *			read/write/erase/lock/unlock operations
 * @unprepare:		[OPTIONAL] do some post work after the
 *			read/write/erase/lock/unlock operations
 * @read_reg:		[DRIVER-SPECIFIC] read out the register
 * @write_reg:		[DRIVER-SPECIFIC] write data to the register
 * @read:		[DRIVER-SPECIFIC] read data from the SPI NOR
 * @write:		[DRIVER-SPECIFIC] write data to the SPI NOR
 * @erase:		[DRIVER-SPECIFIC] erase a sector of the SPI NOR
 *			at the offset @offs; if not provided by the driver,
 *			spi-nor will send the erase opcode via write_reg()
 * @flash_lock:		[FLASH-SPECIFIC] lock a region of the SPI NOR
 * @flash_unlock:	[FLASH-SPECIFIC] unlock a region of the SPI NOR
 * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
 *			completely locked
 * @priv:		the private data
 */
struct spi_nor {
	struct mtd_info		mtd;
	struct mutex		lock;
	struct device		*dev;
	u32			page_size;
	u8			addr_width;
	u8			erase_opcode;
	u8			read_opcode;
	u8			read_dummy;
	u8			program_opcode;
	enum read_mode		flash_read;
	bool			sst_write_second;
	u32			flags;
	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];

	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);

	int (*read)(struct spi_nor *nor, loff_t from,
			size_t len, size_t *retlen, u_char *read_buf);
	void (*write)(struct spi_nor *nor, loff_t to,
			size_t len, size_t *retlen, const u_char *write_buf);
	int (*erase)(struct spi_nor *nor, loff_t offs);

	int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
	int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
	int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);

	void *priv;
};

static inline void spi_nor_set_flash_node(struct spi_nor *nor,
					  struct device_node *np)
{
	mtd_set_of_node(&nor->mtd, np);
}

static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
{
	return mtd_get_of_node(&nor->mtd);
}

/**
 * spi_nor_scan() - scan the SPI NOR
 * @nor:	the spi_nor structure
 * @name:	the chip type name
 * @mode:	the read mode supported by the driver
 *
 * The drivers can use this fuction to scan the SPI NOR.
 * In the scanning, it will try to get all the necessary information to
 * fill the mtd_info{} and the spi_nor{}.
 *
 * The chip type name can be provided through the @name parameter.
 *
 * Return: 0 for success, others for failure.
 */
int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);

#endif
Commit	Line	Data
8eabdd1e HS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
f39d2fa0 HS	10	#ifndef __LINUX_MTD_SPI_NOR_H
	11	#define __LINUX_MTD_SPI_NOR_H
	12
801cf21b	13	#include <linux/bitops.h>
db4745ed	14	#include <linux/mtd/cfi.h>
2c81de77	15	#include <linux/mtd/mtd.h>
db4745ed BN	16
	17	/*
	18	* Manufacturer IDs
	19	*
	20	* The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
	21	* Sometimes these are the same as CFI IDs, but sometimes they aren't.
	22	*/
	23	#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
	24	#define SNOR_MFR_INTEL CFI_MFR_INTEL
	25	#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
	26	#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
	27	#define SNOR_MFR_SPANSION CFI_MFR_AMD
	28	#define SNOR_MFR_SST CFI_MFR_SST
67b9bcd3	29	#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
801cf21b	30
58b89a1f BN	31	/*
	32	* Note on opcode nomenclature: some opcodes have a format like
	33	* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
	34	* of I/O lines used for the opcode, address, and data (respectively). The
	35	* FUNCTION has an optional suffix of '4', to represent an opcode which
	36	* requires a 4-byte (32-bit) address.
	37	*/
	38
f39d2fa0	39	/* Flash opcodes. */
b02e7f3e BN	40	#define SPINOR_OP_WREN 0x06 /* Write enable */
	41	#define SPINOR_OP_RDSR 0x05 /* Read status register */
	42	#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
58b89a1f BN	43	#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
	44	#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
	45	#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
	46	#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
b02e7f3e BN	47	#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
	48	#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
	49	#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
	50	#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
	51	#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
	52	#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
	53	#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
	54	#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
c14dedde	55	#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
f39d2fa0 HS	56
f39d2fa0 HS	57	/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
58b89a1f BN	58	#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
	59	#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
	60	#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
	61	#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
b02e7f3e BN	62	#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
b02e7f3e BN	63	#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
f39d2fa0 HS	64
f39d2fa0 HS	65	/* Used for SST flashes only. */
b02e7f3e BN	66	#define SPINOR_OP_BP 0x02 /* Byte program */
	67	#define SPINOR_OP_WRDI 0x04 /* Write disable */
	68	#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
f39d2fa0 HS	69
f39d2fa0 HS	70	/* Used for Macronix and Winbond flashes. */
b02e7f3e BN	71	#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
b02e7f3e BN	72	#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
f39d2fa0 HS	73
f39d2fa0 HS	74	/* Used for Spansion flashes only. */
b02e7f3e	75	#define SPINOR_OP_BRWR 0x17 /* Bank register write */
f39d2fa0	76
548cd3ab BH	77	/* Used for Micron flashes only. */
	78	#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
	79	#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
	80
f39d2fa0	81	/* Status Register bits. */
a8a16454 BN	82	#define SR_WIP BIT(0) /* Write in progress */
a8a16454 BN	83	#define SR_WEL BIT(1) /* Write enable latch */
f39d2fa0	84	/* meaning of other SR_* bits may differ between vendors */
a8a16454 BN	85	#define SR_BP0 BIT(2) /* Block protect 0 */
	86	#define SR_BP1 BIT(3) /* Block protect 1 */
	87	#define SR_BP2 BIT(4) /* Block protect 2 */
3dd8012a	88	#define SR_TB BIT(5) /* Top/Bottom protect */
a8a16454	89	#define SR_SRWD BIT(7) /* SR write protect */
f39d2fa0	90
a8a16454	91	#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
f39d2fa0	92
548cd3ab	93	/* Enhanced Volatile Configuration Register bits */
a8a16454	94	#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
548cd3ab	95
c14dedde	96	/* Flag Status Register bits */
a8a16454	97	#define FSR_READY BIT(7)
c14dedde	98
f39d2fa0	99	/* Configuration Register bits. */
a8a16454	100	#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
f39d2fa0	101
6e602ef7 HS	102	enum read_mode {
	103	SPI_NOR_NORMAL = 0,
	104	SPI_NOR_FAST,
	105	SPI_NOR_DUAL,
	106	SPI_NOR_QUAD,
	107	};
	108
becd0cb8	109	#define SPI_NOR_MAX_CMD_SIZE 8
6e602ef7 HS	110	enum spi_nor_ops {
	111	SPI_NOR_OPS_READ = 0,
	112	SPI_NOR_OPS_WRITE,
	113	SPI_NOR_OPS_ERASE,
	114	SPI_NOR_OPS_LOCK,
	115	SPI_NOR_OPS_UNLOCK,
	116	};
	117
6af91949 BN	118	enum spi_nor_option_flags {
6af91949 BN	119	SNOR_F_USE_FSR = BIT(0),
3dd8012a	120	SNOR_F_HAS_SR_TB = BIT(1),
6af91949 BN	121	};
6af91949 BN	122
6e602ef7 HS	123	/**
	124	* struct spi_nor - Structure for defining a the SPI NOR layer
	125	* @mtd: point to a mtd_info structure
	126	* @lock: the lock for the read/write/erase/lock/unlock operations
	127	* @dev: point to a spi device, or a spi nor controller device.
	128	* @page_size: the page size of the SPI NOR
	129	* @addr_width: number of address bytes
	130	* @erase_opcode: the opcode for erasing a sector
	131	* @read_opcode: the read opcode
	132	* @read_dummy: the dummy needed by the read operation
	133	* @program_opcode: the program opcode
	134	* @flash_read: the mode of the read
	135	* @sst_write_second: used by the SST write operation
6af91949	136	* @flags: flag options for the current SPI-NOR (SNOR_F_*)
6e602ef7 HS	137	* @cmd_buf: used by the write_reg
	138	* @prepare: [OPTIONAL] do some preparations for the
	139	* read/write/erase/lock/unlock operations
	140	* @unprepare: [OPTIONAL] do some post work after the
	141	* read/write/erase/lock/unlock operations
6e602ef7 HS	142	* @read_reg: [DRIVER-SPECIFIC] read out the register
6e602ef7 HS	143	* @write_reg: [DRIVER-SPECIFIC] write data to the register
6e602ef7 HS	144	* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
	145	* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
	146	* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
c67cbb83 BN	147	* at the offset @offs; if not provided by the driver,
c67cbb83 BN	148	* spi-nor will send the erase opcode via write_reg()
f8900258 BN	149	* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
f8900258 BN	150	* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
5bf0e69b BN	151	* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
5bf0e69b BN	152	* completely locked
6e602ef7 HS	153	* @priv: the private data
	154	*/
	155	struct spi_nor {
19763671	156	struct mtd_info mtd;
6e602ef7 HS	157	struct mutex lock;
	158	struct device *dev;
	159	u32 page_size;
	160	u8 addr_width;
	161	u8 erase_opcode;
	162	u8 read_opcode;
	163	u8 read_dummy;
	164	u8 program_opcode;
	165	enum read_mode flash_read;
	166	bool sst_write_second;
6af91949	167	u32 flags;
6e602ef7 HS	168	u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
	169
	170	int (prepare)(struct spi_nor nor, enum spi_nor_ops ops);
	171	void (unprepare)(struct spi_nor nor, enum spi_nor_ops ops);
6e602ef7	172	int (read_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len);
f9f3ce83	173	int (write_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len);
6e602ef7 HS	174
	175	int (read)(struct spi_nor nor, loff_t from,
	176	size_t len, size_t retlen, u_char read_buf);
	177	void (write)(struct spi_nor nor, loff_t to,
	178	size_t len, size_t retlen, const u_char write_buf);
	179	int (erase)(struct spi_nor nor, loff_t offs);
	180
8cc7f33a BN	181	int (flash_lock)(struct spi_nor nor, loff_t ofs, uint64_t len);
8cc7f33a BN	182	int (flash_unlock)(struct spi_nor nor, loff_t ofs, uint64_t len);
5bf0e69b	183	int (flash_is_locked)(struct spi_nor nor, loff_t ofs, uint64_t len);
8cc7f33a	184
6e602ef7 HS	185	void *priv;
6e602ef7 HS	186	};
b199489d	187
28b8b26b BN	188	static inline void spi_nor_set_flash_node(struct spi_nor *nor,
	189	struct device_node *np)
	190	{
30069af7	191	mtd_set_of_node(&nor->mtd, np);
28b8b26b BN	192	}
	193
	194	static inline struct device_node spi_nor_get_flash_node(struct spi_nor nor)
	195	{
30069af7	196	return mtd_get_of_node(&nor->mtd);
28b8b26b BN	197	}
28b8b26b BN	198
b199489d HS	199	/**
	200	* spi_nor_scan() - scan the SPI NOR
	201	* @nor: the spi_nor structure
70f3ce05	202	* @name: the chip type name
b199489d HS	203	* @mode: the read mode supported by the driver
	204	*
	205	* The drivers can use this fuction to scan the SPI NOR.
	206	* In the scanning, it will try to get all the necessary information to
	207	* fill the mtd_info{} and the spi_nor{}.
	208	*
70f3ce05	209	* The chip type name can be provided through the @name parameter.
b199489d HS	210	*
	211	* Return: 0 for success, others for failure.
	212	*/
70f3ce05	213	int spi_nor_scan(struct spi_nor nor, const char name, enum read_mode mode);
b199489d	214
f39d2fa0	215	#endif