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[SK_BUFF]: Introduce skb_reset_transport_header(skb)
[deliverable/linux.git] / include / linux / pci.h
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1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
4352dfd5
GKH		 20/* Include the pci register defines */
21#include <linux/pci_regs.h>
1da177e4 22
1da177e4
LT		 23/*
24 * The PCI interface treats multi-function devices as independent
25 * devices. The slot/function address of each device is encoded
26 * in a single byte as follows:
27 *
28 * 7:3 = slot
29 * 2:0 = function
30 */
31#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
32#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
33#define PCI_FUNC(devfn) ((devfn) & 0x07)
34
35/* Ioctls for /proc/bus/pci/X/Y nodes. */
36#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
37#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
38#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
39#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
40#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
41
42#ifdef __KERNEL__
43
778382e0
DW		 44#include <linux/mod_devicetable.h>
45
1da177e4 46#include <linux/types.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
bae94d02 51#include <asm/atomic.h>
1da177e4
LT		 52#include <linux/device.h>
53
7e7a43c3
AB		 54/* Include the ID list */
55#include <linux/pci_ids.h>
56
1da177e4
LT		 57/* File state for mmap()s on /proc/bus/pci/X/Y */
58enum pci_mmap_state {
59 pci_mmap_io,
60 pci_mmap_mem
61};
62
63/* This defines the direction arg to the DMA mapping routines. */
64#define PCI_DMA_BIDIRECTIONAL 0
65#define PCI_DMA_TODEVICE 1
66#define PCI_DMA_FROMDEVICE 2
67#define PCI_DMA_NONE 3
68
69#define DEVICE_COUNT_COMPATIBLE 4
70#define DEVICE_COUNT_RESOURCE 12
71
72typedef int __bitwise pci_power_t;
73
4352dfd5
GKH		 74#define PCI_D0 ((pci_power_t __force) 0)
75#define PCI_D1 ((pci_power_t __force) 1)
76#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 77#define PCI_D3hot ((pci_power_t __force) 3)
78#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 79#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 80#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 81
392a1ce7 82/** The pci_channel state describes connectivity between the CPU and
83 * the pci device. If some PCI bus between here and the pci device
84 * has crashed or locked up, this info is reflected here.
85 */
86typedef unsigned int __bitwise pci_channel_state_t;
87
88enum pci_channel_state {
89 /* I/O channel is in normal state */
90 pci_channel_io_normal = (__force pci_channel_state_t) 1,
91
92 /* I/O to channel is blocked */
93 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
94
95 /* PCI card is dead */
96 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
97};
98
6e325a62
MT		 99typedef unsigned short __bitwise pci_bus_flags_t;
100enum pci_bus_flags {
e778272d 101 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
6e325a62
MT		 102};
103
41017f0c
SL		 104struct pci_cap_saved_state {
105 struct hlist_node next;
106 char cap_nr;
107 u32 data[0];
108};
109
1da177e4
LT		 110/*
111 * The pci_dev structure is used to describe PCI devices.
112 */
113struct pci_dev {
114 struct list_head global_list; /* node in list of all PCI devices */
115 struct list_head bus_list; /* node in per-bus list */
116 struct pci_bus *bus; /* bus this device is on */
117 struct pci_bus *subordinate; /* bus this device bridges to */
118
119 void *sysdata; /* hook for sys-specific extension */
120 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
121
122 unsigned int devfn; /* encoded device & function index */
123 unsigned short vendor;
124 unsigned short device;
125 unsigned short subsystem_vendor;
126 unsigned short subsystem_device;
127 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
128 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
129 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 130 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 131
132 struct pci_driver *driver; /* which driver has allocated this device */
133 u64 dma_mask; /* Mask of the bits of bus address this
134 device implements. Normally this is
135 0xffffffff. You only need to change
136 this if your device has broken DMA
137 or supports 64-bit transfers. */
138
139 pci_power_t current_state; /* Current operating state. In ACPI-speak,
140 this is D0-D3, D0 being fully functional,
141 and D3 being off. */
142
392a1ce7 143 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 144 struct device dev; /* Generic device interface */
145
146 /* device is compatible with these IDs */
147 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
148 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
149
150 int cfg_size; /* Size of configuration space */
151
152 /*
153 * Instead of touching interrupt line and base address registers
154 * directly, use the values stored here. They might be different!
155 */
156 unsigned int irq;
157 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
158
159 /* These fields are used by common fixups */
160 unsigned int transparent:1; /* Transparent PCI bridge */
161 unsigned int multifunction:1;/* Part of multi-function device */
162 /* keep track of device state */
1da177e4 163 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 164 unsigned int no_msi:1; /* device may not use msi */
ffadcc2f 165 unsigned int no_d1d2:1; /* only allow d0 or d3 */
e04b0ea2 166 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
bd8481e1 167 unsigned int broken_parity_status:1; /* Device generates false positive parity */
99dc804d
SL		 168 unsigned int msi_enabled:1;
169 unsigned int msix_enabled:1;
9ac7849e 170 unsigned int is_managed:1;
bae94d02 171 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 172
1da177e4 173 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 174 struct hlist_head saved_cap_space;
1da177e4
LT		 175 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
176 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
177 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
ded86d8d
EB		 178#ifdef CONFIG_PCI_MSI
179 unsigned int first_msi_irq;
180#endif
1da177e4
LT		 181};
182
183#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
184#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
185#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
186#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
187
a7369f1f
LV		 188static inline int pci_channel_offline(struct pci_dev *pdev)
189{
190 return (pdev->error_state != pci_channel_io_normal);
191}
192
41017f0c
SL		 193static inline struct pci_cap_saved_state *pci_find_saved_cap(
194 struct pci_dev *pci_dev,char cap)
195{
196 struct pci_cap_saved_state *tmp;
197 struct hlist_node *pos;
198
199 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
200 if (tmp->cap_nr == cap)
201 return tmp;
202 }
203 return NULL;
204}
205
206static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
207 struct pci_cap_saved_state *new_cap)
208{
209 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
210}
211
1da177e4
LT		 212/*
213 * For PCI devices, the region numbers are assigned this way:
214 *
215 * 0-5 standard PCI regions
216 * 6 expansion ROM
217 * 7-10 bridges: address space assigned to buses behind the bridge
218 */
219
4352dfd5
GKH		 220#define PCI_ROM_RESOURCE 6
221#define PCI_BRIDGE_RESOURCES 7
222#define PCI_NUM_RESOURCES 11
1da177e4
LT		 223
224#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 225#define PCI_BUS_NUM_RESOURCES 8
1da177e4 226#endif
4352dfd5
GKH		 227
228#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 229
230struct pci_bus {
231 struct list_head node; /* node in list of buses */
232 struct pci_bus *parent; /* parent bus this bridge is on */
233 struct list_head children; /* list of child buses */
234 struct list_head devices; /* list of devices on this bus */
235 struct pci_dev *self; /* bridge device as seen by parent */
236 struct resource *resource[PCI_BUS_NUM_RESOURCES];
237 /* address space routed to this bus */
238
239 struct pci_ops *ops; /* configuration access functions */
240 void *sysdata; /* hook for sys-specific extension */
241 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
242
243 unsigned char number; /* bus number */
244 unsigned char primary; /* number of primary bridge */
245 unsigned char secondary; /* number of secondary bridge */
246 unsigned char subordinate; /* max number of subordinate buses */
247
248 char name[48];
249
250 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 251 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4
LT		 252 struct device *bridge;
253 struct class_device class_dev;
254 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
255 struct bin_attribute *legacy_mem; /* legacy mem */
256};
257
258#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
259#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
260
261/*
262 * Error values that may be returned by PCI functions.
263 */
264#define PCIBIOS_SUCCESSFUL 0x00
265#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
266#define PCIBIOS_BAD_VENDOR_ID 0x83
267#define PCIBIOS_DEVICE_NOT_FOUND 0x86
268#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
269#define PCIBIOS_SET_FAILED 0x88
270#define PCIBIOS_BUFFER_TOO_SMALL 0x89
271
272/* Low-level architecture-dependent routines */
273
274struct pci_ops {
275 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
276 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
277};
278
279struct pci_raw_ops {
280 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
281 int reg, int len, u32 *val);
282 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
283 int reg, int len, u32 val);
284};
285
286extern struct pci_raw_ops *raw_pci_ops;
287
288struct pci_bus_region {
289 unsigned long start;
290 unsigned long end;
291};
292
293struct pci_dynids {
294 spinlock_t lock; /* protects list, index */
295 struct list_head list; /* for IDs added at runtime */
296 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
297};
298
392a1ce7 299/* ---------------------------------------------------------------- */
300/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
301 * a set fof callbacks in struct pci_error_handlers, then that device driver
302 * will be notified of PCI bus errors, and will be driven to recovery
303 * when an error occurs.
304 */
305
306typedef unsigned int __bitwise pci_ers_result_t;
307
308enum pci_ers_result {
309 /* no result/none/not supported in device driver */
310 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
311
312 /* Device driver can recover without slot reset */
313 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
314
315 /* Device driver wants slot to be reset. */
316 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
317
318 /* Device has completely failed, is unrecoverable */
319 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
320
321 /* Device driver is fully recovered and operational */
322 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
323};
324
325/* PCI bus error event callbacks */
326struct pci_error_handlers
327{
328 /* PCI bus error detected on this device */
329 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
330 enum pci_channel_state error);
331
332 /* MMIO has been re-enabled, but not DMA */
333 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
334
335 /* PCI Express link has been reset */
336 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
337
338 /* PCI slot has been reset */
339 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
340
341 /* Device driver may resume normal operations */
342 void (*resume)(struct pci_dev *dev);
343};
344
345/* ---------------------------------------------------------------- */
346
1da177e4
LT		 347struct module;
348struct pci_driver {
349 struct list_head node;
350 char *name;
1da177e4
LT		 351 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
352 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
353 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
354 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 355 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
356 int (*resume_early) (struct pci_dev *dev);
1da177e4 357 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 358 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 359 void (*shutdown) (struct pci_dev *dev);
1da177e4 360
392a1ce7 361 struct pci_error_handlers *err_handler;
1da177e4
LT		 362 struct device_driver driver;
363 struct pci_dynids dynids;
50b00755
AC		 364
365 int multithread_probe;
1da177e4
LT		 366};
367
368#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
369
370/**
371 * PCI_DEVICE - macro used to describe a specific pci device
372 * @vend: the 16 bit PCI Vendor ID
373 * @dev: the 16 bit PCI Device ID
374 *
375 * This macro is used to create a struct pci_device_id that matches a
376 * specific device. The subvendor and subdevice fields will be set to
377 * PCI_ANY_ID.
378 */
379#define PCI_DEVICE(vend,dev) \
380 .vendor = (vend), .device = (dev), \
381 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
382
383/**
384 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
385 * @dev_class: the class, subclass, prog-if triple for this device
386 * @dev_class_mask: the class mask for this device
387 *
388 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 389 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 390 * fields will be set to PCI_ANY_ID.
391 */
392#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
393 .class = (dev_class), .class_mask = (dev_class_mask), \
394 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
395 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
396
4352dfd5 397/*
1da177e4
LT		 398 * pci_module_init is obsolete, this stays here till we fix up all usages of it
399 * in the tree.
400 */
401#define pci_module_init pci_register_driver
402
1597cacb
AC		 403/**
404 * PCI_VDEVICE - macro used to describe a specific pci device in short form
405 * @vend: the vendor name
406 * @dev: the 16 bit PCI Device ID
407 *
408 * This macro is used to create a struct pci_device_id that matches a
409 * specific PCI device. The subvendor, and subdevice fields will be set
410 * to PCI_ANY_ID. The macro allows the next field to follow as the device
411 * private data.
412 */
413
414#define PCI_VDEVICE(vendor, device) \
415 PCI_VENDOR_ID_##vendor, (device), \
416 PCI_ANY_ID, PCI_ANY_ID, 0, 0
417
1da177e4
LT		 418/* these external functions are only available when PCI support is enabled */
419#ifdef CONFIG_PCI
420
421extern struct bus_type pci_bus_type;
422
423/* Do NOT directly access these two variables, unless you are arch specific pci
424 * code, or pci core code. */
425extern struct list_head pci_root_buses; /* list of all known PCI buses */
426extern struct list_head pci_devices; /* list of all devices */
427
428void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 429int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1da177e4
LT		 430char *pcibios_setup (char *str);
431
432/* Used only when drivers/pci/setup.c is used */
e31dd6e4
GKH		 433void pcibios_align_resource(void *, struct resource *, resource_size_t,
434 resource_size_t);
1da177e4
LT		 435void pcibios_update_irq(struct pci_dev *, int irq);
436
437/* Generic PCI functions used internally */
438
439extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 440void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 441struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
442static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
443{
c431ada4
RS		 444 struct pci_bus *root_bus;
445 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
446 if (root_bus)
447 pci_bus_add_devices(root_bus);
448 return root_bus;
1da177e4 449}
cdb9b9f7
PM		 450struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
451struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
1da177e4
LT		 452int pci_scan_slot(struct pci_bus *bus, int devfn);
453struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 454void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 455unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 456int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 457void pci_read_bridge_bases(struct pci_bus *child);
458struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
459int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
460extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
461extern void pci_dev_put(struct pci_dev *dev);
462extern void pci_remove_bus(struct pci_bus *b);
463extern void pci_remove_bus_device(struct pci_dev *dev);
24f8aa9b 464extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 465void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 466extern void pci_sort_breadthfirst(void);
1da177e4
LT		 467
468/* Generic PCI functions exported to card drivers */
469
429538ad 470struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
1da177e4
LT		 471struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
472int pci_find_capability (struct pci_dev *dev, int cap);
24a4e377 473int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
3a720d72 474int pci_find_ext_capability (struct pci_dev *dev, int cap);
687d5fe3
ME		 475int pci_find_ht_capability (struct pci_dev *dev, int ht_cap);
476int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 477struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 478
d42552c3
AM		 479struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
480 struct pci_dev *from);
481struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
482 struct pci_dev *from);
483
1da177e4
LT		 484struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
485 unsigned int ss_vendor, unsigned int ss_device,
486 struct pci_dev *from);
487struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
29f3eb64 488struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
1da177e4
LT		 489struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
490int pci_dev_present(const struct pci_device_id *ids);
d86f90f9 491const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
1da177e4
LT		 492
493int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
494int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
495int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
496int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
497int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
498int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
499
500static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
501{
502 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
503}
504static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
505{
506 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
507}
508static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
509{
510 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
511}
512static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
513{
514 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
515}
516static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
517{
518 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
519}
520static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
521{
522 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
523}
524
4a7fb636
AM		 525int __must_check pci_enable_device(struct pci_dev *dev);
526int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
9ac7849e
TH		 527int __must_check pcim_enable_device(struct pci_dev *pdev);
528void pcim_pin_device(struct pci_dev *pdev);
529
530static inline int pci_is_managed(struct pci_dev *pdev)
531{
532 return pdev->is_managed;
533}
534
1da177e4
LT		 535void pci_disable_device(struct pci_dev *dev);
536void pci_set_master(struct pci_dev *dev);
537#define HAVE_PCI_SET_MWI
4a7fb636 538int __must_check pci_set_mwi(struct pci_dev *dev);
1da177e4 539void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 540void pci_intx(struct pci_dev *dev, int enable);
f5f2b131 541void pci_msi_off(struct pci_dev *dev);
9c8550ee
LT		 542int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
543int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 544void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
4a7fb636
AM		 545int __must_check pci_assign_resource(struct pci_dev *dev, int i);
546int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
064b53db 547void pci_restore_bars(struct pci_dev *dev);
c87deff7 548int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 549
550/* ROM control related routines */
144a50ea
DJ		 551void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
552void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 553void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
554void pci_remove_rom(struct pci_dev *pdev);
555
556/* Power management related routines */
557int pci_save_state(struct pci_dev *dev);
558int pci_restore_state(struct pci_dev *dev);
9c8550ee
LT		 559int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
560pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
561int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 562
563/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
564void pci_bus_assign_resources(struct pci_bus *bus);
565void pci_bus_size_bridges(struct pci_bus *bus);
566int pci_claim_resource(struct pci_dev *, int);
567void pci_assign_unassigned_resources(void);
568void pdev_enable_device(struct pci_dev *);
569void pdev_sort_resources(struct pci_dev *, struct resource_list *);
570void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
571 int (*)(struct pci_dev *, u8, u8));
572#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 573int __must_check pci_request_regions(struct pci_dev *, const char *);
1da177e4 574void pci_release_regions(struct pci_dev *);
4a7fb636 575int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 576void pci_release_region(struct pci_dev *, int);
c87deff7
HS		 577int pci_request_selected_regions(struct pci_dev *, int, const char *);
578void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 579
580/* drivers/pci/bus.c */
4a7fb636
AM		 581int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
582 struct resource *res, resource_size_t size,
583 resource_size_t align, resource_size_t min,
584 unsigned int type_mask,
585 void (*alignf)(void *, struct resource *,
586 resource_size_t, resource_size_t),
587 void *alignf_data);
1da177e4
LT		 588void pci_enable_bridges(struct pci_bus *bus);
589
863b18f4 590/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 591int __must_check __pci_register_driver(struct pci_driver *, struct module *,
592 const char *mod_name);
4a7fb636 593static inline int __must_check pci_register_driver(struct pci_driver *driver)
863b18f4 594{
725522b5 595 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
863b18f4
L		 596}
597
1da177e4
LT		 598void pci_unregister_driver(struct pci_driver *);
599void pci_remove_behind_bridge(struct pci_dev *);
600struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 601const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
602const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 603int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
604
cecf4864
PM		 605void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
606 void *userdata);
ac7dc65a 607int pci_cfg_space_size(struct pci_dev *dev);
b82db5ce 608unsigned char pci_bus_max_busnr(struct pci_bus* bus);
cecf4864 609
1da177e4
LT		 610/* kmem_cache style wrapper around pci_alloc_consistent() */
611
612#include <linux/dmapool.h>
613
614#define pci_pool dma_pool
615#define pci_pool_create(name, pdev, size, align, allocation) \
616 dma_pool_create(name, &pdev->dev, size, align, allocation)
617#define pci_pool_destroy(pool) dma_pool_destroy(pool)
618#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
619#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
620
e24c2d96
DM		 621enum pci_dma_burst_strategy {
622 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
623 strategy_parameter is N/A */
624 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
625 byte boundaries */
626 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
627 strategy_parameter byte boundaries */
628};
629
1da177e4
LT		 630struct msix_entry {
631 u16 vector; /* kernel uses to write allocated vector */
632 u16 entry; /* driver uses to specify entry, OS writes */
633};
634
0366f8f7 635
1da177e4 636#ifndef CONFIG_PCI_MSI
1da177e4
LT		 637static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
638static inline void pci_disable_msi(struct pci_dev *dev) {}
639static inline int pci_enable_msix(struct pci_dev* dev,
640 struct msix_entry *entries, int nvec) {return -1;}
641static inline void pci_disable_msix(struct pci_dev *dev) {}
642static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
643#else
1da177e4
LT		 644extern int pci_enable_msi(struct pci_dev *dev);
645extern void pci_disable_msi(struct pci_dev *dev);
646extern int pci_enable_msix(struct pci_dev* dev,
647 struct msix_entry *entries, int nvec);
648extern void pci_disable_msix(struct pci_dev *dev);
649extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
650#endif
651
8b955b0d 652#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 653/* The functions a driver should call */
654int ht_create_irq(struct pci_dev *dev, int idx);
655void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 656#endif /* CONFIG_HT_IRQ */
657
e04b0ea2
BK		 658extern void pci_block_user_cfg_access(struct pci_dev *dev);
659extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
660
4352dfd5
GKH		 661/*
662 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
663 * a PCI domain is defined to be a set of PCI busses which share
664 * configuration space.
665 */
666#ifndef CONFIG_PCI_DOMAINS
667static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
668static inline int pci_proc_domain(struct pci_bus *bus)
669{
670 return 0;
671}
672#endif
1da177e4 673
4352dfd5 674#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 675
676/*
677 * If the system does not have PCI, clearly these return errors. Define
678 * these as simple inline functions to avoid hair in drivers.
679 */
680
1da177e4
LT		 681#define _PCI_NOP(o,s,t) \
682 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
683 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
684#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
685 _PCI_NOP(o,word,u16 x) \
686 _PCI_NOP(o,dword,u32 x)
687_PCI_NOP_ALL(read, *)
688_PCI_NOP_ALL(write,)
689
690static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
691{ return NULL; }
692
693static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
694{ return NULL; }
695
d42552c3
AM		 696static inline struct pci_dev *pci_get_device(unsigned int vendor,
697 unsigned int device, struct pci_dev *from)
698{ return NULL; }
699
700static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
701 unsigned int device, struct pci_dev *from)
1da177e4
LT		 702{ return NULL; }
703
704static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
705unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
706{ return NULL; }
707
708static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
709{ return NULL; }
710
711#define pci_dev_present(ids) (0)
d86f90f9 712#define pci_find_present(ids) (NULL)
1da177e4
LT		 713#define pci_dev_put(dev) do { } while (0)
714
715static inline void pci_set_master(struct pci_dev *dev) { }
716static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
717static inline void pci_disable_device(struct pci_dev *dev) { }
718static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4 719static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
863b18f4 720static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
1da177e4
LT		 721static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
722static inline void pci_unregister_driver(struct pci_driver *drv) { }
723static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
24a4e377 724static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
3a720d72 725static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
1da177e4
LT		 726static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
727
728/* Power management related routines */
729static inline int pci_save_state(struct pci_dev *dev) { return 0; }
730static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
731static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 732static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 733static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
734
a46e8126
KG		 735#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
736
e04b0ea2
BK		 737static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
738static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
739
4352dfd5 740#endif /* CONFIG_PCI */
1da177e4 741
4352dfd5
GKH		 742/* Include architecture-dependent settings and functions */
743
744#include <asm/pci.h>
1da177e4
LT		 745
746/* these helpers provide future and backwards compatibility
747 * for accessing popular PCI BAR info */
748#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
749#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
750#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
751#define pci_resource_len(dev,bar) \
752 ((pci_resource_start((dev),(bar)) == 0 && \
753 pci_resource_end((dev),(bar)) == \
754 pci_resource_start((dev),(bar))) ? 0 : \
755 \
756 (pci_resource_end((dev),(bar)) - \
757 pci_resource_start((dev),(bar)) + 1))
758
759/* Similar to the helpers above, these manipulate per-pci_dev
760 * driver-specific data. They are really just a wrapper around
761 * the generic device structure functions of these calls.
762 */
763static inline void *pci_get_drvdata (struct pci_dev *pdev)
764{
765 return dev_get_drvdata(&pdev->dev);
766}
767
768static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
769{
770 dev_set_drvdata(&pdev->dev, data);
771}
772
773/* If you want to know what to call your pci_dev, ask this function.
774 * Again, it's a wrapper around the generic device.
775 */
776static inline char *pci_name(struct pci_dev *pdev)
777{
778 return pdev->dev.bus_id;
779}
780
2311b1f2
ME		 781
782/* Some archs don't want to expose struct resource to userland as-is
783 * in sysfs and /proc
784 */
785#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
786static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
e31dd6e4
GKH		 787 const struct resource *rsrc, resource_size_t *start,
788 resource_size_t *end)
2311b1f2
ME		 789{
790 *start = rsrc->start;
791 *end = rsrc->end;
792}
793#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
794
795
1da177e4
LT		 796/*
797 * The world is not perfect and supplies us with broken PCI devices.
798 * For at least a part of these bugs we need a work-around, so both
799 * generic (drivers/pci/quirks.c) and per-architecture code can define
800 * fixup hooks to be called for particular buggy devices.
801 */
802
803struct pci_fixup {
804 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
805 void (*hook)(struct pci_dev *dev);
806};
807
808enum pci_fixup_pass {
809 pci_fixup_early, /* Before probing BARs */
810 pci_fixup_header, /* After reading configuration header */
811 pci_fixup_final, /* Final phase of device fixups */
812 pci_fixup_enable, /* pci_enable_device() time */
1597cacb 813 pci_fixup_resume, /* pci_enable_device() time */
1da177e4
LT		 814};
815
816/* Anonymous variables would be nice... */
817#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 818 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 819 __attribute__((__section__(#section))) = { vendor, device, hook };
820#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
821 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
822 vendor##device##hook, vendor, device, hook)
823#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
824 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
825 vendor##device##hook, vendor, device, hook)
826#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
827 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
828 vendor##device##hook, vendor, device, hook)
829#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
830 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
831 vendor##device##hook, vendor, device, hook)
1597cacb
AC		 832#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
833 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
834 resume##vendor##device##hook, vendor, device, hook)
1da177e4
LT		 835
836
837void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
838
5ea81769
AV		 839void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
840void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
841void __iomem * const * pcim_iomap_table(struct pci_dev *pdev);
842int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
843
1da177e4 844extern int pci_pci_problems;
236561e5 845#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 846#define PCIPCI_TRITON 2
847#define PCIPCI_NATOMA 4
848#define PCIPCI_VIAETBF 8
849#define PCIPCI_VSFX 16
236561e5
AC		 850#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
851#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 852
4516a618
AN		 853extern unsigned long pci_cardbus_io_size;
854extern unsigned long pci_cardbus_mem_size;
855
1da177e4
LT		 856#endif /* __KERNEL__ */
857#endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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