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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy...
[deliverable/linux.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
4352dfd5
GKH		 20/* Include the pci register defines */
21#include <linux/pci_regs.h>
1da177e4 22
1da177e4
LT		 23/*
24 * The PCI interface treats multi-function devices as independent
25 * devices. The slot/function address of each device is encoded
26 * in a single byte as follows:
27 *
28 * 7:3 = slot
29 * 2:0 = function
30 */
31#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
32#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
33#define PCI_FUNC(devfn) ((devfn) & 0x07)
34
35/* Ioctls for /proc/bus/pci/X/Y nodes. */
36#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
37#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
38#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
39#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
40#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
41
42#ifdef __KERNEL__
43
778382e0
DW		 44#include <linux/mod_devicetable.h>
45
1da177e4 46#include <linux/types.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
bae94d02 51#include <asm/atomic.h>
1da177e4
LT		 52#include <linux/device.h>
53
7e7a43c3
AB		 54/* Include the ID list */
55#include <linux/pci_ids.h>
56
1da177e4
LT		 57/* File state for mmap()s on /proc/bus/pci/X/Y */
58enum pci_mmap_state {
59 pci_mmap_io,
60 pci_mmap_mem
61};
62
63/* This defines the direction arg to the DMA mapping routines. */
64#define PCI_DMA_BIDIRECTIONAL 0
65#define PCI_DMA_TODEVICE 1
66#define PCI_DMA_FROMDEVICE 2
67#define PCI_DMA_NONE 3
68
69#define DEVICE_COUNT_COMPATIBLE 4
70#define DEVICE_COUNT_RESOURCE 12
71
72typedef int __bitwise pci_power_t;
73
4352dfd5
GKH		 74#define PCI_D0 ((pci_power_t __force) 0)
75#define PCI_D1 ((pci_power_t __force) 1)
76#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 77#define PCI_D3hot ((pci_power_t __force) 3)
78#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 79#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 80#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 81
392a1ce7 82/** The pci_channel state describes connectivity between the CPU and
83 * the pci device. If some PCI bus between here and the pci device
84 * has crashed or locked up, this info is reflected here.
85 */
86typedef unsigned int __bitwise pci_channel_state_t;
87
88enum pci_channel_state {
89 /* I/O channel is in normal state */
90 pci_channel_io_normal = (__force pci_channel_state_t) 1,
91
92 /* I/O to channel is blocked */
93 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
94
95 /* PCI card is dead */
96 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
97};
98
f7bdd12d
BK		 99typedef unsigned int __bitwise pcie_reset_state_t;
100
101enum pcie_reset_state {
102 /* Reset is NOT asserted (Use to deassert reset) */
103 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
104
105 /* Use #PERST to reset PCI-E device */
106 pcie_warm_reset = (__force pcie_reset_state_t) 2,
107
108 /* Use PCI-E Hot Reset to reset device */
109 pcie_hot_reset = (__force pcie_reset_state_t) 3
110};
111
6e325a62
MT		 112typedef unsigned short __bitwise pci_bus_flags_t;
113enum pci_bus_flags {
e778272d 114 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
6e325a62
MT		 115};
116
41017f0c
SL		 117struct pci_cap_saved_state {
118 struct hlist_node next;
119 char cap_nr;
120 u32 data[0];
121};
122
1da177e4
LT		 123/*
124 * The pci_dev structure is used to describe PCI devices.
125 */
126struct pci_dev {
127 struct list_head global_list; /* node in list of all PCI devices */
128 struct list_head bus_list; /* node in per-bus list */
129 struct pci_bus *bus; /* bus this device is on */
130 struct pci_bus *subordinate; /* bus this device bridges to */
131
132 void *sysdata; /* hook for sys-specific extension */
133 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
134
135 unsigned int devfn; /* encoded device & function index */
136 unsigned short vendor;
137 unsigned short device;
138 unsigned short subsystem_vendor;
139 unsigned short subsystem_device;
140 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
141 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
142 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 143 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 144
145 struct pci_driver *driver; /* which driver has allocated this device */
146 u64 dma_mask; /* Mask of the bits of bus address this
147 device implements. Normally this is
148 0xffffffff. You only need to change
149 this if your device has broken DMA
150 or supports 64-bit transfers. */
151
152 pci_power_t current_state; /* Current operating state. In ACPI-speak,
153 this is D0-D3, D0 being fully functional,
154 and D3 being off. */
155
392a1ce7 156 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 157 struct device dev; /* Generic device interface */
158
159 /* device is compatible with these IDs */
160 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
161 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
162
163 int cfg_size; /* Size of configuration space */
164
165 /*
166 * Instead of touching interrupt line and base address registers
167 * directly, use the values stored here. They might be different!
168 */
169 unsigned int irq;
170 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
171
172 /* These fields are used by common fixups */
173 unsigned int transparent:1; /* Transparent PCI bridge */
174 unsigned int multifunction:1;/* Part of multi-function device */
175 /* keep track of device state */
1da177e4 176 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 177 unsigned int no_msi:1; /* device may not use msi */
ffadcc2f 178 unsigned int no_d1d2:1; /* only allow d0 or d3 */
e04b0ea2 179 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
bd8481e1 180 unsigned int broken_parity_status:1; /* Device generates false positive parity */
99dc804d
SL		 181 unsigned int msi_enabled:1;
182 unsigned int msix_enabled:1;
9ac7849e 183 unsigned int is_managed:1;
bae94d02 184 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 185
1da177e4 186 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 187 struct hlist_head saved_cap_space;
1da177e4
LT		 188 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
189 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
190 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
ded86d8d 191#ifdef CONFIG_PCI_MSI
4aa9bc95 192 struct list_head msi_list;
ded86d8d 193#endif
1da177e4
LT		 194};
195
65891215
ME		 196extern struct pci_dev *alloc_pci_dev(void);
197
1da177e4
LT		 198#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
199#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
200#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
201#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
202
a7369f1f
LV		 203static inline int pci_channel_offline(struct pci_dev *pdev)
204{
205 return (pdev->error_state != pci_channel_io_normal);
206}
207
41017f0c
SL		 208static inline struct pci_cap_saved_state *pci_find_saved_cap(
209 struct pci_dev *pci_dev,char cap)
210{
211 struct pci_cap_saved_state *tmp;
212 struct hlist_node *pos;
213
214 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
215 if (tmp->cap_nr == cap)
216 return tmp;
217 }
218 return NULL;
219}
220
221static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
222 struct pci_cap_saved_state *new_cap)
223{
224 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
225}
226
1da177e4
LT		 227/*
228 * For PCI devices, the region numbers are assigned this way:
229 *
230 * 0-5 standard PCI regions
231 * 6 expansion ROM
232 * 7-10 bridges: address space assigned to buses behind the bridge
233 */
234
4352dfd5
GKH		 235#define PCI_ROM_RESOURCE 6
236#define PCI_BRIDGE_RESOURCES 7
237#define PCI_NUM_RESOURCES 11
1da177e4
LT		 238
239#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 240#define PCI_BUS_NUM_RESOURCES 8
1da177e4 241#endif
4352dfd5
GKH		 242
243#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 244
245struct pci_bus {
246 struct list_head node; /* node in list of buses */
247 struct pci_bus *parent; /* parent bus this bridge is on */
248 struct list_head children; /* list of child buses */
249 struct list_head devices; /* list of devices on this bus */
250 struct pci_dev *self; /* bridge device as seen by parent */
251 struct resource *resource[PCI_BUS_NUM_RESOURCES];
252 /* address space routed to this bus */
253
254 struct pci_ops *ops; /* configuration access functions */
255 void *sysdata; /* hook for sys-specific extension */
256 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
257
258 unsigned char number; /* bus number */
259 unsigned char primary; /* number of primary bridge */
260 unsigned char secondary; /* number of secondary bridge */
261 unsigned char subordinate; /* max number of subordinate buses */
262
263 char name[48];
264
265 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 266 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4
LT		 267 struct device *bridge;
268 struct class_device class_dev;
269 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
270 struct bin_attribute *legacy_mem; /* legacy mem */
271};
272
273#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
274#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
275
276/*
277 * Error values that may be returned by PCI functions.
278 */
279#define PCIBIOS_SUCCESSFUL 0x00
280#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
281#define PCIBIOS_BAD_VENDOR_ID 0x83
282#define PCIBIOS_DEVICE_NOT_FOUND 0x86
283#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
284#define PCIBIOS_SET_FAILED 0x88
285#define PCIBIOS_BUFFER_TOO_SMALL 0x89
286
287/* Low-level architecture-dependent routines */
288
289struct pci_ops {
290 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
291 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
292};
293
294struct pci_raw_ops {
295 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
296 int reg, int len, u32 *val);
297 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
298 int reg, int len, u32 val);
299};
300
301extern struct pci_raw_ops *raw_pci_ops;
302
303struct pci_bus_region {
304 unsigned long start;
305 unsigned long end;
306};
307
308struct pci_dynids {
309 spinlock_t lock; /* protects list, index */
310 struct list_head list; /* for IDs added at runtime */
311 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
312};
313
392a1ce7 314/* ---------------------------------------------------------------- */
315/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
316 * a set fof callbacks in struct pci_error_handlers, then that device driver
317 * will be notified of PCI bus errors, and will be driven to recovery
318 * when an error occurs.
319 */
320
321typedef unsigned int __bitwise pci_ers_result_t;
322
323enum pci_ers_result {
324 /* no result/none/not supported in device driver */
325 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
326
327 /* Device driver can recover without slot reset */
328 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
329
330 /* Device driver wants slot to be reset. */
331 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
332
333 /* Device has completely failed, is unrecoverable */
334 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
335
336 /* Device driver is fully recovered and operational */
337 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
338};
339
340/* PCI bus error event callbacks */
341struct pci_error_handlers
342{
343 /* PCI bus error detected on this device */
344 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
345 enum pci_channel_state error);
346
347 /* MMIO has been re-enabled, but not DMA */
348 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
349
350 /* PCI Express link has been reset */
351 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
352
353 /* PCI slot has been reset */
354 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
355
356 /* Device driver may resume normal operations */
357 void (*resume)(struct pci_dev *dev);
358};
359
360/* ---------------------------------------------------------------- */
361
1da177e4
LT		 362struct module;
363struct pci_driver {
364 struct list_head node;
365 char *name;
1da177e4
LT		 366 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
367 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
368 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
369 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 370 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
371 int (*resume_early) (struct pci_dev *dev);
1da177e4 372 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 373 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 374 void (*shutdown) (struct pci_dev *dev);
1da177e4 375
392a1ce7 376 struct pci_error_handlers *err_handler;
1da177e4
LT		 377 struct device_driver driver;
378 struct pci_dynids dynids;
379};
380
381#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
382
383/**
384 * PCI_DEVICE - macro used to describe a specific pci device
385 * @vend: the 16 bit PCI Vendor ID
386 * @dev: the 16 bit PCI Device ID
387 *
388 * This macro is used to create a struct pci_device_id that matches a
389 * specific device. The subvendor and subdevice fields will be set to
390 * PCI_ANY_ID.
391 */
392#define PCI_DEVICE(vend,dev) \
393 .vendor = (vend), .device = (dev), \
394 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
395
396/**
397 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
398 * @dev_class: the class, subclass, prog-if triple for this device
399 * @dev_class_mask: the class mask for this device
400 *
401 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 402 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 403 * fields will be set to PCI_ANY_ID.
404 */
405#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
406 .class = (dev_class), .class_mask = (dev_class_mask), \
407 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
408 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
409
1597cacb
AC		 410/**
411 * PCI_VDEVICE - macro used to describe a specific pci device in short form
412 * @vend: the vendor name
413 * @dev: the 16 bit PCI Device ID
414 *
415 * This macro is used to create a struct pci_device_id that matches a
416 * specific PCI device. The subvendor, and subdevice fields will be set
417 * to PCI_ANY_ID. The macro allows the next field to follow as the device
418 * private data.
419 */
420
421#define PCI_VDEVICE(vendor, device) \
422 PCI_VENDOR_ID_##vendor, (device), \
423 PCI_ANY_ID, PCI_ANY_ID, 0, 0
424
1da177e4
LT		 425/* these external functions are only available when PCI support is enabled */
426#ifdef CONFIG_PCI
427
428extern struct bus_type pci_bus_type;
429
430/* Do NOT directly access these two variables, unless you are arch specific pci
431 * code, or pci core code. */
432extern struct list_head pci_root_buses; /* list of all known PCI buses */
433extern struct list_head pci_devices; /* list of all devices */
434
435void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 436int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1da177e4
LT		 437char *pcibios_setup (char *str);
438
439/* Used only when drivers/pci/setup.c is used */
e31dd6e4
GKH		 440void pcibios_align_resource(void *, struct resource *, resource_size_t,
441 resource_size_t);
1da177e4
LT		 442void pcibios_update_irq(struct pci_dev *, int irq);
443
444/* Generic PCI functions used internally */
445
446extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 447void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 448struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
449static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
450{
c431ada4
RS		 451 struct pci_bus *root_bus;
452 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
453 if (root_bus)
454 pci_bus_add_devices(root_bus);
455 return root_bus;
1da177e4 456}
cdb9b9f7
PM		 457struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
458struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
1da177e4
LT		 459int pci_scan_slot(struct pci_bus *bus, int devfn);
460struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 461void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 462unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 463int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 464void pci_read_bridge_bases(struct pci_bus *child);
465struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
466int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
467extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
468extern void pci_dev_put(struct pci_dev *dev);
469extern void pci_remove_bus(struct pci_bus *b);
470extern void pci_remove_bus_device(struct pci_dev *dev);
24f8aa9b 471extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 472void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 473extern void pci_sort_breadthfirst(void);
1da177e4
LT		 474
475/* Generic PCI functions exported to card drivers */
476
429538ad 477struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
1da177e4
LT		 478struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
479int pci_find_capability (struct pci_dev *dev, int cap);
24a4e377 480int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
3a720d72 481int pci_find_ext_capability (struct pci_dev *dev, int cap);
687d5fe3
ME		 482int pci_find_ht_capability (struct pci_dev *dev, int ht_cap);
483int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 484struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 485
d42552c3
AM		 486struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
487 struct pci_dev *from);
488struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
489 struct pci_dev *from);
490
1da177e4
LT		 491struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
492 unsigned int ss_vendor, unsigned int ss_device,
493 struct pci_dev *from);
494struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
29f3eb64 495struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
1da177e4
LT		 496struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
497int pci_dev_present(const struct pci_device_id *ids);
d86f90f9 498const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
1da177e4
LT		 499
500int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
501int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
502int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
503int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
504int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
505int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
506
507static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
508{
509 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
510}
511static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
512{
513 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
514}
515static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
516{
517 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
518}
519static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
520{
521 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
522}
523static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
524{
525 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
526}
527static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
528{
529 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
530}
531
4a7fb636
AM		 532int __must_check pci_enable_device(struct pci_dev *dev);
533int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
9ac7849e
TH		 534int __must_check pcim_enable_device(struct pci_dev *pdev);
535void pcim_pin_device(struct pci_dev *pdev);
536
537static inline int pci_is_managed(struct pci_dev *pdev)
538{
539 return pdev->is_managed;
540}
541
1da177e4
LT		 542void pci_disable_device(struct pci_dev *dev);
543void pci_set_master(struct pci_dev *dev);
f7bdd12d 544int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1da177e4 545#define HAVE_PCI_SET_MWI
4a7fb636 546int __must_check pci_set_mwi(struct pci_dev *dev);
1da177e4 547void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 548void pci_intx(struct pci_dev *dev, int enable);
f5f2b131 549void pci_msi_off(struct pci_dev *dev);
9c8550ee
LT		 550int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
551int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 552void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
4a7fb636
AM		 553int __must_check pci_assign_resource(struct pci_dev *dev, int i);
554int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
064b53db 555void pci_restore_bars(struct pci_dev *dev);
c87deff7 556int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 557
558/* ROM control related routines */
144a50ea
DJ		 559void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
560void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 561void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
562void pci_remove_rom(struct pci_dev *pdev);
563
564/* Power management related routines */
565int pci_save_state(struct pci_dev *dev);
566int pci_restore_state(struct pci_dev *dev);
9c8550ee
LT		 567int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
568pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
569int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 570
571/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
572void pci_bus_assign_resources(struct pci_bus *bus);
573void pci_bus_size_bridges(struct pci_bus *bus);
574int pci_claim_resource(struct pci_dev *, int);
575void pci_assign_unassigned_resources(void);
576void pdev_enable_device(struct pci_dev *);
577void pdev_sort_resources(struct pci_dev *, struct resource_list *);
578void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
579 int (*)(struct pci_dev *, u8, u8));
580#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 581int __must_check pci_request_regions(struct pci_dev *, const char *);
1da177e4 582void pci_release_regions(struct pci_dev *);
4a7fb636 583int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 584void pci_release_region(struct pci_dev *, int);
c87deff7
HS		 585int pci_request_selected_regions(struct pci_dev *, int, const char *);
586void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 587
588/* drivers/pci/bus.c */
4a7fb636
AM		 589int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
590 struct resource *res, resource_size_t size,
591 resource_size_t align, resource_size_t min,
592 unsigned int type_mask,
593 void (*alignf)(void *, struct resource *,
594 resource_size_t, resource_size_t),
595 void *alignf_data);
1da177e4
LT		 596void pci_enable_bridges(struct pci_bus *bus);
597
863b18f4 598/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 599int __must_check __pci_register_driver(struct pci_driver *, struct module *,
600 const char *mod_name);
4a7fb636 601static inline int __must_check pci_register_driver(struct pci_driver *driver)
863b18f4 602{
725522b5 603 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
863b18f4
L		 604}
605
1da177e4
LT		 606void pci_unregister_driver(struct pci_driver *);
607void pci_remove_behind_bridge(struct pci_dev *);
608struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 609const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
610const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 611int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
612
cecf4864
PM		 613void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
614 void *userdata);
ac7dc65a 615int pci_cfg_space_size(struct pci_dev *dev);
b82db5ce 616unsigned char pci_bus_max_busnr(struct pci_bus* bus);
cecf4864 617
1da177e4
LT		 618/* kmem_cache style wrapper around pci_alloc_consistent() */
619
620#include <linux/dmapool.h>
621
622#define pci_pool dma_pool
623#define pci_pool_create(name, pdev, size, align, allocation) \
624 dma_pool_create(name, &pdev->dev, size, align, allocation)
625#define pci_pool_destroy(pool) dma_pool_destroy(pool)
626#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
627#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
628
e24c2d96
DM		 629enum pci_dma_burst_strategy {
630 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
631 strategy_parameter is N/A */
632 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
633 byte boundaries */
634 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
635 strategy_parameter byte boundaries */
636};
637
1da177e4
LT		 638struct msix_entry {
639 u16 vector; /* kernel uses to write allocated vector */
640 u16 entry; /* driver uses to specify entry, OS writes */
641};
642
0366f8f7 643
1da177e4 644#ifndef CONFIG_PCI_MSI
1da177e4
LT		 645static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
646static inline void pci_disable_msi(struct pci_dev *dev) {}
647static inline int pci_enable_msix(struct pci_dev* dev,
648 struct msix_entry *entries, int nvec) {return -1;}
649static inline void pci_disable_msix(struct pci_dev *dev) {}
650static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
651#else
1da177e4
LT		 652extern int pci_enable_msi(struct pci_dev *dev);
653extern void pci_disable_msi(struct pci_dev *dev);
654extern int pci_enable_msix(struct pci_dev* dev,
655 struct msix_entry *entries, int nvec);
656extern void pci_disable_msix(struct pci_dev *dev);
657extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
658#endif
659
8b955b0d 660#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 661/* The functions a driver should call */
662int ht_create_irq(struct pci_dev *dev, int idx);
663void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 664#endif /* CONFIG_HT_IRQ */
665
e04b0ea2
BK		 666extern void pci_block_user_cfg_access(struct pci_dev *dev);
667extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
668
4352dfd5
GKH		 669/*
670 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
671 * a PCI domain is defined to be a set of PCI busses which share
672 * configuration space.
673 */
674#ifndef CONFIG_PCI_DOMAINS
675static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
676static inline int pci_proc_domain(struct pci_bus *bus)
677{
678 return 0;
679}
680#endif
1da177e4 681
4352dfd5 682#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 683
684/*
685 * If the system does not have PCI, clearly these return errors. Define
686 * these as simple inline functions to avoid hair in drivers.
687 */
688
1da177e4
LT		 689#define _PCI_NOP(o,s,t) \
690 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
691 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
692#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
693 _PCI_NOP(o,word,u16 x) \
694 _PCI_NOP(o,dword,u32 x)
695_PCI_NOP_ALL(read, *)
696_PCI_NOP_ALL(write,)
697
698static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
699{ return NULL; }
700
701static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
702{ return NULL; }
703
d42552c3
AM		 704static inline struct pci_dev *pci_get_device(unsigned int vendor,
705 unsigned int device, struct pci_dev *from)
706{ return NULL; }
707
708static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
709 unsigned int device, struct pci_dev *from)
1da177e4
LT		 710{ return NULL; }
711
712static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
713unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
714{ return NULL; }
715
716static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
717{ return NULL; }
718
719#define pci_dev_present(ids) (0)
d86f90f9 720#define pci_find_present(ids) (NULL)
1da177e4
LT		 721#define pci_dev_put(dev) do { } while (0)
722
723static inline void pci_set_master(struct pci_dev *dev) { }
724static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
725static inline void pci_disable_device(struct pci_dev *dev) { }
726static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4 727static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
863b18f4 728static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
1da177e4
LT		 729static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
730static inline void pci_unregister_driver(struct pci_driver *drv) { }
731static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
24a4e377 732static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
3a720d72 733static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
1da177e4
LT		 734static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
735
736/* Power management related routines */
737static inline int pci_save_state(struct pci_dev *dev) { return 0; }
738static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
739static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 740static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 741static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
742
0da0ead9
SS		 743static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) { return -EIO; }
744static inline void pci_release_regions(struct pci_dev *dev) { }
745
a46e8126
KG		 746#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
747
e04b0ea2
BK		 748static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
749static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
750
4352dfd5 751#endif /* CONFIG_PCI */
1da177e4 752
4352dfd5
GKH		 753/* Include architecture-dependent settings and functions */
754
755#include <asm/pci.h>
1da177e4
LT		 756
757/* these helpers provide future and backwards compatibility
758 * for accessing popular PCI BAR info */
759#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
760#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
761#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
762#define pci_resource_len(dev,bar) \
763 ((pci_resource_start((dev),(bar)) == 0 && \
764 pci_resource_end((dev),(bar)) == \
765 pci_resource_start((dev),(bar))) ? 0 : \
766 \
767 (pci_resource_end((dev),(bar)) - \
768 pci_resource_start((dev),(bar)) + 1))
769
770/* Similar to the helpers above, these manipulate per-pci_dev
771 * driver-specific data. They are really just a wrapper around
772 * the generic device structure functions of these calls.
773 */
774static inline void *pci_get_drvdata (struct pci_dev *pdev)
775{
776 return dev_get_drvdata(&pdev->dev);
777}
778
779static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
780{
781 dev_set_drvdata(&pdev->dev, data);
782}
783
784/* If you want to know what to call your pci_dev, ask this function.
785 * Again, it's a wrapper around the generic device.
786 */
787static inline char *pci_name(struct pci_dev *pdev)
788{
789 return pdev->dev.bus_id;
790}
791
2311b1f2
ME		 792
793/* Some archs don't want to expose struct resource to userland as-is
794 * in sysfs and /proc
795 */
796#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
797static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
e31dd6e4
GKH		 798 const struct resource *rsrc, resource_size_t *start,
799 resource_size_t *end)
2311b1f2
ME		 800{
801 *start = rsrc->start;
802 *end = rsrc->end;
803}
804#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
805
806
1da177e4
LT		 807/*
808 * The world is not perfect and supplies us with broken PCI devices.
809 * For at least a part of these bugs we need a work-around, so both
810 * generic (drivers/pci/quirks.c) and per-architecture code can define
811 * fixup hooks to be called for particular buggy devices.
812 */
813
814struct pci_fixup {
815 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
816 void (*hook)(struct pci_dev *dev);
817};
818
819enum pci_fixup_pass {
820 pci_fixup_early, /* Before probing BARs */
821 pci_fixup_header, /* After reading configuration header */
822 pci_fixup_final, /* Final phase of device fixups */
823 pci_fixup_enable, /* pci_enable_device() time */
1597cacb 824 pci_fixup_resume, /* pci_enable_device() time */
1da177e4
LT		 825};
826
827/* Anonymous variables would be nice... */
828#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 829 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 830 __attribute__((__section__(#section))) = { vendor, device, hook };
831#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
832 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
833 vendor##device##hook, vendor, device, hook)
834#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
836 vendor##device##hook, vendor, device, hook)
837#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
838 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
839 vendor##device##hook, vendor, device, hook)
840#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
841 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
842 vendor##device##hook, vendor, device, hook)
1597cacb
AC		 843#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
844 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
845 resume##vendor##device##hook, vendor, device, hook)
1da177e4
LT		 846
847
848void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
849
5ea81769
AV		 850void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
851void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
852void __iomem * const * pcim_iomap_table(struct pci_dev *pdev);
853int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
ec04b075 854void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
5ea81769 855
1da177e4 856extern int pci_pci_problems;
236561e5 857#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 858#define PCIPCI_TRITON 2
859#define PCIPCI_NATOMA 4
860#define PCIPCI_VIAETBF 8
861#define PCIPCI_VSFX 16
236561e5
AC		 862#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
863#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 864
4516a618
AN		 865extern unsigned long pci_cardbus_io_size;
866extern unsigned long pci_cardbus_mem_size;
867
1da177e4
LT		 868#endif /* __KERNEL__ */
869#endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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