Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
f46753c5 | 20 | #include <linux/pci_regs.h> /* The pci register defines */ |
1da177e4 | 21 | |
1da177e4 LT |
22 | /* |
23 | * The PCI interface treats multi-function devices as independent | |
24 | * devices. The slot/function address of each device is encoded | |
25 | * in a single byte as follows: | |
26 | * | |
27 | * 7:3 = slot | |
28 | * 2:0 = function | |
29 | */ | |
05cca6e5 | 30 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
31 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
32 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
33 | ||
34 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
35 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
36 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
37 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
38 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
39 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
40 | ||
41 | #ifdef __KERNEL__ | |
42 | ||
778382e0 DW |
43 | #include <linux/mod_devicetable.h> |
44 | ||
1da177e4 | 45 | #include <linux/types.h> |
98db6f19 | 46 | #include <linux/init.h> |
1da177e4 LT |
47 | #include <linux/ioport.h> |
48 | #include <linux/list.h> | |
4a7fb636 | 49 | #include <linux/compiler.h> |
1da177e4 | 50 | #include <linux/errno.h> |
f46753c5 | 51 | #include <linux/kobject.h> |
bae94d02 | 52 | #include <asm/atomic.h> |
1da177e4 | 53 | #include <linux/device.h> |
1388cc96 | 54 | #include <linux/io.h> |
1da177e4 | 55 | |
7e7a43c3 AB |
56 | /* Include the ID list */ |
57 | #include <linux/pci_ids.h> | |
58 | ||
f46753c5 AC |
59 | /* pci_slot represents a physical slot */ |
60 | struct pci_slot { | |
61 | struct pci_bus *bus; /* The bus this slot is on */ | |
62 | struct list_head list; /* node in list of slots on this bus */ | |
63 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
64 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
65 | struct kobject kobj; | |
66 | }; | |
67 | ||
0ad772ec AC |
68 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
69 | { | |
70 | return kobject_name(&slot->kobj); | |
71 | } | |
72 | ||
1da177e4 LT |
73 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
74 | enum pci_mmap_state { | |
75 | pci_mmap_io, | |
76 | pci_mmap_mem | |
77 | }; | |
78 | ||
79 | /* This defines the direction arg to the DMA mapping routines. */ | |
80 | #define PCI_DMA_BIDIRECTIONAL 0 | |
81 | #define PCI_DMA_TODEVICE 1 | |
82 | #define PCI_DMA_FROMDEVICE 2 | |
83 | #define PCI_DMA_NONE 3 | |
84 | ||
fde09c6d YZ |
85 | /* |
86 | * For PCI devices, the region numbers are assigned this way: | |
87 | */ | |
88 | enum { | |
89 | /* #0-5: standard PCI resources */ | |
90 | PCI_STD_RESOURCES, | |
91 | PCI_STD_RESOURCE_END = 5, | |
92 | ||
93 | /* #6: expansion ROM resource */ | |
94 | PCI_ROM_RESOURCE, | |
95 | ||
96 | /* resources assigned to buses behind the bridge */ | |
97 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
98 | ||
99 | PCI_BRIDGE_RESOURCES, | |
100 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
101 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
102 | ||
103 | /* total resources associated with a PCI device */ | |
104 | PCI_NUM_RESOURCES, | |
105 | ||
106 | /* preserve this for compatibility */ | |
107 | DEVICE_COUNT_RESOURCE | |
108 | }; | |
1da177e4 LT |
109 | |
110 | typedef int __bitwise pci_power_t; | |
111 | ||
4352dfd5 GKH |
112 | #define PCI_D0 ((pci_power_t __force) 0) |
113 | #define PCI_D1 ((pci_power_t __force) 1) | |
114 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
115 | #define PCI_D3hot ((pci_power_t __force) 3) |
116 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 117 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 118 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 119 | |
392a1ce7 | 120 | /** The pci_channel state describes connectivity between the CPU and |
121 | * the pci device. If some PCI bus between here and the pci device | |
122 | * has crashed or locked up, this info is reflected here. | |
123 | */ | |
124 | typedef unsigned int __bitwise pci_channel_state_t; | |
125 | ||
126 | enum pci_channel_state { | |
127 | /* I/O channel is in normal state */ | |
128 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
129 | ||
130 | /* I/O to channel is blocked */ | |
131 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
132 | ||
133 | /* PCI card is dead */ | |
134 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
135 | }; | |
136 | ||
f7bdd12d BK |
137 | typedef unsigned int __bitwise pcie_reset_state_t; |
138 | ||
139 | enum pcie_reset_state { | |
140 | /* Reset is NOT asserted (Use to deassert reset) */ | |
141 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
142 | ||
143 | /* Use #PERST to reset PCI-E device */ | |
144 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
145 | ||
146 | /* Use PCI-E Hot Reset to reset device */ | |
147 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
148 | }; | |
149 | ||
ba698ad4 DM |
150 | typedef unsigned short __bitwise pci_dev_flags_t; |
151 | enum pci_dev_flags { | |
152 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
153 | * generation too. | |
154 | */ | |
155 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
979b1791 AC |
156 | /* Device configuration is irrevocably lost if disabled into D3 */ |
157 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, | |
ba698ad4 DM |
158 | }; |
159 | ||
e1d3a908 SA |
160 | enum pci_irq_reroute_variant { |
161 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
162 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
163 | }; | |
164 | ||
6e325a62 MT |
165 | typedef unsigned short __bitwise pci_bus_flags_t; |
166 | enum pci_bus_flags { | |
d556ad4b PO |
167 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
168 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
169 | }; |
170 | ||
41017f0c SL |
171 | struct pci_cap_saved_state { |
172 | struct hlist_node next; | |
173 | char cap_nr; | |
174 | u32 data[0]; | |
175 | }; | |
176 | ||
7d715a6c | 177 | struct pcie_link_state; |
ee69439c JB |
178 | struct pci_vpd; |
179 | ||
1da177e4 LT |
180 | /* |
181 | * The pci_dev structure is used to describe PCI devices. | |
182 | */ | |
183 | struct pci_dev { | |
1da177e4 LT |
184 | struct list_head bus_list; /* node in per-bus list */ |
185 | struct pci_bus *bus; /* bus this device is on */ | |
186 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
187 | ||
188 | void *sysdata; /* hook for sys-specific extension */ | |
189 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 190 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
191 | |
192 | unsigned int devfn; /* encoded device & function index */ | |
193 | unsigned short vendor; | |
194 | unsigned short device; | |
195 | unsigned short subsystem_vendor; | |
196 | unsigned short subsystem_device; | |
197 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 198 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 199 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
994a65e2 | 200 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 201 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 202 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
203 | |
204 | struct pci_driver *driver; /* which driver has allocated this device */ | |
205 | u64 dma_mask; /* Mask of the bits of bus address this | |
206 | device implements. Normally this is | |
207 | 0xffffffff. You only need to change | |
208 | this if your device has broken DMA | |
209 | or supports 64-bit transfers. */ | |
210 | ||
4d57cdfa FT |
211 | struct device_dma_parameters dma_parms; |
212 | ||
1da177e4 LT |
213 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
214 | this is D0-D3, D0 being fully functional, | |
215 | and D3 being off. */ | |
337001b6 RW |
216 | int pm_cap; /* PM capability offset in the |
217 | configuration space */ | |
218 | unsigned int pme_support:5; /* Bitmask of states from which PME# | |
219 | can be generated */ | |
220 | unsigned int d1_support:1; /* Low power state D1 is supported */ | |
221 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
222 | unsigned int no_d1d2:1; /* Only allow D0 and D3 */ | |
1da177e4 | 223 | |
7d715a6c SL |
224 | #ifdef CONFIG_PCIEASPM |
225 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
226 | #endif | |
227 | ||
392a1ce7 | 228 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
229 | struct device dev; /* Generic device interface */ |
230 | ||
1da177e4 LT |
231 | int cfg_size; /* Size of configuration space */ |
232 | ||
233 | /* | |
234 | * Instead of touching interrupt line and base address registers | |
235 | * directly, use the values stored here. They might be different! | |
236 | */ | |
237 | unsigned int irq; | |
238 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
239 | ||
240 | /* These fields are used by common fixups */ | |
241 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
242 | unsigned int multifunction:1;/* Part of multi-function device */ | |
243 | /* keep track of device state */ | |
8a1bc901 | 244 | unsigned int is_added:1; |
1da177e4 | 245 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 246 | unsigned int no_msi:1; /* device may not use msi */ |
e04b0ea2 | 247 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 248 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 249 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
99dc804d SL |
250 | unsigned int msi_enabled:1; |
251 | unsigned int msix_enabled:1; | |
58c3a727 | 252 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 253 | unsigned int is_managed:1; |
994a65e2 | 254 | unsigned int is_pcie:1; |
ba698ad4 | 255 | pci_dev_flags_t dev_flags; |
bae94d02 | 256 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 257 | |
1da177e4 | 258 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 259 | struct hlist_head saved_cap_space; |
1da177e4 LT |
260 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
261 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
262 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 263 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 264 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 265 | struct list_head msi_list; |
ded86d8d | 266 | #endif |
94e61088 | 267 | struct pci_vpd *vpd; |
1da177e4 LT |
268 | }; |
269 | ||
65891215 ME |
270 | extern struct pci_dev *alloc_pci_dev(void); |
271 | ||
1da177e4 LT |
272 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
273 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
274 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
275 | ||
a7369f1f LV |
276 | static inline int pci_channel_offline(struct pci_dev *pdev) |
277 | { | |
278 | return (pdev->error_state != pci_channel_io_normal); | |
279 | } | |
280 | ||
41017f0c | 281 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 282 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
283 | { |
284 | struct pci_cap_saved_state *tmp; | |
285 | struct hlist_node *pos; | |
286 | ||
287 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
288 | if (tmp->cap_nr == cap) | |
289 | return tmp; | |
290 | } | |
291 | return NULL; | |
292 | } | |
293 | ||
294 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
295 | struct pci_cap_saved_state *new_cap) | |
296 | { | |
297 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
298 | } | |
299 | ||
1da177e4 | 300 | #ifndef PCI_BUS_NUM_RESOURCES |
30a18d6c | 301 | #define PCI_BUS_NUM_RESOURCES 16 |
1da177e4 | 302 | #endif |
4352dfd5 GKH |
303 | |
304 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
305 | |
306 | struct pci_bus { | |
307 | struct list_head node; /* node in list of buses */ | |
308 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
309 | struct list_head children; /* list of child buses */ | |
310 | struct list_head devices; /* list of devices on this bus */ | |
311 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 312 | struct list_head slots; /* list of slots on this bus */ |
1da177e4 LT |
313 | struct resource *resource[PCI_BUS_NUM_RESOURCES]; |
314 | /* address space routed to this bus */ | |
315 | ||
316 | struct pci_ops *ops; /* configuration access functions */ | |
317 | void *sysdata; /* hook for sys-specific extension */ | |
318 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
319 | ||
320 | unsigned char number; /* bus number */ | |
321 | unsigned char primary; /* number of primary bridge */ | |
322 | unsigned char secondary; /* number of secondary bridge */ | |
323 | unsigned char subordinate; /* max number of subordinate buses */ | |
324 | ||
325 | char name[48]; | |
326 | ||
327 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 328 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 329 | struct device *bridge; |
fd7d1ced | 330 | struct device dev; |
1da177e4 LT |
331 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
332 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 333 | unsigned int is_added:1; |
1da177e4 LT |
334 | }; |
335 | ||
336 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 337 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 LT |
338 | |
339 | /* | |
340 | * Error values that may be returned by PCI functions. | |
341 | */ | |
342 | #define PCIBIOS_SUCCESSFUL 0x00 | |
343 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
344 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
345 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
346 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
347 | #define PCIBIOS_SET_FAILED 0x88 | |
348 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
349 | ||
350 | /* Low-level architecture-dependent routines */ | |
351 | ||
352 | struct pci_ops { | |
353 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
354 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
355 | }; | |
356 | ||
b6ce068a MW |
357 | /* |
358 | * ACPI needs to be able to access PCI config space before we've done a | |
359 | * PCI bus scan and created pci_bus structures. | |
360 | */ | |
361 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
362 | unsigned int devfn, int reg, int len, u32 *val); | |
363 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
364 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
365 | |
366 | struct pci_bus_region { | |
c40a22e0 BH |
367 | resource_size_t start; |
368 | resource_size_t end; | |
1da177e4 LT |
369 | }; |
370 | ||
371 | struct pci_dynids { | |
372 | spinlock_t lock; /* protects list, index */ | |
373 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
374 | }; |
375 | ||
392a1ce7 | 376 | /* ---------------------------------------------------------------- */ |
377 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 378 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 | 379 | * will be notified of PCI bus errors, and will be driven to recovery |
380 | * when an error occurs. | |
381 | */ | |
382 | ||
383 | typedef unsigned int __bitwise pci_ers_result_t; | |
384 | ||
385 | enum pci_ers_result { | |
386 | /* no result/none/not supported in device driver */ | |
387 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
388 | ||
389 | /* Device driver can recover without slot reset */ | |
390 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
391 | ||
392 | /* Device driver wants slot to be reset. */ | |
393 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
394 | ||
395 | /* Device has completely failed, is unrecoverable */ | |
396 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
397 | ||
398 | /* Device driver is fully recovered and operational */ | |
399 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
400 | }; | |
401 | ||
402 | /* PCI bus error event callbacks */ | |
05cca6e5 | 403 | struct pci_error_handlers { |
392a1ce7 | 404 | /* PCI bus error detected on this device */ |
405 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 406 | enum pci_channel_state error); |
392a1ce7 | 407 | |
408 | /* MMIO has been re-enabled, but not DMA */ | |
409 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
410 | ||
411 | /* PCI Express link has been reset */ | |
412 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
413 | ||
414 | /* PCI slot has been reset */ | |
415 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
416 | ||
417 | /* Device driver may resume normal operations */ | |
418 | void (*resume)(struct pci_dev *dev); | |
419 | }; | |
420 | ||
421 | /* ---------------------------------------------------------------- */ | |
422 | ||
1da177e4 LT |
423 | struct module; |
424 | struct pci_driver { | |
425 | struct list_head node; | |
426 | char *name; | |
1da177e4 LT |
427 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
428 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
429 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
430 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
431 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
432 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 433 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 434 | void (*shutdown) (struct pci_dev *dev); |
392a1ce7 | 435 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
436 | struct device_driver driver; |
437 | struct pci_dynids dynids; | |
438 | }; | |
439 | ||
05cca6e5 | 440 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 441 | |
90a1ba0c | 442 | /** |
9f9351bb | 443 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
444 | * @_table: device table name |
445 | * | |
446 | * This macro is used to create a struct pci_device_id array (a device table) | |
447 | * in a generic manner. | |
448 | */ | |
9f9351bb | 449 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
450 | const struct pci_device_id _table[] __devinitconst |
451 | ||
1da177e4 LT |
452 | /** |
453 | * PCI_DEVICE - macro used to describe a specific pci device | |
454 | * @vend: the 16 bit PCI Vendor ID | |
455 | * @dev: the 16 bit PCI Device ID | |
456 | * | |
457 | * This macro is used to create a struct pci_device_id that matches a | |
458 | * specific device. The subvendor and subdevice fields will be set to | |
459 | * PCI_ANY_ID. | |
460 | */ | |
461 | #define PCI_DEVICE(vend,dev) \ | |
462 | .vendor = (vend), .device = (dev), \ | |
463 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
464 | ||
465 | /** | |
466 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
467 | * @dev_class: the class, subclass, prog-if triple for this device | |
468 | * @dev_class_mask: the class mask for this device | |
469 | * | |
470 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 471 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
472 | * fields will be set to PCI_ANY_ID. |
473 | */ | |
474 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
475 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
476 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
477 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
478 | ||
1597cacb AC |
479 | /** |
480 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c322b28a ZY |
481 | * @vendor: the vendor name |
482 | * @device: the 16 bit PCI Device ID | |
1597cacb AC |
483 | * |
484 | * This macro is used to create a struct pci_device_id that matches a | |
485 | * specific PCI device. The subvendor, and subdevice fields will be set | |
486 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
487 | * private data. | |
488 | */ | |
489 | ||
490 | #define PCI_VDEVICE(vendor, device) \ | |
491 | PCI_VENDOR_ID_##vendor, (device), \ | |
492 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
493 | ||
1da177e4 LT |
494 | /* these external functions are only available when PCI support is enabled */ |
495 | #ifdef CONFIG_PCI | |
496 | ||
497 | extern struct bus_type pci_bus_type; | |
498 | ||
499 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
500 | * code, or pci core code. */ | |
501 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
502 | /* Some device drivers need know if pci is initiated */ |
503 | extern int no_pci_devices(void); | |
1da177e4 LT |
504 | |
505 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 506 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 507 | char *pcibios_setup(char *str); |
1da177e4 LT |
508 | |
509 | /* Used only when drivers/pci/setup.c is used */ | |
e31dd6e4 GKH |
510 | void pcibios_align_resource(void *, struct resource *, resource_size_t, |
511 | resource_size_t); | |
1da177e4 LT |
512 | void pcibios_update_irq(struct pci_dev *, int irq); |
513 | ||
514 | /* Generic PCI functions used internally */ | |
515 | ||
516 | extern struct pci_bus *pci_find_bus(int domain, int busnr); | |
c431ada4 | 517 | void pci_bus_add_devices(struct pci_bus *bus); |
05cca6e5 GKH |
518 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
519 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 520 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 521 | void *sysdata) |
1da177e4 | 522 | { |
c431ada4 RS |
523 | struct pci_bus *root_bus; |
524 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
525 | if (root_bus) | |
526 | pci_bus_add_devices(root_bus); | |
527 | return root_bus; | |
1da177e4 | 528 | } |
05cca6e5 GKH |
529 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
530 | struct pci_ops *ops, void *sysdata); | |
531 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
532 | int busnr); | |
f46753c5 | 533 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
534 | const char *name, |
535 | struct hotplug_slot *hotplug); | |
f46753c5 | 536 | void pci_destroy_slot(struct pci_slot *slot); |
d25b7c8d | 537 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
1da177e4 | 538 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 539 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 540 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 541 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 542 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 543 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
544 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
545 | struct resource *res); | |
57c2cf71 | 546 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
1da177e4 | 547 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 548 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
1da177e4 LT |
549 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); |
550 | extern void pci_dev_put(struct pci_dev *dev); | |
551 | extern void pci_remove_bus(struct pci_bus *b); | |
552 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 553 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 554 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 555 | extern void pci_sort_breadthfirst(void); |
1da177e4 LT |
556 | |
557 | /* Generic PCI functions exported to card drivers */ | |
558 | ||
bd3989e0 | 559 | #ifdef CONFIG_PCI_LEGACY |
05cca6e5 GKH |
560 | struct pci_dev __deprecated *pci_find_device(unsigned int vendor, |
561 | unsigned int device, | |
b08508c4 | 562 | struct pci_dev *from); |
05cca6e5 GKH |
563 | struct pci_dev __deprecated *pci_find_slot(unsigned int bus, |
564 | unsigned int devfn); | |
bd3989e0 JG |
565 | #endif /* CONFIG_PCI_LEGACY */ |
566 | ||
388c8c16 JB |
567 | enum pci_lost_interrupt_reason { |
568 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
569 | PCI_LOST_IRQ_DISABLE_MSI, | |
570 | PCI_LOST_IRQ_DISABLE_MSIX, | |
571 | PCI_LOST_IRQ_DISABLE_ACPI, | |
572 | }; | |
573 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
574 | int pci_find_capability(struct pci_dev *dev, int cap); |
575 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
576 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
577 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
578 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 579 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 580 | |
d42552c3 AM |
581 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
582 | struct pci_dev *from); | |
05cca6e5 | 583 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 584 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 585 | struct pci_dev *from); |
05cca6e5 GKH |
586 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
587 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); | |
588 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); | |
1da177e4 LT |
589 | int pci_dev_present(const struct pci_device_id *ids); |
590 | ||
05cca6e5 GKH |
591 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
592 | int where, u8 *val); | |
593 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
594 | int where, u16 *val); | |
595 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
596 | int where, u32 *val); | |
597 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
598 | int where, u8 val); | |
599 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
600 | int where, u16 val); | |
601 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
602 | int where, u32 val); | |
1da177e4 LT |
603 | |
604 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
605 | { | |
05cca6e5 | 606 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
607 | } |
608 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
609 | { | |
05cca6e5 | 610 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 611 | } |
05cca6e5 GKH |
612 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
613 | u32 *val) | |
1da177e4 | 614 | { |
05cca6e5 | 615 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
616 | } |
617 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
618 | { | |
05cca6e5 | 619 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
620 | } |
621 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
622 | { | |
05cca6e5 | 623 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 624 | } |
05cca6e5 GKH |
625 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
626 | u32 val) | |
1da177e4 | 627 | { |
05cca6e5 | 628 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
629 | } |
630 | ||
4a7fb636 | 631 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
632 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
633 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 634 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
635 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
636 | void pcim_pin_device(struct pci_dev *pdev); | |
637 | ||
638 | static inline int pci_is_managed(struct pci_dev *pdev) | |
639 | { | |
640 | return pdev->is_managed; | |
641 | } | |
642 | ||
1da177e4 LT |
643 | void pci_disable_device(struct pci_dev *dev); |
644 | void pci_set_master(struct pci_dev *dev); | |
f7bdd12d | 645 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
1da177e4 | 646 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 647 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 648 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 649 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 650 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 651 | void pci_msi_off(struct pci_dev *dev); |
9c8550ee LT |
652 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
653 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); | |
4d57cdfa | 654 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 655 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
656 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
657 | int pcix_get_mmrbc(struct pci_dev *dev); | |
658 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 659 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 660 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
8dd7f803 SY |
661 | int pci_reset_function(struct pci_dev *dev); |
662 | int pci_execute_reset_function(struct pci_dev *dev); | |
14add80b | 663 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 664 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
c87deff7 | 665 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
666 | |
667 | /* ROM control related routines */ | |
e416de5e AC |
668 | int pci_enable_rom(struct pci_dev *pdev); |
669 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 670 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 671 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
d7ad2254 | 672 | size_t pci_get_rom_size(void __iomem *rom, size_t size); |
1da177e4 LT |
673 | |
674 | /* Power management related routines */ | |
675 | int pci_save_state(struct pci_dev *dev); | |
676 | int pci_restore_state(struct pci_dev *dev); | |
9c8550ee LT |
677 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
678 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 679 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 680 | void pci_pme_active(struct pci_dev *dev, bool enable); |
9c8550ee | 681 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); |
0235c4fc | 682 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
e5899e1b | 683 | pci_power_t pci_target_state(struct pci_dev *dev); |
404cc2d8 RW |
684 | int pci_prepare_to_sleep(struct pci_dev *dev); |
685 | int pci_back_from_sleep(struct pci_dev *dev); | |
1da177e4 | 686 | |
ce5ccdef | 687 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 688 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
ce5ccdef | 689 | |
287d19ce SH |
690 | /* Vital product data routines */ |
691 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
692 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
db567943 | 693 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
287d19ce | 694 | |
1da177e4 LT |
695 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
696 | void pci_bus_assign_resources(struct pci_bus *bus); | |
697 | void pci_bus_size_bridges(struct pci_bus *bus); | |
698 | int pci_claim_resource(struct pci_dev *, int); | |
699 | void pci_assign_unassigned_resources(void); | |
700 | void pdev_enable_device(struct pci_dev *); | |
701 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 702 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 LT |
703 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
704 | int (*)(struct pci_dev *, u8, u8)); | |
705 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 706 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 707 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 708 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 709 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 710 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 711 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 712 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 713 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 714 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
715 | |
716 | /* drivers/pci/bus.c */ | |
4a7fb636 AM |
717 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
718 | struct resource *res, resource_size_t size, | |
719 | resource_size_t align, resource_size_t min, | |
720 | unsigned int type_mask, | |
721 | void (*alignf)(void *, struct resource *, | |
722 | resource_size_t, resource_size_t), | |
723 | void *alignf_data); | |
1da177e4 LT |
724 | void pci_enable_bridges(struct pci_bus *bus); |
725 | ||
863b18f4 | 726 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
727 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
728 | const char *mod_name); | |
bba81165 AM |
729 | |
730 | /* | |
731 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
732 | */ | |
733 | #define pci_register_driver(driver) \ | |
734 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 735 | |
05cca6e5 GKH |
736 | void pci_unregister_driver(struct pci_driver *dev); |
737 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
738 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
739 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
740 | struct pci_dev *dev); | |
741 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
742 | int pass); | |
1da177e4 | 743 | |
cecf4864 PM |
744 | void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *), |
745 | void *userdata); | |
70b9f7dc | 746 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 747 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 748 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
cecf4864 | 749 | |
1da177e4 LT |
750 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
751 | ||
752 | #include <linux/dmapool.h> | |
753 | ||
754 | #define pci_pool dma_pool | |
755 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
756 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
757 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
758 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
759 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
760 | ||
e24c2d96 DM |
761 | enum pci_dma_burst_strategy { |
762 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
763 | strategy_parameter is N/A */ | |
764 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
765 | byte boundaries */ | |
766 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
767 | strategy_parameter byte boundaries */ | |
768 | }; | |
769 | ||
1da177e4 | 770 | struct msix_entry { |
16dbef4a | 771 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
772 | u16 entry; /* driver uses to specify entry, OS writes */ |
773 | }; | |
774 | ||
0366f8f7 | 775 | |
1da177e4 | 776 | #ifndef CONFIG_PCI_MSI |
05cca6e5 GKH |
777 | static inline int pci_enable_msi(struct pci_dev *dev) |
778 | { | |
779 | return -1; | |
780 | } | |
781 | ||
d52877c7 YL |
782 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
783 | { } | |
05cca6e5 GKH |
784 | static inline void pci_disable_msi(struct pci_dev *dev) |
785 | { } | |
786 | ||
787 | static inline int pci_enable_msix(struct pci_dev *dev, | |
788 | struct msix_entry *entries, int nvec) | |
789 | { | |
790 | return -1; | |
791 | } | |
792 | ||
d52877c7 YL |
793 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
794 | { } | |
05cca6e5 GKH |
795 | static inline void pci_disable_msix(struct pci_dev *dev) |
796 | { } | |
797 | ||
798 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
799 | { } | |
800 | ||
801 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
802 | { } | |
07ae95f9 AP |
803 | static inline int pci_msi_enabled(void) |
804 | { | |
805 | return 0; | |
806 | } | |
1da177e4 | 807 | #else |
1da177e4 | 808 | extern int pci_enable_msi(struct pci_dev *dev); |
d52877c7 | 809 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 810 | extern void pci_disable_msi(struct pci_dev *dev); |
05cca6e5 | 811 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 812 | struct msix_entry *entries, int nvec); |
d52877c7 | 813 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
814 | extern void pci_disable_msix(struct pci_dev *dev); |
815 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 816 | extern void pci_restore_msi_state(struct pci_dev *dev); |
07ae95f9 | 817 | extern int pci_msi_enabled(void); |
1da177e4 LT |
818 | #endif |
819 | ||
3e1b1600 AP |
820 | #ifndef CONFIG_PCIEASPM |
821 | static inline int pcie_aspm_enabled(void) | |
822 | { | |
823 | return 0; | |
824 | } | |
825 | #else | |
826 | extern int pcie_aspm_enabled(void); | |
827 | #endif | |
828 | ||
8b955b0d | 829 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
830 | /* The functions a driver should call */ |
831 | int ht_create_irq(struct pci_dev *dev, int idx); | |
832 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
833 | #endif /* CONFIG_HT_IRQ */ |
834 | ||
e04b0ea2 BK |
835 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
836 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
837 | ||
4352dfd5 GKH |
838 | /* |
839 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
840 | * a PCI domain is defined to be a set of PCI busses which share | |
841 | * configuration space. | |
842 | */ | |
32a2eea7 JG |
843 | #ifdef CONFIG_PCI_DOMAINS |
844 | extern int pci_domains_supported; | |
845 | #else | |
846 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
847 | static inline int pci_domain_nr(struct pci_bus *bus) |
848 | { | |
849 | return 0; | |
850 | } | |
851 | ||
4352dfd5 GKH |
852 | static inline int pci_proc_domain(struct pci_bus *bus) |
853 | { | |
854 | return 0; | |
855 | } | |
32a2eea7 | 856 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 857 | |
4352dfd5 | 858 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
859 | |
860 | /* | |
861 | * If the system does not have PCI, clearly these return errors. Define | |
862 | * these as simple inline functions to avoid hair in drivers. | |
863 | */ | |
864 | ||
05cca6e5 GKH |
865 | #define _PCI_NOP(o, s, t) \ |
866 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
867 | int where, t val) \ | |
1da177e4 | 868 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
869 | |
870 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
871 | _PCI_NOP(o, word, u16 x) \ | |
872 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
873 | _PCI_NOP_ALL(read, *) |
874 | _PCI_NOP_ALL(write,) | |
875 | ||
05cca6e5 GKH |
876 | static inline struct pci_dev *pci_find_device(unsigned int vendor, |
877 | unsigned int device, | |
b08508c4 | 878 | struct pci_dev *from) |
05cca6e5 GKH |
879 | { |
880 | return NULL; | |
881 | } | |
1da177e4 | 882 | |
05cca6e5 GKH |
883 | static inline struct pci_dev *pci_find_slot(unsigned int bus, |
884 | unsigned int devfn) | |
885 | { | |
886 | return NULL; | |
887 | } | |
1da177e4 | 888 | |
d42552c3 | 889 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
890 | unsigned int device, |
891 | struct pci_dev *from) | |
892 | { | |
893 | return NULL; | |
894 | } | |
d42552c3 | 895 | |
05cca6e5 GKH |
896 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
897 | unsigned int device, | |
898 | unsigned int ss_vendor, | |
899 | unsigned int ss_device, | |
b08508c4 | 900 | struct pci_dev *from) |
05cca6e5 GKH |
901 | { |
902 | return NULL; | |
903 | } | |
1da177e4 | 904 | |
05cca6e5 GKH |
905 | static inline struct pci_dev *pci_get_class(unsigned int class, |
906 | struct pci_dev *from) | |
907 | { | |
908 | return NULL; | |
909 | } | |
1da177e4 LT |
910 | |
911 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 912 | #define no_pci_devices() (1) |
1da177e4 LT |
913 | #define pci_dev_put(dev) do { } while (0) |
914 | ||
05cca6e5 GKH |
915 | static inline void pci_set_master(struct pci_dev *dev) |
916 | { } | |
917 | ||
918 | static inline int pci_enable_device(struct pci_dev *dev) | |
919 | { | |
920 | return -EIO; | |
921 | } | |
922 | ||
923 | static inline void pci_disable_device(struct pci_dev *dev) | |
924 | { } | |
925 | ||
926 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
927 | { | |
928 | return -EIO; | |
929 | } | |
930 | ||
80be0385 RD |
931 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
932 | { | |
933 | return -EIO; | |
934 | } | |
935 | ||
4d57cdfa FT |
936 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
937 | unsigned int size) | |
938 | { | |
939 | return -EIO; | |
940 | } | |
941 | ||
59fc67de FT |
942 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
943 | unsigned long mask) | |
944 | { | |
945 | return -EIO; | |
946 | } | |
947 | ||
05cca6e5 GKH |
948 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
949 | { | |
950 | return -EBUSY; | |
951 | } | |
952 | ||
953 | static inline int __pci_register_driver(struct pci_driver *drv, | |
954 | struct module *owner) | |
955 | { | |
956 | return 0; | |
957 | } | |
958 | ||
959 | static inline int pci_register_driver(struct pci_driver *drv) | |
960 | { | |
961 | return 0; | |
962 | } | |
963 | ||
964 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
965 | { } | |
966 | ||
967 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
968 | { | |
969 | return 0; | |
970 | } | |
971 | ||
972 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
973 | int cap) | |
974 | { | |
975 | return 0; | |
976 | } | |
977 | ||
978 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
979 | { | |
980 | return 0; | |
981 | } | |
982 | ||
1da177e4 | 983 | /* Power management related routines */ |
05cca6e5 GKH |
984 | static inline int pci_save_state(struct pci_dev *dev) |
985 | { | |
986 | return 0; | |
987 | } | |
988 | ||
989 | static inline int pci_restore_state(struct pci_dev *dev) | |
990 | { | |
991 | return 0; | |
992 | } | |
1da177e4 | 993 | |
05cca6e5 GKH |
994 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
995 | { | |
996 | return 0; | |
997 | } | |
998 | ||
999 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, | |
1000 | pm_message_t state) | |
1001 | { | |
1002 | return PCI_D0; | |
1003 | } | |
1004 | ||
1005 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
1006 | int enable) | |
1007 | { | |
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) | |
1012 | { | |
1013 | return -EIO; | |
1014 | } | |
1015 | ||
1016 | static inline void pci_release_regions(struct pci_dev *dev) | |
1017 | { } | |
0da0ead9 | 1018 | |
a46e8126 KG |
1019 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1020 | ||
05cca6e5 GKH |
1021 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
1022 | { } | |
1023 | ||
1024 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
1025 | { } | |
e04b0ea2 | 1026 | |
d80d0217 RD |
1027 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1028 | { return NULL; } | |
1029 | ||
1030 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
1031 | unsigned int devfn) | |
1032 | { return NULL; } | |
1033 | ||
1034 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
1035 | unsigned int devfn) | |
1036 | { return NULL; } | |
1037 | ||
4352dfd5 | 1038 | #endif /* CONFIG_PCI */ |
1da177e4 | 1039 | |
4352dfd5 GKH |
1040 | /* Include architecture-dependent settings and functions */ |
1041 | ||
1042 | #include <asm/pci.h> | |
1da177e4 LT |
1043 | |
1044 | /* these helpers provide future and backwards compatibility | |
1045 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1046 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1047 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1048 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1049 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1050 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1051 | pci_resource_end((dev), (bar)) == \ | |
1052 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1053 | \ | |
1054 | (pci_resource_end((dev), (bar)) - \ | |
1055 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1056 | |
1057 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1058 | * driver-specific data. They are really just a wrapper around | |
1059 | * the generic device structure functions of these calls. | |
1060 | */ | |
05cca6e5 | 1061 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1062 | { |
1063 | return dev_get_drvdata(&pdev->dev); | |
1064 | } | |
1065 | ||
05cca6e5 | 1066 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1067 | { |
1068 | dev_set_drvdata(&pdev->dev, data); | |
1069 | } | |
1070 | ||
1071 | /* If you want to know what to call your pci_dev, ask this function. | |
1072 | * Again, it's a wrapper around the generic device. | |
1073 | */ | |
c6c4f070 | 1074 | static inline const char *pci_name(struct pci_dev *pdev) |
1da177e4 | 1075 | { |
c6c4f070 | 1076 | return dev_name(&pdev->dev); |
1da177e4 LT |
1077 | } |
1078 | ||
2311b1f2 ME |
1079 | |
1080 | /* Some archs don't want to expose struct resource to userland as-is | |
1081 | * in sysfs and /proc | |
1082 | */ | |
1083 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1084 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1085 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1086 | resource_size_t *end) |
2311b1f2 ME |
1087 | { |
1088 | *start = rsrc->start; | |
1089 | *end = rsrc->end; | |
1090 | } | |
1091 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1092 | ||
1093 | ||
1da177e4 LT |
1094 | /* |
1095 | * The world is not perfect and supplies us with broken PCI devices. | |
1096 | * For at least a part of these bugs we need a work-around, so both | |
1097 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1098 | * fixup hooks to be called for particular buggy devices. | |
1099 | */ | |
1100 | ||
1101 | struct pci_fixup { | |
1102 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1103 | void (*hook)(struct pci_dev *dev); | |
1104 | }; | |
1105 | ||
1106 | enum pci_fixup_pass { | |
1107 | pci_fixup_early, /* Before probing BARs */ | |
1108 | pci_fixup_header, /* After reading configuration header */ | |
1109 | pci_fixup_final, /* Final phase of device fixups */ | |
1110 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1111 | pci_fixup_resume, /* pci_device_resume() */ |
1112 | pci_fixup_suspend, /* pci_device_suspend */ | |
1113 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1114 | }; |
1115 | ||
1116 | /* Anonymous variables would be nice... */ | |
1117 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1118 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1119 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1120 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1121 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1122 | vendor##device##hook, vendor, device, hook) | |
1123 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1124 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1125 | vendor##device##hook, vendor, device, hook) | |
1126 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1127 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1128 | vendor##device##hook, vendor, device, hook) | |
1129 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1130 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1131 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1132 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1133 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1134 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1135 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1136 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1137 | resume_early##vendor##device##hook, vendor, device, hook) | |
1138 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1139 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1140 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 LT |
1141 | |
1142 | ||
1143 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); | |
1144 | ||
05cca6e5 | 1145 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1146 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1147 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1148 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1149 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1150 | const char *name); | |
ec04b075 | 1151 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1152 | |
1da177e4 | 1153 | extern int pci_pci_problems; |
236561e5 | 1154 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1155 | #define PCIPCI_TRITON 2 |
1156 | #define PCIPCI_NATOMA 4 | |
1157 | #define PCIPCI_VIAETBF 8 | |
1158 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1159 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1160 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1161 | |
4516a618 AN |
1162 | extern unsigned long pci_cardbus_io_size; |
1163 | extern unsigned long pci_cardbus_mem_size; | |
1164 | ||
19792a08 AB |
1165 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1166 | void pcibios_disable_device(struct pci_dev *dev); | |
1167 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1168 | enum pcie_reset_state state); | |
575e3348 | 1169 | |
7752d5cf | 1170 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1171 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1172 | extern void __init pci_mmcfg_late_init(void); |
1173 | #else | |
bb63b421 | 1174 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1175 | static inline void pci_mmcfg_late_init(void) { } |
1176 | #endif | |
1177 | ||
0ef5f8f6 AP |
1178 | int pci_ext_cfg_avail(struct pci_dev *dev); |
1179 | ||
1684f5dd | 1180 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1181 | |
1da177e4 LT |
1182 | #endif /* __KERNEL__ */ |
1183 | #endif /* LINUX_PCI_H */ |