[deliverable/linux.git] / include / linux / perf / arm_pmu.h

/*
 *  linux/arch/arm/include/asm/pmu.h
 *
 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __ARM_PMU_H__
#define __ARM_PMU_H__

#include <linux/interrupt.h>
#include <linux/perf_event.h>

#include <asm/cputype.h>

/*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
 * @handle_irq: an optional handler which will be called from the
 *	interrupt and passed the address of the low level handler,
 *	and can be used to implement any platform specific handling
 *	before or after calling it.
 */
struct arm_pmu_platdata {
	irqreturn_t (*handle_irq)(int irq, void *dev,
				  irq_handler_t pmu_handler);
};

#ifdef CONFIG_ARM_PMU

/*
 * The ARMv7 CPU PMU supports up to 32 event counters.
 */
#define ARMPMU_MAX_HWEVENTS		32

#define HW_OP_UNSUPPORTED		0xFFFF
#define C(_x)				PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED		0xFFFF

#define PERF_MAP_ALL_UNSUPPORTED					\
	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED

#define PERF_CACHE_MAP_ALL_UNSUPPORTED					\
[0 ... C(MAX) - 1] = {							\
	[0 ... C(OP_MAX) - 1] = {					\
		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
	},								\
}

/* The events for a given PMU register set. */
struct pmu_hw_events {
	/*
	 * The events that are active on the PMU for the given index.
	 */
	struct perf_event	*events[ARMPMU_MAX_HWEVENTS];

	/*
	 * A 1 bit for an index indicates that the counter is being used for
	 * an event. A 0 means that the counter can be used.
	 */
	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);

	/*
	 * Hardware lock to serialize accesses to PMU registers. Needed for the
	 * read/modify/write sequences.
	 */
	raw_spinlock_t		pmu_lock;

	/*
	 * When using percpu IRQs, we need a percpu dev_id. Place it here as we
	 * already have to allocate this struct per cpu.
	 */
	struct arm_pmu		*percpu_pmu;
};

struct arm_pmu {
	struct pmu	pmu;
	cpumask_t	active_irqs;
	cpumask_t	supported_cpus;
	int		*irq_affinity;
	char		*name;
	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
	void		(*enable)(struct perf_event *event);
	void		(*disable)(struct perf_event *event);
	int		(*get_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	void		(*clear_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	int		(*set_event_filter)(struct hw_perf_event *evt,
					    struct perf_event_attr *attr);
	u32		(*read_counter)(struct perf_event *event);
	void		(*write_counter)(struct perf_event *event, u32 val);
	void		(*start)(struct arm_pmu *);
	void		(*stop)(struct arm_pmu *);
	void		(*reset)(void *);
	int		(*request_irq)(struct arm_pmu *, irq_handler_t handler);
	void		(*free_irq)(struct arm_pmu *);
	int		(*map_event)(struct perf_event *event);
	int		num_events;
	atomic_t	active_events;
	struct mutex	reserve_mutex;
	u64		max_period;
	bool		secure_access; /* 32-bit ARM only */
#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
	DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
	struct platform_device	*plat_device;
	struct pmu_hw_events	__percpu *hw_events;
	struct notifier_block	hotplug_nb;
	struct notifier_block	cpu_pm_nb;
};

#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))

u64 armpmu_event_update(struct perf_event *event);

int armpmu_event_set_period(struct perf_event *event);

int armpmu_map_event(struct perf_event *event,
		     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
		     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
						[PERF_COUNT_HW_CACHE_OP_MAX]
						[PERF_COUNT_HW_CACHE_RESULT_MAX],
		     u32 raw_event_mask);

struct pmu_probe_info {
	unsigned int cpuid;
	unsigned int mask;
	int (*init)(struct arm_pmu *);
};

#define PMU_PROBE(_cpuid, _mask, _fn)	\
{					\
	.cpuid = (_cpuid),		\
	.mask = (_mask),		\
	.init = (_fn),			\
}

#define ARM_PMU_PROBE(_cpuid, _fn) \
	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)

#define ARM_PMU_XSCALE_MASK	((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)

#define XSCALE_PMU_PROBE(_version, _fn) \
	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)

int arm_pmu_device_probe(struct platform_device *pdev,
			 const struct of_device_id *of_table,
			 const struct pmu_probe_info *probe_table);

#endif /* CONFIG_ARM_PMU */

#endif /* __ARM_PMU_H__ */
Commit	Line	Data
0f4f0672 JI	1	/*
	2	* linux/arch/arm/include/asm/pmu.h
	3	*
	4	* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
	12	#ifndef __ARM_PMU_H__
	13	#define __ARM_PMU_H__
	14
0e25a5c9	15	#include <linux/interrupt.h>
0ce47080	16	#include <linux/perf_event.h>
0e25a5c9	17
548a86ca MR	18	#include <asm/cputype.h>
548a86ca MR	19
0e25a5c9 RV	20	/*
	21	* struct arm_pmu_platdata - ARM PMU platform data
	22	*
e0516a64 ML	23	* @handle_irq: an optional handler which will be called from the
	24	* interrupt and passed the address of the low level handler,
	25	* and can be used to implement any platform specific handling
	26	* before or after calling it.
0e25a5c9 RV	27	*/
	28	struct arm_pmu_platdata {
	29	irqreturn_t (handle_irq)(int irq, void dev,
	30	irq_handler_t pmu_handler);
	31	};
	32
fa8ad788	33	#ifdef CONFIG_ARM_PMU
0ce47080	34
ac8674dc MR	35	/*
	36	* The ARMv7 CPU PMU supports up to 32 event counters.
	37	*/
	38	#define ARMPMU_MAX_HWEVENTS 32
	39
	40	#define HW_OP_UNSUPPORTED 0xFFFF
	41	#define C(_x) PERF_COUNT_HW_CACHE_##_x
	42	#define CACHE_OP_UNSUPPORTED 0xFFFF
	43
1113ff98 MR	44	#define PERF_MAP_ALL_UNSUPPORTED \
	45	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
	46
	47	#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
	48	[0 ... C(MAX) - 1] = { \
	49	[0 ... C(OP_MAX) - 1] = { \
	50	[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
	51	}, \
	52	}
	53
0ce47080 MR	54	/* The events for a given PMU register set. */
	55	struct pmu_hw_events {
	56	/*
	57	* The events that are active on the PMU for the given index.
	58	*/
a4560846	59	struct perf_event *events[ARMPMU_MAX_HWEVENTS];
0ce47080 MR	60
	61	/*
	62	* A 1 bit for an index indicates that the counter is being used for
	63	* an event. A 0 means that the counter can be used.
	64	*/
a4560846	65	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
0ce47080 MR	66
	67	/*
	68	* Hardware lock to serialize accesses to PMU registers. Needed for the
	69	* read/modify/write sequences.
	70	*/
	71	raw_spinlock_t pmu_lock;
5ebd9200 MR	72
	73	/*
	74	* When using percpu IRQs, we need a percpu dev_id. Place it here as we
	75	* already have to allocate this struct per cpu.
	76	*/
	77	struct arm_pmu *percpu_pmu;
0ce47080 MR	78	};
	79
	80	struct arm_pmu {
	81	struct pmu pmu;
0ce47080	82	cpumask_t active_irqs;
cc88116d	83	cpumask_t supported_cpus;
9fd85eb5	84	int *irq_affinity;
4295b898	85	char *name;
0ce47080	86	irqreturn_t (handle_irq)(int irq_num, void dev);
ed6f2a52 SK	87	void (enable)(struct perf_event event);
ed6f2a52 SK	88	void (disable)(struct perf_event event);
0ce47080	89	int (get_event_idx)(struct pmu_hw_events hw_events,
ed6f2a52	90	struct perf_event *event);
eab443ef SB	91	void (clear_event_idx)(struct pmu_hw_events hw_events,
eab443ef SB	92	struct perf_event *event);
0ce47080 MR	93	int (set_event_filter)(struct hw_perf_event evt,
0ce47080 MR	94	struct perf_event_attr *attr);
ed6f2a52 SK	95	u32 (read_counter)(struct perf_event event);
	96	void (write_counter)(struct perf_event event, u32 val);
	97	void (start)(struct arm_pmu );
	98	void (stop)(struct arm_pmu );
0ce47080	99	void (reset)(void );
ed6f2a52 SK	100	int (request_irq)(struct arm_pmu , irq_handler_t handler);
ed6f2a52 SK	101	void (free_irq)(struct arm_pmu );
0ce47080 MR	102	int (map_event)(struct perf_event event);
	103	int num_events;
	104	atomic_t active_events;
	105	struct mutex reserve_mutex;
	106	u64 max_period;
8d1a0ae7	107	bool secure_access; /* 32-bit ARM only */
4b1a9e69 AK	108	#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
4b1a9e69 AK	109	DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
0ce47080	110	struct platform_device *plat_device;
11679250	111	struct pmu_hw_events __percpu *hw_events;
af66abfe	112	struct notifier_block hotplug_nb;
da4e4f18	113	struct notifier_block cpu_pm_nb;
0ce47080 MR	114	};
	115
	116	#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
	117
ed6f2a52	118	u64 armpmu_event_update(struct perf_event *event);
0ce47080	119
ed6f2a52	120	int armpmu_event_set_period(struct perf_event *event);
0ce47080	121
6dbc0029 WD	122	int armpmu_map_event(struct perf_event *event,
	123	const unsigned (*event_map)[PERF_COUNT_HW_MAX],
	124	const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
	125	[PERF_COUNT_HW_CACHE_OP_MAX]
	126	[PERF_COUNT_HW_CACHE_RESULT_MAX],
	127	u32 raw_event_mask);
	128
548a86ca MR	129	struct pmu_probe_info {
	130	unsigned int cpuid;
	131	unsigned int mask;
	132	int (init)(struct arm_pmu );
	133	};
	134
	135	#define PMU_PROBE(_cpuid, _mask, _fn) \
	136	{ \
	137	.cpuid = (_cpuid), \
	138	.mask = (_mask), \
	139	.init = (_fn), \
	140	}
	141
	142	#define ARM_PMU_PROBE(_cpuid, _fn) \
	143	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
	144
	145	#define ARM_PMU_XSCALE_MASK ((0xff << 24) \| ARM_CPU_XSCALE_ARCH_MASK)
	146
	147	#define XSCALE_PMU_PROBE(_version, _fn) \
	148	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 \| _version, ARM_PMU_XSCALE_MASK, _fn)
	149
cfdad299 MR	150	int arm_pmu_device_probe(struct platform_device *pdev,
	151	const struct of_device_id *of_table,
	152	const struct pmu_probe_info *probe_table);
	153
fa8ad788	154	#endif /* CONFIG_ARM_PMU */
0ce47080	155
0f4f0672	156	#endif /* __ARM_PMU_H__ */