[deliverable/linux.git] / include / linux / phy / omap_control_phy.h

/*
 * omap_control_phy.h - Header file for the PHY part of control module.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __OMAP_CONTROL_PHY_H__
#define __OMAP_CONTROL_PHY_H__

enum omap_control_phy_type {
	OMAP_CTRL_TYPE_OTGHS = 1,	/* Mailbox OTGHS_CONTROL */
	OMAP_CTRL_TYPE_USB2,	/* USB2_PHY, power down in CONTROL_DEV_CONF */
	OMAP_CTRL_TYPE_PIPE3,	/* PIPE3 PHY, DPLL & seperate Rx/Tx power */
	OMAP_CTRL_TYPE_PCIE,	/* RX TX control of ACSPCIE */
	OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
	OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
};

struct omap_control_phy {
	struct device *dev;

	u32 __iomem *otghs_control;
	u32 __iomem *power;
	u32 __iomem *power_aux;
	u32 __iomem *pcie_pcs;

	struct clk *sys_clk;

	enum omap_control_phy_type type;
};

enum omap_control_usb_mode {
	USB_MODE_UNDEFINED = 0,
	USB_MODE_HOST,
	USB_MODE_DEVICE,
	USB_MODE_DISCONNECT,
};

#define	OMAP_CTRL_DEV_PHY_PD		BIT(0)

#define	OMAP_CTRL_DEV_AVALID		BIT(0)
#define	OMAP_CTRL_DEV_BVALID		BIT(1)
#define	OMAP_CTRL_DEV_VBUSVALID		BIT(2)
#define	OMAP_CTRL_DEV_SESSEND		BIT(3)
#define	OMAP_CTRL_DEV_IDDIG		BIT(4)

#define	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK		0x003FC000
#define	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT	0xE

#define	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK	0xFFC00000
#define	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT	0x16

#define	OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON	0x3
#define	OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF	0x0

#define	OMAP_CTRL_PCIE_PCS_MASK			0xff
#define	OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT	16

#define OMAP_CTRL_USB2_PHY_PD		BIT(28)

#define AM437X_CTRL_USB2_PHY_PD		BIT(0)
#define AM437X_CTRL_USB2_OTG_PD		BIT(1)
#define AM437X_CTRL_USB2_OTGVDET_EN	BIT(19)
#define AM437X_CTRL_USB2_OTGSESSEND_EN	BIT(20)

#if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
void omap_control_phy_power(struct device *dev, int on);
void omap_control_usb_set_mode(struct device *dev,
			       enum omap_control_usb_mode mode);
void omap_control_pcie_pcs(struct device *dev, u8 delay);
#else

static inline void omap_control_phy_power(struct device *dev, int on)
{
}

static inline void omap_control_usb_set_mode(struct device *dev,
	enum omap_control_usb_mode mode)
{
}

static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
{
}
#endif

#endif	/* __OMAP_CONTROL_PHY_H__ */
Commit	Line	Data
01658f0f	1	/*
14da699b	2	* omap_control_phy.h - Header file for the PHY part of control module.
01658f0f KVA	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
14da699b KVA	19	#ifndef __OMAP_CONTROL_PHY_H__
14da699b KVA	20	#define __OMAP_CONTROL_PHY_H__
01658f0f	21
14da699b	22	enum omap_control_phy_type {
6cb9310a RQ	23	OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
	24	OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
	25	OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
f0e2cf7b	26	OMAP_CTRL_TYPE_PCIE, /* RX TX control of ACSPCIE */
6cb9310a	27	OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
c4b34a3b	28	OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
6cb9310a RQ	29	};
6cb9310a RQ	30
14da699b	31	struct omap_control_phy {
01658f0f KVA	32	struct device *dev;
01658f0f KVA	33
01658f0f	34	u32 __iomem *otghs_control;
6cb9310a RQ	35	u32 __iomem *power;
6cb9310a RQ	36	u32 __iomem *power_aux;
f0e2cf7b	37	u32 __iomem *pcie_pcs;
01658f0f KVA	38
	39	struct clk *sys_clk;
	40
14da699b	41	enum omap_control_phy_type type;
01658f0f KVA	42	};
01658f0f KVA	43
01658f0f KVA	44	enum omap_control_usb_mode {
	45	USB_MODE_UNDEFINED = 0,
	46	USB_MODE_HOST,
	47	USB_MODE_DEVICE,
	48	USB_MODE_DISCONNECT,
	49	};
	50
01658f0f KVA	51	#define OMAP_CTRL_DEV_PHY_PD BIT(0)
	52
	53	#define OMAP_CTRL_DEV_AVALID BIT(0)
	54	#define OMAP_CTRL_DEV_BVALID BIT(1)
	55	#define OMAP_CTRL_DEV_VBUSVALID BIT(2)
	56	#define OMAP_CTRL_DEV_SESSEND BIT(3)
	57	#define OMAP_CTRL_DEV_IDDIG BIT(4)
	58
14da699b KVA	59	#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
14da699b KVA	60	#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
01658f0f	61
14da699b KVA	62	#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
14da699b KVA	63	#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
01658f0f	64
14da699b KVA	65	#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
14da699b KVA	66	#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
01658f0f	67
f0e2cf7b	68	#define OMAP_CTRL_PCIE_PCS_MASK 0xff
0bc09f9c	69	#define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 16
f0e2cf7b	70
6cb9310a RQ	71	#define OMAP_CTRL_USB2_PHY_PD BIT(28)
6cb9310a RQ	72
c4b34a3b GC	73	#define AM437X_CTRL_USB2_PHY_PD BIT(0)
	74	#define AM437X_CTRL_USB2_OTG_PD BIT(1)
	75	#define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
	76	#define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
	77
14da699b KVA	78	#if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
	79	void omap_control_phy_power(struct device *dev, int on);
	80	void omap_control_usb_set_mode(struct device *dev,
	81	enum omap_control_usb_mode mode);
0bc09f9c	82	void omap_control_pcie_pcs(struct device *dev, u8 delay);
01658f0f	83	#else
01658f0f	84
14da699b	85	static inline void omap_control_phy_power(struct device *dev, int on)
01658f0f KVA	86	{
	87	}
	88
01658f0f KVA	89	static inline void omap_control_usb_set_mode(struct device *dev,
	90	enum omap_control_usb_mode mode)
	91	{
	92	}
f0e2cf7b	93
0bc09f9c	94	static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
f0e2cf7b KVA	95	{
f0e2cf7b KVA	96	}
01658f0f KVA	97	#endif
01658f0f KVA	98
14da699b	99	#endif /* __OMAP_CONTROL_PHY_H__ */