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e8db0be1 JP |
1 | #ifndef _LINUX_PM_QOS_H |
2 | #define _LINUX_PM_QOS_H | |
d82b3518 MG |
3 | /* interface for the pm_qos_power infrastructure of the linux kernel. |
4 | * | |
bf1db69f | 5 | * Mark Gross <mgross@linux.intel.com> |
d82b3518 | 6 | */ |
82f68251 | 7 | #include <linux/plist.h> |
d82b3518 MG |
8 | #include <linux/notifier.h> |
9 | #include <linux/miscdevice.h> | |
1a9a9152 | 10 | #include <linux/device.h> |
c4772d19 | 11 | #include <linux/workqueue.h> |
d82b3518 | 12 | |
d031e1de AF |
13 | enum { |
14 | PM_QOS_RESERVED = 0, | |
15 | PM_QOS_CPU_DMA_LATENCY, | |
16 | PM_QOS_NETWORK_LATENCY, | |
17 | PM_QOS_NETWORK_THROUGHPUT, | |
18 | ||
19 | /* insert new class ID */ | |
20 | PM_QOS_NUM_CLASSES, | |
21 | }; | |
d82b3518 | 22 | |
d82b3518 MG |
23 | #define PM_QOS_DEFAULT_VALUE -1 |
24 | ||
333c5ae9 TC |
25 | #define PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) |
26 | #define PM_QOS_NETWORK_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) | |
27 | #define PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE 0 | |
91ff4cb8 | 28 | #define PM_QOS_DEV_LAT_DEFAULT_VALUE 0 |
333c5ae9 | 29 | |
cc749986 JP |
30 | struct pm_qos_request { |
31 | struct plist_node node; | |
82f68251 | 32 | int pm_qos_class; |
c4772d19 | 33 | struct delayed_work work; /* for pm_qos_update_request_timeout */ |
82f68251 | 34 | }; |
d82b3518 | 35 | |
91ff4cb8 JP |
36 | struct dev_pm_qos_request { |
37 | struct plist_node node; | |
38 | struct device *dev; | |
39 | }; | |
40 | ||
4e1779ba JP |
41 | enum pm_qos_type { |
42 | PM_QOS_UNITIALIZED, | |
43 | PM_QOS_MAX, /* return the largest value */ | |
44 | PM_QOS_MIN /* return the smallest value */ | |
45 | }; | |
46 | ||
47 | /* | |
48 | * Note: The lockless read path depends on the CPU accessing | |
49 | * target_value atomically. Atomic access is only guaranteed on all CPU | |
50 | * types linux supports for 32 bit quantites | |
51 | */ | |
52 | struct pm_qos_constraints { | |
53 | struct plist_head list; | |
54 | s32 target_value; /* Do not change to 64 bit */ | |
55 | s32 default_value; | |
56 | enum pm_qos_type type; | |
57 | struct blocking_notifier_head *notifiers; | |
58 | }; | |
59 | ||
abe98ec2 JP |
60 | /* Action requested to pm_qos_update_target */ |
61 | enum pm_qos_req_action { | |
62 | PM_QOS_ADD_REQ, /* Add a new request */ | |
63 | PM_QOS_UPDATE_REQ, /* Update an existing request */ | |
64 | PM_QOS_REMOVE_REQ /* Remove an existing request */ | |
65 | }; | |
66 | ||
91ff4cb8 JP |
67 | static inline int dev_pm_qos_request_active(struct dev_pm_qos_request *req) |
68 | { | |
83618092 | 69 | return req->dev != NULL; |
91ff4cb8 JP |
70 | } |
71 | ||
abe98ec2 JP |
72 | int pm_qos_update_target(struct pm_qos_constraints *c, struct plist_node *node, |
73 | enum pm_qos_req_action action, int value); | |
cc749986 JP |
74 | void pm_qos_add_request(struct pm_qos_request *req, int pm_qos_class, |
75 | s32 value); | |
76 | void pm_qos_update_request(struct pm_qos_request *req, | |
e8db0be1 | 77 | s32 new_value); |
c4772d19 MH |
78 | void pm_qos_update_request_timeout(struct pm_qos_request *req, |
79 | s32 new_value, unsigned long timeout_us); | |
cc749986 | 80 | void pm_qos_remove_request(struct pm_qos_request *req); |
d82b3518 | 81 | |
ed77134b MG |
82 | int pm_qos_request(int pm_qos_class); |
83 | int pm_qos_add_notifier(int pm_qos_class, struct notifier_block *notifier); | |
84 | int pm_qos_remove_notifier(int pm_qos_class, struct notifier_block *notifier); | |
cc749986 | 85 | int pm_qos_request_active(struct pm_qos_request *req); |
b66213cd | 86 | s32 pm_qos_read_value(struct pm_qos_constraints *c); |
91ff4cb8 | 87 | |
a9b542ee | 88 | #ifdef CONFIG_PM |
00dc9ad1 | 89 | s32 __dev_pm_qos_read_value(struct device *dev); |
1a9a9152 | 90 | s32 dev_pm_qos_read_value(struct device *dev); |
91ff4cb8 JP |
91 | int dev_pm_qos_add_request(struct device *dev, struct dev_pm_qos_request *req, |
92 | s32 value); | |
93 | int dev_pm_qos_update_request(struct dev_pm_qos_request *req, s32 new_value); | |
94 | int dev_pm_qos_remove_request(struct dev_pm_qos_request *req); | |
95 | int dev_pm_qos_add_notifier(struct device *dev, | |
96 | struct notifier_block *notifier); | |
97 | int dev_pm_qos_remove_notifier(struct device *dev, | |
98 | struct notifier_block *notifier); | |
b66213cd JP |
99 | int dev_pm_qos_add_global_notifier(struct notifier_block *notifier); |
100 | int dev_pm_qos_remove_global_notifier(struct notifier_block *notifier); | |
91ff4cb8 JP |
101 | void dev_pm_qos_constraints_init(struct device *dev); |
102 | void dev_pm_qos_constraints_destroy(struct device *dev); | |
40a5f8be RW |
103 | int dev_pm_qos_add_ancestor_request(struct device *dev, |
104 | struct dev_pm_qos_request *req, s32 value); | |
e8db0be1 | 105 | #else |
00dc9ad1 RW |
106 | static inline s32 __dev_pm_qos_read_value(struct device *dev) |
107 | { return 0; } | |
1a9a9152 RW |
108 | static inline s32 dev_pm_qos_read_value(struct device *dev) |
109 | { return 0; } | |
91ff4cb8 JP |
110 | static inline int dev_pm_qos_add_request(struct device *dev, |
111 | struct dev_pm_qos_request *req, | |
112 | s32 value) | |
113 | { return 0; } | |
114 | static inline int dev_pm_qos_update_request(struct dev_pm_qos_request *req, | |
115 | s32 new_value) | |
116 | { return 0; } | |
117 | static inline int dev_pm_qos_remove_request(struct dev_pm_qos_request *req) | |
118 | { return 0; } | |
119 | static inline int dev_pm_qos_add_notifier(struct device *dev, | |
120 | struct notifier_block *notifier) | |
121 | { return 0; } | |
122 | static inline int dev_pm_qos_remove_notifier(struct device *dev, | |
123 | struct notifier_block *notifier) | |
124 | { return 0; } | |
b66213cd JP |
125 | static inline int dev_pm_qos_add_global_notifier( |
126 | struct notifier_block *notifier) | |
127 | { return 0; } | |
128 | static inline int dev_pm_qos_remove_global_notifier( | |
129 | struct notifier_block *notifier) | |
130 | { return 0; } | |
91ff4cb8 | 131 | static inline void dev_pm_qos_constraints_init(struct device *dev) |
1a9a9152 RW |
132 | { |
133 | dev->power.power_state = PMSG_ON; | |
134 | } | |
91ff4cb8 | 135 | static inline void dev_pm_qos_constraints_destroy(struct device *dev) |
1a9a9152 RW |
136 | { |
137 | dev->power.power_state = PMSG_INVALID; | |
138 | } | |
40a5f8be RW |
139 | static inline int dev_pm_qos_add_ancestor_request(struct device *dev, |
140 | struct dev_pm_qos_request *req, s32 value) | |
141 | { return 0; } | |
e8db0be1 | 142 | #endif |
d82b3518 | 143 | |
85dc0b8a RW |
144 | #ifdef CONFIG_PM_RUNTIME |
145 | int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value); | |
146 | void dev_pm_qos_hide_latency_limit(struct device *dev); | |
147 | #else | |
148 | static inline int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value) | |
149 | { return 0; } | |
150 | static inline void dev_pm_qos_hide_latency_limit(struct device *dev) {} | |
151 | #endif | |
152 | ||
82f68251 | 153 | #endif |