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fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #ifndef __COMMON_HSI__ | |
10 | #define __COMMON_HSI__ | |
11 | ||
76a9a364 TT |
12 | #define CORE_SPQE_PAGE_SIZE_BYTES 4096 |
13 | ||
fc48b7a6 YM |
14 | #define X_FINAL_CLEANUP_AGG_INT 1 |
15 | ||
fe56b9e6 | 16 | #define FW_MAJOR_VERSION 8 |
fc48b7a6 YM |
17 | #define FW_MINOR_VERSION 7 |
18 | #define FW_REVISION_VERSION 3 | |
fe56b9e6 YM |
19 | #define FW_ENGINEERING_VERSION 0 |
20 | ||
21 | /***********************/ | |
22 | /* COMMON HW CONSTANTS */ | |
23 | /***********************/ | |
24 | ||
25 | /* PCI functions */ | |
26 | #define MAX_NUM_PORTS_K2 (4) | |
27 | #define MAX_NUM_PORTS_BB (2) | |
28 | #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) | |
29 | ||
30 | #define MAX_NUM_PFS_K2 (16) | |
31 | #define MAX_NUM_PFS_BB (8) | |
32 | #define MAX_NUM_PFS (MAX_NUM_PFS_K2) | |
33 | #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ | |
34 | ||
35 | #define MAX_NUM_VFS_K2 (192) | |
36 | #define MAX_NUM_VFS_BB (120) | |
37 | #define MAX_NUM_VFS (MAX_NUM_VFS_K2) | |
38 | ||
39 | #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) | |
40 | #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) | |
41 | ||
42 | #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) | |
43 | #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) | |
44 | ||
45 | #define MAX_NUM_VPORTS_K2 (208) | |
46 | #define MAX_NUM_VPORTS_BB (160) | |
47 | #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) | |
48 | ||
49 | #define MAX_NUM_L2_QUEUES_K2 (320) | |
50 | #define MAX_NUM_L2_QUEUES_BB (256) | |
51 | #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) | |
52 | ||
53 | /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ | |
54 | #define NUM_PHYS_TCS_4PORT_K2 (4) | |
55 | #define NUM_OF_PHYS_TCS (8) | |
56 | ||
57 | #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) | |
58 | #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) | |
59 | ||
60 | #define LB_TC (NUM_OF_PHYS_TCS) | |
61 | ||
62 | /* Num of possible traffic priority values */ | |
63 | #define NUM_OF_PRIO (8) | |
64 | ||
65 | #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) | |
66 | #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) | |
67 | #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) | |
68 | #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) | |
69 | ||
70 | /* CIDs */ | |
71 | #define NUM_OF_CONNECTION_TYPES (8) | |
72 | #define NUM_OF_LCIDS (320) | |
73 | #define NUM_OF_LTIDS (320) | |
74 | ||
75 | /*****************/ | |
76 | /* CDU CONSTANTS */ | |
77 | /*****************/ | |
78 | ||
79 | #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) | |
80 | #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) | |
81 | ||
82 | /*****************/ | |
83 | /* DQ CONSTANTS */ | |
84 | /*****************/ | |
85 | ||
86 | /* DEMS */ | |
87 | #define DQ_DEMS_LEGACY 0 | |
88 | ||
89 | /* XCM agg val selection */ | |
90 | #define DQ_XCM_AGG_VAL_SEL_WORD2 0 | |
91 | #define DQ_XCM_AGG_VAL_SEL_WORD3 1 | |
92 | #define DQ_XCM_AGG_VAL_SEL_WORD4 2 | |
93 | #define DQ_XCM_AGG_VAL_SEL_WORD5 3 | |
94 | #define DQ_XCM_AGG_VAL_SEL_REG3 4 | |
95 | #define DQ_XCM_AGG_VAL_SEL_REG4 5 | |
96 | #define DQ_XCM_AGG_VAL_SEL_REG5 6 | |
97 | #define DQ_XCM_AGG_VAL_SEL_REG6 7 | |
98 | ||
99 | /* XCM agg val selection */ | |
100 | #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \ | |
101 | DQ_XCM_AGG_VAL_SEL_WORD2 | |
102 | #define DQ_XCM_ETH_TX_BD_CONS_CMD \ | |
103 | DQ_XCM_AGG_VAL_SEL_WORD3 | |
104 | #define DQ_XCM_CORE_TX_BD_CONS_CMD \ | |
105 | DQ_XCM_AGG_VAL_SEL_WORD3 | |
106 | #define DQ_XCM_ETH_TX_BD_PROD_CMD \ | |
107 | DQ_XCM_AGG_VAL_SEL_WORD4 | |
108 | #define DQ_XCM_CORE_TX_BD_PROD_CMD \ | |
109 | DQ_XCM_AGG_VAL_SEL_WORD4 | |
110 | #define DQ_XCM_CORE_SPQ_PROD_CMD \ | |
111 | DQ_XCM_AGG_VAL_SEL_WORD4 | |
112 | #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 | |
113 | ||
114 | /* XCM agg counter flag selection */ | |
115 | #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 | |
116 | #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 | |
117 | #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 | |
118 | #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 | |
119 | #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 | |
120 | #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 | |
121 | #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 | |
122 | #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 | |
123 | ||
124 | /* XCM agg counter flag selection */ | |
125 | #define DQ_XCM_ETH_DQ_CF_CMD (1 << \ | |
126 | DQ_XCM_AGG_FLG_SHIFT_CF18) | |
127 | #define DQ_XCM_CORE_DQ_CF_CMD (1 << \ | |
128 | DQ_XCM_AGG_FLG_SHIFT_CF18) | |
129 | #define DQ_XCM_ETH_TERMINATE_CMD (1 << \ | |
130 | DQ_XCM_AGG_FLG_SHIFT_CF19) | |
131 | #define DQ_XCM_CORE_TERMINATE_CMD (1 << \ | |
132 | DQ_XCM_AGG_FLG_SHIFT_CF19) | |
133 | #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \ | |
134 | DQ_XCM_AGG_FLG_SHIFT_CF22) | |
135 | #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \ | |
136 | DQ_XCM_AGG_FLG_SHIFT_CF22) | |
137 | #define DQ_XCM_ETH_TPH_EN_CMD (1 << \ | |
138 | DQ_XCM_AGG_FLG_SHIFT_CF23) | |
139 | ||
140 | /*****************/ | |
141 | /* QM CONSTANTS */ | |
142 | /*****************/ | |
143 | ||
144 | /* number of TX queues in the QM */ | |
145 | #define MAX_QM_TX_QUEUES_K2 512 | |
146 | #define MAX_QM_TX_QUEUES_BB 448 | |
147 | #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 | |
148 | ||
149 | /* number of Other queues in the QM */ | |
150 | #define MAX_QM_OTHER_QUEUES_BB 64 | |
151 | #define MAX_QM_OTHER_QUEUES_K2 128 | |
152 | #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 | |
153 | ||
154 | /* number of queues in a PF queue group */ | |
155 | #define QM_PF_QUEUE_GROUP_SIZE 8 | |
156 | ||
fc48b7a6 YM |
157 | /* the size of a single queue element in bytes */ |
158 | #define QM_PQ_ELEMENT_SIZE 4 | |
159 | ||
fe56b9e6 YM |
160 | /* base number of Tx PQs in the CM PQ representation. |
161 | * should be used when storing PQ IDs in CM PQ registers and context | |
162 | */ | |
163 | #define CM_TX_PQ_BASE 0x200 | |
164 | ||
165 | /* QM registers data */ | |
166 | #define QM_LINE_CRD_REG_WIDTH 16 | |
167 | #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) | |
168 | #define QM_BYTE_CRD_REG_WIDTH 24 | |
169 | #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) | |
170 | #define QM_WFQ_CRD_REG_WIDTH 32 | |
171 | #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) | |
172 | #define QM_RL_CRD_REG_WIDTH 32 | |
173 | #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) | |
174 | ||
175 | /*****************/ | |
176 | /* CAU CONSTANTS */ | |
177 | /*****************/ | |
178 | ||
179 | #define CAU_FSM_ETH_RX 0 | |
180 | #define CAU_FSM_ETH_TX 1 | |
181 | ||
182 | /* Number of Protocol Indices per Status Block */ | |
183 | #define PIS_PER_SB 12 | |
184 | ||
185 | #define CAU_HC_STOPPED_STATE 3 | |
186 | #define CAU_HC_DISABLE_STATE 4 | |
187 | #define CAU_HC_ENABLE_STATE 0 | |
188 | ||
189 | /*****************/ | |
190 | /* IGU CONSTANTS */ | |
191 | /*****************/ | |
192 | ||
193 | #define MAX_SB_PER_PATH_K2 (368) | |
194 | #define MAX_SB_PER_PATH_BB (288) | |
195 | #define MAX_TOT_SB_PER_PATH \ | |
196 | MAX_SB_PER_PATH_K2 | |
197 | ||
198 | #define MAX_SB_PER_PF_MIMD 129 | |
199 | #define MAX_SB_PER_PF_SIMD 64 | |
200 | #define MAX_SB_PER_VF 64 | |
201 | ||
202 | /* Memory addresses on the BAR for the IGU Sub Block */ | |
203 | #define IGU_MEM_BASE 0x0000 | |
204 | ||
205 | #define IGU_MEM_MSIX_BASE 0x0000 | |
206 | #define IGU_MEM_MSIX_UPPER 0x0101 | |
207 | #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff | |
208 | ||
209 | #define IGU_MEM_PBA_MSIX_BASE 0x0200 | |
210 | #define IGU_MEM_PBA_MSIX_UPPER 0x0202 | |
211 | #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff | |
212 | ||
213 | #define IGU_CMD_INT_ACK_BASE 0x0400 | |
214 | #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ | |
215 | MAX_TOT_SB_PER_PATH - \ | |
216 | 1) | |
217 | #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff | |
218 | ||
219 | #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 | |
220 | #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 | |
221 | #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 | |
222 | ||
223 | #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 | |
224 | #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 | |
225 | #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 | |
226 | #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 | |
227 | ||
228 | #define IGU_CMD_PROD_UPD_BASE 0x0600 | |
229 | #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ | |
230 | MAX_TOT_SB_PER_PATH - \ | |
231 | 1) | |
232 | #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff | |
233 | ||
234 | /*****************/ | |
235 | /* PXP CONSTANTS */ | |
236 | /*****************/ | |
237 | ||
238 | /* PTT and GTT */ | |
239 | #define PXP_NUM_PF_WINDOWS 12 | |
240 | #define PXP_PER_PF_ENTRY_SIZE 8 | |
241 | #define PXP_NUM_GLOBAL_WINDOWS 243 | |
242 | #define PXP_GLOBAL_ENTRY_SIZE 4 | |
243 | #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 | |
244 | #define PXP_PF_WINDOW_ADMIN_START 0 | |
245 | #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 | |
246 | #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ | |
247 | PXP_PF_WINDOW_ADMIN_LENGTH - 1) | |
248 | #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 | |
249 | #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ | |
250 | PXP_PER_PF_ENTRY_SIZE) | |
251 | #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ | |
252 | PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) | |
253 | #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 | |
254 | #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ | |
255 | PXP_GLOBAL_ENTRY_SIZE) | |
256 | #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ | |
257 | (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ | |
258 | PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) | |
259 | #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 | |
260 | #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 | |
261 | #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 | |
262 | #define PXP_PF_ME_CONCRETE_ADDR 0x1fc | |
263 | ||
264 | #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 | |
265 | #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS | |
266 | #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 | |
267 | #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ | |
268 | (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ | |
269 | PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) | |
270 | #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ | |
271 | (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ | |
272 | PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) | |
273 | ||
274 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ | |
275 | (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) | |
276 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS | |
277 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 | |
278 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ | |
279 | (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ | |
280 | PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) | |
281 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ | |
282 | (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ | |
283 | PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) | |
284 | ||
285 | #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 | |
286 | #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 | |
287 | ||
288 | /* ILT Records */ | |
289 | #define PXP_NUM_ILT_RECORDS_BB 7600 | |
290 | #define PXP_NUM_ILT_RECORDS_K2 11000 | |
291 | #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) | |
292 | ||
fc48b7a6 YM |
293 | #define SDM_COMP_TYPE_NONE 0 |
294 | #define SDM_COMP_TYPE_WAKE_THREAD 1 | |
295 | #define SDM_COMP_TYPE_AGG_INT 2 | |
296 | #define SDM_COMP_TYPE_CM 3 | |
297 | #define SDM_COMP_TYPE_LOADER 4 | |
298 | #define SDM_COMP_TYPE_PXP 5 | |
299 | #define SDM_COMP_TYPE_INDICATE_ERROR 6 | |
300 | #define SDM_COMP_TYPE_RELEASE_THREAD 7 | |
301 | #define SDM_COMP_TYPE_RAM 8 | |
302 | ||
fe56b9e6 YM |
303 | /******************/ |
304 | /* PBF CONSTANTS */ | |
305 | /******************/ | |
306 | ||
307 | /* Number of PBF command queue lines. Each line is 32B. */ | |
308 | #define PBF_MAX_CMD_LINES 3328 | |
309 | ||
310 | /* Number of BTB blocks. Each block is 256B. */ | |
311 | #define BTB_MAX_BLOCKS 1440 | |
312 | ||
313 | /*****************/ | |
314 | /* PRS CONSTANTS */ | |
315 | /*****************/ | |
316 | ||
317 | /* Async data KCQ CQE */ | |
318 | struct async_data { | |
319 | __le32 cid; | |
320 | __le16 itid; | |
321 | u8 error_code; | |
322 | u8 fw_debug_param; | |
323 | }; | |
324 | ||
325 | struct regpair { | |
326 | __le32 lo; | |
327 | __le32 hi; | |
328 | }; | |
329 | ||
330 | /* Event Data Union */ | |
331 | union event_ring_data { | |
332 | u8 bytes[8]; | |
333 | struct async_data async_info; | |
334 | }; | |
335 | ||
336 | /* Event Ring Entry */ | |
337 | struct event_ring_entry { | |
338 | u8 protocol_id; | |
339 | u8 opcode; | |
340 | __le16 reserved0; | |
341 | __le16 echo; | |
342 | u8 fw_return_code; | |
343 | u8 flags; | |
344 | #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 | |
345 | #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 | |
346 | #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F | |
347 | #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 | |
348 | union event_ring_data data; | |
349 | }; | |
350 | ||
351 | /* Multi function mode */ | |
352 | enum mf_mode { | |
fc48b7a6 | 353 | ERROR_MODE /* Unsupported mode */, |
fe56b9e6 YM |
354 | MF_OVLAN, |
355 | MF_NPAR, | |
356 | MAX_MF_MODE | |
357 | }; | |
358 | ||
359 | /* Per-protocol connection types */ | |
360 | enum protocol_type { | |
361 | PROTOCOLID_RESERVED1, | |
362 | PROTOCOLID_RESERVED2, | |
363 | PROTOCOLID_RESERVED3, | |
364 | PROTOCOLID_CORE, | |
365 | PROTOCOLID_ETH, | |
366 | PROTOCOLID_RESERVED4, | |
367 | PROTOCOLID_RESERVED5, | |
368 | PROTOCOLID_PREROCE, | |
369 | PROTOCOLID_COMMON, | |
370 | PROTOCOLID_RESERVED6, | |
371 | MAX_PROTOCOL_TYPE | |
372 | }; | |
373 | ||
374 | /* status block structure */ | |
375 | struct cau_pi_entry { | |
376 | u32 prod; | |
377 | #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF | |
378 | #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 | |
379 | #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F | |
380 | #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 | |
381 | #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 | |
382 | #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 | |
383 | #define CAU_PI_ENTRY_RESERVED_MASK 0xFF | |
384 | #define CAU_PI_ENTRY_RESERVED_SHIFT 24 | |
385 | }; | |
386 | ||
387 | /* status block structure */ | |
388 | struct cau_sb_entry { | |
389 | u32 data; | |
390 | #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF | |
391 | #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 | |
392 | #define CAU_SB_ENTRY_STATE0_MASK 0xF | |
393 | #define CAU_SB_ENTRY_STATE0_SHIFT 24 | |
394 | #define CAU_SB_ENTRY_STATE1_MASK 0xF | |
395 | #define CAU_SB_ENTRY_STATE1_SHIFT 28 | |
396 | u32 params; | |
397 | #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F | |
398 | #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 | |
399 | #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F | |
400 | #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 | |
401 | #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 | |
402 | #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 | |
403 | #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 | |
404 | #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 | |
405 | #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF | |
406 | #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 | |
407 | #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 | |
408 | #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 | |
409 | #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF | |
410 | #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 | |
411 | #define CAU_SB_ENTRY_TPH_MASK 0x1 | |
412 | #define CAU_SB_ENTRY_TPH_SHIFT 31 | |
413 | }; | |
414 | ||
415 | /* core doorbell data */ | |
416 | struct core_db_data { | |
417 | u8 params; | |
418 | #define CORE_DB_DATA_DEST_MASK 0x3 | |
419 | #define CORE_DB_DATA_DEST_SHIFT 0 | |
420 | #define CORE_DB_DATA_AGG_CMD_MASK 0x3 | |
421 | #define CORE_DB_DATA_AGG_CMD_SHIFT 2 | |
422 | #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 | |
423 | #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 | |
424 | #define CORE_DB_DATA_RESERVED_MASK 0x1 | |
425 | #define CORE_DB_DATA_RESERVED_SHIFT 5 | |
426 | #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 | |
427 | #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 | |
428 | u8 agg_flags; | |
429 | __le16 spq_prod; | |
430 | }; | |
431 | ||
432 | /* Enum of doorbell aggregative command selection */ | |
433 | enum db_agg_cmd_sel { | |
434 | DB_AGG_CMD_NOP, | |
435 | DB_AGG_CMD_SET, | |
436 | DB_AGG_CMD_ADD, | |
437 | DB_AGG_CMD_MAX, | |
438 | MAX_DB_AGG_CMD_SEL | |
439 | }; | |
440 | ||
441 | /* Enum of doorbell destination */ | |
442 | enum db_dest { | |
443 | DB_DEST_XCM, | |
444 | DB_DEST_UCM, | |
445 | DB_DEST_TCM, | |
446 | DB_NUM_DESTINATIONS, | |
447 | MAX_DB_DEST | |
448 | }; | |
449 | ||
450 | /* Structure for doorbell address, in legacy mode */ | |
451 | struct db_legacy_addr { | |
452 | __le32 addr; | |
453 | #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 | |
454 | #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 | |
455 | #define DB_LEGACY_ADDR_DEMS_MASK 0x7 | |
456 | #define DB_LEGACY_ADDR_DEMS_SHIFT 2 | |
457 | #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF | |
458 | #define DB_LEGACY_ADDR_ICID_SHIFT 5 | |
459 | }; | |
460 | ||
461 | /* Igu interrupt command */ | |
462 | enum igu_int_cmd { | |
463 | IGU_INT_ENABLE = 0, | |
464 | IGU_INT_DISABLE = 1, | |
465 | IGU_INT_NOP = 2, | |
466 | IGU_INT_NOP2 = 3, | |
467 | MAX_IGU_INT_CMD | |
468 | }; | |
469 | ||
470 | /* IGU producer or consumer update command */ | |
471 | struct igu_prod_cons_update { | |
472 | u32 sb_id_and_flags; | |
473 | #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF | |
474 | #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 | |
475 | #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 | |
476 | #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 | |
477 | #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 | |
478 | #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 | |
479 | #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 | |
480 | #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 | |
481 | #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 | |
482 | #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 | |
483 | #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 | |
484 | #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 | |
485 | #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 | |
486 | #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 | |
487 | u32 reserved1; | |
488 | }; | |
489 | ||
490 | /* Igu segments access for default status block only */ | |
491 | enum igu_seg_access { | |
492 | IGU_SEG_ACCESS_REG = 0, | |
493 | IGU_SEG_ACCESS_ATTN = 1, | |
494 | MAX_IGU_SEG_ACCESS | |
495 | }; | |
496 | ||
497 | struct parsing_and_err_flags { | |
498 | __le16 flags; | |
499 | #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 | |
500 | #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 | |
501 | #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 | |
502 | #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 | |
503 | #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 | |
504 | #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 | |
505 | #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 | |
506 | #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 | |
507 | #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 | |
508 | #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 | |
509 | #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 | |
510 | #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 | |
511 | #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 | |
512 | #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 | |
513 | #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 | |
514 | #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 | |
515 | #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 | |
516 | #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 | |
517 | #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 | |
518 | #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 | |
519 | #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 | |
520 | #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 | |
521 | #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 | |
522 | #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 | |
523 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 | |
524 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 | |
525 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 | |
526 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 | |
527 | }; | |
528 | ||
529 | /* Concrete Function ID. */ | |
530 | struct pxp_concrete_fid { | |
531 | __le16 fid; | |
532 | #define PXP_CONCRETE_FID_PFID_MASK 0xF | |
533 | #define PXP_CONCRETE_FID_PFID_SHIFT 0 | |
534 | #define PXP_CONCRETE_FID_PORT_MASK 0x3 | |
535 | #define PXP_CONCRETE_FID_PORT_SHIFT 4 | |
536 | #define PXP_CONCRETE_FID_PATH_MASK 0x1 | |
537 | #define PXP_CONCRETE_FID_PATH_SHIFT 6 | |
538 | #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 | |
539 | #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 | |
540 | #define PXP_CONCRETE_FID_VFID_MASK 0xFF | |
541 | #define PXP_CONCRETE_FID_VFID_SHIFT 8 | |
542 | }; | |
543 | ||
544 | struct pxp_pretend_concrete_fid { | |
545 | __le16 fid; | |
546 | #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF | |
547 | #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 | |
548 | #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 | |
549 | #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 | |
550 | #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 | |
551 | #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 | |
552 | #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF | |
553 | #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 | |
554 | }; | |
555 | ||
556 | union pxp_pretend_fid { | |
557 | struct pxp_pretend_concrete_fid concrete_fid; | |
558 | __le16 opaque_fid; | |
559 | }; | |
560 | ||
561 | /* Pxp Pretend Command Register. */ | |
562 | struct pxp_pretend_cmd { | |
563 | union pxp_pretend_fid fid; | |
564 | __le16 control; | |
565 | #define PXP_PRETEND_CMD_PATH_MASK 0x1 | |
566 | #define PXP_PRETEND_CMD_PATH_SHIFT 0 | |
567 | #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 | |
568 | #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 | |
569 | #define PXP_PRETEND_CMD_PORT_MASK 0x3 | |
570 | #define PXP_PRETEND_CMD_PORT_SHIFT 2 | |
571 | #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF | |
572 | #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 | |
573 | #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF | |
574 | #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 | |
575 | #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 | |
576 | #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 | |
577 | #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 | |
578 | #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 | |
579 | #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 | |
580 | #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 | |
581 | #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 | |
582 | #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 | |
583 | }; | |
584 | ||
585 | /* PTT Record in PXP Admin Window. */ | |
586 | struct pxp_ptt_entry { | |
587 | __le32 offset; | |
588 | #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF | |
589 | #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 | |
590 | #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF | |
591 | #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 | |
592 | struct pxp_pretend_cmd pretend; | |
593 | }; | |
594 | ||
595 | /* RSS hash type */ | |
596 | enum rss_hash_type { | |
597 | RSS_HASH_TYPE_DEFAULT = 0, | |
598 | RSS_HASH_TYPE_IPV4 = 1, | |
599 | RSS_HASH_TYPE_TCP_IPV4 = 2, | |
600 | RSS_HASH_TYPE_IPV6 = 3, | |
601 | RSS_HASH_TYPE_TCP_IPV6 = 4, | |
602 | RSS_HASH_TYPE_UDP_IPV4 = 5, | |
603 | RSS_HASH_TYPE_UDP_IPV6 = 6, | |
604 | MAX_RSS_HASH_TYPE | |
605 | }; | |
606 | ||
607 | /* status block structure */ | |
608 | struct status_block { | |
609 | __le16 pi_array[PIS_PER_SB]; | |
610 | __le32 sb_num; | |
611 | #define STATUS_BLOCK_SB_NUM_MASK 0x1FF | |
612 | #define STATUS_BLOCK_SB_NUM_SHIFT 0 | |
613 | #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F | |
614 | #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 | |
615 | #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF | |
616 | #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 | |
617 | __le32 prod_index; | |
618 | #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF | |
619 | #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 | |
620 | #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF | |
621 | #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 | |
622 | }; | |
623 | ||
fc48b7a6 YM |
624 | struct tunnel_parsing_flags { |
625 | u8 flags; | |
626 | #define TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3 | |
627 | #define TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0 | |
628 | #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1 | |
629 | #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2 | |
630 | #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3 | |
631 | #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3 | |
632 | #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1 | |
633 | #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5 | |
634 | #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1 | |
635 | #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6 | |
636 | #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1 | |
637 | #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7 | |
638 | }; | |
fe56b9e6 | 639 | #endif /* __COMMON_HSI__ */ |