Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/serial_core.h | |
3 | * | |
4 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #ifndef LINUX_SERIAL_CORE_H | |
21 | #define LINUX_SERIAL_CORE_H | |
22 | ||
ccce6deb AC |
23 | #include <linux/serial.h> |
24 | ||
1da177e4 LT |
25 | /* |
26 | * The type definitions. These are from Ted Ts'o's serial.h | |
27 | */ | |
28 | #define PORT_UNKNOWN 0 | |
29 | #define PORT_8250 1 | |
30 | #define PORT_16450 2 | |
31 | #define PORT_16550 3 | |
32 | #define PORT_16550A 4 | |
33 | #define PORT_CIRRUS 5 | |
34 | #define PORT_16650 6 | |
35 | #define PORT_16650V2 7 | |
36 | #define PORT_16750 8 | |
37 | #define PORT_STARTECH 9 | |
38 | #define PORT_16C950 10 | |
39 | #define PORT_16654 11 | |
40 | #define PORT_16850 12 | |
41 | #define PORT_RSA 13 | |
42 | #define PORT_NS16550A 14 | |
43 | #define PORT_XSCALE 15 | |
bd71c182 | 44 | #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ |
6b06f191 | 45 | #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ |
08e0992f | 46 | #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ |
71cad055 PL |
47 | #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ |
48 | #define PORT_MAX_8250 19 /* max port ID */ | |
1da177e4 LT |
49 | |
50 | /* | |
51 | * ARM specific type numbers. These are not currently guaranteed | |
52 | * to be implemented, and will change in the future. These are | |
53 | * separate so any additions to the old serial.c that occur before | |
54 | * we are merged can be easily merged here. | |
55 | */ | |
56 | #define PORT_PXA 31 | |
57 | #define PORT_AMBA 32 | |
58 | #define PORT_CLPS711X 33 | |
59 | #define PORT_SA1100 34 | |
60 | #define PORT_UART00 35 | |
61 | #define PORT_21285 37 | |
62 | ||
63 | /* Sparc type numbers. */ | |
64 | #define PORT_SUNZILOG 38 | |
65 | #define PORT_SUNSAB 39 | |
66 | ||
8b4a4080 MR |
67 | /* DEC */ |
68 | #define PORT_DZ 46 | |
69 | #define PORT_ZS 47 | |
1da177e4 LT |
70 | |
71 | /* Parisc type numbers. */ | |
72 | #define PORT_MUX 48 | |
73 | ||
9ab4f88b HS |
74 | /* Atmel AT91 / AT32 SoC */ |
75 | #define PORT_ATMEL 49 | |
1e6c9c28 | 76 | |
1da177e4 LT |
77 | /* Macintosh Zilog type numbers */ |
78 | #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */ | |
79 | #define PORT_PMAC_ZILOG 51 | |
80 | ||
81 | /* SH-SCI */ | |
82 | #define PORT_SCI 52 | |
83 | #define PORT_SCIF 53 | |
84 | #define PORT_IRDA 54 | |
85 | ||
86 | /* Samsung S3C2410 SoC and derivatives thereof */ | |
87 | #define PORT_S3C2410 55 | |
88 | ||
89 | /* SGI IP22 aka Indy / Challenge S / Indigo 2 */ | |
90 | #define PORT_IP22ZILOG 56 | |
91 | ||
92 | /* Sharp LH7a40x -- an ARM9 SoC series */ | |
93 | #define PORT_LH7A40X 57 | |
94 | ||
95 | /* PPC CPM type number */ | |
96 | #define PORT_CPM 58 | |
97 | ||
98 | /* MPC52xx type numbers */ | |
99 | #define PORT_MPC52xx 59 | |
100 | ||
101 | /* IBM icom */ | |
102 | #define PORT_ICOM 60 | |
103 | ||
104 | /* Samsung S3C2440 SoC */ | |
105 | #define PORT_S3C2440 61 | |
106 | ||
107 | /* Motorola i.MX SoC */ | |
108 | #define PORT_IMX 62 | |
109 | ||
110 | /* Marvell MPSC */ | |
111 | #define PORT_MPSC 63 | |
112 | ||
113 | /* TXX9 type number */ | |
e5c2d749 | 114 | #define PORT_TXX9 64 |
1da177e4 LT |
115 | |
116 | /* NEC VR4100 series SIU/DSIU */ | |
117 | #define PORT_VR41XX_SIU 65 | |
118 | #define PORT_VR41XX_DSIU 66 | |
119 | ||
120 | /* Samsung S3C2400 SoC */ | |
121 | #define PORT_S3C2400 67 | |
122 | ||
123 | /* M32R SIO */ | |
124 | #define PORT_M32R_SIO 68 | |
125 | ||
126 | /*Digi jsm */ | |
913ade51 RK |
127 | #define PORT_JSM 69 |
128 | ||
e6fa0ba3 | 129 | #define PORT_PNX8XXX 70 |
1da177e4 | 130 | |
f5417612 SH |
131 | /* Hilscher netx */ |
132 | #define PORT_NETX 71 | |
133 | ||
02fd473b DM |
134 | /* SUN4V Hypervisor Console */ |
135 | #define PORT_SUNHV 72 | |
136 | ||
73e55cb3 BD |
137 | #define PORT_S3C2412 73 |
138 | ||
238b8721 PK |
139 | /* Xilinx uartlite */ |
140 | #define PORT_UARTLITE 74 | |
73e55cb3 | 141 | |
194de561 BW |
142 | /* Blackfin bf5xx */ |
143 | #define PORT_BFIN 75 | |
144 | ||
2c7ee6ab AV |
145 | /* Micrel KS8695 */ |
146 | #define PORT_KS8695 76 | |
147 | ||
b45d5279 MR |
148 | /* Broadcom SB1250, etc. SOC */ |
149 | #define PORT_SB1250_DUART 77 | |
150 | ||
f0c15f48 GU |
151 | /* Freescale ColdFire */ |
152 | #define PORT_MCF 78 | |
153 | ||
2f351741 BW |
154 | /* Blackfin SPORT */ |
155 | #define PORT_BFIN_SPORT 79 | |
2c7ee6ab | 156 | |
ef3d5347 DH |
157 | /* MN10300 on-chip UART numbers */ |
158 | #define PORT_MN10300 80 | |
159 | #define PORT_MN10300_CTS 81 | |
160 | ||
2f351741 BW |
161 | #define PORT_SC26XX 82 |
162 | ||
1a22f08d YS |
163 | /* SH-SCI */ |
164 | #define PORT_SCIFA 83 | |
165 | ||
b690ace5 BD |
166 | #define PORT_S3C6400 84 |
167 | ||
5886188d BK |
168 | /* NWPSERIAL */ |
169 | #define PORT_NWPSERIAL 85 | |
170 | ||
1dcb884c CP |
171 | /* MAX3100 */ |
172 | #define PORT_MAX3100 86 | |
173 | ||
34aec591 RR |
174 | /* Timberdale UART */ |
175 | #define PORT_TIMBUART 87 | |
176 | ||
04896a77 RL |
177 | /* Qualcomm MSM SoCs */ |
178 | #define PORT_MSM 88 | |
179 | ||
9fcd66e5 MB |
180 | /* BCM63xx family SoCs */ |
181 | #define PORT_BCM63XX 89 | |
182 | ||
d4ac42a5 KG |
183 | /* Aeroflex Gaisler GRLIB APBUART */ |
184 | #define PORT_APBUART 90 | |
185 | ||
5bcd6010 TK |
186 | /* Altera UARTs */ |
187 | #define PORT_ALTERA_JTAGUART 91 | |
6b7d8f8b | 188 | #define PORT_ALTERA_UART 92 |
5bcd6010 | 189 | |
75b93489 GL |
190 | /* SH-SCI */ |
191 | #define PORT_SCIFB 93 | |
192 | ||
61fd1526 AC |
193 | /* MAX3107 */ |
194 | #define PORT_MAX3107 94 | |
195 | ||
d843fc6e FT |
196 | /* High Speed UART for Medfield */ |
197 | #define PORT_MFD 95 | |
61fd1526 | 198 | |
1da177e4 LT |
199 | #ifdef __KERNEL__ |
200 | ||
661f83a6 | 201 | #include <linux/compiler.h> |
1da177e4 LT |
202 | #include <linux/interrupt.h> |
203 | #include <linux/circ_buf.h> | |
204 | #include <linux/spinlock.h> | |
205 | #include <linux/sched.h> | |
206 | #include <linux/tty.h> | |
e2862f6a | 207 | #include <linux/mutex.h> |
b11115c1 | 208 | #include <linux/sysrq.h> |
1da177e4 LT |
209 | |
210 | struct uart_port; | |
1da177e4 LT |
211 | struct serial_struct; |
212 | struct device; | |
213 | ||
214 | /* | |
215 | * This structure describes all the operations that can be | |
216 | * done on the physical hardware. | |
217 | */ | |
218 | struct uart_ops { | |
219 | unsigned int (*tx_empty)(struct uart_port *); | |
220 | void (*set_mctrl)(struct uart_port *, unsigned int mctrl); | |
221 | unsigned int (*get_mctrl)(struct uart_port *); | |
b129a8cc RK |
222 | void (*stop_tx)(struct uart_port *); |
223 | void (*start_tx)(struct uart_port *); | |
1da177e4 LT |
224 | void (*send_xchar)(struct uart_port *, char ch); |
225 | void (*stop_rx)(struct uart_port *); | |
226 | void (*enable_ms)(struct uart_port *); | |
227 | void (*break_ctl)(struct uart_port *, int ctl); | |
228 | int (*startup)(struct uart_port *); | |
229 | void (*shutdown)(struct uart_port *); | |
6bb0e3a5 | 230 | void (*flush_buffer)(struct uart_port *); |
606d099c AC |
231 | void (*set_termios)(struct uart_port *, struct ktermios *new, |
232 | struct ktermios *old); | |
d87d9b7d | 233 | void (*set_ldisc)(struct uart_port *, int new); |
1da177e4 LT |
234 | void (*pm)(struct uart_port *, unsigned int state, |
235 | unsigned int oldstate); | |
236 | int (*set_wake)(struct uart_port *, unsigned int state); | |
237 | ||
238 | /* | |
239 | * Return a string describing the type of the port | |
240 | */ | |
241 | const char *(*type)(struct uart_port *); | |
242 | ||
243 | /* | |
244 | * Release IO and memory resources used by the port. | |
245 | * This includes iounmap if necessary. | |
246 | */ | |
247 | void (*release_port)(struct uart_port *); | |
248 | ||
249 | /* | |
250 | * Request IO and memory resources used by the port. | |
251 | * This includes iomapping the port if necessary. | |
252 | */ | |
253 | int (*request_port)(struct uart_port *); | |
254 | void (*config_port)(struct uart_port *, int); | |
255 | int (*verify_port)(struct uart_port *, struct serial_struct *); | |
256 | int (*ioctl)(struct uart_port *, unsigned int, unsigned long); | |
f2d937f3 JW |
257 | #ifdef CONFIG_CONSOLE_POLL |
258 | void (*poll_put_char)(struct uart_port *, unsigned char); | |
259 | int (*poll_get_char)(struct uart_port *); | |
260 | #endif | |
1da177e4 LT |
261 | }; |
262 | ||
f5316b4a | 263 | #define NO_POLL_CHAR 0x00ff0000 |
1da177e4 LT |
264 | #define UART_CONFIG_TYPE (1 << 0) |
265 | #define UART_CONFIG_IRQ (1 << 1) | |
266 | ||
267 | struct uart_icount { | |
268 | __u32 cts; | |
269 | __u32 dsr; | |
270 | __u32 rng; | |
271 | __u32 dcd; | |
272 | __u32 rx; | |
273 | __u32 tx; | |
274 | __u32 frame; | |
275 | __u32 overrun; | |
276 | __u32 parity; | |
277 | __u32 brk; | |
278 | __u32 buf_overrun; | |
279 | }; | |
280 | ||
0077d45e RK |
281 | typedef unsigned int __bitwise__ upf_t; |
282 | ||
1da177e4 LT |
283 | struct uart_port { |
284 | spinlock_t lock; /* port lock */ | |
0c8946d9 | 285 | unsigned long iobase; /* in/out[bwl] */ |
1da177e4 | 286 | unsigned char __iomem *membase; /* read/write[bwl] */ |
7d6a07d1 DD |
287 | unsigned int (*serial_in)(struct uart_port *, int); |
288 | void (*serial_out)(struct uart_port *, int, int); | |
235dae5d PL |
289 | void (*set_termios)(struct uart_port *, |
290 | struct ktermios *new, | |
291 | struct ktermios *old); | |
c161afe9 ML |
292 | void (*pm)(struct uart_port *, unsigned int state, |
293 | unsigned int old); | |
1da177e4 | 294 | unsigned int irq; /* irq number */ |
1c2f0493 | 295 | unsigned long irqflags; /* irq flags */ |
1da177e4 | 296 | unsigned int uartclk; /* base uart clock */ |
947deee8 | 297 | unsigned int fifosize; /* tx fifo size */ |
1da177e4 LT |
298 | unsigned char x_char; /* xon/xoff char */ |
299 | unsigned char regshift; /* reg offset shift */ | |
300 | unsigned char iotype; /* io access style */ | |
947deee8 | 301 | unsigned char unused1; |
1da177e4 LT |
302 | |
303 | #define UPIO_PORT (0) | |
304 | #define UPIO_HUB6 (1) | |
305 | #define UPIO_MEM (2) | |
306 | #define UPIO_MEM32 (3) | |
21c614a7 | 307 | #define UPIO_AU (4) /* Au1x00 type IO */ |
3be91ec7 | 308 | #define UPIO_TSI (5) /* Tsi108/109 type IO */ |
beab697a | 309 | #define UPIO_DWAPB (6) /* DesignWare APB UART */ |
bd71c182 | 310 | #define UPIO_RM9000 (7) /* RM9000 type IO */ |
1da177e4 LT |
311 | |
312 | unsigned int read_status_mask; /* driver specific */ | |
313 | unsigned int ignore_status_mask; /* driver specific */ | |
ebd2c8f6 | 314 | struct uart_state *state; /* pointer to parent state */ |
1da177e4 LT |
315 | struct uart_icount icount; /* statistics */ |
316 | ||
317 | struct console *cons; /* struct console, if any */ | |
06e82df0 | 318 | #if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ) |
1da177e4 LT |
319 | unsigned long sysrq; /* sysrq timeout */ |
320 | #endif | |
321 | ||
0077d45e RK |
322 | upf_t flags; |
323 | ||
324 | #define UPF_FOURPORT ((__force upf_t) (1 << 1)) | |
325 | #define UPF_SAK ((__force upf_t) (1 << 2)) | |
326 | #define UPF_SPD_MASK ((__force upf_t) (0x1030)) | |
327 | #define UPF_SPD_HI ((__force upf_t) (0x0010)) | |
328 | #define UPF_SPD_VHI ((__force upf_t) (0x0020)) | |
329 | #define UPF_SPD_CUST ((__force upf_t) (0x0030)) | |
330 | #define UPF_SPD_SHI ((__force upf_t) (0x1000)) | |
331 | #define UPF_SPD_WARP ((__force upf_t) (0x1010)) | |
332 | #define UPF_SKIP_TEST ((__force upf_t) (1 << 6)) | |
333 | #define UPF_AUTO_IRQ ((__force upf_t) (1 << 7)) | |
334 | #define UPF_HARDPPS_CD ((__force upf_t) (1 << 11)) | |
335 | #define UPF_LOW_LATENCY ((__force upf_t) (1 << 13)) | |
336 | #define UPF_BUGGY_UART ((__force upf_t) (1 << 14)) | |
b6adea33 | 337 | #define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15)) |
0077d45e RK |
338 | #define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16)) |
339 | #define UPF_CONS_FLOW ((__force upf_t) (1 << 23)) | |
340 | #define UPF_SHARE_IRQ ((__force upf_t) (1 << 24)) | |
8e23fcc8 DD |
341 | /* The exact UART type is known and should not be probed. */ |
342 | #define UPF_FIXED_TYPE ((__force upf_t) (1 << 27)) | |
0077d45e | 343 | #define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28)) |
abb4a239 | 344 | #define UPF_FIXED_PORT ((__force upf_t) (1 << 29)) |
68ac64cd | 345 | #define UPF_DEAD ((__force upf_t) (1 << 30)) |
0077d45e RK |
346 | #define UPF_IOREMAP ((__force upf_t) (1 << 31)) |
347 | ||
348 | #define UPF_CHANGE_MASK ((__force upf_t) (0x17fff)) | |
349 | #define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY)) | |
1da177e4 LT |
350 | |
351 | unsigned int mctrl; /* current modem ctrl settings */ | |
352 | unsigned int timeout; /* character-based timeout */ | |
353 | unsigned int type; /* port type */ | |
ba899dbc | 354 | const struct uart_ops *ops; |
1da177e4 LT |
355 | unsigned int custom_divisor; |
356 | unsigned int line; /* port index */ | |
4f640efb | 357 | resource_size_t mapbase; /* for ioremap */ |
1da177e4 LT |
358 | struct device *dev; /* parent device */ |
359 | unsigned char hub6; /* this should be in the 8250 driver */ | |
b3b708fa GL |
360 | unsigned char suspended; |
361 | unsigned char unused[2]; | |
beab697a | 362 | void *private_data; /* generic platform data pointer */ |
1da177e4 LT |
363 | }; |
364 | ||
ebd2c8f6 AC |
365 | /* |
366 | * This is the state information which is persistent across opens. | |
ebd2c8f6 AC |
367 | */ |
368 | struct uart_state { | |
df4f4dd4 | 369 | struct tty_port port; |
ebd2c8f6 | 370 | |
ebd2c8f6 | 371 | int pm_state; |
1da177e4 | 372 | struct circ_buf xmit; |
1da177e4 | 373 | |
1da177e4 | 374 | struct tasklet_struct tlet; |
ebd2c8f6 | 375 | struct uart_port *uart_port; |
f751928e AC |
376 | }; |
377 | ||
378 | #define UART_XMIT_SIZE PAGE_SIZE | |
379 | ||
380 | ||
1da177e4 LT |
381 | /* number of characters left in xmit buffer before we ask for more */ |
382 | #define WAKEUP_CHARS 256 | |
383 | ||
384 | struct module; | |
385 | struct tty_driver; | |
386 | ||
387 | struct uart_driver { | |
388 | struct module *owner; | |
389 | const char *driver_name; | |
390 | const char *dev_name; | |
1da177e4 LT |
391 | int major; |
392 | int minor; | |
393 | int nr; | |
394 | struct console *cons; | |
395 | ||
396 | /* | |
397 | * these are private; the low level driver should not | |
398 | * touch these; they should be initialised to NULL | |
399 | */ | |
400 | struct uart_state *state; | |
401 | struct tty_driver *tty_driver; | |
402 | }; | |
403 | ||
404 | void uart_write_wakeup(struct uart_port *port); | |
405 | ||
406 | /* | |
407 | * Baud rate helpers. | |
408 | */ | |
409 | void uart_update_timeout(struct uart_port *port, unsigned int cflag, | |
410 | unsigned int baud); | |
606d099c AC |
411 | unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios, |
412 | struct ktermios *old, unsigned int min, | |
1da177e4 LT |
413 | unsigned int max); |
414 | unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud); | |
415 | ||
54381067 AV |
416 | /* Base timer interval for polling */ |
417 | static inline int uart_poll_timeout(struct uart_port *port) | |
418 | { | |
419 | int timeout = port->timeout; | |
420 | ||
421 | return timeout > 6 ? (timeout / 2 - 2) : 1; | |
422 | } | |
423 | ||
1da177e4 LT |
424 | /* |
425 | * Console helpers. | |
426 | */ | |
427 | struct uart_port *uart_get_console(struct uart_port *ports, int nr, | |
428 | struct console *c); | |
429 | void uart_parse_options(char *options, int *baud, int *parity, int *bits, | |
430 | int *flow); | |
431 | int uart_set_options(struct uart_port *port, struct console *co, int baud, | |
432 | int parity, int bits, int flow); | |
433 | struct tty_driver *uart_console_device(struct console *co, int *index); | |
d358788f RK |
434 | void uart_console_write(struct uart_port *port, const char *s, |
435 | unsigned int count, | |
436 | void (*putchar)(struct uart_port *, int)); | |
1da177e4 LT |
437 | |
438 | /* | |
439 | * Port/driver registration/removal | |
440 | */ | |
441 | int uart_register_driver(struct uart_driver *uart); | |
442 | void uart_unregister_driver(struct uart_driver *uart); | |
1da177e4 LT |
443 | int uart_add_one_port(struct uart_driver *reg, struct uart_port *port); |
444 | int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port); | |
445 | int uart_match_port(struct uart_port *port1, struct uart_port *port2); | |
446 | ||
447 | /* | |
448 | * Power Management | |
449 | */ | |
450 | int uart_suspend_port(struct uart_driver *reg, struct uart_port *port); | |
451 | int uart_resume_port(struct uart_driver *reg, struct uart_port *port); | |
452 | ||
453 | #define uart_circ_empty(circ) ((circ)->head == (circ)->tail) | |
454 | #define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0) | |
455 | ||
456 | #define uart_circ_chars_pending(circ) \ | |
457 | (CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE)) | |
458 | ||
459 | #define uart_circ_chars_free(circ) \ | |
460 | (CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE)) | |
461 | ||
f751928e AC |
462 | static inline int uart_tx_stopped(struct uart_port *port) |
463 | { | |
ebd2c8f6 | 464 | struct tty_struct *tty = port->state->port.tty; |
f751928e AC |
465 | if(tty->stopped || tty->hw_stopped) |
466 | return 1; | |
467 | return 0; | |
468 | } | |
1da177e4 LT |
469 | |
470 | /* | |
471 | * The following are helper functions for the low level drivers. | |
472 | */ | |
1da177e4 | 473 | static inline int |
7d12e780 | 474 | uart_handle_sysrq_char(struct uart_port *port, unsigned int ch) |
1da177e4 | 475 | { |
93c37f29 | 476 | #ifdef SUPPORT_SYSRQ |
1da177e4 LT |
477 | if (port->sysrq) { |
478 | if (ch && time_before(jiffies, port->sysrq)) { | |
f335397d | 479 | handle_sysrq(ch); |
1da177e4 LT |
480 | port->sysrq = 0; |
481 | return 1; | |
482 | } | |
483 | port->sysrq = 0; | |
484 | } | |
93c37f29 | 485 | #endif |
1da177e4 LT |
486 | return 0; |
487 | } | |
4e149184 | 488 | #ifndef SUPPORT_SYSRQ |
7d12e780 | 489 | #define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0) |
4e149184 | 490 | #endif |
1da177e4 LT |
491 | |
492 | /* | |
493 | * We do the SysRQ and SAK checking like this... | |
494 | */ | |
495 | static inline int uart_handle_break(struct uart_port *port) | |
496 | { | |
ebd2c8f6 | 497 | struct uart_state *state = port->state; |
1da177e4 LT |
498 | #ifdef SUPPORT_SYSRQ |
499 | if (port->cons && port->cons->index == port->line) { | |
500 | if (!port->sysrq) { | |
501 | port->sysrq = jiffies + HZ*5; | |
502 | return 1; | |
503 | } | |
504 | port->sysrq = 0; | |
505 | } | |
506 | #endif | |
27ae7a74 | 507 | if (port->flags & UPF_SAK) |
ebd2c8f6 | 508 | do_SAK(state->port.tty); |
1da177e4 LT |
509 | return 0; |
510 | } | |
511 | ||
512 | /** | |
513 | * uart_handle_dcd_change - handle a change of carrier detect state | |
1b9894f3 | 514 | * @uport: uart_port structure for the open port |
1da177e4 LT |
515 | * @status: new carrier detect status, nonzero if active |
516 | */ | |
517 | static inline void | |
ccce6deb | 518 | uart_handle_dcd_change(struct uart_port *uport, unsigned int status) |
1da177e4 | 519 | { |
ccce6deb AC |
520 | struct uart_state *state = uport->state; |
521 | struct tty_port *port = &state->port; | |
a0880df0 RG |
522 | struct tty_ldisc *ld = tty_ldisc_ref(port->tty); |
523 | struct timespec ts; | |
1da177e4 | 524 | |
a0880df0 RG |
525 | if (ld && ld->ops->dcd_change) |
526 | getnstimeofday(&ts); | |
1da177e4 | 527 | |
a0880df0 | 528 | uport->icount.dcd++; |
1da177e4 | 529 | #ifdef CONFIG_HARD_PPS |
ccce6deb | 530 | if ((uport->flags & UPF_HARDPPS_CD) && status) |
1da177e4 LT |
531 | hardpps(); |
532 | #endif | |
533 | ||
ccce6deb | 534 | if (port->flags & ASYNC_CHECK_CD) { |
1da177e4 | 535 | if (status) |
ccce6deb AC |
536 | wake_up_interruptible(&port->open_wait); |
537 | else if (port->tty) | |
538 | tty_hangup(port->tty); | |
1da177e4 | 539 | } |
a0880df0 RG |
540 | |
541 | if (ld && ld->ops->dcd_change) | |
542 | ld->ops->dcd_change(port->tty, status, &ts); | |
543 | if (ld) | |
544 | tty_ldisc_deref(ld); | |
1da177e4 LT |
545 | } |
546 | ||
547 | /** | |
548 | * uart_handle_cts_change - handle a change of clear-to-send state | |
1b9894f3 | 549 | * @uport: uart_port structure for the open port |
1da177e4 LT |
550 | * @status: new clear to send status, nonzero if active |
551 | */ | |
552 | static inline void | |
ccce6deb | 553 | uart_handle_cts_change(struct uart_port *uport, unsigned int status) |
1da177e4 | 554 | { |
ccce6deb AC |
555 | struct tty_port *port = &uport->state->port; |
556 | struct tty_struct *tty = port->tty; | |
1da177e4 | 557 | |
ccce6deb | 558 | uport->icount.cts++; |
1da177e4 | 559 | |
ccce6deb | 560 | if (port->flags & ASYNC_CTS_FLOW) { |
1da177e4 LT |
561 | if (tty->hw_stopped) { |
562 | if (status) { | |
563 | tty->hw_stopped = 0; | |
ccce6deb AC |
564 | uport->ops->start_tx(uport); |
565 | uart_write_wakeup(uport); | |
1da177e4 LT |
566 | } |
567 | } else { | |
568 | if (!status) { | |
569 | tty->hw_stopped = 1; | |
ccce6deb | 570 | uport->ops->stop_tx(uport); |
1da177e4 LT |
571 | } |
572 | } | |
573 | } | |
574 | } | |
575 | ||
05ab3014 RK |
576 | #include <linux/tty_flip.h> |
577 | ||
578 | static inline void | |
579 | uart_insert_char(struct uart_port *port, unsigned int status, | |
580 | unsigned int overrun, unsigned int ch, unsigned int flag) | |
581 | { | |
ebd2c8f6 | 582 | struct tty_struct *tty = port->state->port.tty; |
05ab3014 RK |
583 | |
584 | if ((status & port->ignore_status_mask & ~overrun) == 0) | |
585 | tty_insert_flip_char(tty, ch, flag); | |
586 | ||
587 | /* | |
588 | * Overrun is special. Since it's reported immediately, | |
589 | * it doesn't affect the current character. | |
590 | */ | |
591 | if (status & ~port->ignore_status_mask & overrun) | |
592 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
593 | } | |
594 | ||
1da177e4 LT |
595 | /* |
596 | * UART_ENABLE_MS - determine if port should enable modem status irqs | |
597 | */ | |
598 | #define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD || \ | |
599 | (cflag) & CRTSCTS || \ | |
600 | !((cflag) & CLOCAL)) | |
601 | ||
602 | #endif | |
603 | ||
604 | #endif /* LINUX_SERIAL_CORE_H */ |