[deliverable/linux.git] / include / linux / serial_sci.h

#ifndef __LINUX_SERIAL_SCI_H
#define __LINUX_SERIAL_SCI_H

#include <linux/serial_core.h>
#include <linux/sh_dma.h>

/*
 * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
 */

#define SCIx_NOT_SUPPORTED	(-1)

enum {
	SCBRR_ALGO_NONE,	/* Compute sampling rate in the driver */
	SCBRR_ALGO_1,		/* clk / (16 * bps) */
	SCBRR_ALGO_2,		/* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
	SCBRR_ALGO_3,		/* clk / (8 * bps) */
	SCBRR_ALGO_4,		/* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
	SCBRR_ALGO_6,		/* HSCIF variable sample rate algorithm */
};

#define SCSCR_TIE	(1 << 7)
#define SCSCR_RIE	(1 << 6)
#define SCSCR_TE	(1 << 5)
#define SCSCR_RE	(1 << 4)
#define SCSCR_REIE	(1 << 3)	/* not supported by all parts */
#define SCSCR_TOIE	(1 << 2)	/* not supported by all parts */
#define SCSCR_CKE1	(1 << 1)
#define SCSCR_CKE0	(1 << 0)

/* SCxSR SCI */
#define SCI_TDRE  0x80
#define SCI_RDRF  0x40
#define SCI_ORER  0x20
#define SCI_FER   0x10
#define SCI_PER   0x08
#define SCI_TEND  0x04

#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)

/* SCxSR SCIF, HSCIF */
#define SCIF_ER    0x0080
#define SCIF_TEND  0x0040
#define SCIF_TDFE  0x0020
#define SCIF_BRK   0x0010
#define SCIF_FER   0x0008
#define SCIF_PER   0x0004
#define SCIF_RDF   0x0002
#define SCIF_DR    0x0001

#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)

/* SCSPTR, optional */
#define SCSPTR_RTSIO	(1 << 7)
#define SCSPTR_CTSIO	(1 << 5)
#define SCSPTR_SPB2IO	(1 << 1)
#define SCSPTR_SPB2DT	(1 << 0)

/* HSSRR HSCIF */
#define HSCIF_SRE	0x8000

/* Offsets into the sci_port->irqs array */
enum {
	SCIx_ERI_IRQ,
	SCIx_RXI_IRQ,
	SCIx_TXI_IRQ,
	SCIx_BRI_IRQ,
	SCIx_NR_IRQS,

	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
};

enum {
	SCIx_PROBE_REGTYPE,

	SCIx_SCI_REGTYPE,
	SCIx_IRDA_REGTYPE,
	SCIx_SCIFA_REGTYPE,
	SCIx_SCIFB_REGTYPE,
	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
	SCIx_SH3_SCIF_REGTYPE,
	SCIx_SH4_SCIF_REGTYPE,
	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
	SCIx_SH7705_SCIF_REGTYPE,
	SCIx_HSCIF_REGTYPE,

	SCIx_NR_REGTYPES,
};

#define SCIx_IRQ_MUXED(irq)		\
{					\
	[SCIx_ERI_IRQ]	= (irq),	\
	[SCIx_RXI_IRQ]	= (irq),	\
	[SCIx_TXI_IRQ]	= (irq),	\
	[SCIx_BRI_IRQ]	= (irq),	\
}

#define SCIx_IRQ_IS_MUXED(port)			\
	((port)->irqs[SCIx_ERI_IRQ] ==	\
	 (port)->irqs[SCIx_RXI_IRQ]) ||	\
	((port)->irqs[SCIx_ERI_IRQ] &&	\
	 ((port)->irqs[SCIx_RXI_IRQ] < 0))
/*
 * SCI register subset common for all port types.
 * Not all registers will exist on all parts.
 */
enum {
	SCSMR, SCBRR, SCSCR, SCxSR,
	SCFCR, SCFDR, SCxTDR, SCxRDR,
	SCLSR, SCTFDR, SCRFDR, SCSPTR,
	HSSRR,

	SCIx_NR_REGS,
};

struct device;

struct plat_sci_port_ops {
	void (*init_pins)(struct uart_port *, unsigned int cflag);
};

/*
 * Port-specific capabilities
 */
#define SCIx_HAVE_RTSCTS	(1 << 0)

/*
 * Platform device specific platform_data struct
 */
struct plat_sci_port {
	unsigned long	mapbase;		/* resource base */
	unsigned int	irqs[SCIx_NR_IRQS];	/* ERI, RXI, TXI, BRI */
	unsigned int	type;			/* SCI / SCIF / IRDA / HSCIF */
	upf_t		flags;			/* UPF_* flags */
	unsigned long	capabilities;		/* Port features/capabilities */

	unsigned int	sampling_rate;
	unsigned int	scbrr_algo_id;		/* SCBRR calculation algo */
	unsigned int	scscr;			/* SCSCR initialization */

	/*
	 * Platform overrides if necessary, defaults otherwise.
	 */
	int		port_reg;
	unsigned char	regshift;
	unsigned char	regtype;

	struct plat_sci_port_ops	*ops;

	unsigned int	dma_slave_tx;
	unsigned int	dma_slave_rx;
};

#endif /* __LINUX_SERIAL_SCI_H */
Commit	Line	Data
96de1a8f PM	1	#ifndef __LINUX_SERIAL_SCI_H
96de1a8f PM	2	#define __LINUX_SERIAL_SCI_H
ecd95616 PM	3
ecd95616 PM	4	#include <linux/serial_core.h>
14baf9d7	5	#include <linux/sh_dma.h>
ecd95616 PM	6
ecd95616 PM	7	/*
4b084784	8	* Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
ecd95616 PM	9	*/
ecd95616 PM	10
debf9507 PM	11	#define SCIx_NOT_SUPPORTED (-1)
debf9507 PM	12
26c92f37	13	enum {
ec09c5eb	14	SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
6557b1f6 LP	15	SCBRR_ALGO_1, /* clk / (16 * bps) */
	16	SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
	17	SCBRR_ALGO_3, /* clk / (8 * bps) */
	18	SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
f303b364	19	SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
26c92f37 PM	20	};
26c92f37 PM	21
00b9de9c PM	22	#define SCSCR_TIE (1 << 7)
	23	#define SCSCR_RIE (1 << 6)
	24	#define SCSCR_TE (1 << 5)
	25	#define SCSCR_RE (1 << 4)
f43dc23d	26	#define SCSCR_REIE (1 << 3) /* not supported by all parts */
00b9de9c PM	27	#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
	28	#define SCSCR_CKE1 (1 << 1)
	29	#define SCSCR_CKE0 (1 << 0)
	30
debf9507 PM	31	/* SCxSR SCI */
	32	#define SCI_TDRE 0x80
	33	#define SCI_RDRF 0x40
	34	#define SCI_ORER 0x20
	35	#define SCI_FER 0x10
	36	#define SCI_PER 0x08
	37	#define SCI_TEND 0x04
	38
	39	#define SCI_DEFAULT_ERROR_MASK (SCI_PER \| SCI_FER)
	40
f303b364	41	/* SCxSR SCIF, HSCIF */
debf9507 PM	42	#define SCIF_ER 0x0080
	43	#define SCIF_TEND 0x0040
	44	#define SCIF_TDFE 0x0020
	45	#define SCIF_BRK 0x0010
	46	#define SCIF_FER 0x0008
	47	#define SCIF_PER 0x0004
	48	#define SCIF_RDF 0x0002
	49	#define SCIF_DR 0x0001
	50
	51	#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER \| SCIF_FER \| SCIF_ER \| SCIF_BRK)
	52
faf02f8f PM	53	/* SCSPTR, optional */
	54	#define SCSPTR_RTSIO (1 << 7)
	55	#define SCSPTR_CTSIO (1 << 5)
bbb4ce50 SY	56	#define SCSPTR_SPB2IO (1 << 1)
bbb4ce50 SY	57	#define SCSPTR_SPB2DT (1 << 0)
faf02f8f	58
f303b364 UH	59	/* HSSRR HSCIF */
	60	#define HSCIF_SRE 0x8000
	61
ecd95616 PM	62	/* Offsets into the sci_port->irqs array */
	63	enum {
	64	SCIx_ERI_IRQ,
	65	SCIx_RXI_IRQ,
	66	SCIx_TXI_IRQ,
	67	SCIx_BRI_IRQ,
	68	SCIx_NR_IRQS,
9174fc8f PM	69
9174fc8f PM	70	SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
ecd95616 PM	71	};
ecd95616 PM	72
61a6976b PM	73	enum {
	74	SCIx_PROBE_REGTYPE,
	75
	76	SCIx_SCI_REGTYPE,
	77	SCIx_IRDA_REGTYPE,
	78	SCIx_SCIFA_REGTYPE,
	79	SCIx_SCIFB_REGTYPE,
3af1f8a4	80	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
61a6976b PM	81	SCIx_SH3_SCIF_REGTYPE,
	82	SCIx_SH4_SCIF_REGTYPE,
	83	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
	84	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
	85	SCIx_SH7705_SCIF_REGTYPE,
f303b364	86	SCIx_HSCIF_REGTYPE,
61a6976b PM	87
	88	SCIx_NR_REGTYPES,
	89	};
	90
22cc8378 PM	91	#define SCIx_IRQ_MUXED(irq) \
	92	{ \
	93	[SCIx_ERI_IRQ] = (irq), \
	94	[SCIx_RXI_IRQ] = (irq), \
	95	[SCIx_TXI_IRQ] = (irq), \
	96	[SCIx_BRI_IRQ] = (irq), \
	97	}
	98
9174fc8f	99	#define SCIx_IRQ_IS_MUXED(port) \
1fcc91a6 LP	100	((port)->irqs[SCIx_ERI_IRQ] == \
	101	(port)->irqs[SCIx_RXI_IRQ]) \|\| \
	102	((port)->irqs[SCIx_ERI_IRQ] && \
	103	((port)->irqs[SCIx_RXI_IRQ] < 0))
61a6976b PM	104	/*
	105	* SCI register subset common for all port types.
	106	* Not all registers will exist on all parts.
	107	*/
	108	enum {
	109	SCSMR, SCBRR, SCSCR, SCxSR,
	110	SCFCR, SCFDR, SCxTDR, SCxRDR,
	111	SCLSR, SCTFDR, SCRFDR, SCSPTR,
f303b364	112	HSSRR,
61a6976b PM	113
	114	SCIx_NR_REGS,
	115	};
	116
73a19e4c GL	117	struct device;
73a19e4c GL	118
61a6976b PM	119	struct plat_sci_port_ops {
	120	void (init_pins)(struct uart_port , unsigned int cflag);
	121	};
	122
faf02f8f PM	123	/*
	124	* Port-specific capabilities
	125	*/
	126	#define SCIx_HAVE_RTSCTS (1 << 0)
	127
ecd95616 PM	128	/*
	129	* Platform device specific platform_data struct
	130	*/
	131	struct plat_sci_port {
ecd95616 PM	132	unsigned long mapbase; /* resource base */
ecd95616 PM	133	unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
f303b364	134	unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
ecd95616	135	upf_t flags; /* UPF_* flags */
faf02f8f	136	unsigned long capabilities; /* Port features/capabilities */
00b9de9c	137
ec09c5eb	138	unsigned int sampling_rate;
26c92f37	139	unsigned int scbrr_algo_id; /* SCBRR calculation algo */
00b9de9c	140	unsigned int scscr; /* SCSCR initialization */
f43dc23d	141
debf9507 PM	142	/*
	143	* Platform overrides if necessary, defaults otherwise.
	144	*/
514820eb	145	int port_reg;
61a6976b PM	146	unsigned char regshift;
	147	unsigned char regtype;
	148
	149	struct plat_sci_port_ops *ops;
514820eb	150
27bd1075 PM	151	unsigned int dma_slave_tx;
27bd1075 PM	152	unsigned int dma_slave_rx;
ecd95616 PM	153	};
ecd95616 PM	154
96de1a8f	155	#endif /* __LINUX_SERIAL_SCI_H */