serial: sh-sci: Avoid FIFO clear for MCE toggle.
[deliverable/linux.git] / include / linux / serial_sci.h
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1#ifndef __LINUX_SERIAL_SCI_H
2#define __LINUX_SERIAL_SCI_H
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3
4#include <linux/serial_core.h>
14baf9d7 5#include <linux/sh_dma.h>
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6
7/*
96de1a8f 8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
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9 */
10
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11#define SCIx_NOT_SUPPORTED (-1)
12
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13enum {
14 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
15 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
16 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
17 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
18 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
19};
20
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21#define SCSCR_TIE (1 << 7)
22#define SCSCR_RIE (1 << 6)
23#define SCSCR_TE (1 << 5)
24#define SCSCR_RE (1 << 4)
f43dc23d 25#define SCSCR_REIE (1 << 3) /* not supported by all parts */
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26#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
27#define SCSCR_CKE1 (1 << 1)
28#define SCSCR_CKE0 (1 << 0)
29
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30/* SCxSR SCI */
31#define SCI_TDRE 0x80
32#define SCI_RDRF 0x40
33#define SCI_ORER 0x20
34#define SCI_FER 0x10
35#define SCI_PER 0x08
36#define SCI_TEND 0x04
37
38#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
39
40/* SCxSR SCIF */
41#define SCIF_ER 0x0080
42#define SCIF_TEND 0x0040
43#define SCIF_TDFE 0x0020
44#define SCIF_BRK 0x0010
45#define SCIF_FER 0x0008
46#define SCIF_PER 0x0004
47#define SCIF_RDF 0x0002
48#define SCIF_DR 0x0001
49
50#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
51
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52/* SCSPTR, optional */
53#define SCSPTR_RTSIO (1 << 7)
54#define SCSPTR_CTSIO (1 << 5)
55
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56/* Offsets into the sci_port->irqs array */
57enum {
58 SCIx_ERI_IRQ,
59 SCIx_RXI_IRQ,
60 SCIx_TXI_IRQ,
61 SCIx_BRI_IRQ,
62 SCIx_NR_IRQS,
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63
64 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
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65};
66
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67enum {
68 SCIx_PROBE_REGTYPE,
69
70 SCIx_SCI_REGTYPE,
71 SCIx_IRDA_REGTYPE,
72 SCIx_SCIFA_REGTYPE,
73 SCIx_SCIFB_REGTYPE,
3af1f8a4 74 SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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75 SCIx_SH3_SCIF_REGTYPE,
76 SCIx_SH4_SCIF_REGTYPE,
77 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
78 SCIx_SH4_SCIF_FIFODATA_REGTYPE,
79 SCIx_SH7705_SCIF_REGTYPE,
80
81 SCIx_NR_REGTYPES,
82};
83
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84#define SCIx_IRQ_MUXED(irq) \
85{ \
86 [SCIx_ERI_IRQ] = (irq), \
87 [SCIx_RXI_IRQ] = (irq), \
88 [SCIx_TXI_IRQ] = (irq), \
89 [SCIx_BRI_IRQ] = (irq), \
90}
91
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92#define SCIx_IRQ_IS_MUXED(port) \
93 ((port)->cfg->irqs[SCIx_ERI_IRQ] == \
94 (port)->cfg->irqs[SCIx_RXI_IRQ]) || \
95 ((port)->cfg->irqs[SCIx_ERI_IRQ] && \
96 !(port)->cfg->irqs[SCIx_RXI_IRQ])
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97/*
98 * SCI register subset common for all port types.
99 * Not all registers will exist on all parts.
100 */
101enum {
102 SCSMR, SCBRR, SCSCR, SCxSR,
103 SCFCR, SCFDR, SCxTDR, SCxRDR,
104 SCLSR, SCTFDR, SCRFDR, SCSPTR,
105
106 SCIx_NR_REGS,
107};
108
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109struct device;
110
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111struct plat_sci_port_ops {
112 void (*init_pins)(struct uart_port *, unsigned int cflag);
113};
114
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115/*
116 * Port-specific capabilities
117 */
118#define SCIx_HAVE_RTSCTS (1 << 0)
119
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120/*
121 * Platform device specific platform_data struct
122 */
123struct plat_sci_port {
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124 unsigned long mapbase; /* resource base */
125 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
126 unsigned int type; /* SCI / SCIF / IRDA */
127 upf_t flags; /* UPF_* flags */
faf02f8f 128 unsigned long capabilities; /* Port features/capabilities */
00b9de9c 129
26c92f37 130 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
00b9de9c 131 unsigned int scscr; /* SCSCR initialization */
f43dc23d 132
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133 /*
134 * Platform overrides if necessary, defaults otherwise.
135 */
136 int overrun_bit;
137 unsigned int error_mask;
138
514820eb 139 int port_reg;
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140 unsigned char regshift;
141 unsigned char regtype;
142
143 struct plat_sci_port_ops *ops;
514820eb 144
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145 unsigned int dma_slave_tx;
146 unsigned int dma_slave_rx;
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147};
148
96de1a8f 149#endif /* __LINUX_SERIAL_SCI_H */
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