[deliverable/linux.git] / include / linux / sh_clk.h

#ifndef __SH_CLOCK_H
#define __SH_CLOCK_H

#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/cpufreq.h>
#include <linux/types.h>
#include <linux/kref.h>
#include <linux/clk.h>
#include <linux/err.h>

struct clk;

struct clk_mapping {
	phys_addr_t		phys;
	void __iomem		*base;
	unsigned long		len;
	struct kref		ref;
};

struct clk_ops {
	void (*init)(struct clk *clk);
	int (*enable)(struct clk *clk);
	void (*disable)(struct clk *clk);
	unsigned long (*recalc)(struct clk *clk);
	int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
	int (*set_parent)(struct clk *clk, struct clk *parent);
	long (*round_rate)(struct clk *clk, unsigned long rate);
};

struct clk {
	struct list_head	node;
	struct clk		*parent;
	struct clk		**parent_table;	/* list of parents to */
	unsigned short		parent_num;	/* choose between */
	unsigned char		src_shift;	/* source clock field in the */
	unsigned char		src_width;	/* configuration register */
	struct clk_ops		*ops;

	struct list_head	children;
	struct list_head	sibling;	/* node for children */

	int			usecount;

	unsigned long		rate;
	unsigned long		flags;

	void __iomem		*enable_reg;
	unsigned int		enable_bit;

	unsigned long		arch_flags;
	void			*priv;
	struct dentry		*dentry;
	struct clk_mapping	*mapping;
	struct cpufreq_frequency_table *freq_table;
};

#define CLK_ENABLE_ON_INIT	(1 << 0)

/* drivers/sh/clk.c */
unsigned long followparent_recalc(struct clk *);
void recalculate_root_clocks(void);
void propagate_rate(struct clk *);
int clk_reparent(struct clk *child, struct clk *parent);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
void clk_enable_init_clocks(void);

/**
 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
 * @clk: clock source
 * @rate: desired clock rate in Hz
 * @algo_id: algorithm id to be passed down to ops->set_rate
 *
 * Returns success (0) or negative errno.
 */
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);

enum clk_sh_algo_id {
	NO_CHANGE = 0,

	IUS_N1_N1,
	IUS_322,
	IUS_522,
	IUS_N11,

	SB_N1,

	SB3_N1,
	SB3_32,
	SB3_43,
	SB3_54,

	BP_N1,

	IP_N1,
};

struct clk_div_mult_table {
	unsigned int *divisors;
	unsigned int nr_divisors;
	unsigned int *multipliers;
	unsigned int nr_multipliers;
};

struct cpufreq_frequency_table;
void clk_rate_table_build(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  int nr_freqs,
			  struct clk_div_mult_table *src_table,
			  unsigned long *bitmap);

long clk_rate_table_round(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  unsigned long rate);

int clk_rate_table_find(struct clk *clk,
			struct cpufreq_frequency_table *freq_table,
			unsigned long rate);

#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags)	\
{									\
	.parent		= _parent,					\
	.enable_reg	= (void __iomem *)_enable_reg,			\
	.enable_bit	= _enable_bit,					\
	.flags		= _flags,					\
}

int sh_clk_mstp32_register(struct clk *clks, int nr);

#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags)	\
{								\
	.parent = _parent,					\
	.enable_reg = (void __iomem *)_reg,			\
	.enable_bit = _shift,					\
	.arch_flags = _div_bitmap,				\
	.flags = _flags,					\
}

struct clk_div4_table {
	struct clk_div_mult_table *div_mult_table;
	void (*kick)(struct clk *clk);
};

int sh_clk_div4_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_enable_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_reparent_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);

#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents,	\
			_num_parents, _src_shift, _src_width)	\
{								\
	.parent = _parent,					\
	.enable_reg = (void __iomem *)_reg,			\
	.flags = _flags,					\
	.parent_table = _parents,				\
	.parent_num = _num_parents,				\
	.src_shift = _src_shift,				\
	.src_width = _src_width,				\
}

#define SH_CLK_DIV6(_parent, _reg, _flags)			\
	SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)

int sh_clk_div6_register(struct clk *clks, int nr);
int sh_clk_div6_reparent_register(struct clk *clks, int nr);

#endif /* __SH_CLOCK_H */
Commit	Line	Data
d28bdf05 MD	1	#ifndef __SH_CLOCK_H
	2	#define __SH_CLOCK_H
	3
	4	#include <linux/list.h>
	5	#include <linux/seq_file.h>
	6	#include <linux/cpufreq.h>
28085bc5 PM	7	#include <linux/types.h>
28085bc5 PM	8	#include <linux/kref.h>
d28bdf05 MD	9	#include <linux/clk.h>
	10	#include <linux/err.h>
	11
	12	struct clk;
	13
28085bc5 PM	14	struct clk_mapping {
	15	phys_addr_t phys;
	16	void __iomem *base;
	17	unsigned long len;
	18	struct kref ref;
	19	};
	20
d28bdf05 MD	21	struct clk_ops {
	22	void (init)(struct clk clk);
	23	int (enable)(struct clk clk);
	24	void (disable)(struct clk clk);
	25	unsigned long (recalc)(struct clk clk);
	26	int (set_rate)(struct clk clk, unsigned long rate, int algo_id);
	27	int (set_parent)(struct clk clk, struct clk *parent);
	28	long (round_rate)(struct clk clk, unsigned long rate);
	29	};
	30
	31	struct clk {
	32	struct list_head node;
d28bdf05	33	struct clk *parent;
b5272b50 GL	34	struct clk *parent_table; / list of parents to */
	35	unsigned short parent_num; /* choose between */
	36	unsigned char src_shift; /* source clock field in the */
	37	unsigned char src_width; /* configuration register */
d28bdf05 MD	38	struct clk_ops *ops;
	39
	40	struct list_head children;
	41	struct list_head sibling; /* node for children */
	42
	43	int usecount;
	44
	45	unsigned long rate;
	46	unsigned long flags;
	47
	48	void __iomem *enable_reg;
	49	unsigned int enable_bit;
	50
	51	unsigned long arch_flags;
	52	void *priv;
	53	struct dentry *dentry;
28085bc5	54	struct clk_mapping *mapping;
d28bdf05 MD	55	struct cpufreq_frequency_table *freq_table;
	56	};
	57
	58	#define CLK_ENABLE_ON_INIT (1 << 0)
	59
a71ba096	60	/* drivers/sh/clk.c */
d28bdf05 MD	61	unsigned long followparent_recalc(struct clk *);
	62	void recalculate_root_clocks(void);
	63	void propagate_rate(struct clk *);
	64	int clk_reparent(struct clk child, struct clk parent);
	65	int clk_register(struct clk *);
	66	void clk_unregister(struct clk *);
8b5ee113	67	void clk_enable_init_clocks(void);
d28bdf05	68
d28bdf05 MD	69	/**
	70	* clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
	71	* @clk: clock source
	72	* @rate: desired clock rate in Hz
	73	* @algo_id: algorithm id to be passed down to ops->set_rate
	74	*
	75	* Returns success (0) or negative errno.
	76	*/
	77	int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
	78
	79	enum clk_sh_algo_id {
	80	NO_CHANGE = 0,
	81
	82	IUS_N1_N1,
	83	IUS_322,
	84	IUS_522,
	85	IUS_N11,
	86
	87	SB_N1,
	88
	89	SB3_N1,
	90	SB3_32,
	91	SB3_43,
	92	SB3_54,
	93
	94	BP_N1,
	95
	96	IP_N1,
	97	};
	98
	99	struct clk_div_mult_table {
	100	unsigned int *divisors;
	101	unsigned int nr_divisors;
	102	unsigned int *multipliers;
	103	unsigned int nr_multipliers;
	104	};
	105
	106	struct cpufreq_frequency_table;
	107	void clk_rate_table_build(struct clk *clk,
	108	struct cpufreq_frequency_table *freq_table,
	109	int nr_freqs,
	110	struct clk_div_mult_table *src_table,
	111	unsigned long *bitmap);
	112
	113	long clk_rate_table_round(struct clk *clk,
	114	struct cpufreq_frequency_table *freq_table,
	115	unsigned long rate);
	116
	117	int clk_rate_table_find(struct clk *clk,
	118	struct cpufreq_frequency_table *freq_table,
	119	unsigned long rate);
	120
	121	#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
	122	{ \
	123	.parent = _parent, \
	124	.enable_reg = (void __iomem *)_enable_reg, \
	125	.enable_bit = _enable_bit, \
	126	.flags = _flags, \
	127	}
	128
	129	int sh_clk_mstp32_register(struct clk *clks, int nr);
	130
	131	#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
	132	{ \
133	.parent = _parent, \
134	.enable_reg = (void __iomem *)_reg, \
135	.enable_bit = _shift, \
136	.arch_flags = _div_bitmap, \
137	.flags = _flags, \
138	}
139
140	struct clk_div4_table {
141	struct clk_div_mult_table *div_mult_table;
142	void (kick)(struct clk clk);
143	};
144
145	int sh_clk_div4_register(struct clk *clks, int nr,
146	struct clk_div4_table *table);
147	int sh_clk_div4_enable_register(struct clk *clks, int nr,
148	struct clk_div4_table *table);
149	int sh_clk_div4_reparent_register(struct clk *clks, int nr,
150	struct clk_div4_table *table);
151
b3dd51a8 GL	152	#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \
	153	_num_parents, _src_shift, _src_width) \
	154	{ \
	155	.parent = _parent, \
	156	.enable_reg = (void __iomem *)_reg, \
	157	.flags = _flags, \
	158	.parent_table = _parents, \
	159	.parent_num = _num_parents, \
	160	.src_shift = _src_shift, \
	161	.src_width = _src_width, \
d28bdf05 MD	162	}
d28bdf05 MD	163
b3dd51a8 GL	164	#define SH_CLK_DIV6(_parent, _reg, _flags) \
	165	SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)
	166
d28bdf05	167	int sh_clk_div6_register(struct clk *clks, int nr);
b3dd51a8	168	int sh_clk_div6_reparent_register(struct clk *clks, int nr);
d28bdf05 MD	169
d28bdf05 MD	170	#endif /* __SH_CLOCK_H */