[deliverable/linux.git] / include / linux / sh_clk.h

#ifndef __SH_CLOCK_H
#define __SH_CLOCK_H

#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/cpufreq.h>
#include <linux/types.h>
#include <linux/kref.h>
#include <linux/clk.h>
#include <linux/err.h>

struct clk;

struct clk_mapping {
	phys_addr_t		phys;
	void __iomem		*base;
	unsigned long		len;
	struct kref		ref;
};

#define sh_clk_ops clk_ops

struct clk_ops {
#ifdef CONFIG_SH_CLK_CPG_LEGACY
	void (*init)(struct clk *clk);
#endif
	int (*enable)(struct clk *clk);
	void (*disable)(struct clk *clk);
	unsigned long (*recalc)(struct clk *clk);
	int (*set_rate)(struct clk *clk, unsigned long rate);
	int (*set_parent)(struct clk *clk, struct clk *parent);
	long (*round_rate)(struct clk *clk, unsigned long rate);
};

struct clk {
	struct list_head	node;
	struct clk		*parent;
	struct clk		**parent_table;	/* list of parents to */
	unsigned short		parent_num;	/* choose between */
	unsigned char		src_shift;	/* source clock field in the */
	unsigned char		src_width;	/* configuration register */
	struct clk_ops		*ops;

	struct list_head	children;
	struct list_head	sibling;	/* node for children */

	int			usecount;

	unsigned long		rate;
	unsigned long		flags;

	void __iomem		*enable_reg;
	unsigned int		enable_bit;
	void __iomem		*mapped_reg;

	unsigned long		arch_flags;
	void			*priv;
	struct clk_mapping	*mapping;
	struct cpufreq_frequency_table *freq_table;
	unsigned int		nr_freqs;
};

#define CLK_ENABLE_ON_INIT	(1 << 0)

/* drivers/sh/clk.c */
unsigned long followparent_recalc(struct clk *);
void recalculate_root_clocks(void);
void propagate_rate(struct clk *);
int clk_reparent(struct clk *child, struct clk *parent);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
void clk_enable_init_clocks(void);

struct clk_div_mult_table {
	unsigned int *divisors;
	unsigned int nr_divisors;
	unsigned int *multipliers;
	unsigned int nr_multipliers;
};

struct cpufreq_frequency_table;
void clk_rate_table_build(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  int nr_freqs,
			  struct clk_div_mult_table *src_table,
			  unsigned long *bitmap);

long clk_rate_table_round(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  unsigned long rate);

int clk_rate_table_find(struct clk *clk,
			struct cpufreq_frequency_table *freq_table,
			unsigned long rate);

long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
			      unsigned int div_max, unsigned long rate);

long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
			       unsigned int mult_max, unsigned long rate);

long clk_round_parent(struct clk *clk, unsigned long target,
		      unsigned long *best_freq, unsigned long *parent_freq,
		      unsigned int div_min, unsigned int div_max);

#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags)	\
{									\
	.parent		= _parent,					\
	.enable_reg	= (void __iomem *)_enable_reg,			\
	.enable_bit	= _enable_bit,					\
	.flags		= _flags,					\
}

int sh_clk_mstp32_register(struct clk *clks, int nr);

#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags)	\
{								\
	.parent = _parent,					\
	.enable_reg = (void __iomem *)_reg,			\
	.enable_bit = _shift,					\
	.arch_flags = _div_bitmap,				\
	.flags = _flags,					\
}

struct clk_div4_table {
	struct clk_div_mult_table *div_mult_table;
	void (*kick)(struct clk *clk);
};

int sh_clk_div4_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_enable_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_reparent_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);

#define SH_CLK_DIV6_EXT(_reg, _flags, _parents,			\
			_num_parents, _src_shift, _src_width)	\
{								\
	.enable_reg = (void __iomem *)_reg,			\
	.flags = _flags,					\
	.parent_table = _parents,				\
	.parent_num = _num_parents,				\
	.src_shift = _src_shift,				\
	.src_width = _src_width,				\
}

#define SH_CLK_DIV6(_parent, _reg, _flags)			\
{								\
	.parent		= _parent,				\
	.enable_reg	= (void __iomem *)_reg,			\
	.flags		= _flags,				\
}

int sh_clk_div6_register(struct clk *clks, int nr);
int sh_clk_div6_reparent_register(struct clk *clks, int nr);

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }

#endif /* __SH_CLOCK_H */
Commit	Line	Data
d28bdf05 MD	1	#ifndef __SH_CLOCK_H
	2	#define __SH_CLOCK_H
	3
	4	#include <linux/list.h>
	5	#include <linux/seq_file.h>
	6	#include <linux/cpufreq.h>
28085bc5 PM	7	#include <linux/types.h>
28085bc5 PM	8	#include <linux/kref.h>
d28bdf05 MD	9	#include <linux/clk.h>
	10	#include <linux/err.h>
	11
	12	struct clk;
	13
28085bc5 PM	14	struct clk_mapping {
	15	phys_addr_t phys;
	16	void __iomem *base;
	17	unsigned long len;
	18	struct kref ref;
	19	};
	20
e3482829 MD	21	#define sh_clk_ops clk_ops
e3482829 MD	22
d28bdf05	23	struct clk_ops {
549015c3	24	#ifdef CONFIG_SH_CLK_CPG_LEGACY
d28bdf05	25	void (init)(struct clk clk);
549015c3	26	#endif
d28bdf05 MD	27	int (enable)(struct clk clk);
	28	void (disable)(struct clk clk);
	29	unsigned long (recalc)(struct clk clk);
35a96c73	30	int (set_rate)(struct clk clk, unsigned long rate);
d28bdf05 MD	31	int (set_parent)(struct clk clk, struct clk *parent);
	32	long (round_rate)(struct clk clk, unsigned long rate);
	33	};
	34
	35	struct clk {
	36	struct list_head node;
d28bdf05	37	struct clk *parent;
b5272b50 GL	38	struct clk *parent_table; / list of parents to */
	39	unsigned short parent_num; /* choose between */
	40	unsigned char src_shift; /* source clock field in the */
	41	unsigned char src_width; /* configuration register */
d28bdf05 MD	42	struct clk_ops *ops;
	43
	44	struct list_head children;
	45	struct list_head sibling; /* node for children */
	46
	47	int usecount;
	48
	49	unsigned long rate;
	50	unsigned long flags;
	51
	52	void __iomem *enable_reg;
	53	unsigned int enable_bit;
eda2030a	54	void __iomem *mapped_reg;
d28bdf05 MD	55
	56	unsigned long arch_flags;
	57	void *priv;
28085bc5	58	struct clk_mapping *mapping;
d28bdf05	59	struct cpufreq_frequency_table *freq_table;
f586903d	60	unsigned int nr_freqs;
d28bdf05 MD	61	};
	62
	63	#define CLK_ENABLE_ON_INIT (1 << 0)
	64
a71ba096	65	/* drivers/sh/clk.c */
d28bdf05 MD	66	unsigned long followparent_recalc(struct clk *);
	67	void recalculate_root_clocks(void);
	68	void propagate_rate(struct clk *);
	69	int clk_reparent(struct clk child, struct clk parent);
	70	int clk_register(struct clk *);
	71	void clk_unregister(struct clk *);
8b5ee113	72	void clk_enable_init_clocks(void);
d28bdf05	73
d28bdf05 MD	74	struct clk_div_mult_table {
	75	unsigned int *divisors;
	76	unsigned int nr_divisors;
	77	unsigned int *multipliers;
	78	unsigned int nr_multipliers;
	79	};
	80
	81	struct cpufreq_frequency_table;
	82	void clk_rate_table_build(struct clk *clk,
	83	struct cpufreq_frequency_table *freq_table,
	84	int nr_freqs,
	85	struct clk_div_mult_table *src_table,
	86	unsigned long *bitmap);
	87
	88	long clk_rate_table_round(struct clk *clk,
	89	struct cpufreq_frequency_table *freq_table,
	90	unsigned long rate);
	91
	92	int clk_rate_table_find(struct clk *clk,
	93	struct cpufreq_frequency_table *freq_table,
	94	unsigned long rate);
	95
8e122db6 PM	96	long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
	97	unsigned int div_max, unsigned long rate);
	98
dd2c0ca1 KM	99	long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
	100	unsigned int mult_max, unsigned long rate);
	101
6af26c6c GL	102	long clk_round_parent(struct clk *clk, unsigned long target,
	103	unsigned long best_freq, unsigned long parent_freq,
	104	unsigned int div_min, unsigned int div_max);
	105
d28bdf05 MD	106	#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
	107	{ \
	108	.parent = _parent, \
	109	.enable_reg = (void __iomem *)_enable_reg, \
	110	.enable_bit = _enable_bit, \
	111	.flags = _flags, \
	112	}
	113
	114	int sh_clk_mstp32_register(struct clk *clks, int nr);
	115
	116	#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
	117	{ \
	118	.parent = _parent, \
	119	.enable_reg = (void __iomem *)_reg, \
	120	.enable_bit = _shift, \
	121	.arch_flags = _div_bitmap, \
	122	.flags = _flags, \
	123	}
	124
	125	struct clk_div4_table {
	126	struct clk_div_mult_table *div_mult_table;
	127	void (kick)(struct clk clk);
	128	};
	129
	130	int sh_clk_div4_register(struct clk *clks, int nr,
	131	struct clk_div4_table *table);
	132	int sh_clk_div4_enable_register(struct clk *clks, int nr,
	133	struct clk_div4_table *table);
	134	int sh_clk_div4_reparent_register(struct clk *clks, int nr,
	135	struct clk_div4_table *table);
	136
56242a1f	137	#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
b3dd51a8 GL	138	_num_parents, _src_shift, _src_width) \
b3dd51a8 GL	139	{ \
b3dd51a8 GL	140	.enable_reg = (void __iomem *)_reg, \
	141	.flags = _flags, \
	142	.parent_table = _parents, \
	143	.parent_num = _num_parents, \
	144	.src_shift = _src_shift, \
	145	.src_width = _src_width, \
d28bdf05 MD	146	}
d28bdf05 MD	147
b3dd51a8	148	#define SH_CLK_DIV6(_parent, _reg, _flags) \
56242a1f KM	149	{ \
	150	.parent = _parent, \
	151	.enable_reg = (void __iomem *)_reg, \
	152	.flags = _flags, \
	153	}
b3dd51a8	154
d28bdf05	155	int sh_clk_div6_register(struct clk *clks, int nr);
b3dd51a8	156	int sh_clk_div6_reparent_register(struct clk *clks, int nr);
d28bdf05	157
1522043b KM	158	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	159	#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
	160	#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
	161
d28bdf05	162	#endif /* __SH_CLOCK_H */