[deliverable/linux.git] / include / linux / sh_dma.h

/*
 * Header for the new SH dmaengine driver
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef SH_DMA_H
#define SH_DMA_H

#include <linux/dmaengine.h>
#include <linux/list.h>
#include <linux/shdma-base.h>

/* Used by slave DMA clients to request DMA to/from a specific peripheral */
struct sh_dmae_slave {
	union {
		unsigned int		slave_id; /* Set by the platform */
		struct shdma_slave	shdma_slave;
	};
	struct device			*dma_dev; /* Set by the platform */
	const struct sh_dmae_slave_config	*config;  /* Set by the driver */
};

struct sh_dmae_regs {
	u32 sar; /* SAR / source address */
	u32 dar; /* DAR / destination address */
	u32 tcr; /* TCR / transfer count */
};

struct sh_desc {
	struct sh_dmae_regs hw;
	struct list_head node;
	struct dma_async_tx_descriptor async_tx;
	enum dma_transfer_direction direction;
	dma_cookie_t cookie;
	size_t partial;
	int chunks;
	int mark;
};

struct sh_dmae_slave_config {
	unsigned int			slave_id;
	dma_addr_t			addr;
	u32				chcr;
	char				mid_rid;
};

struct sh_dmae_channel {
	unsigned int	offset;
	unsigned int	dmars;
	unsigned int	dmars_bit;
	unsigned int	chclr_offset;
};

struct sh_dmae_pdata {
	const struct sh_dmae_slave_config *slave;
	int slave_num;
	const struct sh_dmae_channel *channel;
	int channel_num;
	unsigned int ts_low_shift;
	unsigned int ts_low_mask;
	unsigned int ts_high_shift;
	unsigned int ts_high_mask;
	const unsigned int *ts_shift;
	int ts_shift_num;
	u16 dmaor_init;
	unsigned int chcr_offset;
	u32 chcr_ie_bit;

	unsigned int dmaor_is_32bit:1;
	unsigned int needs_tend_set:1;
	unsigned int no_dmars:1;
	unsigned int chclr_present:1;
	unsigned int slave_only:1;
};

/* DMA register */
#define SAR	0x00
#define DAR	0x04
#define TCR	0x08
#define CHCR	0x0C
#define DMAOR	0x40

#define TEND	0x18 /* USB-DMAC */

/* DMAOR definitions */
#define DMAOR_AE	0x00000004
#define DMAOR_NMIF	0x00000002
#define DMAOR_DME	0x00000001

/* Definitions for the SuperH DMAC */
#define REQ_L	0x00000000
#define REQ_E	0x00080000
#define RACK_H	0x00000000
#define RACK_L	0x00040000
#define ACK_R	0x00000000
#define ACK_W	0x00020000
#define ACK_H	0x00000000
#define ACK_L	0x00010000
#define DM_INC	0x00004000
#define DM_DEC	0x00008000
#define DM_FIX	0x0000c000
#define SM_INC	0x00001000
#define SM_DEC	0x00002000
#define SM_FIX	0x00003000
#define RS_IN	0x00000200
#define RS_OUT	0x00000300
#define TS_BLK	0x00000040
#define TM_BUR	0x00000020
#define CHCR_DE	0x00000001
#define CHCR_TE	0x00000002
#define CHCR_IE	0x00000004

#endif
Commit	Line	Data
b2623a61 MD	1	/*
	2	* Header for the new SH dmaengine driver
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef SH_DMA_H
	11	#define SH_DMA_H
	12
b2623a61	13	#include <linux/dmaengine.h>
5902c9a7 GL	14	#include <linux/list.h>
5902c9a7 GL	15	#include <linux/shdma-base.h>
b2623a61 MD	16
	17	/* Used by slave DMA clients to request DMA to/from a specific peripheral */
	18	struct sh_dmae_slave {
5902c9a7 GL	19	union {
	20	unsigned int slave_id; /* Set by the platform */
	21	struct shdma_slave shdma_slave;
	22	};
b2623a61	23	struct device dma_dev; / Set by the platform */
5bac942d	24	const struct sh_dmae_slave_config config; / Set by the driver */
b2623a61 MD	25	};
	26
	27	struct sh_dmae_regs {
	28	u32 sar; /* SAR / source address */
	29	u32 dar; /* DAR / destination address */
	30	u32 tcr; /* TCR / transfer count */
	31	};
	32
	33	struct sh_desc {
	34	struct sh_dmae_regs hw;
	35	struct list_head node;
	36	struct dma_async_tx_descriptor async_tx;
db8196df	37	enum dma_transfer_direction direction;
b2623a61 MD	38	dma_cookie_t cookie;
	39	size_t partial;
	40	int chunks;
	41	int mark;
	42	};
5bac942d	43
b2623a61 MD	44	struct sh_dmae_slave_config {
	45	unsigned int slave_id;
	46	dma_addr_t addr;
	47	u32 chcr;
	48	char mid_rid;
	49	};
	50
	51	struct sh_dmae_channel {
	52	unsigned int offset;
	53	unsigned int dmars;
	54	unsigned int dmars_bit;
c11b46c3	55	unsigned int chclr_offset;
b2623a61 MD	56	};
	57
	58	struct sh_dmae_pdata {
5bac942d	59	const struct sh_dmae_slave_config *slave;
b2623a61	60	int slave_num;
5bac942d	61	const struct sh_dmae_channel *channel;
b2623a61 MD	62	int channel_num;
	63	unsigned int ts_low_shift;
	64	unsigned int ts_low_mask;
	65	unsigned int ts_high_shift;
	66	unsigned int ts_high_mask;
5bac942d	67	const unsigned int *ts_shift;
b2623a61 MD	68	int ts_shift_num;
b2623a61 MD	69	u16 dmaor_init;
5899a723	70	unsigned int chcr_offset;
67c6269e	71	u32 chcr_ie_bit;
e76c3af8 KM	72
e76c3af8 KM	73	unsigned int dmaor_is_32bit:1;
260bf2c5 KM	74	unsigned int needs_tend_set:1;
260bf2c5 KM	75	unsigned int no_dmars:1;
c11b46c3	76	unsigned int chclr_present:1;
e9c8d7a0	77	unsigned int slave_only:1;
b2623a61 MD	78	};
	79
	80	/* DMA register */
	81	#define SAR 0x00
	82	#define DAR 0x04
	83	#define TCR 0x08
	84	#define CHCR 0x0C
	85	#define DMAOR 0x40
	86
260bf2c5 KM	87	#define TEND 0x18 /* USB-DMAC */
260bf2c5 KM	88
b2623a61 MD	89	/* DMAOR definitions */
	90	#define DMAOR_AE 0x00000004
	91	#define DMAOR_NMIF 0x00000002
	92	#define DMAOR_DME 0x00000001
	93
	94	/* Definitions for the SuperH DMAC */
	95	#define REQ_L 0x00000000
	96	#define REQ_E 0x00080000
	97	#define RACK_H 0x00000000
	98	#define RACK_L 0x00040000
	99	#define ACK_R 0x00000000
	100	#define ACK_W 0x00020000
	101	#define ACK_H 0x00000000
	102	#define ACK_L 0x00010000
	103	#define DM_INC 0x00004000
	104	#define DM_DEC 0x00008000
	105	#define DM_FIX 0x0000c000
	106	#define SM_INC 0x00001000
	107	#define SM_DEC 0x00002000
	108	#define SM_FIX 0x00003000
	109	#define RS_IN 0x00000200
	110	#define RS_OUT 0x00000300
	111	#define TS_BLK 0x00000040
	112	#define TM_BUR 0x00000020
	113	#define CHCR_DE 0x00000001
	114	#define CHCR_TE 0x00000002
	115	#define CHCR_IE 0x00000004
	116
	117	#endif