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bbfbd8b1 PM |
1 | #ifndef __SH_INTC_H |
2 | #define __SH_INTC_H | |
3 | ||
4 | typedef unsigned char intc_enum; | |
5 | ||
6 | struct intc_vect { | |
7 | intc_enum enum_id; | |
8 | unsigned short vect; | |
9 | }; | |
10 | ||
11 | #define INTC_VECT(enum_id, vect) { enum_id, vect } | |
12 | #define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq)) | |
13 | ||
14 | struct intc_group { | |
15 | intc_enum enum_id; | |
16 | intc_enum enum_ids[32]; | |
17 | }; | |
18 | ||
19 | #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } } | |
20 | ||
21 | struct intc_mask_reg { | |
22 | unsigned long set_reg, clr_reg, reg_width; | |
23 | intc_enum enum_ids[32]; | |
24 | #ifdef CONFIG_SMP | |
25 | unsigned long smp; | |
26 | #endif | |
27 | }; | |
28 | ||
29 | struct intc_prio_reg { | |
30 | unsigned long set_reg, clr_reg, reg_width, field_width; | |
31 | intc_enum enum_ids[16]; | |
32 | #ifdef CONFIG_SMP | |
33 | unsigned long smp; | |
34 | #endif | |
35 | }; | |
36 | ||
37 | struct intc_sense_reg { | |
38 | unsigned long reg, reg_width, field_width; | |
39 | intc_enum enum_ids[16]; | |
40 | }; | |
41 | ||
42 | #ifdef CONFIG_SMP | |
43 | #define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8) | |
44 | #else | |
45 | #define INTC_SMP(stride, nr) | |
46 | #endif | |
47 | ||
577cd758 | 48 | struct intc_hw_desc { |
bbfbd8b1 PM |
49 | struct intc_vect *vectors; |
50 | unsigned int nr_vectors; | |
51 | struct intc_group *groups; | |
52 | unsigned int nr_groups; | |
53 | struct intc_mask_reg *mask_regs; | |
54 | unsigned int nr_mask_regs; | |
55 | struct intc_prio_reg *prio_regs; | |
56 | unsigned int nr_prio_regs; | |
57 | struct intc_sense_reg *sense_regs; | |
58 | unsigned int nr_sense_regs; | |
bbfbd8b1 PM |
59 | struct intc_mask_reg *ack_regs; |
60 | unsigned int nr_ack_regs; | |
bbfbd8b1 PM |
61 | }; |
62 | ||
63 | #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) | |
577cd758 MD |
64 | #define INTC_HW_DESC(vectors, groups, mask_regs, \ |
65 | prio_regs, sense_regs, ack_regs) \ | |
66 | { \ | |
67 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ | |
68 | _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ | |
69 | _INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \ | |
70 | } | |
71 | ||
72 | struct intc_desc { | |
73 | char *name; | |
d5190953 | 74 | intc_enum force_enable; |
d85429a3 | 75 | intc_enum force_disable; |
577cd758 MD |
76 | struct intc_hw_desc hw; |
77 | }; | |
78 | ||
bbfbd8b1 PM |
79 | #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ |
80 | mask_regs, prio_regs, sense_regs) \ | |
81 | struct intc_desc symbol __initdata = { \ | |
577cd758 MD |
82 | .name = chipname, \ |
83 | .hw = INTC_HW_DESC(vectors, groups, mask_regs, \ | |
84 | prio_regs, sense_regs, NULL), \ | |
bbfbd8b1 PM |
85 | } |
86 | ||
bbfbd8b1 PM |
87 | #define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \ |
88 | mask_regs, prio_regs, sense_regs, ack_regs) \ | |
89 | struct intc_desc symbol __initdata = { \ | |
577cd758 MD |
90 | .name = chipname, \ |
91 | .hw = INTC_HW_DESC(vectors, groups, mask_regs, \ | |
92 | prio_regs, sense_regs, ack_regs), \ | |
bbfbd8b1 | 93 | } |
bbfbd8b1 PM |
94 | |
95 | void __init register_intc_controller(struct intc_desc *desc); | |
96 | int intc_set_priority(unsigned int irq, unsigned int prio); | |
97 | ||
45b9deaf PM |
98 | int reserve_irq_vector(unsigned int irq); |
99 | void reserve_irq_legacy(void); | |
100 | ||
bbfbd8b1 | 101 | #endif /* __SH_INTC_H */ |