[deliverable/linux.git] / include / linux / sh_intc.h

#ifndef __SH_INTC_H
#define __SH_INTC_H

#include <linux/ioport.h>

/*
 * Convert back and forth between INTEVT and IRQ values.
 */
#ifdef CONFIG_CPU_HAS_INTEVT
#define evt2irq(evt)		(((evt) >> 5) - 16)
#define irq2evt(irq)		(((irq) + 16) << 5)
#else
#define evt2irq(evt)		(evt)
#define irq2evt(irq)		(irq)
#endif

typedef unsigned char intc_enum;

struct intc_vect {
	intc_enum enum_id;
	unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }
#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))

struct intc_group {
	intc_enum enum_id;
	intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }

struct intc_subgroup {
	unsigned long reg, reg_width;
	intc_enum parent_id;
	intc_enum enum_ids[32];
};

struct intc_mask_reg {
	unsigned long set_reg, clr_reg, reg_width;
	intc_enum enum_ids[32];
#ifdef CONFIG_INTC_BALANCING
	unsigned long dist_reg;
#endif
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_prio_reg {
	unsigned long set_reg, clr_reg, reg_width, field_width;
	intc_enum enum_ids[16];
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_sense_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

#ifdef CONFIG_INTC_BALANCING
#define INTC_SMP_BALANCING(reg)	.dist_reg = (reg)
#else
#define INTC_SMP_BALANCING(reg)
#endif

#ifdef CONFIG_SMP
#define INTC_SMP(stride, nr)	.smp = (stride) | ((nr) << 8)
#else
#define INTC_SMP(stride, nr)
#endif

struct intc_hw_desc {
	struct intc_vect *vectors;
	unsigned int nr_vectors;
	struct intc_group *groups;
	unsigned int nr_groups;
	struct intc_mask_reg *mask_regs;
	unsigned int nr_mask_regs;
	struct intc_prio_reg *prio_regs;
	unsigned int nr_prio_regs;
	struct intc_sense_reg *sense_regs;
	unsigned int nr_sense_regs;
	struct intc_mask_reg *ack_regs;
	unsigned int nr_ack_regs;
	struct intc_subgroup *subgroups;
	unsigned int nr_subgroups;
};

#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)

#define INTC_HW_DESC(vectors, groups, mask_regs,	\
		     prio_regs,	sense_regs, ack_regs)	\
{							\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),	\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),	\
	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs),	\
}

struct intc_desc {
	char *name;
	struct resource *resource;
	unsigned int num_resources;
	intc_enum force_enable;
	intc_enum force_disable;
	bool skip_syscore_suspend;
	struct intc_hw_desc hw;
};

#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
	mask_regs, prio_regs, sense_regs)				\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, NULL),		\
}

#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,	\
	mask_regs, prio_regs, sense_regs, ack_regs)			\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, ack_regs),		\
}

int register_intc_controller(struct intc_desc *desc);
void reserve_intc_vectors(struct intc_vect *vectors, unsigned int nr_vecs);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
void intc_finalize(void);

#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
static inline int register_intc_userimask(unsigned long addr)
{
	return 0;
}
#endif

#endif /* __SH_INTC_H */
Commit	Line	Data
bbfbd8b1 PM	1	#ifndef __SH_INTC_H
	2	#define __SH_INTC_H
	3
dec710b7 MD	4	#include <linux/ioport.h>
dec710b7 MD	5
7f1e7637 RH	6	/*
	7	* Convert back and forth between INTEVT and IRQ values.
	8	*/
	9	#ifdef CONFIG_CPU_HAS_INTEVT
	10	#define evt2irq(evt) (((evt) >> 5) - 16)
	11	#define irq2evt(irq) (((irq) + 16) << 5)
	12	#else
	13	#define evt2irq(evt) (evt)
	14	#define irq2evt(irq) (irq)
	15	#endif
	16
bbfbd8b1 PM	17	typedef unsigned char intc_enum;
	18
	19	struct intc_vect {
	20	intc_enum enum_id;
	21	unsigned short vect;
	22	};
	23
	24	#define INTC_VECT(enum_id, vect) { enum_id, vect }
	25	#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
	26
	27	struct intc_group {
	28	intc_enum enum_id;
	29	intc_enum enum_ids[32];
	30	};
	31
	32	#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
	33
c1e30ad9 PM	34	struct intc_subgroup {
	35	unsigned long reg, reg_width;
	36	intc_enum parent_id;
	37	intc_enum enum_ids[32];
	38	};
	39
bbfbd8b1 PM	40	struct intc_mask_reg {
	41	unsigned long set_reg, clr_reg, reg_width;
	42	intc_enum enum_ids[32];
dc825b17 PM	43	#ifdef CONFIG_INTC_BALANCING
	44	unsigned long dist_reg;
	45	#endif
bbfbd8b1 PM	46	#ifdef CONFIG_SMP
	47	unsigned long smp;
	48	#endif
	49	};
	50
	51	struct intc_prio_reg {
	52	unsigned long set_reg, clr_reg, reg_width, field_width;
	53	intc_enum enum_ids[16];
	54	#ifdef CONFIG_SMP
	55	unsigned long smp;
	56	#endif
	57	};
	58
	59	struct intc_sense_reg {
	60	unsigned long reg, reg_width, field_width;
	61	intc_enum enum_ids[16];
	62	};
	63
dc825b17 PM	64	#ifdef CONFIG_INTC_BALANCING
	65	#define INTC_SMP_BALANCING(reg) .dist_reg = (reg)
	66	#else
	67	#define INTC_SMP_BALANCING(reg)
	68	#endif
	69
bbfbd8b1	70	#ifdef CONFIG_SMP
dc825b17	71	#define INTC_SMP(stride, nr) .smp = (stride) \| ((nr) << 8)
bbfbd8b1 PM	72	#else
	73	#define INTC_SMP(stride, nr)
	74	#endif
	75
577cd758	76	struct intc_hw_desc {
bbfbd8b1 PM	77	struct intc_vect *vectors;
	78	unsigned int nr_vectors;
	79	struct intc_group *groups;
	80	unsigned int nr_groups;
	81	struct intc_mask_reg *mask_regs;
	82	unsigned int nr_mask_regs;
	83	struct intc_prio_reg *prio_regs;
	84	unsigned int nr_prio_regs;
	85	struct intc_sense_reg *sense_regs;
	86	unsigned int nr_sense_regs;
bbfbd8b1 PM	87	struct intc_mask_reg *ack_regs;
bbfbd8b1 PM	88	unsigned int nr_ack_regs;
c1e30ad9 PM	89	struct intc_subgroup *subgroups;
c1e30ad9 PM	90	unsigned int nr_subgroups;
bbfbd8b1 PM	91	};
bbfbd8b1 PM	92
99870bd7	93	#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)
c1e30ad9	94
577cd758 MD	95	#define INTC_HW_DESC(vectors, groups, mask_regs, \
	96	prio_regs, sense_regs, ack_regs) \
	97	{ \
	98	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	99	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	100	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \
	101	}
	102
	103	struct intc_desc {
	104	char *name;
dec710b7 MD	105	struct resource *resource;
dec710b7 MD	106	unsigned int num_resources;
d5190953	107	intc_enum force_enable;
d85429a3	108	intc_enum force_disable;
0f966d74	109	bool skip_syscore_suspend;
577cd758 MD	110	struct intc_hw_desc hw;
	111	};
	112
bbfbd8b1 PM	113	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
	114	mask_regs, prio_regs, sense_regs) \
	115	struct intc_desc symbol __initdata = { \
577cd758 MD	116	.name = chipname, \
	117	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	118	prio_regs, sense_regs, NULL), \
bbfbd8b1 PM	119	}
bbfbd8b1 PM	120
bbfbd8b1 PM	121	#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
	122	mask_regs, prio_regs, sense_regs, ack_regs) \
	123	struct intc_desc symbol __initdata = { \
577cd758 MD	124	.name = chipname, \
	125	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	126	prio_regs, sense_regs, ack_regs), \
bbfbd8b1	127	}
bbfbd8b1	128
2be6bb0c	129	int register_intc_controller(struct intc_desc *desc);
4bacd796	130	void reserve_intc_vectors(struct intc_vect *vectors, unsigned int nr_vecs);
bbfbd8b1	131	int intc_set_priority(unsigned int irq, unsigned int prio);
d74310d3	132	int intc_irq_lookup(const char *chipname, intc_enum enum_id);
c1e30ad9	133	void intc_finalize(void);
bbfbd8b1	134
43b8774d PM	135	#ifdef CONFIG_INTC_USERIMASK
	136	int register_intc_userimask(unsigned long addr);
	137	#else
	138	static inline int register_intc_userimask(unsigned long addr)
	139	{
	140	return 0;
	141	}
	142	#endif
	143
bbfbd8b1	144	#endif /* __SH_INTC_H */