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fae43399 MD |
1 | /* |
2 | * SuperH Pin Function Controller Support | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #ifndef __SH_PFC_H | |
12 | #define __SH_PFC_H | |
13 | ||
72c7afa1 | 14 | #include <linux/stringify.h> |
fae43399 MD |
15 | #include <asm-generic/gpio.h> |
16 | ||
17 | typedef unsigned short pinmux_enum_t; | |
18 | typedef unsigned short pinmux_flag_t; | |
19 | ||
06d5631f PM |
20 | enum { |
21 | PINMUX_TYPE_NONE, | |
fae43399 | 22 | |
06d5631f PM |
23 | PINMUX_TYPE_FUNCTION, |
24 | PINMUX_TYPE_GPIO, | |
25 | PINMUX_TYPE_OUTPUT, | |
26 | PINMUX_TYPE_INPUT, | |
27 | PINMUX_TYPE_INPUT_PULLUP, | |
28 | PINMUX_TYPE_INPUT_PULLDOWN, | |
29 | ||
30 | PINMUX_FLAG_TYPE, /* must be last */ | |
31 | }; | |
fae43399 MD |
32 | |
33 | #define PINMUX_FLAG_DBIT_SHIFT 5 | |
34 | #define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) | |
35 | #define PINMUX_FLAG_DREG_SHIFT 10 | |
36 | #define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) | |
37 | ||
38 | struct pinmux_gpio { | |
39 | pinmux_enum_t enum_id; | |
40 | pinmux_flag_t flags; | |
72c7afa1 | 41 | const char *name; |
fae43399 MD |
42 | }; |
43 | ||
06d5631f | 44 | #define PINMUX_GPIO(gpio, data_or_mark) \ |
72c7afa1 | 45 | [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE } |
06d5631f | 46 | |
fae43399 MD |
47 | #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 |
48 | ||
49 | struct pinmux_cfg_reg { | |
50 | unsigned long reg, reg_width, field_width; | |
51 | unsigned long *cnt; | |
52 | pinmux_enum_t *enum_ids; | |
f78a26f5 | 53 | unsigned long *var_field_width; |
fae43399 MD |
54 | }; |
55 | ||
56 | #define PINMUX_CFG_REG(name, r, r_width, f_width) \ | |
57 | .reg = r, .reg_width = r_width, .field_width = f_width, \ | |
58 | .cnt = (unsigned long [r_width / f_width]) {}, \ | |
f78a26f5 MD |
59 | .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) |
60 | ||
61 | #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ | |
62 | .reg = r, .reg_width = r_width, \ | |
63 | .cnt = (unsigned long [r_width]) {}, \ | |
64 | .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ | |
65 | .enum_ids = (pinmux_enum_t []) | |
fae43399 MD |
66 | |
67 | struct pinmux_data_reg { | |
68 | unsigned long reg, reg_width, reg_shadow; | |
69 | pinmux_enum_t *enum_ids; | |
b0e10211 | 70 | void __iomem *mapped_reg; |
fae43399 MD |
71 | }; |
72 | ||
73 | #define PINMUX_DATA_REG(name, r, r_width) \ | |
74 | .reg = r, .reg_width = r_width, \ | |
75 | .enum_ids = (pinmux_enum_t [r_width]) \ | |
76 | ||
ad2a8e7e MD |
77 | struct pinmux_irq { |
78 | int irq; | |
79 | pinmux_enum_t *enum_ids; | |
80 | }; | |
81 | ||
82 | #define PINMUX_IRQ(irq_nr, ids...) \ | |
83 | { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \ | |
84 | ||
fae43399 MD |
85 | struct pinmux_range { |
86 | pinmux_enum_t begin; | |
87 | pinmux_enum_t end; | |
88 | pinmux_enum_t force; | |
89 | }; | |
90 | ||
d4e62d00 | 91 | struct sh_pfc_platform_data { |
fae43399 MD |
92 | char *name; |
93 | pinmux_enum_t reserved_id; | |
94 | struct pinmux_range data; | |
95 | struct pinmux_range input; | |
96 | struct pinmux_range input_pd; | |
97 | struct pinmux_range input_pu; | |
98 | struct pinmux_range output; | |
99 | struct pinmux_range mark; | |
100 | struct pinmux_range function; | |
101 | ||
102 | unsigned first_gpio, last_gpio; | |
103 | ||
104 | struct pinmux_gpio *gpios; | |
105 | struct pinmux_cfg_reg *cfg_regs; | |
106 | struct pinmux_data_reg *data_regs; | |
107 | ||
108 | pinmux_enum_t *gpio_data; | |
109 | unsigned int gpio_data_size; | |
110 | ||
ad2a8e7e MD |
111 | struct pinmux_irq *gpio_irq; |
112 | unsigned int gpio_irq_size; | |
113 | ||
b0e10211 MD |
114 | struct resource *resource; |
115 | unsigned int num_resources; | |
b0e10211 | 116 | |
e499ada8 | 117 | unsigned long unlock_reg; |
fae43399 MD |
118 | }; |
119 | ||
b3c185a7 | 120 | /* XXX compat for now */ |
d4e62d00 | 121 | #define pinmux_info sh_pfc_platform_data |
b3c185a7 | 122 | |
afae021a | 123 | /* drivers/sh/pfc/core.c */ |
d4e62d00 | 124 | int register_sh_pfc(struct sh_pfc_platform_data *pfc); |
b3c185a7 | 125 | |
b3c185a7 PM |
126 | /* xxx */ |
127 | static inline int register_pinmux(struct pinmux_info *pip) | |
128 | { | |
d4e62d00 LP |
129 | struct sh_pfc_platform_data *pdata = pip; |
130 | return register_sh_pfc(pdata); | |
b3c185a7 PM |
131 | } |
132 | ||
133 | enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; | |
fae43399 | 134 | |
972c3fb6 KM |
135 | /* helper macro for port */ |
136 | #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) | |
137 | ||
138 | #define PORT_10(fn, pfx, sfx) \ | |
139 | PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ | |
140 | PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ | |
141 | PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ | |
142 | PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ | |
143 | PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) | |
144 | ||
145 | #define PORT_90(fn, pfx, sfx) \ | |
146 | PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ | |
147 | PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ | |
148 | PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ | |
149 | PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ | |
150 | PORT_10(fn, pfx##9, sfx) | |
151 | ||
152 | #define _PORT_ALL(pfx, sfx) pfx##_##sfx | |
153 | #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) | |
154 | #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) | |
155 | #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) | |
156 | #define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) | |
157 | ||
bd8d0cba KM |
158 | /* helper macro for pinmux_enum_t */ |
159 | #define PORT_DATA_I(nr) \ | |
160 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) | |
161 | ||
162 | #define PORT_DATA_I_PD(nr) \ | |
163 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | |
164 | PORT##nr##_IN, PORT##nr##_IN_PD) | |
165 | ||
166 | #define PORT_DATA_I_PU(nr) \ | |
167 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | |
168 | PORT##nr##_IN, PORT##nr##_IN_PU) | |
169 | ||
170 | #define PORT_DATA_I_PU_PD(nr) \ | |
171 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | |
172 | PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) | |
173 | ||
174 | #define PORT_DATA_O(nr) \ | |
175 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) | |
176 | ||
177 | #define PORT_DATA_IO(nr) \ | |
178 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ | |
179 | PORT##nr##_IN) | |
180 | ||
181 | #define PORT_DATA_IO_PD(nr) \ | |
182 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ | |
183 | PORT##nr##_IN, PORT##nr##_IN_PD) | |
184 | ||
185 | #define PORT_DATA_IO_PU(nr) \ | |
186 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ | |
187 | PORT##nr##_IN, PORT##nr##_IN_PU) | |
188 | ||
189 | #define PORT_DATA_IO_PU_PD(nr) \ | |
190 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ | |
191 | PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) | |
192 | ||
9b49139b KM |
193 | /* helper macro for top 4 bits in PORTnCR */ |
194 | #define _PCRH(in, in_pd, in_pu, out) \ | |
195 | 0, (out), (in), 0, \ | |
196 | 0, 0, 0, 0, \ | |
197 | 0, 0, (in_pd), 0, \ | |
198 | 0, 0, (in_pu), 0 | |
199 | ||
200 | #define PORTCR(nr, reg) \ | |
201 | { \ | |
202 | PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ | |
203 | _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ | |
204 | PORT##nr##_IN_PU, PORT##nr##_OUT), \ | |
205 | PORT##nr##_FN0, PORT##nr##_FN1, \ | |
206 | PORT##nr##_FN2, PORT##nr##_FN3, \ | |
207 | PORT##nr##_FN4, PORT##nr##_FN5, \ | |
208 | PORT##nr##_FN6, PORT##nr##_FN7 } \ | |
209 | } | |
bd8d0cba | 210 | |
fae43399 | 211 | #endif /* __SH_PFC_H */ |