[deliverable/linux.git] / include / linux / spi / mxs-spi.h

/*
 * include/linux/spi/mxs-spi.h
 *
 * Freescale i.MX233/i.MX28 SPI controller register definition
 *
 * Copyright 2008 Embedded Alley Solutions, Inc.
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef __LINUX_SPI_MXS_SPI_H__
#define __LINUX_SPI_MXS_SPI_H__

#include <linux/dmaengine.h>

#define ssp_is_old(host)	((host)->devid == IMX23_SSP)

/* SSP registers */
#define HW_SSP_CTRL0				0x000
#define  BM_SSP_CTRL0_RUN			(1 << 29)
#define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
#define  BM_SSP_CTRL0_LOCK_CS			(1 << 27)
#define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)
#define  BM_SSP_CTRL0_READ			(1 << 25)
#define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)
#define  BP_SSP_CTRL0_BUS_WIDTH			22
#define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)
#define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)
#define  BM_SSP_CTRL0_WAIT_FOR_CMD		(1 << 20)
#define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)
#define  BM_SSP_CTRL0_GET_RESP			(1 << 17)
#define  BM_SSP_CTRL0_ENABLE			(1 << 16)
#define  BP_SSP_CTRL0_XFER_COUNT		0
#define  BM_SSP_CTRL0_XFER_COUNT		0xffff
#define HW_SSP_CMD0				0x010
#define  BM_SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
#define  BM_SSP_CMD0_SLOW_CLKING_EN		(1 << 22)
#define  BM_SSP_CMD0_CONT_CLKING_EN		(1 << 21)
#define  BM_SSP_CMD0_APPEND_8CYC		(1 << 20)
#define  BP_SSP_CMD0_BLOCK_SIZE			16
#define  BM_SSP_CMD0_BLOCK_SIZE			(0xf << 16)
#define  BP_SSP_CMD0_BLOCK_COUNT		8
#define  BM_SSP_CMD0_BLOCK_COUNT		(0xff << 8)
#define  BP_SSP_CMD0_CMD			0
#define  BM_SSP_CMD0_CMD			0xff
#define HW_SSP_CMD1				0x020
#define HW_SSP_XFER_SIZE			0x030
#define HW_SSP_BLOCK_SIZE			0x040
#define  BP_SSP_BLOCK_SIZE_BLOCK_COUNT		4
#define  BM_SSP_BLOCK_SIZE_BLOCK_COUNT		(0xffffff << 4)
#define  BP_SSP_BLOCK_SIZE_BLOCK_SIZE		0
#define  BM_SSP_BLOCK_SIZE_BLOCK_SIZE		0xf
#define HW_SSP_TIMING(h)			(ssp_is_old(h) ? 0x050 : 0x070)
#define  BP_SSP_TIMING_TIMEOUT			16
#define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)
#define  BP_SSP_TIMING_CLOCK_DIVIDE		8
#define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)
#define  BF_SSP_TIMING_CLOCK_DIVIDE(v)		\
			(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
#define  BP_SSP_TIMING_CLOCK_RATE		0
#define  BM_SSP_TIMING_CLOCK_RATE		0xff
#define BF_SSP_TIMING_CLOCK_RATE(v)		\
			(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
#define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)
#define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)
#define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)
#define  BM_SSP_CTRL1_RESP_ERR_IRQ		(1 << 29)
#define  BM_SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN	(1 << 26)
#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN	(1 << 24)
#define  BM_SSP_CTRL1_DATA_CRC_IRQ		(1 << 23)
#define  BM_SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN	(1 << 20)
#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN	(1 << 16)
#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)
#define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)
#define  BM_SSP_CTRL1_PHASE			(1 << 10)
#define  BM_SSP_CTRL1_POLARITY			(1 << 9)
#define  BP_SSP_CTRL1_WORD_LENGTH		4
#define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
#define  BF_SSP_CTRL1_WORD_LENGTH(v)		\
			(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
#define  BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS	0x3
#define  BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS	0x7
#define  BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS	0xF
#define  BP_SSP_CTRL1_SSP_MODE			0
#define  BM_SSP_CTRL1_SSP_MODE			0xf
#define  BF_SSP_CTRL1_SSP_MODE(v)		\
			(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
#define  BV_SSP_CTRL1_SSP_MODE__SPI		0x0
#define  BV_SSP_CTRL1_SSP_MODE__SSI		0x1
#define  BV_SSP_CTRL1_SSP_MODE__SD_MMC		0x3
#define  BV_SSP_CTRL1_SSP_MODE__MS		0x4

#define HW_SSP_DATA(h)				(ssp_is_old(h) ? 0x070 : 0x090)

#define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)
#define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)
#define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
#define HW_SSP_SDRESP3(h)			(ssp_is_old(h) ? 0x0b0 : 0x0d0)
#define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)
#define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)
#define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)
#define  BM_SSP_STATUS_FIFO_EMPTY		(1 << 5)

#define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)

#define SSP_PIO_NUM	3

enum mxs_ssp_id {
	IMX23_SSP,
	IMX28_SSP,
};

struct mxs_ssp {
	struct device			*dev;
	void __iomem			*base;
	struct clk			*clk;
	unsigned int			clk_rate;
	enum mxs_ssp_id			devid;

	struct dma_chan			*dmach;
	unsigned int			dma_dir;
	enum dma_transfer_direction	slave_dirn;
	u32				ssp_pio_words[SSP_PIO_NUM];
};

void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);

#endif	/* __LINUX_SPI_MXS_SPI_H__ */
Commit	Line	Data
8be3d3b2 MV	1	/*
	2	* include/linux/spi/mxs-spi.h
	3	*
	4	* Freescale i.MX233/i.MX28 SPI controller register definition
	5	*
	6	* Copyright 2008 Embedded Alley Solutions, Inc.
	7	* Copyright 2009-2011 Freescale Semiconductor, Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, write to the Free Software Foundation, Inc.,
	21	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	22	*/
	23
	24	#ifndef __LINUX_SPI_MXS_SPI_H__
	25	#define __LINUX_SPI_MXS_SPI_H__
	26
26aafa77	27	#include <linux/dmaengine.h>
65defb9b	28
600a991f	29	#define ssp_is_old(host) ((host)->devid == IMX23_SSP)
8be3d3b2 MV	30
	31	/* SSP registers */
	32	#define HW_SSP_CTRL0 0x000
	33	#define BM_SSP_CTRL0_RUN (1 << 29)
	34	#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
f83b7380	35	#define BM_SSP_CTRL0_LOCK_CS (1 << 27)
8be3d3b2 MV	36	#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
	37	#define BM_SSP_CTRL0_READ (1 << 25)
	38	#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
	39	#define BP_SSP_CTRL0_BUS_WIDTH 22
	40	#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
	41	#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
f83b7380	42	#define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
8be3d3b2 MV	43	#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
	44	#define BM_SSP_CTRL0_GET_RESP (1 << 17)
	45	#define BM_SSP_CTRL0_ENABLE (1 << 16)
	46	#define BP_SSP_CTRL0_XFER_COUNT 0
	47	#define BM_SSP_CTRL0_XFER_COUNT 0xffff
	48	#define HW_SSP_CMD0 0x010
	49	#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
	50	#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
	51	#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
	52	#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
	53	#define BP_SSP_CMD0_BLOCK_SIZE 16
	54	#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
	55	#define BP_SSP_CMD0_BLOCK_COUNT 8
	56	#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
	57	#define BP_SSP_CMD0_CMD 0
	58	#define BM_SSP_CMD0_CMD 0xff
	59	#define HW_SSP_CMD1 0x020
	60	#define HW_SSP_XFER_SIZE 0x030
	61	#define HW_SSP_BLOCK_SIZE 0x040
	62	#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
	63	#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
	64	#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
	65	#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf
	66	#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
	67	#define BP_SSP_TIMING_TIMEOUT 16
	68	#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
	69	#define BP_SSP_TIMING_CLOCK_DIVIDE 8
	70	#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
f83b7380 MV	71	#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
f83b7380 MV	72	(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
8be3d3b2 MV	73	#define BP_SSP_TIMING_CLOCK_RATE 0
8be3d3b2 MV	74	#define BM_SSP_TIMING_CLOCK_RATE 0xff
f83b7380 MV	75	#define BF_SSP_TIMING_CLOCK_RATE(v) \
f83b7380 MV	76	(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
8be3d3b2 MV	77	#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
	78	#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
	79	#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
	80	#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
	81	#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
	82	#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
	83	#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
	84	#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
	85	#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
	86	#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
	87	#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
	88	#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
	89	#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
	90	#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
	91	#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
	92	#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
	93	#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
	94	#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
f83b7380	95	#define BM_SSP_CTRL1_PHASE (1 << 10)
8be3d3b2 MV	96	#define BM_SSP_CTRL1_POLARITY (1 << 9)
	97	#define BP_SSP_CTRL1_WORD_LENGTH 4
	98	#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
f83b7380 MV	99	#define BF_SSP_CTRL1_WORD_LENGTH(v) \
	100	(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
	101	#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
	102	#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
	103	#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
8be3d3b2 MV	104	#define BP_SSP_CTRL1_SSP_MODE 0
8be3d3b2 MV	105	#define BM_SSP_CTRL1_SSP_MODE 0xf
f83b7380 MV	106	#define BF_SSP_CTRL1_SSP_MODE(v) \
	107	(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
	108	#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
	109	#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
	110	#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
	111	#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
	112
	113	#define HW_SSP_DATA(h) (ssp_is_old(h) ? 0x070 : 0x090)
	114
8be3d3b2 MV	115	#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
	116	#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
	117	#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
	118	#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
	119	#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
	120	#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
	121	#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
f83b7380	122	#define BM_SSP_STATUS_FIFO_EMPTY (1 << 5)
8be3d3b2 MV	123
	124	#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
	125
	126	#define SSP_PIO_NUM 3
	127
600a991f MV	128	enum mxs_ssp_id {
	129	IMX23_SSP,
	130	IMX28_SSP,
8be3d3b2 MV	131	};
8be3d3b2 MV	132
829c1bf4 MV	133	struct mxs_ssp {
	134	struct device *dev;
	135	void __iomem *base;
	136	struct clk *clk;
	137	unsigned int clk_rate;
	138	enum mxs_ssp_id devid;
65defb9b	139
65defb9b	140	struct dma_chan *dmach;
65defb9b MV	141	unsigned int dma_dir;
	142	enum dma_transfer_direction slave_dirn;
	143	u32 ssp_pio_words[SSP_PIO_NUM];
829c1bf4 MV	144	};
829c1bf4 MV	145
13082398 MV	146	void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);
13082398 MV	147
8be3d3b2	148	#endif /* __LINUX_SPI_MXS_SPI_H__ */