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8ae12a0d DB |
1 | /* |
2 | * Copyright (C) 2005 David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_SPI_H | |
20 | #define __LINUX_SPI_H | |
21 | ||
22 | /* | |
b885244e | 23 | * INTERFACES between SPI master-side drivers and SPI infrastructure. |
8ae12a0d | 24 | * (There's no SPI slave support for Linux yet...) |
8ae12a0d DB |
25 | */ |
26 | extern struct bus_type spi_bus_type; | |
27 | ||
28 | /** | |
29 | * struct spi_device - Master side proxy for an SPI slave device | |
30 | * @dev: Driver model representation of the device. | |
31 | * @master: SPI controller used with the device. | |
32 | * @max_speed_hz: Maximum clock rate to be used with this chip | |
33 | * (on this board); may be changed by the device's driver. | |
4cff33f9 | 34 | * The spi_transfer.speed_hz can override this for each transfer. |
8ae12a0d DB |
35 | * @chip-select: Chipselect, distinguishing chips handled by "master". |
36 | * @mode: The spi mode defines how data is clocked out and in. | |
37 | * This may be changed by the device's driver. | |
ccf77cc4 DB |
38 | * The "active low" default for chipselect mode can be overridden, |
39 | * as can the "MSB first" default for each word in a transfer. | |
8ae12a0d | 40 | * @bits_per_word: Data transfers involve one or more words; word sizes |
747d844e | 41 | * like eight or 12 bits are common. In-memory wordsizes are |
8ae12a0d | 42 | * powers of two bytes (e.g. 20 bit samples use 32 bits). |
ccf77cc4 DB |
43 | * This may be changed by the device's driver, or left at the |
44 | * default (0) indicating protocol words are eight bit bytes. | |
4cff33f9 | 45 | * The spi_transfer.bits_per_word can override this for each transfer. |
8ae12a0d | 46 | * @irq: Negative, or the number passed to request_irq() to receive |
747d844e | 47 | * interrupts from this device. |
8ae12a0d | 48 | * @controller_state: Controller's runtime state |
b885244e | 49 | * @controller_data: Board-specific definitions for controller, such as |
747d844e | 50 | * FIFO initialization parameters; from board_info.controller_data |
8ae12a0d DB |
51 | * |
52 | * An spi_device is used to interchange data between an SPI slave | |
53 | * (usually a discrete chip) and CPU memory. | |
54 | * | |
55 | * In "dev", the platform_data is used to hold information about this | |
56 | * device that's meaningful to the device's protocol driver, but not | |
57 | * to its controller. One example might be an identifier for a chip | |
58 | * variant with slightly different functionality. | |
59 | */ | |
60 | struct spi_device { | |
61 | struct device dev; | |
62 | struct spi_master *master; | |
63 | u32 max_speed_hz; | |
64 | u8 chip_select; | |
65 | u8 mode; | |
b885244e DB |
66 | #define SPI_CPHA 0x01 /* clock phase */ |
67 | #define SPI_CPOL 0x02 /* clock polarity */ | |
0c868461 DB |
68 | #define SPI_MODE_0 (0|0) /* (original MicroWire) */ |
69 | #define SPI_MODE_1 (0|SPI_CPHA) | |
8ae12a0d DB |
70 | #define SPI_MODE_2 (SPI_CPOL|0) |
71 | #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) | |
b885244e | 72 | #define SPI_CS_HIGH 0x04 /* chipselect active high? */ |
ccf77cc4 | 73 | #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ |
8ae12a0d DB |
74 | u8 bits_per_word; |
75 | int irq; | |
76 | void *controller_state; | |
b885244e | 77 | void *controller_data; |
8ae12a0d DB |
78 | const char *modalias; |
79 | ||
80 | // likely need more hooks for more protocol options affecting how | |
b885244e | 81 | // the controller talks to each chip, like: |
8ae12a0d DB |
82 | // - memory packing (12 bit samples into low bits, others zeroed) |
83 | // - priority | |
b885244e | 84 | // - drop chipselect after each word |
8ae12a0d DB |
85 | // - chipselect delays |
86 | // - ... | |
87 | }; | |
88 | ||
89 | static inline struct spi_device *to_spi_device(struct device *dev) | |
90 | { | |
b885244e | 91 | return dev ? container_of(dev, struct spi_device, dev) : NULL; |
8ae12a0d DB |
92 | } |
93 | ||
94 | /* most drivers won't need to care about device refcounting */ | |
95 | static inline struct spi_device *spi_dev_get(struct spi_device *spi) | |
96 | { | |
97 | return (spi && get_device(&spi->dev)) ? spi : NULL; | |
98 | } | |
99 | ||
100 | static inline void spi_dev_put(struct spi_device *spi) | |
101 | { | |
102 | if (spi) | |
103 | put_device(&spi->dev); | |
104 | } | |
105 | ||
106 | /* ctldata is for the bus_master driver's runtime state */ | |
107 | static inline void *spi_get_ctldata(struct spi_device *spi) | |
108 | { | |
109 | return spi->controller_state; | |
110 | } | |
111 | ||
112 | static inline void spi_set_ctldata(struct spi_device *spi, void *state) | |
113 | { | |
114 | spi->controller_state = state; | |
115 | } | |
116 | ||
9b40ff4d BD |
117 | /* device driver data */ |
118 | ||
119 | static inline void spi_set_drvdata(struct spi_device *spi, void *data) | |
120 | { | |
121 | dev_set_drvdata(&spi->dev, data); | |
122 | } | |
123 | ||
124 | static inline void *spi_get_drvdata(struct spi_device *spi) | |
125 | { | |
126 | return dev_get_drvdata(&spi->dev); | |
127 | } | |
8ae12a0d DB |
128 | |
129 | struct spi_message; | |
130 | ||
131 | ||
b885244e DB |
132 | |
133 | struct spi_driver { | |
134 | int (*probe)(struct spi_device *spi); | |
135 | int (*remove)(struct spi_device *spi); | |
136 | void (*shutdown)(struct spi_device *spi); | |
137 | int (*suspend)(struct spi_device *spi, pm_message_t mesg); | |
138 | int (*resume)(struct spi_device *spi); | |
139 | struct device_driver driver; | |
140 | }; | |
141 | ||
142 | static inline struct spi_driver *to_spi_driver(struct device_driver *drv) | |
143 | { | |
144 | return drv ? container_of(drv, struct spi_driver, driver) : NULL; | |
145 | } | |
146 | ||
147 | extern int spi_register_driver(struct spi_driver *sdrv); | |
148 | ||
149 | static inline void spi_unregister_driver(struct spi_driver *sdrv) | |
150 | { | |
ddc1e975 BD |
151 | if (sdrv) |
152 | driver_unregister(&sdrv->driver); | |
b885244e DB |
153 | } |
154 | ||
155 | ||
8ae12a0d DB |
156 | /** |
157 | * struct spi_master - interface to SPI master controller | |
158 | * @cdev: class interface to this driver | |
159 | * @bus_num: board-specific (and often SOC-specific) identifier for a | |
747d844e | 160 | * given SPI controller. |
b885244e | 161 | * @num_chipselect: chipselects are used to distinguish individual |
747d844e DB |
162 | * SPI slaves, and are numbered from zero to num_chipselects. |
163 | * each slave has a chipselect signal, but it's common that not | |
164 | * every chipselect is connected to a slave. | |
8ae12a0d | 165 | * @setup: updates the device mode and clocking records used by a |
747d844e | 166 | * device's SPI controller; protocol code may call this. |
8ae12a0d DB |
167 | * @transfer: adds a message to the controller's transfer queue. |
168 | * @cleanup: frees controller-specific state | |
169 | * | |
170 | * Each SPI master controller can communicate with one or more spi_device | |
171 | * children. These make a small bus, sharing MOSI, MISO and SCK signals | |
172 | * but not chip select signals. Each device may be configured to use a | |
173 | * different clock rate, since those shared signals are ignored unless | |
174 | * the chip is selected. | |
175 | * | |
176 | * The driver for an SPI controller manages access to those devices through | |
177 | * a queue of spi_message transactions, copyin data between CPU memory and | |
178 | * an SPI slave device). For each such message it queues, it calls the | |
179 | * message's completion function when the transaction completes. | |
180 | */ | |
181 | struct spi_master { | |
07b24630 | 182 | struct class_device cdev; |
8ae12a0d | 183 | |
a020ed75 | 184 | /* other than negative (== assign one dynamically), bus_num is fully |
8ae12a0d | 185 | * board-specific. usually that simplifies to being SOC-specific. |
a020ed75 | 186 | * example: one SOC has three SPI controllers, numbered 0..2, |
8ae12a0d DB |
187 | * and one board's schematics might show it using SPI-2. software |
188 | * would normally use bus_num=2 for that controller. | |
189 | */ | |
a020ed75 | 190 | s16 bus_num; |
8ae12a0d DB |
191 | |
192 | /* chipselects will be integral to many controllers; some others | |
193 | * might use board-specific GPIOs. | |
194 | */ | |
195 | u16 num_chipselect; | |
196 | ||
197 | /* setup mode and clock, etc (spi driver may call many times) */ | |
198 | int (*setup)(struct spi_device *spi); | |
199 | ||
200 | /* bidirectional bulk transfers | |
201 | * | |
202 | * + The transfer() method may not sleep; its main role is | |
203 | * just to add the message to the queue. | |
204 | * + For now there's no remove-from-queue operation, or | |
205 | * any other request management | |
206 | * + To a given spi_device, message queueing is pure fifo | |
207 | * | |
208 | * + The master's main job is to process its message queue, | |
209 | * selecting a chip then transferring data | |
210 | * + If there are multiple spi_device children, the i/o queue | |
211 | * arbitration algorithm is unspecified (round robin, fifo, | |
212 | * priority, reservations, preemption, etc) | |
213 | * | |
214 | * + Chipselect stays active during the entire message | |
215 | * (unless modified by spi_transfer.cs_change != 0). | |
216 | * + The message transfers use clock and SPI mode parameters | |
217 | * previously established by setup() for this device | |
218 | */ | |
219 | int (*transfer)(struct spi_device *spi, | |
220 | struct spi_message *mesg); | |
221 | ||
222 | /* called on release() to free memory provided by spi_master */ | |
0ffa0285 | 223 | void (*cleanup)(struct spi_device *spi); |
8ae12a0d DB |
224 | }; |
225 | ||
0c868461 DB |
226 | static inline void *spi_master_get_devdata(struct spi_master *master) |
227 | { | |
07b24630 | 228 | return class_get_devdata(&master->cdev); |
0c868461 DB |
229 | } |
230 | ||
231 | static inline void spi_master_set_devdata(struct spi_master *master, void *data) | |
232 | { | |
07b24630 | 233 | class_set_devdata(&master->cdev, data); |
0c868461 DB |
234 | } |
235 | ||
236 | static inline struct spi_master *spi_master_get(struct spi_master *master) | |
237 | { | |
07b24630 | 238 | if (!master || !class_device_get(&master->cdev)) |
0c868461 DB |
239 | return NULL; |
240 | return master; | |
241 | } | |
242 | ||
243 | static inline void spi_master_put(struct spi_master *master) | |
244 | { | |
245 | if (master) | |
07b24630 | 246 | class_device_put(&master->cdev); |
0c868461 DB |
247 | } |
248 | ||
249 | ||
8ae12a0d DB |
250 | /* the spi driver core manages memory for the spi_master classdev */ |
251 | extern struct spi_master * | |
252 | spi_alloc_master(struct device *host, unsigned size); | |
253 | ||
254 | extern int spi_register_master(struct spi_master *master); | |
255 | extern void spi_unregister_master(struct spi_master *master); | |
256 | ||
257 | extern struct spi_master *spi_busnum_to_master(u16 busnum); | |
258 | ||
259 | /*---------------------------------------------------------------------------*/ | |
260 | ||
261 | /* | |
262 | * I/O INTERFACE between SPI controller and protocol drivers | |
263 | * | |
264 | * Protocol drivers use a queue of spi_messages, each transferring data | |
265 | * between the controller and memory buffers. | |
266 | * | |
267 | * The spi_messages themselves consist of a series of read+write transfer | |
268 | * segments. Those segments always read the same number of bits as they | |
269 | * write; but one or the other is easily ignored by passing a null buffer | |
270 | * pointer. (This is unlike most types of I/O API, because SPI hardware | |
271 | * is full duplex.) | |
272 | * | |
273 | * NOTE: Allocation of spi_transfer and spi_message memory is entirely | |
274 | * up to the protocol driver, which guarantees the integrity of both (as | |
275 | * well as the data buffers) for as long as the message is queued. | |
276 | */ | |
277 | ||
278 | /** | |
279 | * struct spi_transfer - a read/write buffer pair | |
8275c642 VW |
280 | * @tx_buf: data to be written (dma-safe memory), or NULL |
281 | * @rx_buf: data to be read (dma-safe memory), or NULL | |
282 | * @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped | |
283 | * @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped | |
8ae12a0d | 284 | * @len: size of rx and tx buffers (in bytes) |
4cff33f9 ID |
285 | * @speed_hz: Select a speed other then the device default for this |
286 | * transfer. If 0 the default (from spi_device) is used. | |
287 | * @bits_per_word: select a bits_per_word other then the device default | |
288 | * for this transfer. If 0 the default (from spi_device) is used. | |
8ae12a0d DB |
289 | * @cs_change: affects chipselect after this transfer completes |
290 | * @delay_usecs: microseconds to delay after this transfer before | |
747d844e DB |
291 | * (optionally) changing the chipselect status, then starting |
292 | * the next transfer or completing this spi_message. | |
8275c642 | 293 | * @transfer_list: transfers are sequenced through spi_message.transfers |
8ae12a0d DB |
294 | * |
295 | * SPI transfers always write the same number of bytes as they read. | |
296 | * Protocol drivers should always provide rx_buf and/or tx_buf. | |
297 | * In some cases, they may also want to provide DMA addresses for | |
298 | * the data being transferred; that may reduce overhead, when the | |
299 | * underlying driver uses dma. | |
300 | * | |
4b1badf5 | 301 | * If the transmit buffer is null, zeroes will be shifted out |
8275c642 VW |
302 | * while filling rx_buf. If the receive buffer is null, the data |
303 | * shifted in will be discarded. Only "len" bytes shift out (or in). | |
304 | * It's an error to try to shift out a partial word. (For example, by | |
305 | * shifting out three bytes with word size of sixteen or twenty bits; | |
306 | * the former uses two bytes per word, the latter uses four bytes.) | |
307 | * | |
308 | * All SPI transfers start with the relevant chipselect active. Normally | |
309 | * it stays selected until after the last transfer in a message. Drivers | |
310 | * can affect the chipselect signal using cs_change: | |
8ae12a0d DB |
311 | * |
312 | * (i) If the transfer isn't the last one in the message, this flag is | |
313 | * used to make the chipselect briefly go inactive in the middle of the | |
314 | * message. Toggling chipselect in this way may be needed to terminate | |
315 | * a chip command, letting a single spi_message perform all of group of | |
316 | * chip transactions together. | |
317 | * | |
318 | * (ii) When the transfer is the last one in the message, the chip may | |
319 | * stay selected until the next transfer. This is purely a performance | |
320 | * hint; the controller driver may need to select a different device | |
321 | * for the next message. | |
0c868461 DB |
322 | * |
323 | * The code that submits an spi_message (and its spi_transfers) | |
324 | * to the lower layers is responsible for managing its memory. | |
325 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
326 | * insulate against future API updates. After you submit a message |
327 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
328 | */ |
329 | struct spi_transfer { | |
330 | /* it's ok if tx_buf == rx_buf (right?) | |
331 | * for MicroWire, one buffer must be null | |
0c868461 DB |
332 | * buffers must work with dma_*map_single() calls, unless |
333 | * spi_message.is_dma_mapped reports a pre-existing mapping | |
8ae12a0d DB |
334 | */ |
335 | const void *tx_buf; | |
336 | void *rx_buf; | |
337 | unsigned len; | |
338 | ||
339 | dma_addr_t tx_dma; | |
340 | dma_addr_t rx_dma; | |
341 | ||
342 | unsigned cs_change:1; | |
4cff33f9 | 343 | u8 bits_per_word; |
8ae12a0d | 344 | u16 delay_usecs; |
4cff33f9 | 345 | u32 speed_hz; |
8275c642 VW |
346 | |
347 | struct list_head transfer_list; | |
8ae12a0d DB |
348 | }; |
349 | ||
350 | /** | |
351 | * struct spi_message - one multi-segment SPI transaction | |
8275c642 | 352 | * @transfers: list of transfer segments in this transaction |
8ae12a0d DB |
353 | * @spi: SPI device to which the transaction is queued |
354 | * @is_dma_mapped: if true, the caller provided both dma and cpu virtual | |
355 | * addresses for each transfer buffer | |
356 | * @complete: called to report transaction completions | |
357 | * @context: the argument to complete() when it's called | |
b885244e DB |
358 | * @actual_length: the total number of bytes that were transferred in all |
359 | * successful segments | |
8ae12a0d DB |
360 | * @status: zero for success, else negative errno |
361 | * @queue: for use by whichever driver currently owns the message | |
362 | * @state: for use by whichever driver currently owns the message | |
0c868461 | 363 | * |
8275c642 VW |
364 | * An spi_message is used to execute an atomic sequence of data transfers, |
365 | * each represented by a struct spi_transfer. The sequence is "atomic" | |
366 | * in the sense that no other spi_message may use that SPI bus until that | |
367 | * sequence completes. On some systems, many such sequences can execute as | |
368 | * as single programmed DMA transfer. On all systems, these messages are | |
369 | * queued, and might complete after transactions to other devices. Messages | |
370 | * sent to a given spi_device are alway executed in FIFO order. | |
371 | * | |
0c868461 DB |
372 | * The code that submits an spi_message (and its spi_transfers) |
373 | * to the lower layers is responsible for managing its memory. | |
374 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
375 | * insulate against future API updates. After you submit a message |
376 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
377 | */ |
378 | struct spi_message { | |
747d844e | 379 | struct list_head transfers; |
8ae12a0d DB |
380 | |
381 | struct spi_device *spi; | |
382 | ||
383 | unsigned is_dma_mapped:1; | |
384 | ||
385 | /* REVISIT: we might want a flag affecting the behavior of the | |
386 | * last transfer ... allowing things like "read 16 bit length L" | |
387 | * immediately followed by "read L bytes". Basically imposing | |
388 | * a specific message scheduling algorithm. | |
389 | * | |
390 | * Some controller drivers (message-at-a-time queue processing) | |
391 | * could provide that as their default scheduling algorithm. But | |
b885244e | 392 | * others (with multi-message pipelines) could need a flag to |
8ae12a0d DB |
393 | * tell them about such special cases. |
394 | */ | |
395 | ||
396 | /* completion is reported through a callback */ | |
747d844e | 397 | void (*complete)(void *context); |
8ae12a0d DB |
398 | void *context; |
399 | unsigned actual_length; | |
400 | int status; | |
401 | ||
402 | /* for optional use by whatever driver currently owns the | |
403 | * spi_message ... between calls to spi_async and then later | |
404 | * complete(), that's the spi_master controller driver. | |
405 | */ | |
406 | struct list_head queue; | |
407 | void *state; | |
408 | }; | |
409 | ||
8275c642 VW |
410 | static inline void spi_message_init(struct spi_message *m) |
411 | { | |
412 | memset(m, 0, sizeof *m); | |
413 | INIT_LIST_HEAD(&m->transfers); | |
414 | } | |
415 | ||
416 | static inline void | |
417 | spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) | |
418 | { | |
419 | list_add_tail(&t->transfer_list, &m->transfers); | |
420 | } | |
421 | ||
422 | static inline void | |
423 | spi_transfer_del(struct spi_transfer *t) | |
424 | { | |
425 | list_del(&t->transfer_list); | |
426 | } | |
427 | ||
0c868461 DB |
428 | /* It's fine to embed message and transaction structures in other data |
429 | * structures so long as you don't free them while they're in use. | |
430 | */ | |
431 | ||
432 | static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) | |
433 | { | |
434 | struct spi_message *m; | |
435 | ||
436 | m = kzalloc(sizeof(struct spi_message) | |
437 | + ntrans * sizeof(struct spi_transfer), | |
438 | flags); | |
439 | if (m) { | |
8275c642 VW |
440 | int i; |
441 | struct spi_transfer *t = (struct spi_transfer *)(m + 1); | |
442 | ||
443 | INIT_LIST_HEAD(&m->transfers); | |
444 | for (i = 0; i < ntrans; i++, t++) | |
445 | spi_message_add_tail(t, m); | |
0c868461 DB |
446 | } |
447 | return m; | |
448 | } | |
449 | ||
450 | static inline void spi_message_free(struct spi_message *m) | |
451 | { | |
452 | kfree(m); | |
453 | } | |
454 | ||
8ae12a0d DB |
455 | /** |
456 | * spi_setup -- setup SPI mode and clock rate | |
457 | * @spi: the device whose settings are being modified | |
458 | * | |
459 | * SPI protocol drivers may need to update the transfer mode if the | |
460 | * device doesn't work with the mode 0 default. They may likewise need | |
461 | * to update clock rates or word sizes from initial values. This function | |
462 | * changes those settings, and must be called from a context that can sleep. | |
8275c642 VW |
463 | * The changes take effect the next time the device is selected and data |
464 | * is transferred to or from it. | |
8ae12a0d DB |
465 | */ |
466 | static inline int | |
467 | spi_setup(struct spi_device *spi) | |
468 | { | |
469 | return spi->master->setup(spi); | |
470 | } | |
471 | ||
472 | ||
473 | /** | |
474 | * spi_async -- asynchronous SPI transfer | |
475 | * @spi: device with which data will be exchanged | |
476 | * @message: describes the data transfers, including completion callback | |
477 | * | |
478 | * This call may be used in_irq and other contexts which can't sleep, | |
479 | * as well as from task contexts which can sleep. | |
480 | * | |
481 | * The completion callback is invoked in a context which can't sleep. | |
482 | * Before that invocation, the value of message->status is undefined. | |
483 | * When the callback is issued, message->status holds either zero (to | |
0c868461 DB |
484 | * indicate complete success) or a negative error code. After that |
485 | * callback returns, the driver which issued the transfer request may | |
486 | * deallocate the associated memory; it's no longer in use by any SPI | |
487 | * core or controller driver code. | |
8ae12a0d DB |
488 | * |
489 | * Note that although all messages to a spi_device are handled in | |
490 | * FIFO order, messages may go to different devices in other orders. | |
491 | * Some device might be higher priority, or have various "hard" access | |
492 | * time requirements, for example. | |
b885244e DB |
493 | * |
494 | * On detection of any fault during the transfer, processing of | |
495 | * the entire message is aborted, and the device is deselected. | |
496 | * Until returning from the associated message completion callback, | |
497 | * no other spi_message queued to that device will be processed. | |
498 | * (This rule applies equally to all the synchronous transfer calls, | |
499 | * which are wrappers around this core asynchronous primitive.) | |
8ae12a0d DB |
500 | */ |
501 | static inline int | |
502 | spi_async(struct spi_device *spi, struct spi_message *message) | |
503 | { | |
504 | message->spi = spi; | |
505 | return spi->master->transfer(spi, message); | |
506 | } | |
507 | ||
508 | /*---------------------------------------------------------------------------*/ | |
509 | ||
510 | /* All these synchronous SPI transfer routines are utilities layered | |
511 | * over the core async transfer primitive. Here, "synchronous" means | |
512 | * they will sleep uninterruptibly until the async transfer completes. | |
513 | */ | |
514 | ||
515 | extern int spi_sync(struct spi_device *spi, struct spi_message *message); | |
516 | ||
517 | /** | |
518 | * spi_write - SPI synchronous write | |
519 | * @spi: device to which data will be written | |
520 | * @buf: data buffer | |
521 | * @len: data buffer size | |
522 | * | |
523 | * This writes the buffer and returns zero or a negative error code. | |
524 | * Callable only from contexts that can sleep. | |
525 | */ | |
526 | static inline int | |
527 | spi_write(struct spi_device *spi, const u8 *buf, size_t len) | |
528 | { | |
529 | struct spi_transfer t = { | |
530 | .tx_buf = buf, | |
8ae12a0d | 531 | .len = len, |
8ae12a0d | 532 | }; |
8275c642 | 533 | struct spi_message m; |
8ae12a0d | 534 | |
8275c642 VW |
535 | spi_message_init(&m); |
536 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
537 | return spi_sync(spi, &m); |
538 | } | |
539 | ||
540 | /** | |
541 | * spi_read - SPI synchronous read | |
542 | * @spi: device from which data will be read | |
543 | * @buf: data buffer | |
544 | * @len: data buffer size | |
545 | * | |
546 | * This writes the buffer and returns zero or a negative error code. | |
547 | * Callable only from contexts that can sleep. | |
548 | */ | |
549 | static inline int | |
550 | spi_read(struct spi_device *spi, u8 *buf, size_t len) | |
551 | { | |
552 | struct spi_transfer t = { | |
8ae12a0d DB |
553 | .rx_buf = buf, |
554 | .len = len, | |
8ae12a0d | 555 | }; |
8275c642 | 556 | struct spi_message m; |
8ae12a0d | 557 | |
8275c642 VW |
558 | spi_message_init(&m); |
559 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
560 | return spi_sync(spi, &m); |
561 | } | |
562 | ||
0c868461 | 563 | /* this copies txbuf and rxbuf data; for small transfers only! */ |
8ae12a0d DB |
564 | extern int spi_write_then_read(struct spi_device *spi, |
565 | const u8 *txbuf, unsigned n_tx, | |
566 | u8 *rxbuf, unsigned n_rx); | |
567 | ||
568 | /** | |
569 | * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read | |
570 | * @spi: device with which data will be exchanged | |
571 | * @cmd: command to be written before data is read back | |
572 | * | |
573 | * This returns the (unsigned) eight bit number returned by the | |
574 | * device, or else a negative error code. Callable only from | |
575 | * contexts that can sleep. | |
576 | */ | |
577 | static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) | |
578 | { | |
579 | ssize_t status; | |
580 | u8 result; | |
581 | ||
582 | status = spi_write_then_read(spi, &cmd, 1, &result, 1); | |
583 | ||
584 | /* return negative errno or unsigned value */ | |
585 | return (status < 0) ? status : result; | |
586 | } | |
587 | ||
588 | /** | |
589 | * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read | |
590 | * @spi: device with which data will be exchanged | |
591 | * @cmd: command to be written before data is read back | |
592 | * | |
593 | * This returns the (unsigned) sixteen bit number returned by the | |
594 | * device, or else a negative error code. Callable only from | |
595 | * contexts that can sleep. | |
596 | * | |
597 | * The number is returned in wire-order, which is at least sometimes | |
598 | * big-endian. | |
599 | */ | |
600 | static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) | |
601 | { | |
602 | ssize_t status; | |
603 | u16 result; | |
604 | ||
605 | status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2); | |
606 | ||
607 | /* return negative errno or unsigned value */ | |
608 | return (status < 0) ? status : result; | |
609 | } | |
610 | ||
611 | /*---------------------------------------------------------------------------*/ | |
612 | ||
613 | /* | |
614 | * INTERFACE between board init code and SPI infrastructure. | |
615 | * | |
616 | * No SPI driver ever sees these SPI device table segments, but | |
617 | * it's how the SPI core (or adapters that get hotplugged) grows | |
618 | * the driver model tree. | |
619 | * | |
620 | * As a rule, SPI devices can't be probed. Instead, board init code | |
621 | * provides a table listing the devices which are present, with enough | |
622 | * information to bind and set up the device's driver. There's basic | |
623 | * support for nonstatic configurations too; enough to handle adding | |
624 | * parport adapters, or microcontrollers acting as USB-to-SPI bridges. | |
625 | */ | |
626 | ||
627 | /* board-specific information about each SPI device */ | |
628 | struct spi_board_info { | |
629 | /* the device name and module name are coupled, like platform_bus; | |
630 | * "modalias" is normally the driver name. | |
631 | * | |
632 | * platform_data goes to spi_device.dev.platform_data, | |
b885244e | 633 | * controller_data goes to spi_device.controller_data, |
8ae12a0d DB |
634 | * irq is copied too |
635 | */ | |
636 | char modalias[KOBJ_NAME_LEN]; | |
637 | const void *platform_data; | |
b885244e | 638 | void *controller_data; |
8ae12a0d DB |
639 | int irq; |
640 | ||
641 | /* slower signaling on noisy or low voltage boards */ | |
642 | u32 max_speed_hz; | |
643 | ||
644 | ||
645 | /* bus_num is board specific and matches the bus_num of some | |
646 | * spi_master that will probably be registered later. | |
647 | * | |
648 | * chip_select reflects how this chip is wired to that master; | |
649 | * it's less than num_chipselect. | |
650 | */ | |
651 | u16 bus_num; | |
652 | u16 chip_select; | |
653 | ||
980a01c9 DB |
654 | /* mode becomes spi_device.mode, and is essential for chips |
655 | * where the default of SPI_CS_HIGH = 0 is wrong. | |
656 | */ | |
657 | u8 mode; | |
658 | ||
8ae12a0d DB |
659 | /* ... may need additional spi_device chip config data here. |
660 | * avoid stuff protocol drivers can set; but include stuff | |
661 | * needed to behave without being bound to a driver: | |
8ae12a0d DB |
662 | * - quirks like clock rate mattering when not selected |
663 | */ | |
664 | }; | |
665 | ||
666 | #ifdef CONFIG_SPI | |
667 | extern int | |
668 | spi_register_board_info(struct spi_board_info const *info, unsigned n); | |
669 | #else | |
670 | /* board init code may ignore whether SPI is configured or not */ | |
671 | static inline int | |
672 | spi_register_board_info(struct spi_board_info const *info, unsigned n) | |
673 | { return 0; } | |
674 | #endif | |
675 | ||
676 | ||
677 | /* If you're hotplugging an adapter with devices (parport, usb, etc) | |
0c868461 DB |
678 | * use spi_new_device() to describe each device. You can also call |
679 | * spi_unregister_device() to start making that device vanish, but | |
680 | * normally that would be handled by spi_unregister_master(). | |
8ae12a0d DB |
681 | */ |
682 | extern struct spi_device * | |
683 | spi_new_device(struct spi_master *, struct spi_board_info *); | |
684 | ||
685 | static inline void | |
686 | spi_unregister_device(struct spi_device *spi) | |
687 | { | |
688 | if (spi) | |
689 | device_unregister(&spi->dev); | |
690 | } | |
691 | ||
692 | #endif /* __LINUX_SPI_H */ |