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8ae12a0d DB |
1 | /* |
2 | * Copyright (C) 2005 David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
8ae12a0d DB |
13 | */ |
14 | ||
15 | #ifndef __LINUX_SPI_H | |
16 | #define __LINUX_SPI_H | |
17 | ||
0a30c5ce | 18 | #include <linux/device.h> |
75368bf6 | 19 | #include <linux/mod_devicetable.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
ffbbdd21 | 21 | #include <linux/kthread.h> |
b158935f | 22 | #include <linux/completion.h> |
6ad45a27 | 23 | #include <linux/scatterlist.h> |
0a30c5ce | 24 | |
99adef31 | 25 | struct dma_chan; |
0a30c5ce | 26 | |
8ae12a0d | 27 | /* |
b885244e | 28 | * INTERFACES between SPI master-side drivers and SPI infrastructure. |
8ae12a0d | 29 | * (There's no SPI slave support for Linux yet...) |
8ae12a0d DB |
30 | */ |
31 | extern struct bus_type spi_bus_type; | |
32 | ||
33 | /** | |
34 | * struct spi_device - Master side proxy for an SPI slave device | |
35 | * @dev: Driver model representation of the device. | |
36 | * @master: SPI controller used with the device. | |
37 | * @max_speed_hz: Maximum clock rate to be used with this chip | |
38 | * (on this board); may be changed by the device's driver. | |
4cff33f9 | 39 | * The spi_transfer.speed_hz can override this for each transfer. |
33e34dc6 | 40 | * @chip_select: Chipselect, distinguishing chips handled by @master. |
8ae12a0d DB |
41 | * @mode: The spi mode defines how data is clocked out and in. |
42 | * This may be changed by the device's driver. | |
33e34dc6 DB |
43 | * The "active low" default for chipselect mode can be overridden |
44 | * (by specifying SPI_CS_HIGH) as can the "MSB first" default for | |
45 | * each word in a transfer (by specifying SPI_LSB_FIRST). | |
8ae12a0d | 46 | * @bits_per_word: Data transfers involve one or more words; word sizes |
747d844e | 47 | * like eight or 12 bits are common. In-memory wordsizes are |
8ae12a0d | 48 | * powers of two bytes (e.g. 20 bit samples use 32 bits). |
ccf77cc4 DB |
49 | * This may be changed by the device's driver, or left at the |
50 | * default (0) indicating protocol words are eight bit bytes. | |
4cff33f9 | 51 | * The spi_transfer.bits_per_word can override this for each transfer. |
8ae12a0d | 52 | * @irq: Negative, or the number passed to request_irq() to receive |
747d844e | 53 | * interrupts from this device. |
8ae12a0d | 54 | * @controller_state: Controller's runtime state |
b885244e | 55 | * @controller_data: Board-specific definitions for controller, such as |
747d844e | 56 | * FIFO initialization parameters; from board_info.controller_data |
33e34dc6 DB |
57 | * @modalias: Name of the driver to use with this device, or an alias |
58 | * for that name. This appears in the sysfs "modalias" attribute | |
59 | * for driver coldplugging, and in uevents used for hotplugging | |
446411e1 | 60 | * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when |
095c3752 | 61 | * when not using a GPIO line) |
8ae12a0d | 62 | * |
33e34dc6 | 63 | * A @spi_device is used to interchange data between an SPI slave |
8ae12a0d DB |
64 | * (usually a discrete chip) and CPU memory. |
65 | * | |
33e34dc6 | 66 | * In @dev, the platform_data is used to hold information about this |
8ae12a0d DB |
67 | * device that's meaningful to the device's protocol driver, but not |
68 | * to its controller. One example might be an identifier for a chip | |
33e34dc6 DB |
69 | * variant with slightly different functionality; another might be |
70 | * information about how this particular board wires the chip's pins. | |
8ae12a0d DB |
71 | */ |
72 | struct spi_device { | |
73 | struct device dev; | |
74 | struct spi_master *master; | |
75 | u32 max_speed_hz; | |
76 | u8 chip_select; | |
89c1f607 | 77 | u8 bits_per_word; |
f477b7fb | 78 | u16 mode; |
b885244e DB |
79 | #define SPI_CPHA 0x01 /* clock phase */ |
80 | #define SPI_CPOL 0x02 /* clock polarity */ | |
0c868461 DB |
81 | #define SPI_MODE_0 (0|0) /* (original MicroWire) */ |
82 | #define SPI_MODE_1 (0|SPI_CPHA) | |
8ae12a0d DB |
83 | #define SPI_MODE_2 (SPI_CPOL|0) |
84 | #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) | |
b885244e | 85 | #define SPI_CS_HIGH 0x04 /* chipselect active high? */ |
ccf77cc4 | 86 | #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ |
c06e677a | 87 | #define SPI_3WIRE 0x10 /* SI/SO signals shared */ |
4ef7af50 | 88 | #define SPI_LOOP 0x20 /* loopback mode */ |
b55f627f DB |
89 | #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ |
90 | #define SPI_READY 0x80 /* slave pulls low to pause */ | |
f477b7fb | 91 | #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ |
92 | #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ | |
93 | #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ | |
94 | #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ | |
8ae12a0d DB |
95 | int irq; |
96 | void *controller_state; | |
b885244e | 97 | void *controller_data; |
75368bf6 | 98 | char modalias[SPI_NAME_SIZE]; |
74317984 | 99 | int cs_gpio; /* chip select gpio */ |
8ae12a0d | 100 | |
33e34dc6 DB |
101 | /* |
102 | * likely need more hooks for more protocol options affecting how | |
103 | * the controller talks to each chip, like: | |
104 | * - memory packing (12 bit samples into low bits, others zeroed) | |
105 | * - priority | |
106 | * - drop chipselect after each word | |
107 | * - chipselect delays | |
108 | * - ... | |
109 | */ | |
8ae12a0d DB |
110 | }; |
111 | ||
112 | static inline struct spi_device *to_spi_device(struct device *dev) | |
113 | { | |
b885244e | 114 | return dev ? container_of(dev, struct spi_device, dev) : NULL; |
8ae12a0d DB |
115 | } |
116 | ||
117 | /* most drivers won't need to care about device refcounting */ | |
118 | static inline struct spi_device *spi_dev_get(struct spi_device *spi) | |
119 | { | |
120 | return (spi && get_device(&spi->dev)) ? spi : NULL; | |
121 | } | |
122 | ||
123 | static inline void spi_dev_put(struct spi_device *spi) | |
124 | { | |
125 | if (spi) | |
126 | put_device(&spi->dev); | |
127 | } | |
128 | ||
129 | /* ctldata is for the bus_master driver's runtime state */ | |
130 | static inline void *spi_get_ctldata(struct spi_device *spi) | |
131 | { | |
132 | return spi->controller_state; | |
133 | } | |
134 | ||
135 | static inline void spi_set_ctldata(struct spi_device *spi, void *state) | |
136 | { | |
137 | spi->controller_state = state; | |
138 | } | |
139 | ||
9b40ff4d BD |
140 | /* device driver data */ |
141 | ||
142 | static inline void spi_set_drvdata(struct spi_device *spi, void *data) | |
143 | { | |
144 | dev_set_drvdata(&spi->dev, data); | |
145 | } | |
146 | ||
147 | static inline void *spi_get_drvdata(struct spi_device *spi) | |
148 | { | |
149 | return dev_get_drvdata(&spi->dev); | |
150 | } | |
8ae12a0d DB |
151 | |
152 | struct spi_message; | |
b158935f | 153 | struct spi_transfer; |
b885244e | 154 | |
2604288f DB |
155 | /** |
156 | * struct spi_driver - Host side "protocol" driver | |
75368bf6 | 157 | * @id_table: List of SPI devices supported by this driver |
2604288f DB |
158 | * @probe: Binds this driver to the spi device. Drivers can verify |
159 | * that the device is actually present, and may need to configure | |
160 | * characteristics (such as bits_per_word) which weren't needed for | |
161 | * the initial configuration done during system setup. | |
162 | * @remove: Unbinds this driver from the spi device | |
163 | * @shutdown: Standard shutdown callback used during system state | |
164 | * transitions such as powerdown/halt and kexec | |
165 | * @suspend: Standard suspend callback used during system state transitions | |
166 | * @resume: Standard resume callback used during system state transitions | |
167 | * @driver: SPI device drivers should initialize the name and owner | |
168 | * field of this structure. | |
169 | * | |
170 | * This represents the kind of device driver that uses SPI messages to | |
171 | * interact with the hardware at the other end of a SPI link. It's called | |
172 | * a "protocol" driver because it works through messages rather than talking | |
173 | * directly to SPI hardware (which is what the underlying SPI controller | |
174 | * driver does to pass those messages). These protocols are defined in the | |
175 | * specification for the device(s) supported by the driver. | |
176 | * | |
177 | * As a rule, those device protocols represent the lowest level interface | |
178 | * supported by a driver, and it will support upper level interfaces too. | |
179 | * Examples of such upper levels include frameworks like MTD, networking, | |
180 | * MMC, RTC, filesystem character device nodes, and hardware monitoring. | |
181 | */ | |
b885244e | 182 | struct spi_driver { |
75368bf6 | 183 | const struct spi_device_id *id_table; |
b885244e DB |
184 | int (*probe)(struct spi_device *spi); |
185 | int (*remove)(struct spi_device *spi); | |
186 | void (*shutdown)(struct spi_device *spi); | |
187 | int (*suspend)(struct spi_device *spi, pm_message_t mesg); | |
188 | int (*resume)(struct spi_device *spi); | |
189 | struct device_driver driver; | |
190 | }; | |
191 | ||
192 | static inline struct spi_driver *to_spi_driver(struct device_driver *drv) | |
193 | { | |
194 | return drv ? container_of(drv, struct spi_driver, driver) : NULL; | |
195 | } | |
196 | ||
197 | extern int spi_register_driver(struct spi_driver *sdrv); | |
198 | ||
33e34dc6 DB |
199 | /** |
200 | * spi_unregister_driver - reverse effect of spi_register_driver | |
201 | * @sdrv: the driver to unregister | |
202 | * Context: can sleep | |
203 | */ | |
b885244e DB |
204 | static inline void spi_unregister_driver(struct spi_driver *sdrv) |
205 | { | |
ddc1e975 BD |
206 | if (sdrv) |
207 | driver_unregister(&sdrv->driver); | |
b885244e DB |
208 | } |
209 | ||
3acbb014 LPC |
210 | /** |
211 | * module_spi_driver() - Helper macro for registering a SPI driver | |
212 | * @__spi_driver: spi_driver struct | |
213 | * | |
214 | * Helper macro for SPI drivers which do not do anything special in module | |
215 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
216 | * use this macro once, and calling it replaces module_init() and module_exit() | |
217 | */ | |
218 | #define module_spi_driver(__spi_driver) \ | |
219 | module_driver(__spi_driver, spi_register_driver, \ | |
220 | spi_unregister_driver) | |
b885244e | 221 | |
8ae12a0d DB |
222 | /** |
223 | * struct spi_master - interface to SPI master controller | |
49dce689 | 224 | * @dev: device interface to this driver |
2b9603a0 | 225 | * @list: link with the global spi_master list |
8ae12a0d | 226 | * @bus_num: board-specific (and often SOC-specific) identifier for a |
747d844e | 227 | * given SPI controller. |
b885244e | 228 | * @num_chipselect: chipselects are used to distinguish individual |
747d844e DB |
229 | * SPI slaves, and are numbered from zero to num_chipselects. |
230 | * each slave has a chipselect signal, but it's common that not | |
231 | * every chipselect is connected to a slave. | |
fd5e191e | 232 | * @dma_alignment: SPI controller constraint on DMA buffers alignment. |
b73b2559 | 233 | * @mode_bits: flags understood by this controller driver |
543bb255 SW |
234 | * @bits_per_word_mask: A mask indicating which values of bits_per_word are |
235 | * supported by the driver. Bit n indicates that a bits_per_word n+1 is | |
e227867f | 236 | * supported. If set, the SPI core will reject any transfer with an |
543bb255 SW |
237 | * unsupported bits_per_word. If not set, this value is simply ignored, |
238 | * and it's up to the individual driver to perform any validation. | |
a2fd4f9f MB |
239 | * @min_speed_hz: Lowest supported transfer speed |
240 | * @max_speed_hz: Highest supported transfer speed | |
b73b2559 | 241 | * @flags: other constraints relevant to this driver |
5c79a5ae ES |
242 | * @bus_lock_spinlock: spinlock for SPI bus locking |
243 | * @bus_lock_mutex: mutex for SPI bus locking | |
244 | * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use | |
8ae12a0d | 245 | * @setup: updates the device mode and clocking records used by a |
80224561 DB |
246 | * device's SPI controller; protocol code may call this. This |
247 | * must fail if an unrecognized or unsupported mode is requested. | |
33e34dc6 DB |
248 | * It's always safe to call this unless transfers are pending on |
249 | * the device whose settings are being modified. | |
8ae12a0d DB |
250 | * @transfer: adds a message to the controller's transfer queue. |
251 | * @cleanup: frees controller-specific state | |
2c675689 | 252 | * @can_dma: determine whether this master supports DMA |
ffbbdd21 LW |
253 | * @queued: whether this master is providing an internal message queue |
254 | * @kworker: thread struct for message pump | |
255 | * @kworker_task: pointer to task for message pump kworker thread | |
256 | * @pump_messages: work struct for scheduling work to the message pump | |
257 | * @queue_lock: spinlock to syncronise access to message queue | |
258 | * @queue: message queue | |
0461a414 | 259 | * @idling: the device is entering idle state |
ffbbdd21 | 260 | * @cur_msg: the currently in-flight message |
2841a5fc MB |
261 | * @cur_msg_prepared: spi_prepare_message was called for the currently |
262 | * in-flight message | |
2c675689 | 263 | * @cur_msg_mapped: message has been mapped for DMA |
e227867f | 264 | * @xfer_completion: used by core transfer_one_message() |
ffbbdd21 LW |
265 | * @busy: message pump is busy |
266 | * @running: message pump is running | |
267 | * @rt: whether this queue is set to run as a realtime task | |
49834de2 MB |
268 | * @auto_runtime_pm: the core should ensure a runtime PM reference is held |
269 | * while the hardware is prepared, using the parent | |
270 | * device for the spidev | |
6ad45a27 | 271 | * @max_dma_len: Maximum length of a DMA transfer for the device. |
ffbbdd21 LW |
272 | * @prepare_transfer_hardware: a message will soon arrive from the queue |
273 | * so the subsystem requests the driver to prepare the transfer hardware | |
274 | * by issuing this call | |
275 | * @transfer_one_message: the subsystem calls the driver to transfer a single | |
276 | * message while queuing transfers that arrive in the meantime. When the | |
277 | * driver is finished with this message, it must call | |
278 | * spi_finalize_current_message() so the subsystem can issue the next | |
e9305331 | 279 | * message |
dbabe0d6 | 280 | * @unprepare_transfer_hardware: there are currently no more messages on the |
ffbbdd21 LW |
281 | * queue so the subsystem notifies the driver that it may relax the |
282 | * hardware by issuing this call | |
bd6857a0 | 283 | * @set_cs: set the logic level of the chip select line. May be called |
b158935f | 284 | * from interrupt context. |
2841a5fc MB |
285 | * @prepare_message: set up the controller to transfer a single message, |
286 | * for example doing DMA mapping. Called from threaded | |
287 | * context. | |
0516712c GU |
288 | * @transfer_one: transfer a single spi_transfer. |
289 | * - return 0 if the transfer is finished, | |
290 | * - return 1 if the transfer is still in progress. When | |
291 | * the driver is finished with this transfer it must | |
292 | * call spi_finalize_current_transfer() so the subsystem | |
6e5f5267 BS |
293 | * can issue the next transfer. Note: transfer_one and |
294 | * transfer_one_message are mutually exclusive; when both | |
295 | * are set, the generic subsystem does not call your | |
296 | * transfer_one callback. | |
2841a5fc | 297 | * @unprepare_message: undo any work done by prepare_message(). |
095c3752 | 298 | * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS |
446411e1 | 299 | * number. Any individual value may be -ENOENT for CS lines that |
095c3752 | 300 | * are not GPIOs (driven by the SPI controller itself). |
2c675689 TR |
301 | * @dma_tx: DMA transmit channel |
302 | * @dma_rx: DMA receive channel | |
303 | * @dummy_rx: dummy receive buffer for full-duplex devices | |
304 | * @dummy_tx: dummy transmit buffer for full-duplex devices | |
8ae12a0d | 305 | * |
33e34dc6 | 306 | * Each SPI master controller can communicate with one or more @spi_device |
8ae12a0d DB |
307 | * children. These make a small bus, sharing MOSI, MISO and SCK signals |
308 | * but not chip select signals. Each device may be configured to use a | |
309 | * different clock rate, since those shared signals are ignored unless | |
310 | * the chip is selected. | |
311 | * | |
312 | * The driver for an SPI controller manages access to those devices through | |
33e34dc6 DB |
313 | * a queue of spi_message transactions, copying data between CPU memory and |
314 | * an SPI slave device. For each such message it queues, it calls the | |
8ae12a0d DB |
315 | * message's completion function when the transaction completes. |
316 | */ | |
317 | struct spi_master { | |
49dce689 | 318 | struct device dev; |
8ae12a0d | 319 | |
2b9603a0 FT |
320 | struct list_head list; |
321 | ||
a020ed75 | 322 | /* other than negative (== assign one dynamically), bus_num is fully |
8ae12a0d | 323 | * board-specific. usually that simplifies to being SOC-specific. |
a020ed75 | 324 | * example: one SOC has three SPI controllers, numbered 0..2, |
8ae12a0d DB |
325 | * and one board's schematics might show it using SPI-2. software |
326 | * would normally use bus_num=2 for that controller. | |
327 | */ | |
a020ed75 | 328 | s16 bus_num; |
8ae12a0d DB |
329 | |
330 | /* chipselects will be integral to many controllers; some others | |
331 | * might use board-specific GPIOs. | |
332 | */ | |
333 | u16 num_chipselect; | |
334 | ||
fd5e191e MR |
335 | /* some SPI controllers pose alignment requirements on DMAable |
336 | * buffers; let protocol drivers know about these requirements. | |
337 | */ | |
338 | u16 dma_alignment; | |
339 | ||
e7db06b5 DB |
340 | /* spi_device.mode flags understood by this controller driver */ |
341 | u16 mode_bits; | |
342 | ||
543bb255 SW |
343 | /* bitmask of supported bits_per_word for transfers */ |
344 | u32 bits_per_word_mask; | |
2922a8de | 345 | #define SPI_BPW_MASK(bits) BIT((bits) - 1) |
b6aa23cc | 346 | #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) |
eca8960a | 347 | #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1)) |
543bb255 | 348 | |
a2fd4f9f MB |
349 | /* limits on transfer speed */ |
350 | u32 min_speed_hz; | |
351 | u32 max_speed_hz; | |
352 | ||
70d6027f DB |
353 | /* other constraints relevant to this driver */ |
354 | u16 flags; | |
355 | #define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */ | |
568d0697 DB |
356 | #define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */ |
357 | #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */ | |
3a2eba9b MB |
358 | #define SPI_MASTER_MUST_RX BIT(3) /* requires rx */ |
359 | #define SPI_MASTER_MUST_TX BIT(4) /* requires tx */ | |
70d6027f | 360 | |
cf32b71e ES |
361 | /* lock and mutex for SPI bus locking */ |
362 | spinlock_t bus_lock_spinlock; | |
363 | struct mutex bus_lock_mutex; | |
364 | ||
365 | /* flag indicating that the SPI bus is locked for exclusive use */ | |
366 | bool bus_lock_flag; | |
367 | ||
6e538aaf DB |
368 | /* Setup mode and clock, etc (spi driver may call many times). |
369 | * | |
370 | * IMPORTANT: this may be called when transfers to another | |
371 | * device are active. DO NOT UPDATE SHARED REGISTERS in ways | |
372 | * which could break those transfers. | |
373 | */ | |
8ae12a0d DB |
374 | int (*setup)(struct spi_device *spi); |
375 | ||
376 | /* bidirectional bulk transfers | |
377 | * | |
378 | * + The transfer() method may not sleep; its main role is | |
379 | * just to add the message to the queue. | |
380 | * + For now there's no remove-from-queue operation, or | |
381 | * any other request management | |
382 | * + To a given spi_device, message queueing is pure fifo | |
383 | * | |
384 | * + The master's main job is to process its message queue, | |
385 | * selecting a chip then transferring data | |
386 | * + If there are multiple spi_device children, the i/o queue | |
387 | * arbitration algorithm is unspecified (round robin, fifo, | |
388 | * priority, reservations, preemption, etc) | |
389 | * | |
390 | * + Chipselect stays active during the entire message | |
391 | * (unless modified by spi_transfer.cs_change != 0). | |
392 | * + The message transfers use clock and SPI mode parameters | |
393 | * previously established by setup() for this device | |
394 | */ | |
395 | int (*transfer)(struct spi_device *spi, | |
396 | struct spi_message *mesg); | |
397 | ||
398 | /* called on release() to free memory provided by spi_master */ | |
0ffa0285 | 399 | void (*cleanup)(struct spi_device *spi); |
ffbbdd21 | 400 | |
99adef31 MB |
401 | /* |
402 | * Used to enable core support for DMA handling, if can_dma() | |
403 | * exists and returns true then the transfer will be mapped | |
404 | * prior to transfer_one() being called. The driver should | |
405 | * not modify or store xfer and dma_tx and dma_rx must be set | |
406 | * while the device is prepared. | |
407 | */ | |
408 | bool (*can_dma)(struct spi_master *master, | |
409 | struct spi_device *spi, | |
410 | struct spi_transfer *xfer); | |
411 | ||
ffbbdd21 LW |
412 | /* |
413 | * These hooks are for drivers that want to use the generic | |
414 | * master transfer queueing mechanism. If these are used, the | |
415 | * transfer() function above must NOT be specified by the driver. | |
416 | * Over time we expect SPI drivers to be phased over to this API. | |
417 | */ | |
418 | bool queued; | |
419 | struct kthread_worker kworker; | |
420 | struct task_struct *kworker_task; | |
421 | struct kthread_work pump_messages; | |
422 | spinlock_t queue_lock; | |
423 | struct list_head queue; | |
424 | struct spi_message *cur_msg; | |
0461a414 | 425 | bool idling; |
ffbbdd21 LW |
426 | bool busy; |
427 | bool running; | |
428 | bool rt; | |
49834de2 | 429 | bool auto_runtime_pm; |
2841a5fc | 430 | bool cur_msg_prepared; |
99adef31 | 431 | bool cur_msg_mapped; |
b158935f | 432 | struct completion xfer_completion; |
6ad45a27 | 433 | size_t max_dma_len; |
ffbbdd21 LW |
434 | |
435 | int (*prepare_transfer_hardware)(struct spi_master *master); | |
436 | int (*transfer_one_message)(struct spi_master *master, | |
437 | struct spi_message *mesg); | |
438 | int (*unprepare_transfer_hardware)(struct spi_master *master); | |
2841a5fc MB |
439 | int (*prepare_message)(struct spi_master *master, |
440 | struct spi_message *message); | |
441 | int (*unprepare_message)(struct spi_master *master, | |
442 | struct spi_message *message); | |
49834de2 | 443 | |
b158935f MB |
444 | /* |
445 | * These hooks are for drivers that use a generic implementation | |
446 | * of transfer_one_message() provied by the core. | |
447 | */ | |
448 | void (*set_cs)(struct spi_device *spi, bool enable); | |
449 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, | |
450 | struct spi_transfer *transfer); | |
451 | ||
74317984 JCPV |
452 | /* gpio chip select */ |
453 | int *cs_gpios; | |
99adef31 MB |
454 | |
455 | /* DMA channels for use with core dmaengine helpers */ | |
456 | struct dma_chan *dma_tx; | |
457 | struct dma_chan *dma_rx; | |
3a2eba9b MB |
458 | |
459 | /* dummy data for full duplex devices */ | |
460 | void *dummy_rx; | |
461 | void *dummy_tx; | |
8ae12a0d DB |
462 | }; |
463 | ||
0c868461 DB |
464 | static inline void *spi_master_get_devdata(struct spi_master *master) |
465 | { | |
49dce689 | 466 | return dev_get_drvdata(&master->dev); |
0c868461 DB |
467 | } |
468 | ||
469 | static inline void spi_master_set_devdata(struct spi_master *master, void *data) | |
470 | { | |
49dce689 | 471 | dev_set_drvdata(&master->dev, data); |
0c868461 DB |
472 | } |
473 | ||
474 | static inline struct spi_master *spi_master_get(struct spi_master *master) | |
475 | { | |
49dce689 | 476 | if (!master || !get_device(&master->dev)) |
0c868461 DB |
477 | return NULL; |
478 | return master; | |
479 | } | |
480 | ||
481 | static inline void spi_master_put(struct spi_master *master) | |
482 | { | |
483 | if (master) | |
49dce689 | 484 | put_device(&master->dev); |
0c868461 DB |
485 | } |
486 | ||
ffbbdd21 LW |
487 | /* PM calls that need to be issued by the driver */ |
488 | extern int spi_master_suspend(struct spi_master *master); | |
489 | extern int spi_master_resume(struct spi_master *master); | |
490 | ||
491 | /* Calls the driver make to interact with the message queue */ | |
492 | extern struct spi_message *spi_get_next_queued_message(struct spi_master *master); | |
493 | extern void spi_finalize_current_message(struct spi_master *master); | |
b158935f | 494 | extern void spi_finalize_current_transfer(struct spi_master *master); |
0c868461 | 495 | |
8ae12a0d DB |
496 | /* the spi driver core manages memory for the spi_master classdev */ |
497 | extern struct spi_master * | |
498 | spi_alloc_master(struct device *host, unsigned size); | |
499 | ||
500 | extern int spi_register_master(struct spi_master *master); | |
666d5b4c MB |
501 | extern int devm_spi_register_master(struct device *dev, |
502 | struct spi_master *master); | |
8ae12a0d DB |
503 | extern void spi_unregister_master(struct spi_master *master); |
504 | ||
505 | extern struct spi_master *spi_busnum_to_master(u16 busnum); | |
506 | ||
507 | /*---------------------------------------------------------------------------*/ | |
508 | ||
509 | /* | |
510 | * I/O INTERFACE between SPI controller and protocol drivers | |
511 | * | |
512 | * Protocol drivers use a queue of spi_messages, each transferring data | |
513 | * between the controller and memory buffers. | |
514 | * | |
515 | * The spi_messages themselves consist of a series of read+write transfer | |
516 | * segments. Those segments always read the same number of bits as they | |
517 | * write; but one or the other is easily ignored by passing a null buffer | |
518 | * pointer. (This is unlike most types of I/O API, because SPI hardware | |
519 | * is full duplex.) | |
520 | * | |
521 | * NOTE: Allocation of spi_transfer and spi_message memory is entirely | |
522 | * up to the protocol driver, which guarantees the integrity of both (as | |
523 | * well as the data buffers) for as long as the message is queued. | |
524 | */ | |
525 | ||
526 | /** | |
527 | * struct spi_transfer - a read/write buffer pair | |
8275c642 VW |
528 | * @tx_buf: data to be written (dma-safe memory), or NULL |
529 | * @rx_buf: data to be read (dma-safe memory), or NULL | |
33e34dc6 DB |
530 | * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped |
531 | * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped | |
e227867f | 532 | * @tx_nbits: number of bits used for writing. If 0 the default |
f477b7fb | 533 | * (SPI_NBITS_SINGLE) is used. |
534 | * @rx_nbits: number of bits used for reading. If 0 the default | |
535 | * (SPI_NBITS_SINGLE) is used. | |
8ae12a0d | 536 | * @len: size of rx and tx buffers (in bytes) |
025dfdaf | 537 | * @speed_hz: Select a speed other than the device default for this |
33e34dc6 | 538 | * transfer. If 0 the default (from @spi_device) is used. |
025dfdaf | 539 | * @bits_per_word: select a bits_per_word other than the device default |
33e34dc6 | 540 | * for this transfer. If 0 the default (from @spi_device) is used. |
8ae12a0d DB |
541 | * @cs_change: affects chipselect after this transfer completes |
542 | * @delay_usecs: microseconds to delay after this transfer before | |
747d844e | 543 | * (optionally) changing the chipselect status, then starting |
33e34dc6 DB |
544 | * the next transfer or completing this @spi_message. |
545 | * @transfer_list: transfers are sequenced through @spi_message.transfers | |
6ad45a27 MB |
546 | * @tx_sg: Scatterlist for transmit, currently not for client use |
547 | * @rx_sg: Scatterlist for receive, currently not for client use | |
8ae12a0d DB |
548 | * |
549 | * SPI transfers always write the same number of bytes as they read. | |
33e34dc6 | 550 | * Protocol drivers should always provide @rx_buf and/or @tx_buf. |
8ae12a0d DB |
551 | * In some cases, they may also want to provide DMA addresses for |
552 | * the data being transferred; that may reduce overhead, when the | |
553 | * underlying driver uses dma. | |
554 | * | |
4b1badf5 | 555 | * If the transmit buffer is null, zeroes will be shifted out |
33e34dc6 | 556 | * while filling @rx_buf. If the receive buffer is null, the data |
8275c642 VW |
557 | * shifted in will be discarded. Only "len" bytes shift out (or in). |
558 | * It's an error to try to shift out a partial word. (For example, by | |
559 | * shifting out three bytes with word size of sixteen or twenty bits; | |
560 | * the former uses two bytes per word, the latter uses four bytes.) | |
561 | * | |
80224561 DB |
562 | * In-memory data values are always in native CPU byte order, translated |
563 | * from the wire byte order (big-endian except with SPI_LSB_FIRST). So | |
564 | * for example when bits_per_word is sixteen, buffers are 2N bytes long | |
33e34dc6 | 565 | * (@len = 2N) and hold N sixteen bit words in CPU byte order. |
80224561 DB |
566 | * |
567 | * When the word size of the SPI transfer is not a power-of-two multiple | |
568 | * of eight bits, those in-memory words include extra bits. In-memory | |
569 | * words are always seen by protocol drivers as right-justified, so the | |
570 | * undefined (rx) or unused (tx) bits are always the most significant bits. | |
571 | * | |
8275c642 VW |
572 | * All SPI transfers start with the relevant chipselect active. Normally |
573 | * it stays selected until after the last transfer in a message. Drivers | |
33e34dc6 | 574 | * can affect the chipselect signal using cs_change. |
8ae12a0d DB |
575 | * |
576 | * (i) If the transfer isn't the last one in the message, this flag is | |
577 | * used to make the chipselect briefly go inactive in the middle of the | |
578 | * message. Toggling chipselect in this way may be needed to terminate | |
579 | * a chip command, letting a single spi_message perform all of group of | |
580 | * chip transactions together. | |
581 | * | |
582 | * (ii) When the transfer is the last one in the message, the chip may | |
f5a9c77d DB |
583 | * stay selected until the next transfer. On multi-device SPI busses |
584 | * with nothing blocking messages going to other devices, this is just | |
585 | * a performance hint; starting a message to another device deselects | |
586 | * this one. But in other cases, this can be used to ensure correctness. | |
587 | * Some devices need protocol transactions to be built from a series of | |
588 | * spi_message submissions, where the content of one message is determined | |
589 | * by the results of previous messages and where the whole transaction | |
590 | * ends when the chipselect goes intactive. | |
0c868461 | 591 | * |
e227867f | 592 | * When SPI can transfer in 1x,2x or 4x. It can get this transfer information |
f477b7fb | 593 | * from device through @tx_nbits and @rx_nbits. In Bi-direction, these |
594 | * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) | |
595 | * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. | |
596 | * | |
0c868461 DB |
597 | * The code that submits an spi_message (and its spi_transfers) |
598 | * to the lower layers is responsible for managing its memory. | |
599 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
600 | * insulate against future API updates. After you submit a message |
601 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
602 | */ |
603 | struct spi_transfer { | |
604 | /* it's ok if tx_buf == rx_buf (right?) | |
605 | * for MicroWire, one buffer must be null | |
0c868461 DB |
606 | * buffers must work with dma_*map_single() calls, unless |
607 | * spi_message.is_dma_mapped reports a pre-existing mapping | |
8ae12a0d DB |
608 | */ |
609 | const void *tx_buf; | |
610 | void *rx_buf; | |
611 | unsigned len; | |
612 | ||
613 | dma_addr_t tx_dma; | |
614 | dma_addr_t rx_dma; | |
6ad45a27 MB |
615 | struct sg_table tx_sg; |
616 | struct sg_table rx_sg; | |
8ae12a0d DB |
617 | |
618 | unsigned cs_change:1; | |
d3fbd457 MB |
619 | unsigned tx_nbits:3; |
620 | unsigned rx_nbits:3; | |
f477b7fb | 621 | #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ |
622 | #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ | |
623 | #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ | |
4cff33f9 | 624 | u8 bits_per_word; |
8ae12a0d | 625 | u16 delay_usecs; |
4cff33f9 | 626 | u32 speed_hz; |
8275c642 VW |
627 | |
628 | struct list_head transfer_list; | |
8ae12a0d DB |
629 | }; |
630 | ||
631 | /** | |
632 | * struct spi_message - one multi-segment SPI transaction | |
8275c642 | 633 | * @transfers: list of transfer segments in this transaction |
8ae12a0d DB |
634 | * @spi: SPI device to which the transaction is queued |
635 | * @is_dma_mapped: if true, the caller provided both dma and cpu virtual | |
636 | * addresses for each transfer buffer | |
637 | * @complete: called to report transaction completions | |
638 | * @context: the argument to complete() when it's called | |
2c675689 | 639 | * @frame_length: the total number of bytes in the message |
b885244e DB |
640 | * @actual_length: the total number of bytes that were transferred in all |
641 | * successful segments | |
8ae12a0d DB |
642 | * @status: zero for success, else negative errno |
643 | * @queue: for use by whichever driver currently owns the message | |
644 | * @state: for use by whichever driver currently owns the message | |
0c868461 | 645 | * |
33e34dc6 | 646 | * A @spi_message is used to execute an atomic sequence of data transfers, |
8275c642 VW |
647 | * each represented by a struct spi_transfer. The sequence is "atomic" |
648 | * in the sense that no other spi_message may use that SPI bus until that | |
649 | * sequence completes. On some systems, many such sequences can execute as | |
650 | * as single programmed DMA transfer. On all systems, these messages are | |
651 | * queued, and might complete after transactions to other devices. Messages | |
c6331ba3 | 652 | * sent to a given spi_device are always executed in FIFO order. |
8275c642 | 653 | * |
0c868461 DB |
654 | * The code that submits an spi_message (and its spi_transfers) |
655 | * to the lower layers is responsible for managing its memory. | |
656 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
657 | * insulate against future API updates. After you submit a message |
658 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
659 | */ |
660 | struct spi_message { | |
747d844e | 661 | struct list_head transfers; |
8ae12a0d DB |
662 | |
663 | struct spi_device *spi; | |
664 | ||
665 | unsigned is_dma_mapped:1; | |
666 | ||
667 | /* REVISIT: we might want a flag affecting the behavior of the | |
668 | * last transfer ... allowing things like "read 16 bit length L" | |
669 | * immediately followed by "read L bytes". Basically imposing | |
670 | * a specific message scheduling algorithm. | |
671 | * | |
672 | * Some controller drivers (message-at-a-time queue processing) | |
673 | * could provide that as their default scheduling algorithm. But | |
b885244e | 674 | * others (with multi-message pipelines) could need a flag to |
8ae12a0d DB |
675 | * tell them about such special cases. |
676 | */ | |
677 | ||
678 | /* completion is reported through a callback */ | |
747d844e | 679 | void (*complete)(void *context); |
8ae12a0d | 680 | void *context; |
078726ce | 681 | unsigned frame_length; |
8ae12a0d DB |
682 | unsigned actual_length; |
683 | int status; | |
684 | ||
685 | /* for optional use by whatever driver currently owns the | |
686 | * spi_message ... between calls to spi_async and then later | |
687 | * complete(), that's the spi_master controller driver. | |
688 | */ | |
689 | struct list_head queue; | |
690 | void *state; | |
691 | }; | |
692 | ||
8275c642 VW |
693 | static inline void spi_message_init(struct spi_message *m) |
694 | { | |
695 | memset(m, 0, sizeof *m); | |
696 | INIT_LIST_HEAD(&m->transfers); | |
697 | } | |
698 | ||
699 | static inline void | |
700 | spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) | |
701 | { | |
702 | list_add_tail(&t->transfer_list, &m->transfers); | |
703 | } | |
704 | ||
705 | static inline void | |
706 | spi_transfer_del(struct spi_transfer *t) | |
707 | { | |
708 | list_del(&t->transfer_list); | |
709 | } | |
710 | ||
6d9eecd4 LPC |
711 | /** |
712 | * spi_message_init_with_transfers - Initialize spi_message and append transfers | |
713 | * @m: spi_message to be initialized | |
714 | * @xfers: An array of spi transfers | |
715 | * @num_xfers: Number of items in the xfer array | |
716 | * | |
717 | * This function initializes the given spi_message and adds each spi_transfer in | |
718 | * the given array to the message. | |
719 | */ | |
720 | static inline void | |
721 | spi_message_init_with_transfers(struct spi_message *m, | |
722 | struct spi_transfer *xfers, unsigned int num_xfers) | |
723 | { | |
724 | unsigned int i; | |
725 | ||
726 | spi_message_init(m); | |
727 | for (i = 0; i < num_xfers; ++i) | |
728 | spi_message_add_tail(&xfers[i], m); | |
729 | } | |
730 | ||
0c868461 DB |
731 | /* It's fine to embed message and transaction structures in other data |
732 | * structures so long as you don't free them while they're in use. | |
733 | */ | |
734 | ||
735 | static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) | |
736 | { | |
737 | struct spi_message *m; | |
738 | ||
739 | m = kzalloc(sizeof(struct spi_message) | |
740 | + ntrans * sizeof(struct spi_transfer), | |
741 | flags); | |
742 | if (m) { | |
8f53602b | 743 | unsigned i; |
8275c642 VW |
744 | struct spi_transfer *t = (struct spi_transfer *)(m + 1); |
745 | ||
746 | INIT_LIST_HEAD(&m->transfers); | |
747 | for (i = 0; i < ntrans; i++, t++) | |
748 | spi_message_add_tail(t, m); | |
0c868461 DB |
749 | } |
750 | return m; | |
751 | } | |
752 | ||
753 | static inline void spi_message_free(struct spi_message *m) | |
754 | { | |
755 | kfree(m); | |
756 | } | |
757 | ||
7d077197 | 758 | extern int spi_setup(struct spi_device *spi); |
568d0697 | 759 | extern int spi_async(struct spi_device *spi, struct spi_message *message); |
cf32b71e ES |
760 | extern int spi_async_locked(struct spi_device *spi, |
761 | struct spi_message *message); | |
8ae12a0d DB |
762 | |
763 | /*---------------------------------------------------------------------------*/ | |
764 | ||
765 | /* All these synchronous SPI transfer routines are utilities layered | |
766 | * over the core async transfer primitive. Here, "synchronous" means | |
767 | * they will sleep uninterruptibly until the async transfer completes. | |
768 | */ | |
769 | ||
770 | extern int spi_sync(struct spi_device *spi, struct spi_message *message); | |
cf32b71e ES |
771 | extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); |
772 | extern int spi_bus_lock(struct spi_master *master); | |
773 | extern int spi_bus_unlock(struct spi_master *master); | |
8ae12a0d DB |
774 | |
775 | /** | |
776 | * spi_write - SPI synchronous write | |
777 | * @spi: device to which data will be written | |
778 | * @buf: data buffer | |
779 | * @len: data buffer size | |
33e34dc6 | 780 | * Context: can sleep |
8ae12a0d DB |
781 | * |
782 | * This writes the buffer and returns zero or a negative error code. | |
783 | * Callable only from contexts that can sleep. | |
784 | */ | |
785 | static inline int | |
0c4a1590 | 786 | spi_write(struct spi_device *spi, const void *buf, size_t len) |
8ae12a0d DB |
787 | { |
788 | struct spi_transfer t = { | |
789 | .tx_buf = buf, | |
8ae12a0d | 790 | .len = len, |
8ae12a0d | 791 | }; |
8275c642 | 792 | struct spi_message m; |
8ae12a0d | 793 | |
8275c642 VW |
794 | spi_message_init(&m); |
795 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
796 | return spi_sync(spi, &m); |
797 | } | |
798 | ||
799 | /** | |
800 | * spi_read - SPI synchronous read | |
801 | * @spi: device from which data will be read | |
802 | * @buf: data buffer | |
803 | * @len: data buffer size | |
33e34dc6 | 804 | * Context: can sleep |
8ae12a0d | 805 | * |
33e34dc6 | 806 | * This reads the buffer and returns zero or a negative error code. |
8ae12a0d DB |
807 | * Callable only from contexts that can sleep. |
808 | */ | |
809 | static inline int | |
0c4a1590 | 810 | spi_read(struct spi_device *spi, void *buf, size_t len) |
8ae12a0d DB |
811 | { |
812 | struct spi_transfer t = { | |
8ae12a0d DB |
813 | .rx_buf = buf, |
814 | .len = len, | |
8ae12a0d | 815 | }; |
8275c642 | 816 | struct spi_message m; |
8ae12a0d | 817 | |
8275c642 VW |
818 | spi_message_init(&m); |
819 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
820 | return spi_sync(spi, &m); |
821 | } | |
822 | ||
6d9eecd4 LPC |
823 | /** |
824 | * spi_sync_transfer - synchronous SPI data transfer | |
825 | * @spi: device with which data will be exchanged | |
826 | * @xfers: An array of spi_transfers | |
827 | * @num_xfers: Number of items in the xfer array | |
828 | * Context: can sleep | |
829 | * | |
830 | * Does a synchronous SPI data transfer of the given spi_transfer array. | |
831 | * | |
832 | * For more specific semantics see spi_sync(). | |
833 | * | |
834 | * It returns zero on success, else a negative error code. | |
835 | */ | |
836 | static inline int | |
837 | spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, | |
838 | unsigned int num_xfers) | |
839 | { | |
840 | struct spi_message msg; | |
841 | ||
842 | spi_message_init_with_transfers(&msg, xfers, num_xfers); | |
843 | ||
844 | return spi_sync(spi, &msg); | |
845 | } | |
846 | ||
0c868461 | 847 | /* this copies txbuf and rxbuf data; for small transfers only! */ |
8ae12a0d | 848 | extern int spi_write_then_read(struct spi_device *spi, |
0c4a1590 MB |
849 | const void *txbuf, unsigned n_tx, |
850 | void *rxbuf, unsigned n_rx); | |
8ae12a0d DB |
851 | |
852 | /** | |
853 | * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read | |
854 | * @spi: device with which data will be exchanged | |
855 | * @cmd: command to be written before data is read back | |
33e34dc6 | 856 | * Context: can sleep |
8ae12a0d DB |
857 | * |
858 | * This returns the (unsigned) eight bit number returned by the | |
859 | * device, or else a negative error code. Callable only from | |
860 | * contexts that can sleep. | |
861 | */ | |
862 | static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) | |
863 | { | |
864 | ssize_t status; | |
865 | u8 result; | |
866 | ||
867 | status = spi_write_then_read(spi, &cmd, 1, &result, 1); | |
868 | ||
869 | /* return negative errno or unsigned value */ | |
870 | return (status < 0) ? status : result; | |
871 | } | |
872 | ||
873 | /** | |
874 | * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read | |
875 | * @spi: device with which data will be exchanged | |
876 | * @cmd: command to be written before data is read back | |
33e34dc6 | 877 | * Context: can sleep |
8ae12a0d DB |
878 | * |
879 | * This returns the (unsigned) sixteen bit number returned by the | |
880 | * device, or else a negative error code. Callable only from | |
881 | * contexts that can sleep. | |
882 | * | |
883 | * The number is returned in wire-order, which is at least sometimes | |
884 | * big-endian. | |
885 | */ | |
886 | static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) | |
887 | { | |
888 | ssize_t status; | |
889 | u16 result; | |
890 | ||
269ccca8 | 891 | status = spi_write_then_read(spi, &cmd, 1, &result, 2); |
8ae12a0d DB |
892 | |
893 | /* return negative errno or unsigned value */ | |
894 | return (status < 0) ? status : result; | |
895 | } | |
896 | ||
05071aa8 LPC |
897 | /** |
898 | * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read | |
899 | * @spi: device with which data will be exchanged | |
900 | * @cmd: command to be written before data is read back | |
901 | * Context: can sleep | |
902 | * | |
903 | * This returns the (unsigned) sixteen bit number returned by the device in cpu | |
904 | * endianness, or else a negative error code. Callable only from contexts that | |
905 | * can sleep. | |
906 | * | |
907 | * This function is similar to spi_w8r16, with the exception that it will | |
908 | * convert the read 16 bit data word from big-endian to native endianness. | |
909 | * | |
910 | */ | |
911 | static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) | |
912 | ||
913 | { | |
914 | ssize_t status; | |
915 | __be16 result; | |
916 | ||
917 | status = spi_write_then_read(spi, &cmd, 1, &result, 2); | |
918 | if (status < 0) | |
919 | return status; | |
920 | ||
921 | return be16_to_cpu(result); | |
922 | } | |
923 | ||
8ae12a0d DB |
924 | /*---------------------------------------------------------------------------*/ |
925 | ||
926 | /* | |
927 | * INTERFACE between board init code and SPI infrastructure. | |
928 | * | |
929 | * No SPI driver ever sees these SPI device table segments, but | |
930 | * it's how the SPI core (or adapters that get hotplugged) grows | |
931 | * the driver model tree. | |
932 | * | |
933 | * As a rule, SPI devices can't be probed. Instead, board init code | |
934 | * provides a table listing the devices which are present, with enough | |
935 | * information to bind and set up the device's driver. There's basic | |
936 | * support for nonstatic configurations too; enough to handle adding | |
937 | * parport adapters, or microcontrollers acting as USB-to-SPI bridges. | |
938 | */ | |
939 | ||
2604288f DB |
940 | /** |
941 | * struct spi_board_info - board-specific template for a SPI device | |
942 | * @modalias: Initializes spi_device.modalias; identifies the driver. | |
943 | * @platform_data: Initializes spi_device.platform_data; the particular | |
944 | * data stored there is driver-specific. | |
945 | * @controller_data: Initializes spi_device.controller_data; some | |
946 | * controllers need hints about hardware setup, e.g. for DMA. | |
947 | * @irq: Initializes spi_device.irq; depends on how the board is wired. | |
948 | * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits | |
949 | * from the chip datasheet and board-specific signal quality issues. | |
950 | * @bus_num: Identifies which spi_master parents the spi_device; unused | |
951 | * by spi_new_device(), and otherwise depends on board wiring. | |
952 | * @chip_select: Initializes spi_device.chip_select; depends on how | |
953 | * the board is wired. | |
954 | * @mode: Initializes spi_device.mode; based on the chip datasheet, board | |
955 | * wiring (some devices support both 3WIRE and standard modes), and | |
956 | * possibly presence of an inverter in the chipselect path. | |
957 | * | |
958 | * When adding new SPI devices to the device tree, these structures serve | |
959 | * as a partial device template. They hold information which can't always | |
960 | * be determined by drivers. Information that probe() can establish (such | |
961 | * as the default transfer wordsize) is not included here. | |
962 | * | |
963 | * These structures are used in two places. Their primary role is to | |
964 | * be stored in tables of board-specific device descriptors, which are | |
965 | * declared early in board initialization and then used (much later) to | |
966 | * populate a controller's device tree after the that controller's driver | |
967 | * initializes. A secondary (and atypical) role is as a parameter to | |
968 | * spi_new_device() call, which happens after those controller drivers | |
969 | * are active in some dynamic board configuration models. | |
970 | */ | |
8ae12a0d DB |
971 | struct spi_board_info { |
972 | /* the device name and module name are coupled, like platform_bus; | |
973 | * "modalias" is normally the driver name. | |
974 | * | |
975 | * platform_data goes to spi_device.dev.platform_data, | |
b885244e | 976 | * controller_data goes to spi_device.controller_data, |
8ae12a0d DB |
977 | * irq is copied too |
978 | */ | |
75368bf6 | 979 | char modalias[SPI_NAME_SIZE]; |
8ae12a0d | 980 | const void *platform_data; |
b885244e | 981 | void *controller_data; |
8ae12a0d DB |
982 | int irq; |
983 | ||
984 | /* slower signaling on noisy or low voltage boards */ | |
985 | u32 max_speed_hz; | |
986 | ||
987 | ||
988 | /* bus_num is board specific and matches the bus_num of some | |
989 | * spi_master that will probably be registered later. | |
990 | * | |
991 | * chip_select reflects how this chip is wired to that master; | |
992 | * it's less than num_chipselect. | |
993 | */ | |
994 | u16 bus_num; | |
995 | u16 chip_select; | |
996 | ||
980a01c9 DB |
997 | /* mode becomes spi_device.mode, and is essential for chips |
998 | * where the default of SPI_CS_HIGH = 0 is wrong. | |
999 | */ | |
f477b7fb | 1000 | u16 mode; |
980a01c9 | 1001 | |
8ae12a0d DB |
1002 | /* ... may need additional spi_device chip config data here. |
1003 | * avoid stuff protocol drivers can set; but include stuff | |
1004 | * needed to behave without being bound to a driver: | |
8ae12a0d DB |
1005 | * - quirks like clock rate mattering when not selected |
1006 | */ | |
1007 | }; | |
1008 | ||
1009 | #ifdef CONFIG_SPI | |
1010 | extern int | |
1011 | spi_register_board_info(struct spi_board_info const *info, unsigned n); | |
1012 | #else | |
1013 | /* board init code may ignore whether SPI is configured or not */ | |
1014 | static inline int | |
1015 | spi_register_board_info(struct spi_board_info const *info, unsigned n) | |
1016 | { return 0; } | |
1017 | #endif | |
1018 | ||
1019 | ||
1020 | /* If you're hotplugging an adapter with devices (parport, usb, etc) | |
0c868461 DB |
1021 | * use spi_new_device() to describe each device. You can also call |
1022 | * spi_unregister_device() to start making that device vanish, but | |
1023 | * normally that would be handled by spi_unregister_master(). | |
dc87c98e GL |
1024 | * |
1025 | * You can also use spi_alloc_device() and spi_add_device() to use a two | |
1026 | * stage registration sequence for each spi_device. This gives the caller | |
1027 | * some more control over the spi_device structure before it is registered, | |
1028 | * but requires that caller to initialize fields that would otherwise | |
1029 | * be defined using the board info. | |
8ae12a0d | 1030 | */ |
dc87c98e GL |
1031 | extern struct spi_device * |
1032 | spi_alloc_device(struct spi_master *master); | |
1033 | ||
1034 | extern int | |
1035 | spi_add_device(struct spi_device *spi); | |
1036 | ||
8ae12a0d DB |
1037 | extern struct spi_device * |
1038 | spi_new_device(struct spi_master *, struct spi_board_info *); | |
1039 | ||
1040 | static inline void | |
1041 | spi_unregister_device(struct spi_device *spi) | |
1042 | { | |
1043 | if (spi) | |
1044 | device_unregister(&spi->dev); | |
1045 | } | |
1046 | ||
75368bf6 AV |
1047 | extern const struct spi_device_id * |
1048 | spi_get_device_id(const struct spi_device *sdev); | |
1049 | ||
b671358a BG |
1050 | static inline bool |
1051 | spi_transfer_is_last(struct spi_master *master, struct spi_transfer *xfer) | |
1052 | { | |
1053 | return list_is_last(&xfer->transfer_list, &master->cur_msg->transfers); | |
1054 | } | |
1055 | ||
8ae12a0d | 1056 | #endif /* __LINUX_SPI_H */ |