usb: add support to the generic PHY framework in OTG
[deliverable/linux.git] / include / linux / usb / chipidea.h
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1/*
2 * Platform data for the chipidea USB dual role controller
3 */
4
5#ifndef __LINUX_USB_CHIPIDEA_H
6#define __LINUX_USB_CHIPIDEA_H
7
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8#include <linux/usb/otg.h>
9
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10struct ci_hdrc;
11struct ci_hdrc_platform_data {
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12 const char *name;
13 /* offset of the capability registers */
14 uintptr_t capoffset;
bd841986 15 unsigned power_budget;
a2c3d690 16 struct usb_phy *phy;
40dcd0e8 17 enum usb_phy_interface phy_mode;
e443b333 18 unsigned long flags;
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19#define CI_HDRC_REGS_SHARED BIT(0)
20#define CI_HDRC_REQUIRE_TRANSCEIVER BIT(1)
8e22978c 21#define CI_HDRC_DISABLE_STREAMING BIT(3)
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22 /*
23 * Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
24 * but otg is not supported (no register otgsc).
25 */
26#define CI_HDRC_DUAL_ROLE_NOT_OTG BIT(4)
ed8f8318 27#define CI_HDRC_IMX28_WRITE_FIX BIT(5)
4f6743d5 28#define CI_HDRC_FORCE_FULLSPEED BIT(6)
691962d1 29 enum usb_dr_mode dr_mode;
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30#define CI_HDRC_CONTROLLER_RESET_EVENT 0
31#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
32 void (*notify_event) (struct ci_hdrc *ci, unsigned event);
1542d9c3 33 struct regulator *reg_vbus;
f6a9ff07 34 bool tpl_support;
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35};
36
37/* Default offset of capability registers */
38#define DEF_CAPOFFSET 0x100
39
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40/* Add ci hdrc device */
41struct platform_device *ci_hdrc_add_device(struct device *dev,
cbc6dc2a 42 struct resource *res, int nres,
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43 struct ci_hdrc_platform_data *platdata);
44/* Remove ci hdrc device */
45void ci_hdrc_remove_device(struct platform_device *pdev);
cbc6dc2a 46
e443b333 47#endif
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