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0af36739 YL |
1 | /* |
2 | * Copyright (c) 2001-2002 by David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_USB_EHCI_DEF_H | |
20 | #define __LINUX_USB_EHCI_DEF_H | |
21 | ||
b9ec1c9d CR |
22 | #include <linux/usb/ehci-dbgp.h> |
23 | ||
0af36739 YL |
24 | /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ |
25 | ||
26 | /* Section 2.2 Host Controller Capability Registers */ | |
27 | struct ehci_caps { | |
28 | /* these fields are specified as 8 and 16 bit registers, | |
29 | * but some hosts can't perform 8 or 16 bit PCI accesses. | |
c430131a JA |
30 | * some hosts treat caplength and hciversion as parts of a 32-bit |
31 | * register, others treat them as two separate registers, this | |
32 | * affects the memory map for big endian controllers. | |
0af36739 YL |
33 | */ |
34 | u32 hc_capbase; | |
c430131a JA |
35 | #define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \ |
36 | (ehci_big_endian_capbase(ehci) ? 24 : 0))) | |
37 | #define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \ | |
38 | (ehci_big_endian_capbase(ehci) ? 0 : 16))) | |
0af36739 YL |
39 | u32 hcs_params; /* HCSPARAMS - offset 0x4 */ |
40 | #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ | |
41 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ | |
42 | #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ | |
43 | #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ | |
44 | #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ | |
45 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ | |
46 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ | |
47 | ||
48 | u32 hcc_params; /* HCCPARAMS - offset 0x8 */ | |
aa4d8342 AD |
49 | /* EHCI 1.1 addendum */ |
50 | #define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19)) | |
51 | #define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18)) | |
52 | #define HCC_LPM(p) ((p)&(1 << 17)) | |
53 | #define HCC_HW_PREFETCH(p) ((p)&(1 << 16)) | |
54 | ||
0af36739 YL |
55 | #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ |
56 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ | |
57 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ | |
58 | #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ | |
59 | #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ | |
60 | #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ | |
0858a3a5 | 61 | u8 portroute[8]; /* nibbles for routing - offset 0xC */ |
13954017 | 62 | }; |
0af36739 YL |
63 | |
64 | ||
65 | /* Section 2.3 Host Controller Operational Registers */ | |
66 | struct ehci_regs { | |
67 | ||
68 | /* USBCMD: offset 0x00 */ | |
69 | u32 command; | |
aa4d8342 AD |
70 | |
71 | /* EHCI 1.1 addendum */ | |
72 | #define CMD_HIRD (0xf<<24) /* host initiated resume duration */ | |
73 | #define CMD_PPCEE (1<<15) /* per port change event enable */ | |
74 | #define CMD_FSP (1<<14) /* fully synchronized prefetch */ | |
75 | #define CMD_ASPE (1<<13) /* async schedule prefetch enable */ | |
76 | #define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */ | |
0af36739 YL |
77 | /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ |
78 | #define CMD_PARK (1<<11) /* enable "park" on async qh */ | |
79 | #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ | |
80 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ | |
81 | #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ | |
82 | #define CMD_ASE (1<<5) /* async schedule enable */ | |
83 | #define CMD_PSE (1<<4) /* periodic schedule enable */ | |
84 | /* 3:2 is periodic frame list size */ | |
85 | #define CMD_RESET (1<<1) /* reset HC not bus */ | |
86 | #define CMD_RUN (1<<0) /* start/stop HC */ | |
87 | ||
88 | /* USBSTS: offset 0x04 */ | |
89 | u32 status; | |
aa4d8342 | 90 | #define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */ |
0af36739 YL |
91 | #define STS_ASS (1<<15) /* Async Schedule Status */ |
92 | #define STS_PSS (1<<14) /* Periodic Schedule Status */ | |
93 | #define STS_RECL (1<<13) /* Reclamation */ | |
94 | #define STS_HALT (1<<12) /* Not running (any reason) */ | |
95 | /* some bits reserved */ | |
96 | /* these STS_* flags are also intr_enable bits (USBINTR) */ | |
97 | #define STS_IAA (1<<5) /* Interrupted on async advance */ | |
98 | #define STS_FATAL (1<<4) /* such as some PCI access errors */ | |
99 | #define STS_FLR (1<<3) /* frame list rolled over */ | |
100 | #define STS_PCD (1<<2) /* port change detect */ | |
101 | #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ | |
102 | #define STS_INT (1<<0) /* "normal" completion (short, ...) */ | |
103 | ||
104 | /* USBINTR: offset 0x08 */ | |
105 | u32 intr_enable; | |
106 | ||
107 | /* FRINDEX: offset 0x0C */ | |
108 | u32 frame_index; /* current microframe number */ | |
109 | /* CTRLDSSEGMENT: offset 0x10 */ | |
110 | u32 segment; /* address bits 63:32 if needed */ | |
111 | /* PERIODICLISTBASE: offset 0x14 */ | |
112 | u32 frame_list; /* points to periodic list */ | |
113 | /* ASYNCLISTADDR: offset 0x18 */ | |
114 | u32 async_next; /* address of next async queue head */ | |
115 | ||
a46af4eb AS |
116 | u32 reserved1[2]; |
117 | ||
118 | /* TXFILLTUNING: offset 0x24 */ | |
119 | u32 txfill_tuning; /* TX FIFO Tuning register */ | |
120 | #define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */ | |
121 | ||
122 | u32 reserved2[6]; | |
0af36739 YL |
123 | |
124 | /* CONFIGFLAG: offset 0x40 */ | |
125 | u32 configured_flag; | |
126 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ | |
127 | ||
128 | /* PORTSC: offset 0x44 */ | |
0858a3a5 | 129 | u32 port_status[0]; /* up to N_PORTS */ |
aa4d8342 AD |
130 | /* EHCI 1.1 addendum */ |
131 | #define PORTSC_SUSPEND_STS_ACK 0 | |
132 | #define PORTSC_SUSPEND_STS_NYET 1 | |
133 | #define PORTSC_SUSPEND_STS_STALL 2 | |
134 | #define PORTSC_SUSPEND_STS_ERR 3 | |
135 | ||
136 | #define PORT_DEV_ADDR (0x7f<<25) /* device address */ | |
137 | #define PORT_SSTS (0x3<<23) /* suspend status */ | |
0af36739 YL |
138 | /* 31:23 reserved */ |
139 | #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ | |
140 | #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ | |
141 | #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ | |
142 | /* 19:16 for port testing */ | |
79ad3b5a BG |
143 | #define PORT_TEST(x) (((x)&0xf)<<16) /* Port Test Control */ |
144 | #define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */ | |
145 | #define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */ | |
0af36739 YL |
146 | #define PORT_LED_OFF (0<<14) |
147 | #define PORT_LED_AMBER (1<<14) | |
148 | #define PORT_LED_GREEN (2<<14) | |
149 | #define PORT_LED_MASK (3<<14) | |
150 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ | |
151 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ | |
152 | #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ | |
153 | /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ | |
154 | /* 9 reserved */ | |
aa4d8342 | 155 | #define PORT_LPM (1<<9) /* LPM transaction */ |
0af36739 YL |
156 | #define PORT_RESET (1<<8) /* reset port */ |
157 | #define PORT_SUSPEND (1<<7) /* suspend port */ | |
158 | #define PORT_RESUME (1<<6) /* resume it */ | |
159 | #define PORT_OCC (1<<5) /* over current change */ | |
160 | #define PORT_OC (1<<4) /* over current active */ | |
161 | #define PORT_PEC (1<<3) /* port enable change */ | |
162 | #define PORT_PE (1<<2) /* port enable */ | |
163 | #define PORT_CSC (1<<1) /* connect status change */ | |
164 | #define PORT_CONNECT (1<<0) /* device connected */ | |
165 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) | |
0af36739 | 166 | |
a46af4eb AS |
167 | u32 reserved3[9]; |
168 | ||
169 | /* USBMODE: offset 0x68 */ | |
170 | u32 usbmode; /* USB Device mode */ | |
0af36739 YL |
171 | #define USBMODE_SDIS (1<<3) /* Stream disable */ |
172 | #define USBMODE_BE (1<<2) /* BE/LE endianness select */ | |
173 | #define USBMODE_CM_HC (3<<0) /* host controller mode */ | |
174 | #define USBMODE_CM_IDLE (0<<0) /* idle state */ | |
175 | ||
45c2da62 | 176 | u32 reserved4[6]; |
a46af4eb | 177 | |
331ac6b2 | 178 | /* Moorestown has some non-standard registers, partially due to the fact that |
25985edc | 179 | * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to |
331ac6b2 AD |
180 | * PORTSCx |
181 | */ | |
a46af4eb | 182 | /* HOSTPC: offset 0x84 */ |
45c2da62 | 183 | u32 hostpc[1]; /* HOSTPC extension */ |
331ac6b2 AD |
184 | #define HOSTPC_PHCD (1<<22) /* Phy clock disable */ |
185 | #define HOSTPC_PSPD (3<<25) /* Port speed detection */ | |
a46af4eb | 186 | |
45c2da62 | 187 | u32 reserved5[16]; |
a46af4eb AS |
188 | |
189 | /* USBMODE_EX: offset 0xc8 */ | |
190 | u32 usbmode_ex; /* USB Device mode extension */ | |
331ac6b2 AD |
191 | #define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ |
192 | #define USBMODE_EX_HC (3<<0) /* host controller mode */ | |
a46af4eb | 193 | }; |
331ac6b2 | 194 | |
0af36739 | 195 | #endif /* __LINUX_USB_EHCI_DEF_H */ |