[deliverable/linux.git] / include / linux / usb / msm_hsusb.h

/* linux/include/asm-arm/arch-msm/hsusb.h
 *
 * Copyright (C) 2008 Google, Inc.
 * Author: Brian Swetland <swetland@google.com>
 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __ASM_ARCH_MSM_HSUSB_H
#define __ASM_ARCH_MSM_HSUSB_H

#include <linux/types.h>
#include <linux/usb/otg.h>
#include <linux/clk.h>

/**
 * OTG control
 *
 * OTG_NO_CONTROL	Id/VBUS notifications not required. Useful in host
 *                      only configuration.
 * OTG_PHY_CONTROL	Id/VBUS notifications comes form USB PHY.
 * OTG_PMIC_CONTROL	Id/VBUS notifications comes from PMIC hardware.
 * OTG_USER_CONTROL	Id/VBUS notifcations comes from User via sysfs.
 *
 */
enum otg_control_type {
	OTG_NO_CONTROL = 0,
	OTG_PHY_CONTROL,
	OTG_PMIC_CONTROL,
	OTG_USER_CONTROL,
};

/**
 * PHY used in
 *
 * INVALID_PHY			Unsupported PHY
 * CI_45NM_INTEGRATED_PHY	Chipidea 45nm integrated PHY
 * SNPS_28NM_INTEGRATED_PHY	Synopsis 28nm integrated PHY
 *
 */
enum msm_usb_phy_type {
	INVALID_PHY = 0,
	CI_45NM_INTEGRATED_PHY,
	SNPS_28NM_INTEGRATED_PHY,
};

#define IDEV_CHG_MAX	1500
#define IUNIT		100

/**
 * Different states involved in USB charger detection.
 *
 * USB_CHG_STATE_UNDEFINED	USB charger is not connected or detection
 *                              process is not yet started.
 * USB_CHG_STATE_WAIT_FOR_DCD	Waiting for Data pins contact.
 * USB_CHG_STATE_DCD_DONE	Data pin contact is detected.
 * USB_CHG_STATE_PRIMARY_DONE	Primary detection is completed (Detects
 *                              between SDP and DCP/CDP).
 * USB_CHG_STATE_SECONDARY_DONE	Secondary detection is completed (Detects
 *                              between DCP and CDP).
 * USB_CHG_STATE_DETECTED	USB charger type is determined.
 *
 */
enum usb_chg_state {
	USB_CHG_STATE_UNDEFINED = 0,
	USB_CHG_STATE_WAIT_FOR_DCD,
	USB_CHG_STATE_DCD_DONE,
	USB_CHG_STATE_PRIMARY_DONE,
	USB_CHG_STATE_SECONDARY_DONE,
	USB_CHG_STATE_DETECTED,
};

/**
 * USB charger types
 *
 * USB_INVALID_CHARGER	Invalid USB charger.
 * USB_SDP_CHARGER	Standard downstream port. Refers to a downstream port
 *                      on USB2.0 compliant host/hub.
 * USB_DCP_CHARGER	Dedicated charger port (AC charger/ Wall charger).
 * USB_CDP_CHARGER	Charging downstream port. Enumeration can happen and
 *                      IDEV_CHG_MAX can be drawn irrespective of USB state.
 *
 */
enum usb_chg_type {
	USB_INVALID_CHARGER = 0,
	USB_SDP_CHARGER,
	USB_DCP_CHARGER,
	USB_CDP_CHARGER,
};

/**
 * struct msm_otg_platform_data - platform device data
 *              for msm_otg driver.
 * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as
 *              "do not overwrite default vaule at this address".
 * @phy_init_sz: PHY configuration sequence size.
 * @vbus_power: VBUS power on/off routine.
 * @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
 * @mode: Supported mode (OTG/peripheral/host).
 * @otg_control: OTG switch controlled by user/Id pin
 */
struct msm_otg_platform_data {
	int *phy_init_seq;
	int phy_init_sz;
	void (*vbus_power)(bool on);
	unsigned power_budget;
	enum usb_dr_mode mode;
	enum otg_control_type otg_control;
	enum msm_usb_phy_type phy_type;
	void (*setup_gpio)(enum usb_otg_state state);
};

/**
 * struct msm_otg: OTG driver data. Shared by HCD and DCD.
 * @otg: USB OTG Transceiver structure.
 * @pdata: otg device platform data.
 * @irq: IRQ number assigned for HSUSB controller.
 * @clk: clock struct of usb_hs_clk.
 * @pclk: clock struct of usb_hs_pclk.
 * @core_clk: clock struct of usb_hs_core_clk.
 * @regs: ioremapped register base address.
 * @inputs: OTG state machine inputs(Id, SessValid etc).
 * @sm_work: OTG state machine work.
 * @in_lpm: indicates low power mode (LPM) state.
 * @async_int: Async interrupt arrived.
 * @cur_power: The amount of mA available from downstream port.
 * @chg_work: Charger detection work.
 * @chg_state: The state of charger detection process.
 * @chg_type: The type of charger attached.
 * @dcd_retires: The retry count used to track Data contact
 *               detection process.
 */
struct msm_otg {
	struct usb_phy phy;
	struct msm_otg_platform_data *pdata;
	int irq;
	struct clk *clk;
	struct clk *pclk;
	struct clk *core_clk;
	void __iomem *regs;
#define ID		0
#define B_SESS_VLD	1
	unsigned long inputs;
	struct work_struct sm_work;
	atomic_t in_lpm;
	int async_int;
	unsigned cur_power;
	int phy_number;
	struct delayed_work chg_work;
	enum usb_chg_state chg_state;
	enum usb_chg_type chg_type;
	u8 dcd_retries;
	struct regulator *v3p3;
	struct regulator *v1p8;
	struct regulator *vddcx;

	struct reset_control *phy_rst;
	struct reset_control *link_rst;
	int vdd_levels[3];
};

#endif
Commit	Line	Data
e0c201f3 PK	1	/* linux/include/asm-arm/arch-msm/hsusb.h
	2	*
	3	* Copyright (C) 2008 Google, Inc.
	4	* Author: Brian Swetland <swetland@google.com>
d860852e	5	* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
e0c201f3 PK	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	*/
	17
	18	#ifndef __ASM_ARCH_MSM_HSUSB_H
	19	#define __ASM_ARCH_MSM_HSUSB_H
	20
	21	#include <linux/types.h>
	22	#include <linux/usb/otg.h>
5146d771	23	#include <linux/clk.h>
e0c201f3	24
e0c201f3 PK	25	/**
	26	* OTG control
	27	*
	28	* OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host
	29	* only configuration.
	30	* OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY.
	31	* OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware.
	32	* OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs.
	33	*
	34	*/
	35	enum otg_control_type {
	36	OTG_NO_CONTROL = 0,
	37	OTG_PHY_CONTROL,
	38	OTG_PMIC_CONTROL,
	39	OTG_USER_CONTROL,
	40	};
	41
d860852e PK	42	/**
	43	* PHY used in
	44	*
	45	* INVALID_PHY Unsupported PHY
	46	* CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
	47	* SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
	48	*
	49	*/
	50	enum msm_usb_phy_type {
	51	INVALID_PHY = 0,
	52	CI_45NM_INTEGRATED_PHY,
	53	SNPS_28NM_INTEGRATED_PHY,
	54	};
	55
	56	#define IDEV_CHG_MAX 1500
	57	#define IUNIT 100
	58
	59	/**
	60	* Different states involved in USB charger detection.
	61	*
	62	* USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
	63	* process is not yet started.
	64	* USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
	65	* USB_CHG_STATE_DCD_DONE Data pin contact is detected.
	66	* USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
	67	* between SDP and DCP/CDP).
	68	* USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
	69	* between DCP and CDP).
	70	* USB_CHG_STATE_DETECTED USB charger type is determined.
	71	*
	72	*/
	73	enum usb_chg_state {
	74	USB_CHG_STATE_UNDEFINED = 0,
	75	USB_CHG_STATE_WAIT_FOR_DCD,
	76	USB_CHG_STATE_DCD_DONE,
	77	USB_CHG_STATE_PRIMARY_DONE,
	78	USB_CHG_STATE_SECONDARY_DONE,
	79	USB_CHG_STATE_DETECTED,
	80	};
	81
	82	/**
	83	* USB charger types
	84	*
	85	* USB_INVALID_CHARGER Invalid USB charger.
	86	* USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
	87	* on USB2.0 compliant host/hub.
	88	* USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
	89	* USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
	90	* IDEV_CHG_MAX can be drawn irrespective of USB state.
	91	*
	92	*/
	93	enum usb_chg_type {
	94	USB_INVALID_CHARGER = 0,
	95	USB_SDP_CHARGER,
	96	USB_DCP_CHARGER,
	97	USB_CDP_CHARGER,
	98	};
	99
e0c201f3 PK	100	/**
e0c201f3 PK	101	* struct msm_otg_platform_data - platform device data
dfb2130c	102	* for msm_otg driver.
8364f9af II	103	* @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as
	104	* "do not overwrite default vaule at this address".
	105	* @phy_init_sz: PHY configuration sequence size.
e0c201f3 PK	106	* @vbus_power: VBUS power on/off routine.
	107	* @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
	108	* @mode: Supported mode (OTG/peripheral/host).
	109	* @otg_control: OTG switch controlled by user/Id pin
e0c201f3 PK	110	*/
	111	struct msm_otg_platform_data {
	112	int *phy_init_seq;
8364f9af	113	int phy_init_sz;
e0c201f3 PK	114	void (*vbus_power)(bool on);
e0c201f3 PK	115	unsigned power_budget;
971232cf	116	enum usb_dr_mode mode;
e0c201f3	117	enum otg_control_type otg_control;
d860852e	118	enum msm_usb_phy_type phy_type;
e0c201f3 PK	119	void (*setup_gpio)(enum usb_otg_state state);
	120	};
	121
	122	/**
	123	* struct msm_otg: OTG driver data. Shared by HCD and DCD.
	124	* @otg: USB OTG Transceiver structure.
	125	* @pdata: otg device platform data.
	126	* @irq: IRQ number assigned for HSUSB controller.
	127	* @clk: clock struct of usb_hs_clk.
	128	* @pclk: clock struct of usb_hs_pclk.
e0c201f3 PK	129	* @core_clk: clock struct of usb_hs_core_clk.
	130	* @regs: ioremapped register base address.
	131	* @inputs: OTG state machine inputs(Id, SessValid etc).
	132	* @sm_work: OTG state machine work.
87c0104a PK	133	* @in_lpm: indicates low power mode (LPM) state.
87c0104a PK	134	* @async_int: Async interrupt arrived.
d860852e PK	135	* @cur_power: The amount of mA available from downstream port.
	136	* @chg_work: Charger detection work.
	137	* @chg_state: The state of charger detection process.
	138	* @chg_type: The type of charger attached.
	139	* @dcd_retires: The retry count used to track Data contact
	140	* detection process.
e0c201f3 PK	141	*/
e0c201f3 PK	142	struct msm_otg {
1d4c9293	143	struct usb_phy phy;
e0c201f3 PK	144	struct msm_otg_platform_data *pdata;
	145	int irq;
	146	struct clk *clk;
	147	struct clk *pclk;
e0c201f3 PK	148	struct clk *core_clk;
	149	void __iomem *regs;
	150	#define ID 0
	151	#define B_SESS_VLD 1
	152	unsigned long inputs;
	153	struct work_struct sm_work;
87c0104a PK	154	atomic_t in_lpm;
87c0104a PK	155	int async_int;
d860852e	156	unsigned cur_power;
cfa3ff5d	157	int phy_number;
d860852e PK	158	struct delayed_work chg_work;
	159	enum usb_chg_state chg_state;
	160	enum usb_chg_type chg_type;
	161	u8 dcd_retries;
37cfdaf7 II	162	struct regulator *v3p3;
	163	struct regulator *v1p8;
	164	struct regulator *vddcx;
a2734543 II	165
	166	struct reset_control *phy_rst;
	167	struct reset_control *link_rst;
01799b62	168	int vdd_levels[3];
e0c201f3 PK	169	};
	170
	171	#endif