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529d6dad SB |
1 | /* |
2 | * Copyright (C) ST-Ericsson AB 2010 | |
3 | * Author: Daniel Martensson / Daniel.Martensson@stericsson.com | |
4 | * License terms: GNU General Public License (GPL) version 2 | |
5 | */ | |
6 | ||
7 | #ifndef CAIF_SPI_H_ | |
8 | #define CAIF_SPI_H_ | |
9 | ||
10 | #include <net/caif/caif_device.h> | |
11 | ||
12 | #define SPI_CMD_WR 0x00 | |
13 | #define SPI_CMD_RD 0x01 | |
14 | #define SPI_CMD_EOT 0x02 | |
15 | #define SPI_CMD_IND 0x04 | |
16 | ||
17 | #define SPI_DMA_BUF_LEN 8192 | |
18 | ||
19 | #define WL_SZ 2 /* 16 bits. */ | |
20 | #define SPI_CMD_SZ 4 /* 32 bits. */ | |
21 | #define SPI_IND_SZ 4 /* 32 bits. */ | |
22 | ||
23 | #define SPI_XFER 0 | |
24 | #define SPI_SS_ON 1 | |
25 | #define SPI_SS_OFF 2 | |
26 | #define SPI_TERMINATE 3 | |
27 | ||
28 | /* Minimum time between different levels is 50 microseconds. */ | |
29 | #define MIN_TRANSITION_TIME_USEC 50 | |
30 | ||
31 | /* Defines for calculating duration of SPI transfers for a particular | |
32 | * number of bytes. | |
33 | */ | |
34 | #define SPI_MASTER_CLK_MHZ 13 | |
35 | #define SPI_XFER_TIME_USEC(bytes, clk) (((bytes) * 8) / clk) | |
36 | ||
37 | /* Normally this should be aligned on the modem in order to benefit from full | |
38 | * duplex transfers. However a size of 8188 provokes errors when running with | |
39 | * the modem. These errors occur when packet sizes approaches 4 kB of data. | |
40 | */ | |
41 | #define CAIF_MAX_SPI_FRAME 4092 | |
42 | ||
43 | /* Maximum number of uplink CAIF frames that can reside in the same SPI frame. | |
44 | * This number should correspond with the modem setting. The application side | |
45 | * CAIF accepts any number of embedded downlink CAIF frames. | |
46 | */ | |
47 | #define CAIF_MAX_SPI_PKTS 9 | |
48 | ||
49 | /* Decides if SPI buffers should be prefilled with 0xFF pattern for easier | |
50 | * debugging. Both TX and RX buffers will be filled before the transfer. | |
51 | */ | |
52 | #define CFSPI_DBG_PREFILL 0 | |
53 | ||
54 | /* Structure describing a SPI transfer. */ | |
55 | struct cfspi_xfer { | |
56 | u16 tx_dma_len; | |
57 | u16 rx_dma_len; | |
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58 | void *va_tx[2]; |
59 | dma_addr_t pa_tx[2]; | |
529d6dad SB |
60 | void *va_rx; |
61 | dma_addr_t pa_rx; | |
62 | }; | |
63 | ||
64 | /* Structure implemented by the SPI interface. */ | |
65 | struct cfspi_ifc { | |
66 | void (*ss_cb) (bool assert, struct cfspi_ifc *ifc); | |
67 | void (*xfer_done_cb) (struct cfspi_ifc *ifc); | |
68 | void *priv; | |
69 | }; | |
70 | ||
71 | /* Structure implemented by SPI clients. */ | |
72 | struct cfspi_dev { | |
73 | int (*init_xfer) (struct cfspi_xfer *xfer, struct cfspi_dev *dev); | |
74 | void (*sig_xfer) (bool xfer, struct cfspi_dev *dev); | |
75 | struct cfspi_ifc *ifc; | |
76 | char *name; | |
77 | u32 clk_mhz; | |
78 | void *priv; | |
79 | }; | |
80 | ||
81 | /* Enumeration describing the CAIF SPI state. */ | |
82 | enum cfspi_state { | |
83 | CFSPI_STATE_WAITING = 0, | |
84 | CFSPI_STATE_AWAKE, | |
85 | CFSPI_STATE_FETCH_PKT, | |
86 | CFSPI_STATE_GET_NEXT, | |
87 | CFSPI_STATE_INIT_XFER, | |
88 | CFSPI_STATE_WAIT_ACTIVE, | |
89 | CFSPI_STATE_SIG_ACTIVE, | |
90 | CFSPI_STATE_WAIT_XFER_DONE, | |
91 | CFSPI_STATE_XFER_DONE, | |
92 | CFSPI_STATE_WAIT_INACTIVE, | |
93 | CFSPI_STATE_SIG_INACTIVE, | |
94 | CFSPI_STATE_DELIVER_PKT, | |
95 | CFSPI_STATE_MAX, | |
96 | }; | |
97 | ||
98 | /* Structure implemented by SPI physical interfaces. */ | |
99 | struct cfspi { | |
100 | struct caif_dev_common cfdev; | |
101 | struct net_device *ndev; | |
102 | struct platform_device *pdev; | |
103 | struct sk_buff_head qhead; | |
104 | struct sk_buff_head chead; | |
105 | u16 cmd; | |
106 | u16 tx_cpck_len; | |
107 | u16 tx_npck_len; | |
108 | u16 rx_cpck_len; | |
109 | u16 rx_npck_len; | |
110 | struct cfspi_ifc ifc; | |
111 | struct cfspi_xfer xfer; | |
112 | struct cfspi_dev *dev; | |
113 | unsigned long state; | |
114 | struct work_struct work; | |
115 | struct workqueue_struct *wq; | |
116 | struct list_head list; | |
117 | int flow_off_sent; | |
118 | u32 qd_low_mark; | |
119 | u32 qd_high_mark; | |
120 | struct completion comp; | |
121 | wait_queue_head_t wait; | |
122 | spinlock_t lock; | |
123 | bool flow_stop; | |
2c24a5d1 SB |
124 | bool slave; |
125 | bool slave_talked; | |
529d6dad SB |
126 | #ifdef CONFIG_DEBUG_FS |
127 | enum cfspi_state dbg_state; | |
128 | u16 pcmd; | |
129 | u16 tx_ppck_len; | |
130 | u16 rx_ppck_len; | |
131 | struct dentry *dbgfs_dir; | |
132 | struct dentry *dbgfs_state; | |
133 | struct dentry *dbgfs_frame; | |
134 | #endif /* CONFIG_DEBUG_FS */ | |
135 | }; | |
136 | ||
137 | extern int spi_frm_align; | |
138 | extern int spi_up_head_align; | |
139 | extern int spi_up_tail_align; | |
140 | extern int spi_down_head_align; | |
141 | extern int spi_down_tail_align; | |
142 | extern struct platform_driver cfspi_spi_driver; | |
143 | ||
144 | void cfspi_dbg_state(struct cfspi *cfspi, int state); | |
145 | int cfspi_xmitfrm(struct cfspi *cfspi, u8 *buf, size_t len); | |
146 | int cfspi_xmitlen(struct cfspi *cfspi); | |
147 | int cfspi_rxfrm(struct cfspi *cfspi, u8 *buf, size_t len); | |
148 | int cfspi_spi_remove(struct platform_device *pdev); | |
149 | int cfspi_spi_probe(struct platform_device *pdev); | |
150 | int cfspi_xmitfrm(struct cfspi *cfspi, u8 *buf, size_t len); | |
151 | int cfspi_xmitlen(struct cfspi *cfspi); | |
152 | int cfspi_rxfrm(struct cfspi *cfspi, u8 *buf, size_t len); | |
153 | void cfspi_xfer(struct work_struct *work); | |
154 | ||
155 | #endif /* CAIF_SPI_H_ */ |