Commit | Line | Data |
---|---|---|
15965411 L |
1 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
2 | ||
3 | * i386.h (i386_optab): Add "nop" with memory reference. | |
4 | ||
46e883c5 L |
5 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
6 | ||
7 | * i386.h (i386_optab): Update comment for 64bit NOP. | |
8 | ||
9622b051 AM |
9 | 2006-06-06 Ben Elliston <bje@au.ibm.com> |
10 | Anton Blanchard <anton@samba.org> | |
11 | ||
12 | * ppc.h (PPC_OPCODE_POWER6): Define. | |
13 | Adjust whitespace. | |
14 | ||
a9e24354 TS |
15 | 2006-06-05 Thiemo Seufer <ths@mips.com> |
16 | ||
17 | * mips.h: Improve description of MT flags. | |
18 | ||
a596001e RS |
19 | 2006-05-25 Richard Sandiford <richard@codesourcery.com> |
20 | ||
21 | * m68k.h (mcf_mask): Define. | |
22 | ||
d43b4baf TS |
23 | 2006-05-05 Thiemo Seufer <ths@mips.com> |
24 | David Ung <davidu@mips.com> | |
25 | ||
26 | * mips.h (enum): Add macro M_CACHE_AB. | |
27 | ||
39a7806d TS |
28 | 2006-05-04 Thiemo Seufer <ths@mips.com> |
29 | Nigel Stephens <nigel@mips.com> | |
30 | David Ung <davidu@mips.com> | |
31 | ||
32 | * mips.h: Add INSN_SMARTMIPS define. | |
33 | ||
9bcd4f99 TS |
34 | 2006-04-30 Thiemo Seufer <ths@mips.com> |
35 | David Ung <davidu@mips.com> | |
36 | ||
37 | * mips.h: Defines udi bits and masks. Add description of | |
38 | characters which may appear in the args field of udi | |
39 | instructions. | |
40 | ||
ef0ee844 TS |
41 | 2006-04-26 Thiemo Seufer <ths@networkno.de> |
42 | ||
43 | * mips.h: Improve comments describing the bitfield instruction | |
44 | fields. | |
45 | ||
f7675147 L |
46 | 2006-04-26 Julian Brown <julian@codesourcery.com> |
47 | ||
48 | * arm.h (FPU_VFP_EXT_V3): Define constant. | |
49 | (FPU_NEON_EXT_V1): Likewise. | |
50 | (FPU_VFP_HARD): Update. | |
51 | (FPU_VFP_V3): Define macro. | |
52 | (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. | |
53 | ||
ef0ee844 | 54 | 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> |
d727e8c2 NC |
55 | |
56 | * avr.h (AVR_ISA_PWMx): New. | |
57 | ||
2da12c60 NS |
58 | 2006-03-28 Nathan Sidwell <nathan@codesourcery.com> |
59 | ||
60 | * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, | |
61 | cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, | |
62 | cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, | |
63 | cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, | |
64 | cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. | |
65 | ||
0715c387 PB |
66 | 2006-03-10 Paul Brook <paul@codesourcery.com> |
67 | ||
68 | * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. | |
69 | ||
34bdd094 DA |
70 | 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
71 | ||
72 | * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come | |
73 | first. Correct mask of bb "B" opcode. | |
74 | ||
331d2d0d L |
75 | 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> |
76 | ||
77 | * i386.h (i386_optab): Support Intel Merom New Instructions. | |
78 | ||
62b3e311 PB |
79 | 2006-02-24 Paul Brook <paul@codesourcery.com> |
80 | ||
81 | * arm.h: Add V7 feature bits. | |
82 | ||
59cf82fe L |
83 | 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> |
84 | ||
85 | * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. | |
86 | ||
e74cfd16 PB |
87 | 2006-01-31 Paul Brook <paul@codesourcery.com> |
88 | Richard Earnshaw <rearnsha@arm.com> | |
89 | ||
90 | * arm.h: Use ARM_CPU_FEATURE. | |
91 | (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. | |
92 | (arm_feature_set): Change to a structure. | |
93 | (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, | |
94 | ARM_FEATURE): New macros. | |
95 | ||
5b3f8a92 HPN |
96 | 2005-12-07 Hans-Peter Nilsson <hp@axis.com> |
97 | ||
98 | * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) | |
99 | (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. | |
100 | (ADD_PC_INCR_OPCODE): Don't define. | |
101 | ||
cb712a9e L |
102 | 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> |
103 | ||
104 | PR gas/1874 | |
105 | * i386.h (i386_optab): Add 64bit support for monitor and mwait. | |
106 | ||
0499d65b TS |
107 | 2005-11-14 David Ung <davidu@mips.com> |
108 | ||
109 | * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore | |
110 | instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for | |
111 | save/restore encoding of the args field. | |
112 | ||
ea5ca089 DB |
113 | 2005-10-28 Dave Brolley <brolley@redhat.com> |
114 | ||
115 | Contribute the following changes: | |
116 | 2005-02-16 Dave Brolley <brolley@redhat.com> | |
117 | ||
118 | * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename | |
119 | cgen_isa_mask_* to cgen_bitset_*. | |
120 | * cgen.h: Likewise. | |
121 | ||
16175d96 DB |
122 | 2003-10-21 Richard Sandiford <rsandifo@redhat.com> |
123 | ||
124 | * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. | |
125 | (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". | |
126 | (CGEN_CPU_TABLE): Make isas a ponter. | |
127 | ||
128 | 2003-09-29 Dave Brolley <brolley@redhat.com> | |
129 | ||
130 | * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. | |
131 | (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. | |
132 | (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. | |
133 | ||
134 | 2002-12-13 Dave Brolley <brolley@redhat.com> | |
135 | ||
136 | * cgen.h (symcat.h): #include it. | |
137 | (cgen-bitset.h): #include it. | |
138 | (CGEN_ATTR_VALUE_TYPE): Now a union. | |
139 | (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. | |
140 | (CGEN_ATTR_ENTRY): 'value' now unsigned. | |
141 | (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). | |
142 | * cgen-bitset.h: New file. | |
143 | ||
3c9b82ba NC |
144 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
145 | ||
146 | * bfin.h: New file. | |
147 | ||
6a2375c6 JB |
148 | 2005-10-24 Jan Beulich <jbeulich@novell.com> |
149 | ||
150 | * ia64.h (enum ia64_opnd): Move memory operand out of set of | |
151 | indirect operands. | |
152 | ||
c06a12f8 DA |
153 | 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
154 | ||
155 | * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. | |
156 | Add FLAG_STRICT to pa10 ftest opcode. | |
157 | ||
4d443107 DA |
158 | 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
159 | ||
160 | * hppa.h (pa_opcodes): Remove lha entries. | |
161 | ||
f0a3b40f DA |
162 | 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
163 | ||
164 | * hppa.h (FLAG_STRICT): Revise comment. | |
165 | (pa_opcode): Revise ordering rules. Add/move strict pa10 variants | |
166 | before corresponding pa11 opcodes. Add strict pa10 register-immediate | |
167 | entries for "fdc". | |
168 | ||
1b7e1362 DA |
169 | 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
170 | ||
171 | * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. | |
172 | ||
089b39de CF |
173 | 2005-09-06 Chao-ying Fu <fu@mips.com> |
174 | ||
175 | * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, | |
176 | OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New | |
177 | define. | |
178 | Document !, $, *, &, g, +t, +T operand formats for MT instructions. | |
179 | (INSN_ASE_MASK): Update to include INSN_MT. | |
180 | (INSN_MT): New define for MT ASE. | |
181 | ||
93c34b9b CF |
182 | 2005-08-25 Chao-ying Fu <fu@mips.com> |
183 | ||
184 | * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, | |
185 | OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, | |
186 | OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, | |
187 | OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, | |
188 | OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. | |
189 | Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP | |
190 | instructions. | |
191 | (INSN_DSP): New define for DSP ASE. | |
192 | ||
848cf006 AM |
193 | 2005-08-18 Alan Modra <amodra@bigpond.net.au> |
194 | ||
195 | * a29k.h: Delete. | |
196 | ||
36ae0db3 DJ |
197 | 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> |
198 | ||
199 | * ppc.h (PPC_OPCODE_E300): Define. | |
200 | ||
8c929562 MS |
201 | 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> |
202 | ||
203 | * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. | |
204 | ||
f7b8cccc DA |
205 | 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
206 | ||
207 | PR gas/336 | |
208 | * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb | |
209 | and pitlb. | |
210 | ||
8b5328ac JB |
211 | 2005-07-27 Jan Beulich <jbeulich@novell.com> |
212 | ||
213 | * i386.h (i386_optab): Add comment to movd. Use LongMem for all | |
214 | movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. | |
215 | Add movq-s as 64-bit variants of movd-s. | |
216 | ||
f417d200 DA |
217 | 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
218 | ||
18b3bdfc DA |
219 | * hppa.h: Fix punctuation in comment. |
220 | ||
f417d200 DA |
221 | * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for |
222 | implicit space-register addressing. Set space-register bits on opcodes | |
223 | using implicit space-register addressing. Add various missing pa20 | |
224 | long-immediate opcodes. Remove various opcodes using implicit 3-bit | |
225 | space-register addressing. Use "fE" instead of "fe" in various | |
226 | fstw opcodes. | |
227 | ||
9a145ce6 JB |
228 | 2005-07-18 Jan Beulich <jbeulich@novell.com> |
229 | ||
230 | * i386.h (i386_optab): Operands of aam and aad are unsigned. | |
231 | ||
90700ea2 L |
232 | 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> |
233 | ||
234 | * i386.h (i386_optab): Support Intel VMX Instructions. | |
235 | ||
48f130a8 DA |
236 | 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
237 | ||
238 | * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. | |
239 | ||
30123838 JB |
240 | 2005-07-05 Jan Beulich <jbeulich@novell.com> |
241 | ||
242 | * i386.h (i386_optab): Add new insns. | |
243 | ||
47b0e7ad NC |
244 | 2005-07-01 Nick Clifton <nickc@redhat.com> |
245 | ||
246 | * sparc.h: Add typedefs to structure declarations. | |
247 | ||
b300c311 L |
248 | 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> |
249 | ||
250 | PR 1013 | |
251 | * i386.h (i386_optab): Update comments for 64bit addressing on | |
252 | mov. Allow 64bit addressing for mov and movq. | |
253 | ||
2db495be DA |
254 | 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
255 | ||
256 | * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, | |
257 | respectively, in various floating-point load and store patterns. | |
258 | ||
caa05036 DA |
259 | 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
260 | ||
261 | * hppa.h (FLAG_STRICT): Correct comment. | |
262 | (pa_opcodes): Update load and store entries to allow both PA 1.X and | |
263 | PA 2.0 mneumonics when equivalent. Entries with cache control | |
264 | completers now require PA 1.1. Adjust whitespace. | |
265 | ||
f4411256 AM |
266 | 2005-05-19 Anton Blanchard <anton@samba.org> |
267 | ||
268 | * ppc.h (PPC_OPCODE_POWER5): Define. | |
269 | ||
e172dbf8 NC |
270 | 2005-05-10 Nick Clifton <nickc@redhat.com> |
271 | ||
272 | * Update the address and phone number of the FSF organization in | |
273 | the GPL notices in the following files: | |
274 | a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, | |
275 | crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, | |
276 | i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, | |
277 | mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, | |
278 | pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, | |
279 | tic54x.h, tic80.h, v850.h, vax.h | |
280 | ||
e44823cf JB |
281 | 2005-05-09 Jan Beulich <jbeulich@novell.com> |
282 | ||
283 | * i386.h (i386_optab): Add ht and hnt. | |
284 | ||
791fe849 MK |
285 | 2005-04-18 Mark Kettenis <kettenis@gnu.org> |
286 | ||
287 | * i386.h: Insert hyphens into selected VIA PadLock extensions. | |
288 | Add xcrypt-ctr. Provide aliases without hyphens. | |
289 | ||
faa7ef87 L |
290 | 2005-04-13 H.J. Lu <hongjiu.lu@intel.com> |
291 | ||
a63027e5 L |
292 | Moved from ../ChangeLog |
293 | ||
faa7ef87 L |
294 | 2005-04-12 Paul Brook <paul@codesourcery.com> |
295 | * m88k.h: Rename psr macros to avoid conflicts. | |
296 | ||
297 | 2005-03-12 Zack Weinberg <zack@codesourcery.com> | |
298 | * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. | |
299 | Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, | |
300 | and ARM_ARCH_V6ZKT2. | |
301 | ||
302 | 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> | |
303 | * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. | |
304 | Remove redundant instruction types. | |
305 | (struct argument): X_op - new field. | |
306 | (struct cst4_entry): Remove. | |
307 | (no_op_insn): Declare. | |
308 | ||
309 | 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> | |
310 | * crx.h (enum argtype): Rename types, remove unused types. | |
311 | ||
312 | 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> | |
313 | * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. | |
314 | (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. | |
315 | (enum operand_type): Rearrange operands, edit comments. | |
316 | replace us<N> with ui<N> for unsigned immediate. | |
317 | replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped | |
318 | displacements (respectively). | |
319 | replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. | |
320 | (instruction type): Add NO_TYPE_INS. | |
321 | (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. | |
322 | (operand_entry): New field - 'flags'. | |
323 | (operand flags): New. | |
324 | ||
325 | 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> | |
326 | * crx.h (operand_type): Remove redundant types i3, i4, | |
327 | i5, i8, i12. | |
328 | Add new unsigned immediate types us3, us4, us5, us16. | |
329 | ||
bc4bd9ab MK |
330 | 2005-04-12 Mark Kettenis <kettenis@gnu.org> |
331 | ||
332 | * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and | |
333 | adjust them accordingly. | |
334 | ||
373ff435 JB |
335 | 2005-04-01 Jan Beulich <jbeulich@novell.com> |
336 | ||
337 | * i386.h (i386_optab): Add rdtscp. | |
338 | ||
4cc91dba L |
339 | 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> |
340 | ||
341 | * i386.h (i386_optab): Don't allow the `l' suffix for moving | |
418a8fca AS |
342 | between memory and segment register. Allow movq for moving between |
343 | general-purpose register and segment register. | |
4cc91dba | 344 | |
9ae09ff9 JB |
345 | 2005-02-09 Jan Beulich <jbeulich@novell.com> |
346 | ||
347 | PR gas/707 | |
348 | * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and | |
349 | FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and | |
350 | fnstsw. | |
351 | ||
638e7a64 NS |
352 | 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> |
353 | ||
354 | * m68k.h (m68008, m68ec030, m68882): Remove. | |
355 | (m68k_mask): New. | |
356 | (cpu_m68k, cpu_cf): New. | |
357 | (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, | |
358 | mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. | |
359 | ||
90219bd0 AO |
360 | 2005-01-25 Alexandre Oliva <aoliva@redhat.com> |
361 | ||
362 | 2004-11-10 Alexandre Oliva <aoliva@redhat.com> | |
363 | * cgen.h (enum cgen_parse_operand_type): Add | |
364 | CGEN_PARSE_OPERAND_SYMBOLIC. | |
365 | ||
239cb185 FF |
366 | 2005-01-21 Fred Fish <fnf@specifixinc.com> |
367 | ||
368 | * mips.h: Change INSN_ALIAS to INSN2_ALIAS. | |
369 | Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. | |
370 | Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. | |
371 | ||
dc9a9f39 FF |
372 | 2005-01-19 Fred Fish <fnf@specifixinc.com> |
373 | ||
374 | * mips.h (struct mips_opcode): Add new pinfo2 member. | |
375 | (INSN_ALIAS): New define for opcode table entries that are | |
376 | specific instances of another entry, such as 'move' for an 'or' | |
377 | with a zero operand. | |
378 | (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. | |
379 | (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. | |
380 | ||
98e7aba8 ILT |
381 | 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> |
382 | ||
383 | * mips.h (CPU_RM9000): Define. | |
384 | (OPCODE_IS_MEMBER): Handle CPU_RM9000. | |
385 | ||
37edbb65 JB |
386 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
387 | ||
388 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves | |
389 | to/from test registers are illegal in 64-bit mode. Add missing | |
390 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix | |
391 | (previously one had to explicitly encode a rex64 prefix). Re-enable | |
392 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings | |
393 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. | |
394 | ||
395 | 2004-11-23 Jan Beulich <jbeulich@novell.com> | |
5c6af06e JB |
396 | |
397 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are | |
398 | available only with SSE2. Change the MMX additions introduced by SSE | |
399 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A | |
400 | instructions by their now designated identifier (since combining i686 | |
401 | and 3DNow! does not really imply 3DNow!A). | |
402 | ||
f5c7edf4 AM |
403 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
404 | ||
405 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, | |
406 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. | |
407 | ||
7499d566 NC |
408 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
409 | Vineet Sharma <vineets@noida.hcltech.com> | |
410 | ||
411 | * maxq.h: New file: Disassembly information for the maxq port. | |
412 | ||
bcb9eebe L |
413 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
414 | ||
415 | * i386.h (i386_optab): Put back "movzb". | |
416 | ||
94bb3d38 HPN |
417 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
418 | ||
419 | * cris.h (enum cris_insn_version_usage): Tweak formatting and | |
420 | comments. Remove member cris_ver_sim. Add members | |
421 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, | |
422 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. | |
423 | (struct cris_support_reg, struct cris_cond15): New types. | |
424 | (cris_conds15): Declare. | |
425 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) | |
426 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) | |
427 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. | |
428 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. | |
429 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and | |
430 | SIZE_FIELD_UNSIGNED. | |
431 | ||
37edbb65 | 432 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
9306ca4a JB |
433 | |
434 | * i386.h (sldx_Suf): Remove. | |
435 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. | |
436 | (q_FP): Define, implying no REX64. | |
437 | (x_FP, sl_FP): Imply FloatMF. | |
438 | (i386_optab): Split reg and mem forms of moving from segment registers | |
439 | so that the memory forms can ignore the 16-/32-bit operand size | |
440 | distinction. Adjust a few others for Intel mode. Remove *FP uses from | |
441 | all non-floating-point instructions. Unite 32- and 64-bit forms of | |
442 | movsx, movzx, and movd. Adjust floating point operations for the above | |
443 | changes to the *FP macros. Add DefaultSize to floating point control | |
444 | insns operating on larger memory ranges. Remove left over comments | |
445 | hinting at certain insns being Intel-syntax ones where the ones | |
446 | actually meant are already gone. | |
447 | ||
48c9f030 NC |
448 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
449 | ||
450 | * crx.h: Add COPS_REG_INS - Coprocessor Special register | |
451 | instruction type. | |
452 | ||
0dd132b6 NC |
453 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
454 | ||
455 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. | |
456 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. | |
457 | ||
23794b24 MM |
458 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
459 | ||
460 | * avr.h: Add support for | |
461 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. | |
462 | ||
2a309db0 AM |
463 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
464 | ||
465 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. | |
466 | ||
b18c562e NC |
467 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
468 | ||
469 | * msp430.h (msp430_opc): Add new instructions. | |
470 | (msp430_rcodes): Declare new instructions. | |
471 | (msp430_hcodes): Likewise.. | |
472 | ||
45d313cd NC |
473 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
474 | ||
475 | PR/301 | |
476 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX | |
477 | processors. | |
478 | ||
30d1c836 ML |
479 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
480 | ||
481 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. | |
482 | ||
9a45f1c2 L |
483 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
484 | ||
485 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. | |
486 | ||
543613e9 NC |
487 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
488 | ||
489 | * i386.h: Adjust instruction descriptions to better match the | |
490 | specification. | |
491 | ||
b781e558 RE |
492 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
493 | ||
494 | * arm.h: Remove all old content. Replace with architecture defines | |
495 | from gas/config/tc-arm.c. | |
496 | ||
8577e690 AS |
497 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
498 | ||
499 | * m68k.h: Fix comment. | |
500 | ||
1fe1f39c NC |
501 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
502 | ||
503 | * crx.h: New file. | |
504 | ||
1d9f512f AM |
505 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
506 | ||
507 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. | |
508 | ||
be8c092b NC |
509 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
510 | ||
511 | * m68k.h: Add 'size' to m68k_opcode. | |
512 | ||
6b6e92f4 NC |
513 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
514 | ||
515 | * m68k.h: Switch from ColdFire chip name to core variant. | |
516 | ||
517 | 2004-04-22 Peter Barada <peter@the-baradas.com> | |
fd99574b NC |
518 | |
519 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand | |
520 | descriptions for new EMAC cases. | |
521 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly | |
522 | handle Motorola MAC syntax. | |
523 | Allow disassembly of ColdFire V4e object files. | |
524 | ||
fdd12ef3 AM |
525 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
526 | ||
527 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. | |
528 | ||
3922a64c L |
529 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
530 | ||
531 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. | |
532 | ||
1f45d988 ML |
533 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
534 | ||
535 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. | |
536 | ||
0f10071e ML |
537 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
538 | ||
539 | * i386.h (i386_optab): Added xstore/xcrypt insns. | |
540 | ||
3255318a NC |
541 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
542 | ||
543 | * h8300.h (32bit ldc/stc): Add relaxing support. | |
544 | ||
ca9a79a1 | 545 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
fdd12ef3 | 546 | |
ca9a79a1 NC |
547 | * h8300.h (BITOP): Pass MEMRELAX flag. |
548 | ||
875a0b14 NC |
549 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
550 | ||
551 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 | |
552 | except for the H8S. | |
252b5132 | 553 | |
c9e214e5 | 554 | For older changes see ChangeLog-9103 |
252b5132 RH |
555 | \f |
556 | Local Variables: | |
c9e214e5 AM |
557 | mode: change-log |
558 | left-margin: 8 | |
559 | fill-column: 74 | |
252b5132 RH |
560 | version-control: never |
561 | End: |