Commit | Line | Data |
---|---|---|
081ba1b3 AM |
1 | 2008-07-30 Michael J. Eager <eager@eagercon.com> |
2 | ||
3 | * ppc.h (PPC_OPCODE_405): Define. | |
4 | (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. | |
5 | ||
fa452fa6 PB |
6 | 2008-06-13 Peter Bergner <bergner@vnet.ibm.com> |
7 | ||
8 | * ppc.h (ppc_cpu_t): New typedef. | |
9 | (struct powerpc_opcode <flags>): Use it. | |
10 | (struct powerpc_operand <insert, extract>): Likewise. | |
11 | (struct powerpc_macro <flags>): Likewise. | |
12 | ||
bb35fb24 NC |
13 | 2008-06-12 Adam Nemet <anemet@caviumnetworks.com> |
14 | ||
15 | * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. | |
16 | Update comment before MIPS16 field descriptors to mention MIPS16. | |
17 | (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for | |
18 | BBIT. | |
19 | (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): | |
20 | New bit masks and shift counts for cins and exts. | |
21 | ||
dd3cbb7e NC |
22 | * mips.h: Document new field descriptors +Q. |
23 | (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. | |
24 | ||
d0799671 AN |
25 | 2008-04-28 Adam Nemet <anemet@caviumnetworks.com> |
26 | ||
27 | * mips.h (INSN_MACRO): Move it up to the the pinfo macros. | |
28 | (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. | |
29 | ||
19a6653c AM |
30 | 2008-04-14 Edmar Wienskoski <edmar@freescale.com> |
31 | ||
32 | * ppc.h: (PPC_OPCODE_E500MC): New. | |
33 | ||
c0f3af97 L |
34 | 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> |
35 | ||
36 | * i386.h (MAX_OPERANDS): Set to 5. | |
37 | (MAX_MNEM_SIZE): Changed to 20. | |
38 | ||
e210c36b NC |
39 | 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> |
40 | ||
41 | * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. | |
42 | ||
b1cc4aeb PB |
43 | 2008-03-09 Paul Brook <paul@codesourcery.com> |
44 | ||
45 | * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. | |
46 | ||
7e806470 PB |
47 | 2008-03-04 Paul Brook <paul@codesourcery.com> |
48 | ||
49 | * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. | |
50 | (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. | |
51 | (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. | |
52 | ||
7b2185f9 | 53 | 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com> |
af7329f0 NC |
54 | Nick Clifton <nickc@redhat.com> |
55 | ||
56 | PR 3134 | |
57 | * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction | |
58 | with a 32-bit displacement but without the top bit of the 4th byte | |
59 | set. | |
60 | ||
796d5313 NC |
61 | 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> |
62 | ||
63 | * cr16.h (cr16_num_optab): Declared. | |
64 | ||
d669d37f NC |
65 | 2008-02-14 Hakan Ardo <hakan@debian.org> |
66 | ||
67 | PR gas/2626 | |
68 | * avr.h (AVR_ISA_2xxe): Define. | |
69 | ||
e6429699 AN |
70 | 2008-02-04 Adam Nemet <anemet@caviumnetworks.com> |
71 | ||
72 | * mips.h: Update copyright. | |
73 | (INSN_CHIP_MASK): New macro. | |
74 | (INSN_OCTEON): New macro. | |
75 | (CPU_OCTEON): New macro. | |
76 | (OPCODE_IS_MEMBER): Handle Octeon instructions. | |
77 | ||
e210c36b NC |
78 | 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> |
79 | ||
80 | * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. | |
81 | ||
82 | 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> | |
83 | ||
84 | * avr.h (AVR_ISA_USB162): Add new opcode set. | |
85 | (AVR_ISA_AVR3): Likewise. | |
86 | ||
350cc38d MS |
87 | 2007-11-29 Mark Shinwell <shinwell@codesourcery.com> |
88 | ||
89 | * mips.h (INSN_LOONGSON_2E): New. | |
90 | (INSN_LOONGSON_2F): New. | |
91 | (CPU_LOONGSON_2E): New. | |
92 | (CPU_LOONGSON_2F): New. | |
93 | (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. | |
94 | ||
56950294 MS |
95 | 2007-11-29 Mark Shinwell <shinwell@codesourcery.com> |
96 | ||
97 | * mips.h (INSN_ISA*): Redefine certain values as an | |
98 | enumeration. Update comments. | |
99 | (mips_isa_table): New. | |
100 | (ISA_MIPS*): Redefine to match enumeration. | |
101 | (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* | |
102 | values. | |
103 | ||
c3d65c1c BE |
104 | 2007-08-08 Ben Elliston <bje@au.ibm.com> |
105 | ||
106 | * ppc.h (PPC_OPCODE_PPCPS): New. | |
107 | ||
0fdaa005 L |
108 | 2007-07-03 Nathan Sidwell <nathan@codesourcery.com> |
109 | ||
110 | * m68k.h: Document j K & E. | |
111 | ||
112 | 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> | |
3d3d428f NC |
113 | |
114 | * cr16.h: New file for CR16 target. | |
115 | ||
3896c469 AM |
116 | 2007-05-02 Alan Modra <amodra@bigpond.net.au> |
117 | ||
118 | * ppc.h (PPC_OPERAND_PLUS1): Update comment. | |
119 | ||
9a2e615a NS |
120 | 2007-04-23 Nathan Sidwell <nathan@codesourcery.com> |
121 | ||
122 | * m68k.h (mcfisa_c): New. | |
123 | (mcfusp, mcf_mask): Adjust. | |
124 | ||
b84bf58a AM |
125 | 2007-04-20 Alan Modra <amodra@bigpond.net.au> |
126 | ||
127 | * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". | |
128 | (num_powerpc_operands): Declare. | |
129 | (PPC_OPERAND_SIGNED et al): Redefine as hex. | |
130 | (PPC_OPERAND_PLUS1): Define. | |
131 | ||
831480e9 | 132 | 2007-03-21 H.J. Lu <hongjiu.lu@intel.com> |
161a04f6 L |
133 | |
134 | * i386.h (REX_MODE64): Renamed to ... | |
135 | (REX_W): This. | |
136 | (REX_EXTX): Renamed to ... | |
137 | (REX_R): This. | |
138 | (REX_EXTY): Renamed to ... | |
139 | (REX_X): This. | |
140 | (REX_EXTZ): Renamed to ... | |
141 | (REX_B): This. | |
142 | ||
0b1cf022 L |
143 | 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> |
144 | ||
145 | * i386.h: Add entries from config/tc-i386.h and move tables | |
146 | to opcodes/i386-opc.h. | |
147 | ||
d796c0ad L |
148 | 2007-03-13 H.J. Lu <hongjiu.lu@intel.com> |
149 | ||
150 | * i386.h (FloatDR): Removed. | |
151 | (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. | |
152 | ||
30ac7323 AM |
153 | 2007-03-01 Alan Modra <amodra@bigpond.net.au> |
154 | ||
155 | * spu-insns.h: Add soma double-float insns. | |
156 | ||
8b082fb1 | 157 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
d796c0ad | 158 | Chao-Ying Fu <fu@mips.com> |
8b082fb1 TS |
159 | |
160 | * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. | |
161 | (INSN_DSPR2): Add flag for DSP R2 instructions. | |
162 | (M_BALIGN): New macro. | |
163 | ||
4eed87de AM |
164 | 2007-02-14 Alan Modra <amodra@bigpond.net.au> |
165 | ||
166 | * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm | |
167 | and Seg3ShortFrom with Shortform. | |
168 | ||
fda592e8 L |
169 | 2007-02-11 H.J. Lu <hongjiu.lu@intel.com> |
170 | ||
171 | PR gas/4027 | |
172 | * i386.h (i386_optab): Put the real "test" before the pseudo | |
173 | one. | |
174 | ||
3bdcfdf4 KH |
175 | 2007-01-08 Kazu Hirata <kazu@codesourcery.com> |
176 | ||
177 | * m68k.h (m68010up): OR fido_a. | |
178 | ||
9840d27e KH |
179 | 2006-12-25 Kazu Hirata <kazu@codesourcery.com> |
180 | ||
181 | * m68k.h (fido_a): New. | |
182 | ||
c629cdac KH |
183 | 2006-12-24 Kazu Hirata <kazu@codesourcery.com> |
184 | ||
185 | * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, | |
186 | mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined | |
187 | values. | |
188 | ||
b7d9ef37 L |
189 | 2006-11-08 H.J. Lu <hongjiu.lu@intel.com> |
190 | ||
191 | * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. | |
192 | ||
b138abaa NC |
193 | 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> |
194 | ||
195 | * score-inst.h (enum score_insn_type): Add Insn_internal. | |
196 | ||
e9f53129 AM |
197 | 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> |
198 | Yukishige Shibata <shibata@rd.scei.sony.co.jp> | |
199 | Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> | |
200 | Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> | |
201 | Alan Modra <amodra@bigpond.net.au> | |
202 | ||
203 | * spu-insns.h: New file. | |
204 | * spu.h: New file. | |
205 | ||
ede602d7 AM |
206 | 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> |
207 | ||
208 | * ppc.h (PPC_OPCODE_CELL): Define. | |
209 | ||
7918206c MM |
210 | 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
211 | ||
212 | * i386.h : Modify opcode to support for the change in POPCNT opcode | |
213 | in amdfam10 architecture. | |
214 | ||
ef05d495 L |
215 | 2006-09-28 H.J. Lu <hongjiu.lu@intel.com> |
216 | ||
217 | * i386.h: Replace CpuMNI with CpuSSSE3. | |
218 | ||
2d447fca JM |
219 | 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> |
220 | Joseph Myers <joseph@codesourcery.com> | |
221 | Ian Lance Taylor <ian@wasabisystems.com> | |
222 | Ben Elliston <bje@wasabisystems.com> | |
223 | ||
224 | * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. | |
225 | ||
1c0d3aa6 NC |
226 | 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> |
227 | ||
228 | * score-datadep.h: New file. | |
229 | * score-inst.h: New file. | |
230 | ||
c2f0420e L |
231 | 2006-07-14 H.J. Lu <hongjiu.lu@intel.com> |
232 | ||
233 | * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, | |
234 | movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, | |
235 | movdq2q and movq2dq. | |
236 | ||
050dfa73 MM |
237 | 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
238 | Michael Meissner <michael.meissner@amd.com> | |
239 | ||
240 | * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). | |
241 | ||
15965411 L |
242 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
243 | ||
244 | * i386.h (i386_optab): Add "nop" with memory reference. | |
245 | ||
46e883c5 L |
246 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
247 | ||
248 | * i386.h (i386_optab): Update comment for 64bit NOP. | |
249 | ||
9622b051 AM |
250 | 2006-06-06 Ben Elliston <bje@au.ibm.com> |
251 | Anton Blanchard <anton@samba.org> | |
252 | ||
253 | * ppc.h (PPC_OPCODE_POWER6): Define. | |
254 | Adjust whitespace. | |
255 | ||
a9e24354 TS |
256 | 2006-06-05 Thiemo Seufer <ths@mips.com> |
257 | ||
258 | * mips.h: Improve description of MT flags. | |
259 | ||
a596001e RS |
260 | 2006-05-25 Richard Sandiford <richard@codesourcery.com> |
261 | ||
262 | * m68k.h (mcf_mask): Define. | |
263 | ||
d43b4baf TS |
264 | 2006-05-05 Thiemo Seufer <ths@mips.com> |
265 | David Ung <davidu@mips.com> | |
266 | ||
267 | * mips.h (enum): Add macro M_CACHE_AB. | |
268 | ||
39a7806d TS |
269 | 2006-05-04 Thiemo Seufer <ths@mips.com> |
270 | Nigel Stephens <nigel@mips.com> | |
271 | David Ung <davidu@mips.com> | |
272 | ||
273 | * mips.h: Add INSN_SMARTMIPS define. | |
274 | ||
9bcd4f99 TS |
275 | 2006-04-30 Thiemo Seufer <ths@mips.com> |
276 | David Ung <davidu@mips.com> | |
277 | ||
278 | * mips.h: Defines udi bits and masks. Add description of | |
279 | characters which may appear in the args field of udi | |
280 | instructions. | |
281 | ||
ef0ee844 TS |
282 | 2006-04-26 Thiemo Seufer <ths@networkno.de> |
283 | ||
284 | * mips.h: Improve comments describing the bitfield instruction | |
285 | fields. | |
286 | ||
f7675147 L |
287 | 2006-04-26 Julian Brown <julian@codesourcery.com> |
288 | ||
289 | * arm.h (FPU_VFP_EXT_V3): Define constant. | |
290 | (FPU_NEON_EXT_V1): Likewise. | |
291 | (FPU_VFP_HARD): Update. | |
292 | (FPU_VFP_V3): Define macro. | |
293 | (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. | |
294 | ||
ef0ee844 | 295 | 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> |
d727e8c2 NC |
296 | |
297 | * avr.h (AVR_ISA_PWMx): New. | |
298 | ||
2da12c60 NS |
299 | 2006-03-28 Nathan Sidwell <nathan@codesourcery.com> |
300 | ||
301 | * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, | |
302 | cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, | |
303 | cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, | |
304 | cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, | |
305 | cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. | |
306 | ||
0715c387 PB |
307 | 2006-03-10 Paul Brook <paul@codesourcery.com> |
308 | ||
309 | * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. | |
310 | ||
34bdd094 DA |
311 | 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
312 | ||
313 | * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come | |
314 | first. Correct mask of bb "B" opcode. | |
315 | ||
331d2d0d L |
316 | 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> |
317 | ||
318 | * i386.h (i386_optab): Support Intel Merom New Instructions. | |
319 | ||
62b3e311 PB |
320 | 2006-02-24 Paul Brook <paul@codesourcery.com> |
321 | ||
322 | * arm.h: Add V7 feature bits. | |
323 | ||
59cf82fe L |
324 | 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> |
325 | ||
326 | * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. | |
327 | ||
e74cfd16 PB |
328 | 2006-01-31 Paul Brook <paul@codesourcery.com> |
329 | Richard Earnshaw <rearnsha@arm.com> | |
330 | ||
331 | * arm.h: Use ARM_CPU_FEATURE. | |
332 | (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. | |
333 | (arm_feature_set): Change to a structure. | |
334 | (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, | |
335 | ARM_FEATURE): New macros. | |
336 | ||
5b3f8a92 HPN |
337 | 2005-12-07 Hans-Peter Nilsson <hp@axis.com> |
338 | ||
339 | * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) | |
340 | (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. | |
341 | (ADD_PC_INCR_OPCODE): Don't define. | |
342 | ||
cb712a9e L |
343 | 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> |
344 | ||
345 | PR gas/1874 | |
346 | * i386.h (i386_optab): Add 64bit support for monitor and mwait. | |
347 | ||
0499d65b TS |
348 | 2005-11-14 David Ung <davidu@mips.com> |
349 | ||
350 | * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore | |
351 | instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for | |
352 | save/restore encoding of the args field. | |
353 | ||
ea5ca089 DB |
354 | 2005-10-28 Dave Brolley <brolley@redhat.com> |
355 | ||
356 | Contribute the following changes: | |
357 | 2005-02-16 Dave Brolley <brolley@redhat.com> | |
358 | ||
359 | * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename | |
360 | cgen_isa_mask_* to cgen_bitset_*. | |
361 | * cgen.h: Likewise. | |
362 | ||
16175d96 DB |
363 | 2003-10-21 Richard Sandiford <rsandifo@redhat.com> |
364 | ||
365 | * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. | |
366 | (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". | |
367 | (CGEN_CPU_TABLE): Make isas a ponter. | |
368 | ||
369 | 2003-09-29 Dave Brolley <brolley@redhat.com> | |
370 | ||
371 | * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. | |
372 | (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. | |
373 | (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. | |
374 | ||
375 | 2002-12-13 Dave Brolley <brolley@redhat.com> | |
376 | ||
377 | * cgen.h (symcat.h): #include it. | |
378 | (cgen-bitset.h): #include it. | |
379 | (CGEN_ATTR_VALUE_TYPE): Now a union. | |
380 | (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. | |
381 | (CGEN_ATTR_ENTRY): 'value' now unsigned. | |
382 | (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). | |
383 | * cgen-bitset.h: New file. | |
384 | ||
3c9b82ba NC |
385 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
386 | ||
387 | * bfin.h: New file. | |
388 | ||
6a2375c6 JB |
389 | 2005-10-24 Jan Beulich <jbeulich@novell.com> |
390 | ||
391 | * ia64.h (enum ia64_opnd): Move memory operand out of set of | |
392 | indirect operands. | |
393 | ||
c06a12f8 DA |
394 | 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
395 | ||
396 | * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. | |
397 | Add FLAG_STRICT to pa10 ftest opcode. | |
398 | ||
4d443107 DA |
399 | 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
400 | ||
401 | * hppa.h (pa_opcodes): Remove lha entries. | |
402 | ||
f0a3b40f DA |
403 | 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
404 | ||
405 | * hppa.h (FLAG_STRICT): Revise comment. | |
406 | (pa_opcode): Revise ordering rules. Add/move strict pa10 variants | |
407 | before corresponding pa11 opcodes. Add strict pa10 register-immediate | |
408 | entries for "fdc". | |
409 | ||
e210c36b NC |
410 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
411 | ||
412 | * bfin.h: New file. | |
413 | ||
1b7e1362 DA |
414 | 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
415 | ||
416 | * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. | |
417 | ||
089b39de CF |
418 | 2005-09-06 Chao-ying Fu <fu@mips.com> |
419 | ||
420 | * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, | |
421 | OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New | |
422 | define. | |
423 | Document !, $, *, &, g, +t, +T operand formats for MT instructions. | |
424 | (INSN_ASE_MASK): Update to include INSN_MT. | |
425 | (INSN_MT): New define for MT ASE. | |
426 | ||
93c34b9b CF |
427 | 2005-08-25 Chao-ying Fu <fu@mips.com> |
428 | ||
429 | * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, | |
430 | OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, | |
431 | OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, | |
432 | OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, | |
433 | OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. | |
434 | Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP | |
435 | instructions. | |
436 | (INSN_DSP): New define for DSP ASE. | |
437 | ||
848cf006 AM |
438 | 2005-08-18 Alan Modra <amodra@bigpond.net.au> |
439 | ||
440 | * a29k.h: Delete. | |
441 | ||
36ae0db3 DJ |
442 | 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> |
443 | ||
444 | * ppc.h (PPC_OPCODE_E300): Define. | |
445 | ||
8c929562 MS |
446 | 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> |
447 | ||
448 | * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. | |
449 | ||
f7b8cccc DA |
450 | 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
451 | ||
452 | PR gas/336 | |
453 | * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb | |
454 | and pitlb. | |
455 | ||
8b5328ac JB |
456 | 2005-07-27 Jan Beulich <jbeulich@novell.com> |
457 | ||
458 | * i386.h (i386_optab): Add comment to movd. Use LongMem for all | |
459 | movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. | |
460 | Add movq-s as 64-bit variants of movd-s. | |
461 | ||
f417d200 DA |
462 | 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
463 | ||
18b3bdfc DA |
464 | * hppa.h: Fix punctuation in comment. |
465 | ||
f417d200 DA |
466 | * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for |
467 | implicit space-register addressing. Set space-register bits on opcodes | |
468 | using implicit space-register addressing. Add various missing pa20 | |
469 | long-immediate opcodes. Remove various opcodes using implicit 3-bit | |
470 | space-register addressing. Use "fE" instead of "fe" in various | |
471 | fstw opcodes. | |
472 | ||
9a145ce6 JB |
473 | 2005-07-18 Jan Beulich <jbeulich@novell.com> |
474 | ||
475 | * i386.h (i386_optab): Operands of aam and aad are unsigned. | |
476 | ||
90700ea2 L |
477 | 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> |
478 | ||
479 | * i386.h (i386_optab): Support Intel VMX Instructions. | |
480 | ||
48f130a8 DA |
481 | 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
482 | ||
483 | * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. | |
484 | ||
30123838 JB |
485 | 2005-07-05 Jan Beulich <jbeulich@novell.com> |
486 | ||
487 | * i386.h (i386_optab): Add new insns. | |
488 | ||
47b0e7ad NC |
489 | 2005-07-01 Nick Clifton <nickc@redhat.com> |
490 | ||
491 | * sparc.h: Add typedefs to structure declarations. | |
492 | ||
b300c311 L |
493 | 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> |
494 | ||
495 | PR 1013 | |
496 | * i386.h (i386_optab): Update comments for 64bit addressing on | |
497 | mov. Allow 64bit addressing for mov and movq. | |
498 | ||
2db495be DA |
499 | 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
500 | ||
501 | * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, | |
502 | respectively, in various floating-point load and store patterns. | |
503 | ||
caa05036 DA |
504 | 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
505 | ||
506 | * hppa.h (FLAG_STRICT): Correct comment. | |
507 | (pa_opcodes): Update load and store entries to allow both PA 1.X and | |
508 | PA 2.0 mneumonics when equivalent. Entries with cache control | |
509 | completers now require PA 1.1. Adjust whitespace. | |
510 | ||
f4411256 AM |
511 | 2005-05-19 Anton Blanchard <anton@samba.org> |
512 | ||
513 | * ppc.h (PPC_OPCODE_POWER5): Define. | |
514 | ||
e172dbf8 NC |
515 | 2005-05-10 Nick Clifton <nickc@redhat.com> |
516 | ||
517 | * Update the address and phone number of the FSF organization in | |
518 | the GPL notices in the following files: | |
519 | a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, | |
520 | crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, | |
521 | i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, | |
522 | mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, | |
523 | pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, | |
524 | tic54x.h, tic80.h, v850.h, vax.h | |
525 | ||
e44823cf JB |
526 | 2005-05-09 Jan Beulich <jbeulich@novell.com> |
527 | ||
528 | * i386.h (i386_optab): Add ht and hnt. | |
529 | ||
791fe849 MK |
530 | 2005-04-18 Mark Kettenis <kettenis@gnu.org> |
531 | ||
532 | * i386.h: Insert hyphens into selected VIA PadLock extensions. | |
533 | Add xcrypt-ctr. Provide aliases without hyphens. | |
534 | ||
faa7ef87 L |
535 | 2005-04-13 H.J. Lu <hongjiu.lu@intel.com> |
536 | ||
a63027e5 L |
537 | Moved from ../ChangeLog |
538 | ||
faa7ef87 L |
539 | 2005-04-12 Paul Brook <paul@codesourcery.com> |
540 | * m88k.h: Rename psr macros to avoid conflicts. | |
541 | ||
542 | 2005-03-12 Zack Weinberg <zack@codesourcery.com> | |
543 | * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. | |
544 | Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, | |
545 | and ARM_ARCH_V6ZKT2. | |
546 | ||
547 | 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> | |
548 | * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. | |
549 | Remove redundant instruction types. | |
550 | (struct argument): X_op - new field. | |
551 | (struct cst4_entry): Remove. | |
552 | (no_op_insn): Declare. | |
553 | ||
554 | 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> | |
555 | * crx.h (enum argtype): Rename types, remove unused types. | |
556 | ||
557 | 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> | |
558 | * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. | |
559 | (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. | |
560 | (enum operand_type): Rearrange operands, edit comments. | |
561 | replace us<N> with ui<N> for unsigned immediate. | |
562 | replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped | |
563 | displacements (respectively). | |
564 | replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. | |
565 | (instruction type): Add NO_TYPE_INS. | |
566 | (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. | |
567 | (operand_entry): New field - 'flags'. | |
568 | (operand flags): New. | |
569 | ||
570 | 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> | |
571 | * crx.h (operand_type): Remove redundant types i3, i4, | |
572 | i5, i8, i12. | |
573 | Add new unsigned immediate types us3, us4, us5, us16. | |
574 | ||
bc4bd9ab MK |
575 | 2005-04-12 Mark Kettenis <kettenis@gnu.org> |
576 | ||
577 | * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and | |
578 | adjust them accordingly. | |
579 | ||
373ff435 JB |
580 | 2005-04-01 Jan Beulich <jbeulich@novell.com> |
581 | ||
582 | * i386.h (i386_optab): Add rdtscp. | |
583 | ||
4cc91dba L |
584 | 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> |
585 | ||
586 | * i386.h (i386_optab): Don't allow the `l' suffix for moving | |
418a8fca AS |
587 | between memory and segment register. Allow movq for moving between |
588 | general-purpose register and segment register. | |
4cc91dba | 589 | |
9ae09ff9 JB |
590 | 2005-02-09 Jan Beulich <jbeulich@novell.com> |
591 | ||
592 | PR gas/707 | |
593 | * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and | |
594 | FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and | |
595 | fnstsw. | |
596 | ||
638e7a64 NS |
597 | 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> |
598 | ||
599 | * m68k.h (m68008, m68ec030, m68882): Remove. | |
600 | (m68k_mask): New. | |
601 | (cpu_m68k, cpu_cf): New. | |
602 | (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, | |
603 | mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. | |
604 | ||
90219bd0 AO |
605 | 2005-01-25 Alexandre Oliva <aoliva@redhat.com> |
606 | ||
607 | 2004-11-10 Alexandre Oliva <aoliva@redhat.com> | |
608 | * cgen.h (enum cgen_parse_operand_type): Add | |
609 | CGEN_PARSE_OPERAND_SYMBOLIC. | |
610 | ||
239cb185 FF |
611 | 2005-01-21 Fred Fish <fnf@specifixinc.com> |
612 | ||
613 | * mips.h: Change INSN_ALIAS to INSN2_ALIAS. | |
614 | Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. | |
615 | Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. | |
616 | ||
dc9a9f39 FF |
617 | 2005-01-19 Fred Fish <fnf@specifixinc.com> |
618 | ||
619 | * mips.h (struct mips_opcode): Add new pinfo2 member. | |
620 | (INSN_ALIAS): New define for opcode table entries that are | |
621 | specific instances of another entry, such as 'move' for an 'or' | |
622 | with a zero operand. | |
623 | (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. | |
624 | (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. | |
625 | ||
98e7aba8 ILT |
626 | 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> |
627 | ||
628 | * mips.h (CPU_RM9000): Define. | |
629 | (OPCODE_IS_MEMBER): Handle CPU_RM9000. | |
630 | ||
37edbb65 JB |
631 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
632 | ||
633 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves | |
634 | to/from test registers are illegal in 64-bit mode. Add missing | |
635 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix | |
636 | (previously one had to explicitly encode a rex64 prefix). Re-enable | |
637 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings | |
638 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. | |
639 | ||
640 | 2004-11-23 Jan Beulich <jbeulich@novell.com> | |
5c6af06e JB |
641 | |
642 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are | |
643 | available only with SSE2. Change the MMX additions introduced by SSE | |
644 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A | |
645 | instructions by their now designated identifier (since combining i686 | |
646 | and 3DNow! does not really imply 3DNow!A). | |
647 | ||
f5c7edf4 AM |
648 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
649 | ||
650 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, | |
651 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. | |
652 | ||
7499d566 NC |
653 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
654 | Vineet Sharma <vineets@noida.hcltech.com> | |
655 | ||
656 | * maxq.h: New file: Disassembly information for the maxq port. | |
657 | ||
bcb9eebe L |
658 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
659 | ||
660 | * i386.h (i386_optab): Put back "movzb". | |
661 | ||
94bb3d38 HPN |
662 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
663 | ||
664 | * cris.h (enum cris_insn_version_usage): Tweak formatting and | |
665 | comments. Remove member cris_ver_sim. Add members | |
666 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, | |
667 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. | |
668 | (struct cris_support_reg, struct cris_cond15): New types. | |
669 | (cris_conds15): Declare. | |
670 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) | |
671 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) | |
672 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. | |
673 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. | |
674 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and | |
675 | SIZE_FIELD_UNSIGNED. | |
676 | ||
37edbb65 | 677 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
9306ca4a JB |
678 | |
679 | * i386.h (sldx_Suf): Remove. | |
680 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. | |
681 | (q_FP): Define, implying no REX64. | |
682 | (x_FP, sl_FP): Imply FloatMF. | |
683 | (i386_optab): Split reg and mem forms of moving from segment registers | |
684 | so that the memory forms can ignore the 16-/32-bit operand size | |
685 | distinction. Adjust a few others for Intel mode. Remove *FP uses from | |
686 | all non-floating-point instructions. Unite 32- and 64-bit forms of | |
687 | movsx, movzx, and movd. Adjust floating point operations for the above | |
688 | changes to the *FP macros. Add DefaultSize to floating point control | |
689 | insns operating on larger memory ranges. Remove left over comments | |
690 | hinting at certain insns being Intel-syntax ones where the ones | |
691 | actually meant are already gone. | |
692 | ||
48c9f030 NC |
693 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
694 | ||
695 | * crx.h: Add COPS_REG_INS - Coprocessor Special register | |
696 | instruction type. | |
697 | ||
0dd132b6 NC |
698 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
699 | ||
700 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. | |
701 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. | |
702 | ||
23794b24 MM |
703 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
704 | ||
705 | * avr.h: Add support for | |
706 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. | |
707 | ||
2a309db0 AM |
708 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
709 | ||
710 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. | |
711 | ||
b18c562e NC |
712 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
713 | ||
714 | * msp430.h (msp430_opc): Add new instructions. | |
715 | (msp430_rcodes): Declare new instructions. | |
716 | (msp430_hcodes): Likewise.. | |
717 | ||
45d313cd NC |
718 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
719 | ||
720 | PR/301 | |
721 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX | |
722 | processors. | |
723 | ||
30d1c836 ML |
724 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
725 | ||
726 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. | |
727 | ||
9a45f1c2 L |
728 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
729 | ||
730 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. | |
731 | ||
543613e9 NC |
732 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
733 | ||
734 | * i386.h: Adjust instruction descriptions to better match the | |
735 | specification. | |
736 | ||
b781e558 RE |
737 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
738 | ||
739 | * arm.h: Remove all old content. Replace with architecture defines | |
740 | from gas/config/tc-arm.c. | |
741 | ||
8577e690 AS |
742 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
743 | ||
744 | * m68k.h: Fix comment. | |
745 | ||
1fe1f39c NC |
746 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
747 | ||
748 | * crx.h: New file. | |
749 | ||
1d9f512f AM |
750 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
751 | ||
752 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. | |
753 | ||
be8c092b NC |
754 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
755 | ||
756 | * m68k.h: Add 'size' to m68k_opcode. | |
757 | ||
6b6e92f4 NC |
758 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
759 | ||
760 | * m68k.h: Switch from ColdFire chip name to core variant. | |
761 | ||
762 | 2004-04-22 Peter Barada <peter@the-baradas.com> | |
fd99574b NC |
763 | |
764 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand | |
765 | descriptions for new EMAC cases. | |
766 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly | |
767 | handle Motorola MAC syntax. | |
768 | Allow disassembly of ColdFire V4e object files. | |
769 | ||
fdd12ef3 AM |
770 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
771 | ||
772 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. | |
773 | ||
3922a64c L |
774 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
775 | ||
776 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. | |
777 | ||
1f45d988 ML |
778 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
779 | ||
780 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. | |
781 | ||
0f10071e ML |
782 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
783 | ||
784 | * i386.h (i386_optab): Added xstore/xcrypt insns. | |
785 | ||
3255318a NC |
786 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
787 | ||
788 | * h8300.h (32bit ldc/stc): Add relaxing support. | |
789 | ||
ca9a79a1 | 790 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
fdd12ef3 | 791 | |
ca9a79a1 NC |
792 | * h8300.h (BITOP): Pass MEMRELAX flag. |
793 | ||
875a0b14 NC |
794 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
795 | ||
796 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 | |
797 | except for the H8S. | |
252b5132 | 798 | |
c9e214e5 | 799 | For older changes see ChangeLog-9103 |
252b5132 RH |
800 | \f |
801 | Local Variables: | |
c9e214e5 AM |
802 | mode: change-log |
803 | left-margin: 8 | |
804 | fill-column: 74 | |
252b5132 RH |
805 | version-control: never |
806 | End: |