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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
0f35dbc4
RS		 12013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
4 (mips_optional_operand_p): New function.
5
14daeee3
RS		 62013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
7 Richard Sandiford <rdsandiford@googlemail.com>
8
9 * mips.h: Document new VU0 operand characters.
10 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
11 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
12 (OP_REG_R5900_ACC): New mips_reg_operand_types.
13 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
14 (mips_vu0_channel_mask): Declare.
15
3ccad066
RS		 162013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
17
18 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
19 (mips_int_operand_min, mips_int_operand_max): New functions.
20 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
21
fc76e730
RS		 222013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
23
24 * mips.h (mips_decode_reg_operand): New function.
25 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
26 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
27 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
28 New macros.
29 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
30 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
31 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
32 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
33 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
34 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
35 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
36 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
37 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
38 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
39 macros to cover the gaps.
40 (INSN2_MOD_SP): Replace with...
41 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
42 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
43 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
44 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
45 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
46 Delete.
47
26545944
RS		 482013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
49
50 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
51 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
52 (MIPS16_INSN_COND_BRANCH): Delete.
53
7e8b059b
L		 542013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
55 Kirill Yukhin <kirill.yukhin@intel.com>
56 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
57
58 * i386.h (BND_PREFIX_OPCODE): New.
59
c3c07478
RS		 602013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
61
62 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
63 OP_SAVE_RESTORE_LIST.
64 (decode_mips16_operand): Declare.
65
ab902481
RS		 662013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
67
68 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
69 (mips_operand, mips_int_operand, mips_mapped_int_operand)
70 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
71 (mips_pcrel_operand): New structures.
72 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
73 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
74 (decode_mips_operand, decode_micromips_operand): Declare.
75
cc537e56
RS		 762013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
77
78 * mips.h: Document MIPS16 "I" opcode.
79
f2ae14a1
RS		 802013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
81
82 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
83 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
84 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
85 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
86 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
87 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
88 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
89 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
90 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
91 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
92 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
93 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
94 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
95 Rename to...
96 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
97 (M_USD_AB): ...these.
98
5c324c16
RS		 992013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
100
101 * mips.h: Remove documentation of "[" and "]". Update documentation
102 of "k" and the MDMX formats.
103
23e69e47
RS		 1042013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
105
106 * mips.h: Update documentation of "+s" and "+S".
107
27c5c572
RS		 1082013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
109
110 * mips.h: Document "+i".
111
e76ff5ab
RS		 1122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
113
114 * mips.h: Remove "mi" documentation. Update "mh" documentation.
115 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
116 Delete.
117 (INSN2_WRITE_GPR_MHI): Rename to...
118 (INSN2_WRITE_GPR_MH): ...this.
119
fa7616a4
RS		 1202013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
121
122 * mips.h: Remove documentation of "+D" and "+T".
123
18870af7
RS		 1242013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
125
126 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
127 Use "source" rather than "destination" for microMIPS "G".
128
833794fc
MR		 1292013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
130
131 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
132 values.
133
c3678916
RS		 1342013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
135
136 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
137
7f3c4072
CM		 1382013-06-17 Catherine Moore <clm@codesourcery.com>
139 Maciej W. Rozycki <macro@codesourcery.com>
140 Chao-Ying Fu <fu@mips.com>
141
142 * mips.h (OP_SH_EVAOFFSET): Define.
143 (OP_MASK_EVAOFFSET): Define.
144 (INSN_ASE_MASK): Delete.
145 (ASE_EVA): Define.
146 (M_CACHEE_AB, M_CACHEE_OB): New.
147 (M_LBE_OB, M_LBE_AB): New.
148 (M_LBUE_OB, M_LBUE_AB): New.
149 (M_LHE_OB, M_LHE_AB): New.
150 (M_LHUE_OB, M_LHUE_AB): New.
151 (M_LLE_AB, M_LLE_OB): New.
152 (M_LWE_OB, M_LWE_AB): New.
153 (M_LWLE_AB, M_LWLE_OB): New.
154 (M_LWRE_AB, M_LWRE_OB): New.
155 (M_PREFE_AB, M_PREFE_OB): New.
156 (M_SCE_AB, M_SCE_OB): New.
157 (M_SBE_OB, M_SBE_AB): New.
158 (M_SHE_OB, M_SHE_AB): New.
159 (M_SWE_OB, M_SWE_AB): New.
160 (M_SWLE_AB, M_SWLE_OB): New.
161 (M_SWRE_AB, M_SWRE_OB): New.
162 (MICROMIPSOP_SH_EVAOFFSET): Define.
163 (MICROMIPSOP_MASK_EVAOFFSET): Define.
164
0c8fe7cf
SL		 1652013-06-12 Sandra Loosemore <sandra@codesourcery.com>
166
167 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
168
c77c0862
RS		 1692013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
170
171 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
172
b015e599
AP		 1732013-05-09 Andrew Pinski <apinski@cavium.com>
174
175 * mips.h (OP_MASK_CODE10): Correct definition.
176 (OP_SH_CODE10): Likewise.
177 Add a comment that "+J" is used now for OP_*CODE10.
178 (INSN_ASE_MASK): Update.
179 (INSN_VIRT): New macro.
180 (INSN_VIRT64): New macro
181
13761a11
NC		 1822013-05-02 Nick Clifton <nickc@redhat.com>
183
184 * msp430.h: Add patterns for MSP430X instructions.
185
0afd1215
DM		 1862013-04-06 David S. Miller <davem@davemloft.net>
187
188 * sparc.h (F_PREFERRED): Define.
189 (F_PREF_ALIAS): Define.
190
41702d50
NC		 1912013-04-03 Nick Clifton <nickc@redhat.com>
192
193 * v850.h (V850_INVERSE_PCREL): Define.
194
e21e1a51
NC		 1952013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
196
197 PR binutils/15068
198 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
199
51dcdd4d
NC		 2002013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
201
202 PR binutils/15068
203 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
204 Add 16-bit opcodes.
205 * tic6xc-opcode-table.h: Add 16-bit insns.
206 * tic6x.h: Add support for 16-bit insns.
207
81f5558e
NC		 2082013-03-21 Michael Schewe <michael.schewe@gmx.net>
209
210 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
211 and mov.b/w/l Rs,@(d:32,ERd).
212
165546ad
NC		 2132013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
214
215 PR gas/15082
216 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
217 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
218 tic6x_operand_xregpair operand coding type.
219 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
220 opcode field, usu ORXREGD1324 for the src2 operand and remove the
221 TIC6X_FLAG_NO_CROSS.
222
795b8e6b
NC		 2232013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
224
225 PR gas/15095
226 * tic6x.h (enum tic6x_coding_method): Add
227 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
228 separately the msb and lsb of a register pair. This is needed to
229 encode the opcodes in the same way as TI assembler does.
230 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
231 and rsqrdp opcodes to use the new field coding types.
232
dd5181d5
KT		 2332013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
234
235 * arm.h (CRC_EXT_ARMV8): New constant.
236 (ARCH_CRC_ARMV8): New macro.
237
e60bb1dd
YZ		 2382013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
239
240 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
241
36591ba1
SL		 2422013-02-06 Sandra Loosemore <sandra@codesourcery.com>
243 Andrew Jenner <andrew@codesourcery.com>
244
245 Based on patches from Altera Corporation.
246
247 * nios2.h: New file.
248
e30181a5
YZ		 2492013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
250
251 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
252
0c9573f4
NC		 2532013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
254
255 PR gas/15069
256 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
257
981dc7f1
NC		 2582013-01-24 Nick Clifton <nickc@redhat.com>
259
260 * v850.h: Add e3v5 support.
261
f5555712
YZ		 2622013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
263
264 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
265
5817ffd1
PB		 2662013-01-10 Peter Bergner <bergner@vnet.ibm.com>
267
268 * ppc.h (PPC_OPCODE_POWER8): New define.
269 (PPC_OPCODE_HTM): Likewise.
270
a3c62988
NC		 2712013-01-10 Will Newton <will.newton@imgtec.com>
272
273 * metag.h: New file.
274
73335eae
NC		 2752013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
276
277 * cr16.h (make_instruction): Rename to cr16_make_instruction.
278 (match_opcode): Rename to cr16_match_opcode.
279
e407c74b
NC		 2802013-01-04 Juergen Urban <JuergenUrban@gmx.de>
281
282 * mips.h: Add support for r5900 instructions including lq and sq.
283
bab4becb
NC		 2842013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
285
286 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
287 (make_instruction,match_opcode): Added function prototypes.
288 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
289
776fc418
AM		 2902012-11-23 Alan Modra <amodra@gmail.com>
291
292 * ppc.h (ppc_parse_cpu): Update prototype.
293
f05682d4
DA		 2942012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
295
296 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
297 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
298
cfc72779
AK		 2992012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
300
301 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
302
b3e14eda
L		 3032012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
304
305 * ia64.h (ia64_opnd): Add new operand types.
306
2c63854f
DM		 3072012-08-21 David S. Miller <davem@davemloft.net>
308
309 * sparc.h (F3F4): New macro.
310
a06ea964 3112012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 312 Laurent Desnogues <laurent.desnogues@arm.com>
313 Jim MacArthur <jim.macarthur@arm.com>
314 Marcus Shawcroft <marcus.shawcroft@arm.com>
315 Nigel Stephens <nigel.stephens@arm.com>
316 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
317 Richard Earnshaw <rearnsha@arm.com>
318 Sofiane Naci <sofiane.naci@arm.com>
319 Tejas Belagod <tejas.belagod@arm.com>
320 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 321
322 * aarch64.h: New file.
323
35d0a169 3242012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 325 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 326
327 * mips.h (mips_opcode): Add the exclusions field.
328 (OPCODE_IS_MEMBER): Remove macro.
329 (cpu_is_member): New inline function.
330 (opcode_is_member): Likewise.
331
03f66e8a 3322012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 333 Catherine Moore <clm@codesourcery.com>
334 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 335
336 * mips.h: Document microMIPS DSP ASE usage.
337 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
338 microMIPS DSP ASE support.
339 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
340 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
341 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
342 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
343 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
344 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
345 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
346
9d7b4c23
MR		 3472012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
348
349 * mips.h: Fix a typo in description.
350
76e879f8
NC		 3512012-06-07 Georg-Johann Lay <avr@gjlay.de>
352
353 * avr.h: (AVR_ISA_XCH): New define.
354 (AVR_ISA_XMEGA): Use it.
355 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
356
6927f982
NC		 3572012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
358
359 * m68hc11.h: Add XGate definitions.
360 (struct m68hc11_opcode): Add xg_mask field.
361
b9c361e0
JL		 3622012-05-14 Catherine Moore <clm@codesourcery.com>
363 Maciej W. Rozycki <macro@codesourcery.com>
364 Rhonda Wittels <rhonda@codesourcery.com>
365
6927f982 366 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 367 (PPC_OP_SA): New macro.
368 (PPC_OP_SE_VLE): New macro.
369 (PPC_OP): Use a variable shift amount.
370 (powerpc_operand): Update comments.
371 (PPC_OPSHIFT_INV): New macro.
372 (PPC_OPERAND_CR): Replace with...
373 (PPC_OPERAND_CR_BIT): ...this and
374 (PPC_OPERAND_CR_REG): ...this.
375
376
f6c1a2d5
NC		 3772012-05-03 Sean Keys <skeys@ipdatasys.com>
378
379 * xgate.h: Header file for XGATE assembler.
380
ec668d69
DM		 3812012-04-27 David S. Miller <davem@davemloft.net>
382
6cda1326
DM		 383 * sparc.h: Document new arg code' )' for crypto RS3
384 immediates.
385
ec668d69
DM		 386 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
387 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
388 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
389 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
390 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
391 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
392 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
393 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
394 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
395 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
396 HWCAP_CBCOND, HWCAP_CRC32): New defines.
397
aea77599
AM		 3982012-03-10 Edmar Wienskoski <edmar@freescale.com>
399
400 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
401
1f42f8b3
AM		 4022012-02-27 Alan Modra <amodra@gmail.com>
403
404 * crx.h (cst4_map): Update declaration.
405
6f7be959
WL		 4062012-02-25 Walter Lee <walt@tilera.com>
407
408 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
409 TILEGX_OPC_LD_TLS.
410 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
411 TILEPRO_OPC_LW_TLS_SN.
412
42164a71
L		 4132012-02-08 H.J. Lu <hongjiu.lu@intel.com>
414
415 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
416 (XRELEASE_PREFIX_OPCODE): Likewise.
417
432233b3 4182011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 419 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 420
421 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
422 (INSN_OCTEON2): New macro.
423 (CPU_OCTEON2): New macro.
424 (OPCODE_IS_MEMBER): Add Octeon2.
425
dd6a37e7
AP		 4262011-11-29 Andrew Pinski <apinski@cavium.com>
427
428 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
429 (INSN_OCTEONP): New macro.
430 (CPU_OCTEONP): New macro.
431 (OPCODE_IS_MEMBER): Add Octeon+.
432 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
433
99c513f6
DD		 4342011-11-01 DJ Delorie <dj@redhat.com>
435
436 * rl78.h: New file.
437
26f85d7a
MR		 4382011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
439
440 * mips.h: Fix a typo in description.
441
9e8c70f9
DM		 4422011-09-21 David S. Miller <davem@davemloft.net>
443
444 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
445 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
446 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
447 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
448
dec0624d 4492011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 450 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 451
452 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
453 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
454 (INSN_ASE_MASK): Add the MCU bit.
455 (INSN_MCU): New macro.
456 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
457 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
458
2b0c8b40
MR		 4592011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
460
461 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
462 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
463 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
464 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
465 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
466 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
467 (INSN2_READ_GPR_MMN): Likewise.
468 (INSN2_READ_FPR_D): Change the bit used.
469 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
470 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
471 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
472 (INSN2_COND_BRANCH): Likewise.
473 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
474 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
475 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
476 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
477 (INSN2_MOD_GPR_MN): Likewise.
478
ea783ef3
DM		 4792011-08-05 David S. Miller <davem@davemloft.net>
480
481 * sparc.h: Document new format codes '4', '5', and '('.
482 (OPF_LOW4, RS3): New macros.
483
7c176fa8
MR		 4842011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
485
486 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
487 order of flags documented.
488
2309ddf2
MR		 4892011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
490
491 * mips.h: Clarify the description of microMIPS instruction
492 manipulation macros.
493 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
494
df58fc94 4952011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 496 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 497
498 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
499 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
500 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
501 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
502 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
503 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
504 (OP_MASK_RS3, OP_SH_RS3): Likewise.
505 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
506 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
507 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
508 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
509 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
510 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
511 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
512 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
513 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
514 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
515 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
516 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
517 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
518 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
519 (INSN_WRITE_GPR_S): New macro.
520 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
521 (INSN2_READ_FPR_D): Likewise.
522 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
523 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
524 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
525 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
526 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
527 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
528 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
529 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
530 (CPU_MICROMIPS): New macro.
531 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
532 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
533 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
534 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
535 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
536 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
537 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
538 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
539 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
540 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
541 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
542 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
543 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
544 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
545 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
546 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
547 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
548 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
549 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
550 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
551 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
552 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
553 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
554 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
555 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
556 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
557 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
558 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
559 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
560 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
561 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
562 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
563 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
564 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
565 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
566 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
567 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
568 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
569 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
570 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
571 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
572 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
573 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
574 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
575 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
576 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
577 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
578 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
579 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
580 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
581 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
582 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
583 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
584 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
585 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
586 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
587 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
588 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
589 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
590 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
591 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
592 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
593 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
594 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
595 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
596 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
597 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
598 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
599 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
600 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
601 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
602 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
603 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
604 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
605 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
606 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
607 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
608 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
609 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
610 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
611 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
612 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
613 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
614 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
615 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
616 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
617 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
618 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
619 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
620 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
621 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
622 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
623 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
624 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
625 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
626 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
627 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
628 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
629 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
630 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
631 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
632 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
633 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
634 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
635 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
636 (micromips_opcodes): New declaration.
637 (bfd_micromips_num_opcodes): Likewise.
638
bcd530a7
RS		 6392011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
640
641 * mips.h (INSN_TRAP): Rename to...
642 (INSN_NO_DELAY_SLOT): ... this.
643 (INSN_SYNC): Remove macro.
644
2dad5a91
EW		 6452011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
646
647 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
648 a duplicate of AVR_ISA_SPM.
649
5d73b1f1
NC		 6502011-07-01 Nick Clifton <nickc@redhat.com>
651
652 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
653
ef26d60e
MF		 6542011-06-18 Robin Getz <robin.getz@analog.com>
655
656 * bfin.h (is_macmod_signed): New func
657
8fb8dca7
MF		 6582011-06-18 Mike Frysinger <vapier@gentoo.org>
659
660 * bfin.h (is_macmod_pmove): Add missing space before func args.
661 (is_macmod_hmove): Likewise.
662
aa137e4d
NC		 6632011-06-13 Walter Lee <walt@tilera.com>
664
665 * tilegx.h: New file.
666 * tilepro.h: New file.
667
3b2f0793
PB		 6682011-05-31 Paul Brook <paul@codesourcery.com>
669
aa137e4d
NC		 670 * arm.h (ARM_ARCH_V7R_IDIV): Define.
671
6722011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
673
674 * s390.h: Replace S390_OPERAND_REG_EVEN with
675 S390_OPERAND_REG_PAIR.
676
6772011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
678
679 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 680
ac7f631b
NC		 6812011-04-18 Julian Brown <julian@codesourcery.com>
682
683 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
684
84701018
NC		 6852011-04-11 Dan McDonald <dan@wellkeeper.com>
686
687 PR gas/12296
688 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
689
8cc66334
EW		 6902011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
691
692 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
693 New instruction set flags.
694 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
695
3eebd5eb
MR		 6962011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
697
698 * mips.h (M_PREF_AB): New enum value.
699
26bb3ddd
MF		 7002011-02-12 Mike Frysinger <vapier@gentoo.org>
701
89c0d58c
MR		 702 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
703 M_IU): Define.
704 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 705
dd76fcb8
MF		 7062011-02-11 Mike Frysinger <vapier@gentoo.org>
707
708 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
709
98d23bef
BS		 7102011-02-04 Bernd Schmidt <bernds@codesourcery.com>
711
712 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
713 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
714
3c853d93
DA		 7152010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
716
717 PR gas/11395
718 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
719 "bb" entries.
720
79676006
DA		 7212010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
722
723 PR gas/11395
724 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
725
1bec78e9
RS		 7262010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
727
728 * mips.h: Update commentary after last commit.
729
98675402
RS		 7302010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
731
732 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
733 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
734 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
735
aa137e4d
NC		 7362010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
737
738 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
739
435b94a4
RS		 7402010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
741
742 * mips.h: Fix previous commit.
743
d051516a
NC		 7442010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
745
746 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
747 (INSN_LOONGSON_3A): Clear bit 31.
748
251665fc
MGD		 7492010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
750
751 PR gas/12198
752 * arm.h (ARM_AEXT_V6M_ONLY): New define.
753 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
754 (ARM_ARCH_V6M_ONLY): New define.
755
fd503541
NC		 7562010-11-11 Mingming Sun <mingm.sun@gmail.com>
757
758 * mips.h (INSN_LOONGSON_3A): Defined.
759 (CPU_LOONGSON_3A): Defined.
760 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
761
4469d2be
AM		 7622010-10-09 Matt Rice <ratmice@gmail.com>
763
764 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
765 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
766
90ec0d68
MGD		 7672010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
768
769 * arm.h (ARM_EXT_VIRT): New define.
770 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
771 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
772 Extensions.
773
eea54501 7742010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 775
eea54501
MGD		 776 * arm.h (ARM_AEXT_ADIV): New define.
777 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
778
b2a5fbdc
MGD		 7792010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
780
781 * arm.h (ARM_EXT_OS): New define.
782 (ARM_AEXT_V6SM): Likewise.
783 (ARM_ARCH_V6SM): Likewise.
784
60e5ef9f
MGD		 7852010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
786
787 * arm.h (ARM_EXT_MP): Add.
788 (ARM_ARCH_V7A_MP): Likewise.
789
73a63ccf
MF		 7902010-09-22 Mike Frysinger <vapier@gentoo.org>
791
792 * bfin.h: Declare pseudoChr structs/defines.
793
ee99860a
MF		 7942010-09-21 Mike Frysinger <vapier@gentoo.org>
795
796 * bfin.h: Strip trailing whitespace.
797
f9c7014e
DD		 7982010-07-29 DJ Delorie <dj@redhat.com>
799
800 * rx.h (RX_Operand_Type): Add TwoReg.
801 (RX_Opcode_ID): Remove ediv and ediv2.
802
93378652
DD		 8032010-07-27 DJ Delorie <dj@redhat.com>
804
805 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
806
1cd986c5
NC		 8072010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
808 Ina Pandit <ina.pandit@kpitcummins.com>
809
810 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
811 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
812 PROCESSOR_V850E2_ALL.
813 Remove PROCESSOR_V850EA support.
814 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
815 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
816 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
817 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
818 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
819 V850_OPERAND_PERCENT.
820 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
821 V850_NOT_R0.
822 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
823 and V850E_PUSH_POP
824
9a2c7088
MR		 8252010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
826
827 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
828 (MIPS16_INSN_BRANCH): Rename to...
829 (MIPS16_INSN_COND_BRANCH): ... this.
830
bdc70b4a
AM		 8312010-07-03 Alan Modra <amodra@gmail.com>
832
833 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
834 Renumber other PPC_OPCODE defines.
835
f2bae120
AM		 8362010-07-03 Alan Modra <amodra@gmail.com>
837
838 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
839
360cfc9c
AM		 8402010-06-29 Alan Modra <amodra@gmail.com>
841
842 * maxq.h: Delete file.
843
e01d869a
AM		 8442010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
845
846 * ppc.h (PPC_OPCODE_E500): Define.
847
f79e2745
CM		 8482010-05-26 Catherine Moore <clm@codesourcery.com>
849
850 * opcode/mips.h (INSN_MIPS16): Remove.
851
2462afa1
JM		 8522010-04-21 Joseph Myers <joseph@codesourcery.com>
853
854 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
855
e4e42b45
NC		 8562010-04-15 Nick Clifton <nickc@redhat.com>
857
858 * alpha.h: Update copyright notice to use GPLv3.
859 * arc.h: Likewise.
860 * arm.h: Likewise.
861 * avr.h: Likewise.
862 * bfin.h: Likewise.
863 * cgen.h: Likewise.
864 * convex.h: Likewise.
865 * cr16.h: Likewise.
866 * cris.h: Likewise.
867 * crx.h: Likewise.
868 * d10v.h: Likewise.
869 * d30v.h: Likewise.
870 * dlx.h: Likewise.
871 * h8300.h: Likewise.
872 * hppa.h: Likewise.
873 * i370.h: Likewise.
874 * i386.h: Likewise.
875 * i860.h: Likewise.
876 * i960.h: Likewise.
877 * ia64.h: Likewise.
878 * m68hc11.h: Likewise.
879 * m68k.h: Likewise.
880 * m88k.h: Likewise.
881 * maxq.h: Likewise.
882 * mips.h: Likewise.
883 * mmix.h: Likewise.
884 * mn10200.h: Likewise.
885 * mn10300.h: Likewise.
886 * msp430.h: Likewise.
887 * np1.h: Likewise.
888 * ns32k.h: Likewise.
889 * or32.h: Likewise.
890 * pdp11.h: Likewise.
891 * pj.h: Likewise.
892 * pn.h: Likewise.
893 * ppc.h: Likewise.
894 * pyr.h: Likewise.
895 * rx.h: Likewise.
896 * s390.h: Likewise.
897 * score-datadep.h: Likewise.
898 * score-inst.h: Likewise.
899 * sparc.h: Likewise.
900 * spu-insns.h: Likewise.
901 * spu.h: Likewise.
902 * tic30.h: Likewise.
903 * tic4x.h: Likewise.
904 * tic54x.h: Likewise.
905 * tic80.h: Likewise.
906 * v850.h: Likewise.
907 * vax.h: Likewise.
908
40b36596
JM		 9092010-03-25 Joseph Myers <joseph@codesourcery.com>
910
911 * tic6x-control-registers.h, tic6x-insn-formats.h,
912 tic6x-opcode-table.h, tic6x.h: New.
913
c67a084a
NC		 9142010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
915
916 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
917
466ef64f
AM		 9182010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
919
920 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
921
1319d143
L		 9222010-01-14 H.J. Lu <hongjiu.lu@intel.com>
923
924 * ia64.h (ia64_find_opcode): Remove argument name.
925 (ia64_find_next_opcode): Likewise.
926 (ia64_dis_opcode): Likewise.
927 (ia64_free_opcode): Likewise.
928 (ia64_find_dependency): Likewise.
929
1fbb9298
DE		 9302009-11-22 Doug Evans <dje@sebabeach.org>
931
932 * cgen.h: Include bfd_stdint.h.
933 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
934
ada65aa3
PB		 9352009-11-18 Paul Brook <paul@codesourcery.com>
936
937 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
938
9e3c6df6
PB		 9392009-11-17 Paul Brook <paul@codesourcery.com>
940 Daniel Jacobowitz <dan@codesourcery.com>
941
942 * arm.h (ARM_EXT_V6_DSP): Define.
943 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
944 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
945
0d734b5d
DD		 9462009-11-04 DJ Delorie <dj@redhat.com>
947
948 * rx.h (rx_decode_opcode) (mvtipl): Add.
949 (mvtcp, mvfcp, opecp): Remove.
950
62f3b8c8
PB		 9512009-11-02 Paul Brook <paul@codesourcery.com>
952
953 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
954 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
955 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
956 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
957 FPU_ARCH_NEON_VFP_V4): Define.
958
ac1e9eca
DE		 9592009-10-23 Doug Evans <dje@sebabeach.org>
960
961 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
962 * cgen.h: Update. Improve multi-inclusion macro name.
963
9fe54b1c
PB		 9642009-10-02 Peter Bergner <bergner@vnet.ibm.com>
965
966 * ppc.h (PPC_OPCODE_476): Define.
967
634b50f2
PB		 9682009-10-01 Peter Bergner <bergner@vnet.ibm.com>
969
970 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
971
c7927a3c
NC		 9722009-09-29 DJ Delorie <dj@redhat.com>
973
974 * rx.h: New file.
975
b961e85b
AM		 9762009-09-22 Peter Bergner <bergner@vnet.ibm.com>
977
978 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
979
e0d602ec
BE		 9802009-09-21 Ben Elliston <bje@au.ibm.com>
981
982 * ppc.h (PPC_OPCODE_PPCA2): New.
983
96d56e9f
NC		 9842009-09-05 Martin Thuresson <martin@mtme.org>
985
986 * ia64.h (struct ia64_operand): Renamed member class to op_class.
987
d3ce72d0
NC		 9882009-08-29 Martin Thuresson <martin@mtme.org>
989
990 * tic30.h (template): Rename type template to
991 insn_template. Updated code to use new name.
992 * tic54x.h (template): Rename type template to
993 insn_template.
994
824b28db
NH		 9952009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
996
997 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
998
f865a31d
AG		 9992009-06-11 Anthony Green <green@moxielogic.com>
1000
1001 * moxie.h (MOXIE_F3_PCREL): Define.
1002 (moxie_form3_opc_info): Grow.
1003
0e7c7f11
AG		 10042009-06-06 Anthony Green <green@moxielogic.com>
1005
1006 * moxie.h (MOXIE_F1_M): Define.
1007
20135e4c
NC		 10082009-04-15 Anthony Green <green@moxielogic.com>
1009
1010 * moxie.h: Created.
1011
bcb012d3
DD		 10122009-04-06 DJ Delorie <dj@redhat.com>
1013
1014 * h8300.h: Add relaxation attributes to MOVA opcodes.
1015
69fe9ce5
AM		 10162009-03-10 Alan Modra <amodra@bigpond.net.au>
1017
1018 * ppc.h (ppc_parse_cpu): Declare.
1019
c3b7224a
NC		 10202009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1021
1022 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1023 and _IMM11 for mbitclr and mbitset.
1024 * score-datadep.h: Update dependency information.
1025
066be9f7
PB		 10262009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1027
1028 * ppc.h (PPC_OPCODE_POWER7): New.
1029
fedc618e
DE		 10302009-02-06 Doug Evans <dje@google.com>
1031
1032 * i386.h: Add comment regarding sse* insns and prefixes.
1033
52b6b6b9
JM		 10342009-02-03 Sandip Matte <sandip@rmicorp.com>
1035
1036 * mips.h (INSN_XLR): Define.
1037 (INSN_CHIP_MASK): Update.
1038 (CPU_XLR): Define.
1039 (OPCODE_IS_MEMBER): Update.
1040 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1041
35669430
DE		 10422009-01-28 Doug Evans <dje@google.com>
1043
1044 * opcode/i386.h: Add multiple inclusion protection.
1045 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1046 (EDI_REG_NUM): New macros.
1047 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1048 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1049 (REX_PREFIX_P): New macro.
35669430 1050
1cb0a767
PB		 10512009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1052
1053 * ppc.h (struct powerpc_opcode): New field "deprecated".
1054 (PPC_OPCODE_NOPOWER4): Delete.
1055
3aa3176b
TS		 10562008-11-28 Joshua Kinard <kumba@gentoo.org>
1057
1058 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1059 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1060
8e79c3df
CM		 10612008-11-18 Catherine Moore <clm@codesourcery.com>
1062
1063 * arm.h (FPU_NEON_FP16): New.
1064 (FPU_ARCH_NEON_FP16): New.
1065
de9a3e51
CF		 10662008-11-06 Chao-ying Fu <fu@mips.com>
1067
1068 * mips.h: Doucument '1' for 5-bit sync type.
1069
1ca35711
L		 10702008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1071
1072 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1073 IA64_RS_CR.
1074
9b4e5766
PB		 10752008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1076
1077 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1078
081ba1b3
AM		 10792008-07-30 Michael J. Eager <eager@eagercon.com>
1080
1081 * ppc.h (PPC_OPCODE_405): Define.
1082 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1083
fa452fa6
PB		 10842008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1085
1086 * ppc.h (ppc_cpu_t): New typedef.
1087 (struct powerpc_opcode <flags>): Use it.
1088 (struct powerpc_operand <insert, extract>): Likewise.
1089 (struct powerpc_macro <flags>): Likewise.
1090
bb35fb24
NC		 10912008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1092
1093 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1094 Update comment before MIPS16 field descriptors to mention MIPS16.
1095 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1096 BBIT.
1097 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1098 New bit masks and shift counts for cins and exts.
1099
dd3cbb7e
NC		 1100 * mips.h: Document new field descriptors +Q.
1101 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1102
d0799671
AN		 11032008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1104
1105 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1106 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1107
19a6653c
AM		 11082008-04-14 Edmar Wienskoski <edmar@freescale.com>
1109
1110 * ppc.h: (PPC_OPCODE_E500MC): New.
1111
c0f3af97
L		 11122008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1113
1114 * i386.h (MAX_OPERANDS): Set to 5.
1115 (MAX_MNEM_SIZE): Changed to 20.
1116
e210c36b
NC		 11172008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1118
1119 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1120
b1cc4aeb
PB		 11212008-03-09 Paul Brook <paul@codesourcery.com>
1122
1123 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1124
7e806470
PB		 11252008-03-04 Paul Brook <paul@codesourcery.com>
1126
1127 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1128 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1129 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1130
7b2185f9 11312008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1132 Nick Clifton <nickc@redhat.com>
1133
1134 PR 3134
1135 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1136 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1137 set.
af7329f0 1138
796d5313
NC		 11392008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1140
1141 * cr16.h (cr16_num_optab): Declared.
1142
d669d37f
NC		 11432008-02-14 Hakan Ardo <hakan@debian.org>
1144
1145 PR gas/2626
1146 * avr.h (AVR_ISA_2xxe): Define.
1147
e6429699
AN		 11482008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1149
1150 * mips.h: Update copyright.
1151 (INSN_CHIP_MASK): New macro.
1152 (INSN_OCTEON): New macro.
1153 (CPU_OCTEON): New macro.
1154 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1155
e210c36b
NC		 11562008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1157
1158 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1159
11602008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1161
1162 * avr.h (AVR_ISA_USB162): Add new opcode set.
1163 (AVR_ISA_AVR3): Likewise.
1164
350cc38d
MS		 11652007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1166
1167 * mips.h (INSN_LOONGSON_2E): New.
1168 (INSN_LOONGSON_2F): New.
1169 (CPU_LOONGSON_2E): New.
1170 (CPU_LOONGSON_2F): New.
1171 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1172
56950294
MS		 11732007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1174
1175 * mips.h (INSN_ISA*): Redefine certain values as an
1176 enumeration. Update comments.
1177 (mips_isa_table): New.
1178 (ISA_MIPS*): Redefine to match enumeration.
1179 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1180 values.
1181
c3d65c1c
BE		 11822007-08-08 Ben Elliston <bje@au.ibm.com>
1183
1184 * ppc.h (PPC_OPCODE_PPCPS): New.
1185
0fdaa005
L		 11862007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1187
1188 * m68k.h: Document j K & E.
1189
11902007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1191
1192 * cr16.h: New file for CR16 target.
1193
3896c469
AM		 11942007-05-02 Alan Modra <amodra@bigpond.net.au>
1195
1196 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1197
9a2e615a
NS		 11982007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1199
1200 * m68k.h (mcfisa_c): New.
1201 (mcfusp, mcf_mask): Adjust.
1202
b84bf58a
AM		 12032007-04-20 Alan Modra <amodra@bigpond.net.au>
1204
1205 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1206 (num_powerpc_operands): Declare.
1207 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1208 (PPC_OPERAND_PLUS1): Define.
1209
831480e9 12102007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1211
1212 * i386.h (REX_MODE64): Renamed to ...
1213 (REX_W): This.
1214 (REX_EXTX): Renamed to ...
1215 (REX_R): This.
1216 (REX_EXTY): Renamed to ...
1217 (REX_X): This.
1218 (REX_EXTZ): Renamed to ...
1219 (REX_B): This.
1220
0b1cf022
L		 12212007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1222
1223 * i386.h: Add entries from config/tc-i386.h and move tables
1224 to opcodes/i386-opc.h.
1225
d796c0ad
L		 12262007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1227
1228 * i386.h (FloatDR): Removed.
1229 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1230
30ac7323
AM		 12312007-03-01 Alan Modra <amodra@bigpond.net.au>
1232
1233 * spu-insns.h: Add soma double-float insns.
1234
8b082fb1 12352007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1236 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1237
1238 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1239 (INSN_DSPR2): Add flag for DSP R2 instructions.
1240 (M_BALIGN): New macro.
1241
4eed87de
AM		 12422007-02-14 Alan Modra <amodra@bigpond.net.au>
1243
1244 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1245 and Seg3ShortFrom with Shortform.
1246
fda592e8
L		 12472007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1248
1249 PR gas/4027
1250 * i386.h (i386_optab): Put the real "test" before the pseudo
1251 one.
1252
3bdcfdf4
KH		 12532007-01-08 Kazu Hirata <kazu@codesourcery.com>
1254
1255 * m68k.h (m68010up): OR fido_a.
1256
9840d27e
KH		 12572006-12-25 Kazu Hirata <kazu@codesourcery.com>
1258
1259 * m68k.h (fido_a): New.
1260
c629cdac
KH		 12612006-12-24 Kazu Hirata <kazu@codesourcery.com>
1262
1263 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1264 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1265 values.
1266
b7d9ef37
L		 12672006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1268
1269 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1270
b138abaa
NC		 12712006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1272
1273 * score-inst.h (enum score_insn_type): Add Insn_internal.
1274
e9f53129
AM		 12752006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1276 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1277 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1278 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1279 Alan Modra <amodra@bigpond.net.au>
1280
1281 * spu-insns.h: New file.
1282 * spu.h: New file.
1283
ede602d7
AM		 12842006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1285
1286 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1287
7918206c
MM		 12882006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1289
e4e42b45 1290 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1291 in amdfam10 architecture.
1292
ef05d495
L		 12932006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1294
1295 * i386.h: Replace CpuMNI with CpuSSSE3.
1296
2d447fca 12972006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1298 Joseph Myers <joseph@codesourcery.com>
1299 Ian Lance Taylor <ian@wasabisystems.com>
1300 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1301
1302 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1303
1c0d3aa6
NC		 13042006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1305
1306 * score-datadep.h: New file.
1307 * score-inst.h: New file.
1308
c2f0420e
L		 13092006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1310
1311 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1312 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1313 movdq2q and movq2dq.
1314
050dfa73
MM		 13152006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1316 Michael Meissner <michael.meissner@amd.com>
1317
1318 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1319
15965411
L		 13202006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1321
1322 * i386.h (i386_optab): Add "nop" with memory reference.
1323
46e883c5
L		 13242006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1325
1326 * i386.h (i386_optab): Update comment for 64bit NOP.
1327
9622b051
AM		 13282006-06-06 Ben Elliston <bje@au.ibm.com>
1329 Anton Blanchard <anton@samba.org>
1330
1331 * ppc.h (PPC_OPCODE_POWER6): Define.
1332 Adjust whitespace.
1333
a9e24354
TS		 13342006-06-05 Thiemo Seufer <ths@mips.com>
1335
e4e42b45 1336 * mips.h: Improve description of MT flags.
a9e24354 1337
a596001e
RS		 13382006-05-25 Richard Sandiford <richard@codesourcery.com>
1339
1340 * m68k.h (mcf_mask): Define.
1341
d43b4baf 13422006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1343 David Ung <davidu@mips.com>
d43b4baf
TS		 1344
1345 * mips.h (enum): Add macro M_CACHE_AB.
1346
39a7806d 13472006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1348 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1349 David Ung <davidu@mips.com>
1350
1351 * mips.h: Add INSN_SMARTMIPS define.
1352
9bcd4f99 13532006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1354 David Ung <davidu@mips.com>
9bcd4f99
TS		 1355
1356 * mips.h: Defines udi bits and masks. Add description of
1357 characters which may appear in the args field of udi
1358 instructions.
1359
ef0ee844
TS		 13602006-04-26 Thiemo Seufer <ths@networkno.de>
1361
1362 * mips.h: Improve comments describing the bitfield instruction
1363 fields.
1364
f7675147
L		 13652006-04-26 Julian Brown <julian@codesourcery.com>
1366
1367 * arm.h (FPU_VFP_EXT_V3): Define constant.
1368 (FPU_NEON_EXT_V1): Likewise.
1369 (FPU_VFP_HARD): Update.
1370 (FPU_VFP_V3): Define macro.
1371 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1372
ef0ee844 13732006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1374
1375 * avr.h (AVR_ISA_PWMx): New.
1376
2da12c60
NS		 13772006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1378
1379 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1380 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1381 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1382 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1383 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1384
0715c387
PB		 13852006-03-10 Paul Brook <paul@codesourcery.com>
1386
1387 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1388
34bdd094
DA		 13892006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1390
1391 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1392 first. Correct mask of bb "B" opcode.
1393
331d2d0d
L		 13942006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1395
1396 * i386.h (i386_optab): Support Intel Merom New Instructions.
1397
62b3e311
PB		 13982006-02-24 Paul Brook <paul@codesourcery.com>
1399
1400 * arm.h: Add V7 feature bits.
1401
59cf82fe
L		 14022006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1403
1404 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1405
e74cfd16
PB		 14062006-01-31 Paul Brook <paul@codesourcery.com>
1407 Richard Earnshaw <rearnsha@arm.com>
1408
1409 * arm.h: Use ARM_CPU_FEATURE.
1410 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1411 (arm_feature_set): Change to a structure.
1412 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1413 ARM_FEATURE): New macros.
1414
5b3f8a92
HPN		 14152005-12-07 Hans-Peter Nilsson <hp@axis.com>
1416
1417 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1418 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1419 (ADD_PC_INCR_OPCODE): Don't define.
1420
cb712a9e
L		 14212005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1422
1423 PR gas/1874
1424 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1425
0499d65b
TS		 14262005-11-14 David Ung <davidu@mips.com>
1427
1428 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1429 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1430 save/restore encoding of the args field.
1431
ea5ca089
DB		 14322005-10-28 Dave Brolley <brolley@redhat.com>
1433
1434 Contribute the following changes:
1435 2005-02-16 Dave Brolley <brolley@redhat.com>
1436
1437 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1438 cgen_isa_mask_* to cgen_bitset_*.
1439 * cgen.h: Likewise.
1440
16175d96
DB		 1441 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1442
1443 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1444 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1445 (CGEN_CPU_TABLE): Make isas a ponter.
1446
1447 2003-09-29 Dave Brolley <brolley@redhat.com>
1448
1449 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1450 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1451 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1452
1453 2002-12-13 Dave Brolley <brolley@redhat.com>
1454
1455 * cgen.h (symcat.h): #include it.
1456 (cgen-bitset.h): #include it.
1457 (CGEN_ATTR_VALUE_TYPE): Now a union.
1458 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1459 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1460 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1461 * cgen-bitset.h: New file.
1462
3c9b82ba
NC		 14632005-09-30 Catherine Moore <clm@cm00re.com>
1464
1465 * bfin.h: New file.
1466
6a2375c6
JB		 14672005-10-24 Jan Beulich <jbeulich@novell.com>
1468
1469 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1470 indirect operands.
1471
c06a12f8
DA		 14722005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1473
1474 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1475 Add FLAG_STRICT to pa10 ftest opcode.
1476
4d443107
DA		 14772005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1478
1479 * hppa.h (pa_opcodes): Remove lha entries.
1480
f0a3b40f
DA		 14812005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1482
1483 * hppa.h (FLAG_STRICT): Revise comment.
1484 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1485 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1486 entries for "fdc".
1487
e210c36b
NC		 14882005-09-30 Catherine Moore <clm@cm00re.com>
1489
1490 * bfin.h: New file.
1491
1b7e1362
DA		 14922005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1493
1494 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1495
089b39de
CF		 14962005-09-06 Chao-ying Fu <fu@mips.com>
1497
1498 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1499 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1500 define.
1501 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1502 (INSN_ASE_MASK): Update to include INSN_MT.
1503 (INSN_MT): New define for MT ASE.
1504
93c34b9b
CF		 15052005-08-25 Chao-ying Fu <fu@mips.com>
1506
1507 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1508 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1509 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1510 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1511 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1512 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1513 instructions.
1514 (INSN_DSP): New define for DSP ASE.
1515
848cf006
AM		 15162005-08-18 Alan Modra <amodra@bigpond.net.au>
1517
1518 * a29k.h: Delete.
1519
36ae0db3
DJ		 15202005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1521
1522 * ppc.h (PPC_OPCODE_E300): Define.
1523
8c929562
MS		 15242005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1525
1526 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1527
f7b8cccc
DA		 15282005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1529
1530 PR gas/336
1531 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1532 and pitlb.
1533
8b5328ac
JB		 15342005-07-27 Jan Beulich <jbeulich@novell.com>
1535
1536 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1537 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1538 Add movq-s as 64-bit variants of movd-s.
1539
f417d200
DA		 15402005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1541
18b3bdfc
DA		 1542 * hppa.h: Fix punctuation in comment.
1543
f417d200
DA		 1544 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1545 implicit space-register addressing. Set space-register bits on opcodes
1546 using implicit space-register addressing. Add various missing pa20
1547 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1548 space-register addressing. Use "fE" instead of "fe" in various
1549 fstw opcodes.
1550
9a145ce6
JB		 15512005-07-18 Jan Beulich <jbeulich@novell.com>
1552
1553 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1554
90700ea2
L		 15552007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1556
1557 * i386.h (i386_optab): Support Intel VMX Instructions.
1558
48f130a8
DA		 15592005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1560
1561 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1562
30123838
JB		 15632005-07-05 Jan Beulich <jbeulich@novell.com>
1564
1565 * i386.h (i386_optab): Add new insns.
1566
47b0e7ad
NC		 15672005-07-01 Nick Clifton <nickc@redhat.com>
1568
1569 * sparc.h: Add typedefs to structure declarations.
1570
b300c311
L		 15712005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1572
1573 PR 1013
1574 * i386.h (i386_optab): Update comments for 64bit addressing on
1575 mov. Allow 64bit addressing for mov and movq.
1576
2db495be
DA		 15772005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1578
1579 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1580 respectively, in various floating-point load and store patterns.
1581
caa05036
DA		 15822005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1583
1584 * hppa.h (FLAG_STRICT): Correct comment.
1585 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1586 PA 2.0 mneumonics when equivalent. Entries with cache control
1587 completers now require PA 1.1. Adjust whitespace.
1588
f4411256
AM		 15892005-05-19 Anton Blanchard <anton@samba.org>
1590
1591 * ppc.h (PPC_OPCODE_POWER5): Define.
1592
e172dbf8
NC		 15932005-05-10 Nick Clifton <nickc@redhat.com>
1594
1595 * Update the address and phone number of the FSF organization in
1596 the GPL notices in the following files:
1597 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1598 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1599 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1600 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1601 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1602 tic54x.h, tic80.h, v850.h, vax.h
1603
e44823cf
JB		 16042005-05-09 Jan Beulich <jbeulich@novell.com>
1605
1606 * i386.h (i386_optab): Add ht and hnt.
1607
791fe849
MK		 16082005-04-18 Mark Kettenis <kettenis@gnu.org>
1609
1610 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1611 Add xcrypt-ctr. Provide aliases without hyphens.
1612
faa7ef87
L		 16132005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1614
a63027e5
L		 1615 Moved from ../ChangeLog
1616
faa7ef87
L		 1617 2005-04-12 Paul Brook <paul@codesourcery.com>
1618 * m88k.h: Rename psr macros to avoid conflicts.
1619
1620 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1621 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1622 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1623 and ARM_ARCH_V6ZKT2.
1624
1625 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1626 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1627 Remove redundant instruction types.
1628 (struct argument): X_op - new field.
1629 (struct cst4_entry): Remove.
1630 (no_op_insn): Declare.
1631
1632 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1633 * crx.h (enum argtype): Rename types, remove unused types.
1634
1635 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1636 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1637 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1638 (enum operand_type): Rearrange operands, edit comments.
1639 replace us<N> with ui<N> for unsigned immediate.
1640 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1641 displacements (respectively).
1642 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1643 (instruction type): Add NO_TYPE_INS.
1644 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1645 (operand_entry): New field - 'flags'.
1646 (operand flags): New.
1647
1648 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1649 * crx.h (operand_type): Remove redundant types i3, i4,
1650 i5, i8, i12.
1651 Add new unsigned immediate types us3, us4, us5, us16.
1652
bc4bd9ab
MK		 16532005-04-12 Mark Kettenis <kettenis@gnu.org>
1654
1655 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1656 adjust them accordingly.
1657
373ff435
JB		 16582005-04-01 Jan Beulich <jbeulich@novell.com>
1659
1660 * i386.h (i386_optab): Add rdtscp.
1661
4cc91dba
L		 16622005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1663
1664 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1665 between memory and segment register. Allow movq for moving between
1666 general-purpose register and segment register.
4cc91dba 1667
9ae09ff9
JB		 16682005-02-09 Jan Beulich <jbeulich@novell.com>
1669
1670 PR gas/707
1671 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1672 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1673 fnstsw.
1674
638e7a64
NS		 16752006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1676
1677 * m68k.h (m68008, m68ec030, m68882): Remove.
1678 (m68k_mask): New.
1679 (cpu_m68k, cpu_cf): New.
1680 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1681 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1682
90219bd0
AO		 16832005-01-25 Alexandre Oliva <aoliva@redhat.com>
1684
1685 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1686 * cgen.h (enum cgen_parse_operand_type): Add
1687 CGEN_PARSE_OPERAND_SYMBOLIC.
1688
239cb185
FF		 16892005-01-21 Fred Fish <fnf@specifixinc.com>
1690
1691 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1692 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1693 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1694
dc9a9f39
FF		 16952005-01-19 Fred Fish <fnf@specifixinc.com>
1696
1697 * mips.h (struct mips_opcode): Add new pinfo2 member.
1698 (INSN_ALIAS): New define for opcode table entries that are
1699 specific instances of another entry, such as 'move' for an 'or'
1700 with a zero operand.
1701 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1702 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1703
98e7aba8
ILT		 17042004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1705
1706 * mips.h (CPU_RM9000): Define.
1707 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1708
37edbb65
JB		 17092004-11-25 Jan Beulich <jbeulich@novell.com>
1710
1711 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1712 to/from test registers are illegal in 64-bit mode. Add missing
1713 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1714 (previously one had to explicitly encode a rex64 prefix). Re-enable
1715 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1716 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1717
17182004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1719
1720 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1721 available only with SSE2. Change the MMX additions introduced by SSE
1722 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1723 instructions by their now designated identifier (since combining i686
1724 and 3DNow! does not really imply 3DNow!A).
1725
f5c7edf4
AM		 17262004-11-19 Alan Modra <amodra@bigpond.net.au>
1727
1728 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1729 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1730
7499d566
NC		 17312004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1732 Vineet Sharma <vineets@noida.hcltech.com>
1733
1734 * maxq.h: New file: Disassembly information for the maxq port.
1735
bcb9eebe
L		 17362004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1737
1738 * i386.h (i386_optab): Put back "movzb".
1739
94bb3d38
HPN		 17402004-11-04 Hans-Peter Nilsson <hp@axis.com>
1741
1742 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1743 comments. Remove member cris_ver_sim. Add members
1744 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1745 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1746 (struct cris_support_reg, struct cris_cond15): New types.
1747 (cris_conds15): Declare.
1748 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1749 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1750 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1751 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1752 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1753 SIZE_FIELD_UNSIGNED.
1754
37edbb65 17552004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1756
1757 * i386.h (sldx_Suf): Remove.
1758 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1759 (q_FP): Define, implying no REX64.
1760 (x_FP, sl_FP): Imply FloatMF.
1761 (i386_optab): Split reg and mem forms of moving from segment registers
1762 so that the memory forms can ignore the 16-/32-bit operand size
1763 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1764 all non-floating-point instructions. Unite 32- and 64-bit forms of
1765 movsx, movzx, and movd. Adjust floating point operations for the above
1766 changes to the *FP macros. Add DefaultSize to floating point control
1767 insns operating on larger memory ranges. Remove left over comments
1768 hinting at certain insns being Intel-syntax ones where the ones
1769 actually meant are already gone.
1770
48c9f030
NC		 17712004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1772
1773 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1774 instruction type.
1775
0dd132b6
NC		 17762004-09-30 Paul Brook <paul@codesourcery.com>
1777
1778 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1779 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1780
23794b24
MM		 17812004-09-11 Theodore A. Roth <troth@openavr.org>
1782
1783 * avr.h: Add support for
1784 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1785
2a309db0
AM		 17862004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1787
1788 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1789
b18c562e
NC		 17902004-08-24 Dmitry Diky <diwil@spec.ru>
1791
1792 * msp430.h (msp430_opc): Add new instructions.
1793 (msp430_rcodes): Declare new instructions.
1794 (msp430_hcodes): Likewise..
1795
45d313cd
NC		 17962004-08-13 Nick Clifton <nickc@redhat.com>
1797
1798 PR/301
1799 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1800 processors.
1801
30d1c836
ML		 18022004-08-30 Michal Ludvig <mludvig@suse.cz>
1803
1804 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1805
9a45f1c2
L		 18062004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1807
1808 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1809
543613e9
NC		 18102004-07-21 Jan Beulich <jbeulich@novell.com>
1811
1812 * i386.h: Adjust instruction descriptions to better match the
1813 specification.
1814
b781e558
RE		 18152004-07-16 Richard Earnshaw <rearnsha@arm.com>
1816
1817 * arm.h: Remove all old content. Replace with architecture defines
1818 from gas/config/tc-arm.c.
1819
8577e690
AS		 18202004-07-09 Andreas Schwab <schwab@suse.de>
1821
1822 * m68k.h: Fix comment.
1823
1fe1f39c
NC		 18242004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1825
1826 * crx.h: New file.
1827
1d9f512f
AM		 18282004-06-24 Alan Modra <amodra@bigpond.net.au>
1829
1830 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1831
be8c092b
NC		 18322004-05-24 Peter Barada <peter@the-baradas.com>
1833
1834 * m68k.h: Add 'size' to m68k_opcode.
1835
6b6e92f4
NC		 18362004-05-05 Peter Barada <peter@the-baradas.com>
1837
1838 * m68k.h: Switch from ColdFire chip name to core variant.
1839
18402004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1841
1842 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1843 descriptions for new EMAC cases.
1844 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1845 handle Motorola MAC syntax.
1846 Allow disassembly of ColdFire V4e object files.
1847
fdd12ef3
AM		 18482004-03-16 Alan Modra <amodra@bigpond.net.au>
1849
1850 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1851
3922a64c
L		 18522004-03-12 Jakub Jelinek <jakub@redhat.com>
1853
1854 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1855
1f45d988
ML		 18562004-03-12 Michal Ludvig <mludvig@suse.cz>
1857
1858 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1859
0f10071e
ML		 18602004-03-12 Michal Ludvig <mludvig@suse.cz>
1861
1862 * i386.h (i386_optab): Added xstore/xcrypt insns.
1863
3255318a
NC		 18642004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1865
1866 * h8300.h (32bit ldc/stc): Add relaxing support.
1867
ca9a79a1 18682004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1869
ca9a79a1
NC		 1870 * h8300.h (BITOP): Pass MEMRELAX flag.
1871
875a0b14
NC		 18722004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1873
1874 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1875 except for the H8S.
252b5132 1876
c9e214e5 1877For older changes see ChangeLog-9103
252b5132 1878\f
752937aa
NC		 1879Copyright (C) 2004-2012 Free Software Foundation, Inc.
1880
1881Copying and distribution of this file, with or without modification,
1882are permitted in any medium without royalty provided the copyright
1883notice and this notice are preserved.
1884
252b5132 1885Local Variables:
c9e214e5
AM		 1886mode: change-log
1887left-margin: 8
1888fill-column: 74
252b5132
RH		 1889version-control: never
1890End:
GDB Binutils - Deliverables
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