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Update comment of linespec_lexer_lex_keyword.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
f63c1776
PA		 12015-02-19 Pedro Alves <palves@redhat.com>
2
3 * cgen.h [__cplusplus]: Wrap in extern "C".
4 * msp430-decode.h [__cplusplus]: Likewise.
5 * nios2.h [__cplusplus]: Likewise.
6 * rl78.h [__cplusplus]: Likewise.
7 * rx.h [__cplusplus]: Likewise.
8 * tilegx.h [__cplusplus]: Likewise.
9
3f8107ab
AM		 102015-01-28 James Bowman <james.bowman@ftdichip.com>
11
12 * ft32.h: New file.
13
1e2e8c52
AK		 142015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
15
16 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
17
b90efa5b
AM		 182015-01-01 Alan Modra <amodra@gmail.com>
19
20 Update year range in copyright notice of all files.
21
bffb6004
AG		 222014-12-27 Anthony Green <green@moxielogic.com>
23
24 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
25 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
26
1945cfa5
EB		 272014-12-06 Eric Botcazou <ebotcazou@adacore.com>
28
29 * visium.h: New file.
30
d306ce58
SL		 312014-11-28 Sandra Loosemore <sandra@codesourcery.com>
32
33 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
34 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
35 (NIOS2_INSN_OPTARG): Renumber.
36
b4714c7c
SL		 372014-11-06 Sandra Loosemore <sandra@codesourcery.com>
38
39 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
40 declaration. Fix obsolete comment.
41
96ba4233
SL		 422014-10-23 Sandra Loosemore <sandra@codesourcery.com>
43
44 * nios2.h (enum iw_format_type): New.
45 (struct nios2_opcode): Update comments. Add size and format fields.
46 (NIOS2_INSN_OPTARG): New.
47 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
48 (struct nios2_reg): Add regtype field.
49 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
50 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
51 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
52 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
53 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
54 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
55 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
56 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
57 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
58 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
59 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
60 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
61 (OP_MASK_OP, OP_SH_OP): Delete.
62 (OP_MASK_IOP, OP_SH_IOP): Delete.
63 (OP_MASK_IRD, OP_SH_IRD): Delete.
64 (OP_MASK_IRT, OP_SH_IRT): Delete.
65 (OP_MASK_IRS, OP_SH_IRS): Delete.
66 (OP_MASK_ROP, OP_SH_ROP): Delete.
67 (OP_MASK_RRD, OP_SH_RRD): Delete.
68 (OP_MASK_RRT, OP_SH_RRT): Delete.
69 (OP_MASK_RRS, OP_SH_RRS): Delete.
70 (OP_MASK_JOP, OP_SH_JOP): Delete.
71 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
72 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
73 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
74 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
75 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
76 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
77 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
78 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
79 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
80 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
81 (OP_MASK_<insn>, OP_MASK): Delete.
82 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
83 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
84 Include nios2r1.h to define new instruction opcode constants
85 and accessors.
86 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
87 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
88 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
89 (NUMOPCODES, NUMREGISTERS): Delete.
90 * nios2r1.h: New file.
91
0b6be415
JM		 922014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
93
94 * sparc.h (HWCAP2_VIS3B): Documentation improved.
95
3d68f91c
JM		 962014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
97
98 * sparc.h (sparc_opcode): new field `hwcaps2'.
99 (HWCAP2_FJATHPLUS): New define.
100 (HWCAP2_VIS3B): Likewise.
101 (HWCAP2_ADP): Likewise.
102 (HWCAP2_SPARC5): Likewise.
103 (HWCAP2_MWAIT): Likewise.
104 (HWCAP2_XMPMUL): Likewise.
105 (HWCAP2_XMONT): Likewise.
106 (HWCAP2_NSEC): Likewise.
107 (HWCAP2_FJATHHPC): Likewise.
108 (HWCAP2_FJDES): Likewise.
109 (HWCAP2_FJAES): Likewise.
110 Document the new operand kind `{', corresponding to the mcdper
111 ancillary state register.
112 Document the new operand kind }, which represents frsd floating
113 point registers (double precision) which must be the same than
114 frs1 in its containing instruction.
115
40c7a7cb
KLC		 1162014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
117
118 * nds32.h: Add new opcode declaration.
119
7361da2c
AB		 1202014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
121 Matthew Fortune <matthew.fortune@imgtec.com>
122
123 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
124 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
125 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
126 +I, +O, +R, +:, +\, +", +;
127 (mips_check_prev_operand): New struct.
128 (INSN2_FORBIDDEN_SLOT): New define.
129 (INSN_ISA32R6): New define.
130 (INSN_ISA64R6): New define.
131 (INSN_UPTO32R6): New define.
132 (INSN_UPTO64R6): New define.
133 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
134 (ISA_MIPS32R6): New define.
135 (ISA_MIPS64R6): New define.
136 (CPU_MIPS32R6): New define.
137 (CPU_MIPS64R6): New define.
138 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
139
ee804238
JW		 1402014-09-03 Jiong Wang <jiong.wang@arm.com>
141
142 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
143 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
144 (aarch64_insn_class): Add lse_atomic.
145 (F_LSE_SZ): New field added.
146 (opcode_has_special_coder): Recognize F_LSE_SZ.
147
5575639b
MR		 1482014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
149
150 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
151 over to `+J'.
152
43885403
MF		 1532014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
154
155 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
156 (INSN_LOAD_COPROC): New define.
157 (INSN_COPROC_MOVE_DELAY): Rename to...
158 (INSN_COPROC_MOVE): New define.
159
f36e8886
BS		 1602014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
161 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
162 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
163 Soundararajan <Sounderarajan.D@atmel.com>
164
165 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
166 (AVR_ISA_2xxxa): Define ISA without LPM.
167 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
168 Add doc for contraint used in 16 bit lds/sts.
169 Adjust ISA group for icall, ijmp, pop and push.
170 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
171
00b32ff2
NC		 1722014-05-19 Nick Clifton <nickc@redhat.com>
173
174 * msp430.h (struct msp430_operand_s): Add vshift field.
175
ae52f483
AB		 1762014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
177
178 * mips.h (INSN_ISA_MASK): Updated.
179 (INSN_ISA32R3): New define.
180 (INSN_ISA32R5): New define.
181 (INSN_ISA64R3): New define.
182 (INSN_ISA64R5): New define.
183 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
184 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
185 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
186 mips64r5.
187 (INSN_UPTO32R3): New define.
188 (INSN_UPTO32R5): New define.
189 (INSN_UPTO64R3): New define.
190 (INSN_UPTO64R5): New define.
191 (ISA_MIPS32R3): New define.
192 (ISA_MIPS32R5): New define.
193 (ISA_MIPS64R3): New define.
194 (ISA_MIPS64R5): New define.
195 (CPU_MIPS32R3): New define.
196 (CPU_MIPS32R5): New define.
197 (CPU_MIPS64R3): New define.
198 (CPU_MIPS64R5): New define.
199
3efe9ec5
RS		 2002014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
201
202 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
203
73589c9d
CS		 2042014-04-22 Christian Svensson <blue@cmd.nu>
205
206 * or32.h: Delete.
207
4b95cf5c
AM		 2082014-03-05 Alan Modra <amodra@gmail.com>
209
210 Update copyright years.
211
e269fea7
AB		 2122013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
213
214 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
215 microMIPS.
216
35c08157
KLC		 2172013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
218 Wei-Cheng Wang <cole945@gmail.com>
219
220 * nds32.h: New file for Andes NDS32.
221
594d8fa8
MF		 2222013-12-07 Mike Frysinger <vapier@gentoo.org>
223
224 * bfin.h: Remove +x file mode.
225
87b8eed7
YZ		 2262013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
227
228 * aarch64.h (aarch64_pstatefields): Change element type to
229 aarch64_sys_reg.
230
c9fb6e58
YZ		 2312013-11-18 Renlin Li <Renlin.Li@arm.com>
232
233 * arm.h (ARM_AEXT_V7VE): New define.
234 (ARM_ARCH_V7VE): New define.
235 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
236
a203d9b7
YZ		 2372013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
238
239 Revert
240
241 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
242
243 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
244 (aarch64_sys_reg_writeonly_p): Ditto.
245
75468c93
YZ		 2462013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
247
248 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
249 (aarch64_sys_reg_writeonly_p): Ditto.
250
49eec193
YZ		 2512013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
252
253 * aarch64.h (aarch64_sys_reg): New typedef.
254 (aarch64_sys_regs): Change to define with the new type.
255 (aarch64_sys_reg_deprecated_p): Declare.
256
68a64283
YZ		 2572013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
258
259 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
260 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
261
387a82f1
CF		 2622013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
263
264 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
265 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
266 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
267 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
268 For MIPS, update extension character sequences after +.
269 (ASE_MSA): New define.
270 (ASE_MSA64): New define.
271 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
272 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
273 For microMIPS, update extension character sequences after +.
274
9aff4b7a
NC		 2752013-08-23 Yuri Chornoivan <yurchor@ukr.net>
276
277 PR binutils/15834
278 * i960.h: Fix typos.
279
e423441d
RS		 2802013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
281
282 * mips.h: Remove references to "+I" and imm2_expr.
283
5e0dc5ba
RS		 2842013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
285
286 * mips.h (M_DEXT, M_DINS): Delete.
287
0f35dbc4
RS		 2882013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
289
290 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
291 (mips_optional_operand_p): New function.
292
14daeee3
RS		 2932013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
294 Richard Sandiford <rdsandiford@googlemail.com>
295
296 * mips.h: Document new VU0 operand characters.
297 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
298 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
299 (OP_REG_R5900_ACC): New mips_reg_operand_types.
300 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
301 (mips_vu0_channel_mask): Declare.
302
3ccad066
RS		 3032013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
304
305 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
306 (mips_int_operand_min, mips_int_operand_max): New functions.
307 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
308
fc76e730
RS		 3092013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
310
311 * mips.h (mips_decode_reg_operand): New function.
312 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
313 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
314 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
315 New macros.
316 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
317 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
318 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
319 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
320 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
321 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
322 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
323 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
324 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
325 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
326 macros to cover the gaps.
327 (INSN2_MOD_SP): Replace with...
328 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
329 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
330 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
331 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
332 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
333 Delete.
334
26545944
RS		 3352013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
336
337 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
338 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
339 (MIPS16_INSN_COND_BRANCH): Delete.
340
7e8b059b
L		 3412013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
342 Kirill Yukhin <kirill.yukhin@intel.com>
343 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
344
345 * i386.h (BND_PREFIX_OPCODE): New.
346
c3c07478
RS		 3472013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
348
349 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
350 OP_SAVE_RESTORE_LIST.
351 (decode_mips16_operand): Declare.
352
ab902481
RS		 3532013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
354
355 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
356 (mips_operand, mips_int_operand, mips_mapped_int_operand)
357 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
358 (mips_pcrel_operand): New structures.
359 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
360 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
361 (decode_mips_operand, decode_micromips_operand): Declare.
362
cc537e56
RS		 3632013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
364
365 * mips.h: Document MIPS16 "I" opcode.
366
f2ae14a1
RS		 3672013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
368
369 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
370 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
371 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
372 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
373 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
374 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
375 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
376 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
377 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
378 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
379 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
380 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
381 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
382 Rename to...
383 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
384 (M_USD_AB): ...these.
385
5c324c16
RS		 3862013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
387
388 * mips.h: Remove documentation of "[" and "]". Update documentation
389 of "k" and the MDMX formats.
390
23e69e47
RS		 3912013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
392
393 * mips.h: Update documentation of "+s" and "+S".
394
27c5c572
RS		 3952013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
396
397 * mips.h: Document "+i".
398
e76ff5ab
RS		 3992013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
400
401 * mips.h: Remove "mi" documentation. Update "mh" documentation.
402 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
403 Delete.
404 (INSN2_WRITE_GPR_MHI): Rename to...
405 (INSN2_WRITE_GPR_MH): ...this.
406
fa7616a4
RS		 4072013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
408
409 * mips.h: Remove documentation of "+D" and "+T".
410
18870af7
RS		 4112013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
412
413 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
414 Use "source" rather than "destination" for microMIPS "G".
415
833794fc
MR		 4162013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
417
418 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
419 values.
420
c3678916
RS		 4212013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
422
423 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
424
7f3c4072
CM		 4252013-06-17 Catherine Moore <clm@codesourcery.com>
426 Maciej W. Rozycki <macro@codesourcery.com>
427 Chao-Ying Fu <fu@mips.com>
428
429 * mips.h (OP_SH_EVAOFFSET): Define.
430 (OP_MASK_EVAOFFSET): Define.
431 (INSN_ASE_MASK): Delete.
432 (ASE_EVA): Define.
433 (M_CACHEE_AB, M_CACHEE_OB): New.
434 (M_LBE_OB, M_LBE_AB): New.
435 (M_LBUE_OB, M_LBUE_AB): New.
436 (M_LHE_OB, M_LHE_AB): New.
437 (M_LHUE_OB, M_LHUE_AB): New.
438 (M_LLE_AB, M_LLE_OB): New.
439 (M_LWE_OB, M_LWE_AB): New.
440 (M_LWLE_AB, M_LWLE_OB): New.
441 (M_LWRE_AB, M_LWRE_OB): New.
442 (M_PREFE_AB, M_PREFE_OB): New.
443 (M_SCE_AB, M_SCE_OB): New.
444 (M_SBE_OB, M_SBE_AB): New.
445 (M_SHE_OB, M_SHE_AB): New.
446 (M_SWE_OB, M_SWE_AB): New.
447 (M_SWLE_AB, M_SWLE_OB): New.
448 (M_SWRE_AB, M_SWRE_OB): New.
449 (MICROMIPSOP_SH_EVAOFFSET): Define.
450 (MICROMIPSOP_MASK_EVAOFFSET): Define.
451
0c8fe7cf
SL		 4522013-06-12 Sandra Loosemore <sandra@codesourcery.com>
453
454 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
455
c77c0862
RS		 4562013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
457
458 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
459
b015e599
AP		 4602013-05-09 Andrew Pinski <apinski@cavium.com>
461
462 * mips.h (OP_MASK_CODE10): Correct definition.
463 (OP_SH_CODE10): Likewise.
464 Add a comment that "+J" is used now for OP_*CODE10.
465 (INSN_ASE_MASK): Update.
466 (INSN_VIRT): New macro.
467 (INSN_VIRT64): New macro
468
13761a11
NC		 4692013-05-02 Nick Clifton <nickc@redhat.com>
470
471 * msp430.h: Add patterns for MSP430X instructions.
472
0afd1215
DM		 4732013-04-06 David S. Miller <davem@davemloft.net>
474
475 * sparc.h (F_PREFERRED): Define.
476 (F_PREF_ALIAS): Define.
477
41702d50
NC		 4782013-04-03 Nick Clifton <nickc@redhat.com>
479
480 * v850.h (V850_INVERSE_PCREL): Define.
481
e21e1a51
NC		 4822013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
483
484 PR binutils/15068
485 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
486
51dcdd4d
NC		 4872013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
488
489 PR binutils/15068
490 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
491 Add 16-bit opcodes.
492 * tic6xc-opcode-table.h: Add 16-bit insns.
493 * tic6x.h: Add support for 16-bit insns.
494
81f5558e
NC		 4952013-03-21 Michael Schewe <michael.schewe@gmx.net>
496
497 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
498 and mov.b/w/l Rs,@(d:32,ERd).
499
165546ad
NC		 5002013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
501
502 PR gas/15082
503 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
504 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
505 tic6x_operand_xregpair operand coding type.
506 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
507 opcode field, usu ORXREGD1324 for the src2 operand and remove the
508 TIC6X_FLAG_NO_CROSS.
509
795b8e6b
NC		 5102013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
511
512 PR gas/15095
513 * tic6x.h (enum tic6x_coding_method): Add
514 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
515 separately the msb and lsb of a register pair. This is needed to
516 encode the opcodes in the same way as TI assembler does.
517 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
518 and rsqrdp opcodes to use the new field coding types.
519
dd5181d5
KT		 5202013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
521
522 * arm.h (CRC_EXT_ARMV8): New constant.
523 (ARCH_CRC_ARMV8): New macro.
524
e60bb1dd
YZ		 5252013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
526
527 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
528
36591ba1
SL		 5292013-02-06 Sandra Loosemore <sandra@codesourcery.com>
530 Andrew Jenner <andrew@codesourcery.com>
531
532 Based on patches from Altera Corporation.
533
534 * nios2.h: New file.
535
e30181a5
YZ		 5362013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
537
538 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
539
0c9573f4
NC		 5402013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
541
542 PR gas/15069
543 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
544
981dc7f1
NC		 5452013-01-24 Nick Clifton <nickc@redhat.com>
546
547 * v850.h: Add e3v5 support.
548
f5555712
YZ		 5492013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
550
551 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
552
5817ffd1
PB		 5532013-01-10 Peter Bergner <bergner@vnet.ibm.com>
554
555 * ppc.h (PPC_OPCODE_POWER8): New define.
556 (PPC_OPCODE_HTM): Likewise.
557
a3c62988
NC		 5582013-01-10 Will Newton <will.newton@imgtec.com>
559
560 * metag.h: New file.
561
73335eae
NC		 5622013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
563
564 * cr16.h (make_instruction): Rename to cr16_make_instruction.
565 (match_opcode): Rename to cr16_match_opcode.
566
e407c74b
NC		 5672013-01-04 Juergen Urban <JuergenUrban@gmx.de>
568
569 * mips.h: Add support for r5900 instructions including lq and sq.
570
bab4becb
NC		 5712013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
572
573 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
574 (make_instruction,match_opcode): Added function prototypes.
575 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
576
776fc418
AM		 5772012-11-23 Alan Modra <amodra@gmail.com>
578
579 * ppc.h (ppc_parse_cpu): Update prototype.
580
f05682d4
DA		 5812012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
582
583 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
584 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
585
cfc72779
AK		 5862012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
587
588 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
589
b3e14eda
L		 5902012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
591
592 * ia64.h (ia64_opnd): Add new operand types.
593
2c63854f
DM		 5942012-08-21 David S. Miller <davem@davemloft.net>
595
596 * sparc.h (F3F4): New macro.
597
a06ea964 5982012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 599 Laurent Desnogues <laurent.desnogues@arm.com>
600 Jim MacArthur <jim.macarthur@arm.com>
601 Marcus Shawcroft <marcus.shawcroft@arm.com>
602 Nigel Stephens <nigel.stephens@arm.com>
603 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
604 Richard Earnshaw <rearnsha@arm.com>
605 Sofiane Naci <sofiane.naci@arm.com>
606 Tejas Belagod <tejas.belagod@arm.com>
607 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 608
609 * aarch64.h: New file.
610
35d0a169 6112012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 612 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 613
614 * mips.h (mips_opcode): Add the exclusions field.
615 (OPCODE_IS_MEMBER): Remove macro.
616 (cpu_is_member): New inline function.
617 (opcode_is_member): Likewise.
618
03f66e8a 6192012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 620 Catherine Moore <clm@codesourcery.com>
621 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 622
623 * mips.h: Document microMIPS DSP ASE usage.
624 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
625 microMIPS DSP ASE support.
626 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
627 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
628 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
629 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
630 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
631 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
632 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
633
9d7b4c23
MR		 6342012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
635
636 * mips.h: Fix a typo in description.
637
76e879f8
NC		 6382012-06-07 Georg-Johann Lay <avr@gjlay.de>
639
640 * avr.h: (AVR_ISA_XCH): New define.
641 (AVR_ISA_XMEGA): Use it.
642 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
643
6927f982
NC		 6442012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
645
646 * m68hc11.h: Add XGate definitions.
647 (struct m68hc11_opcode): Add xg_mask field.
648
b9c361e0
JL		 6492012-05-14 Catherine Moore <clm@codesourcery.com>
650 Maciej W. Rozycki <macro@codesourcery.com>
651 Rhonda Wittels <rhonda@codesourcery.com>
652
6927f982 653 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 654 (PPC_OP_SA): New macro.
655 (PPC_OP_SE_VLE): New macro.
656 (PPC_OP): Use a variable shift amount.
657 (powerpc_operand): Update comments.
658 (PPC_OPSHIFT_INV): New macro.
659 (PPC_OPERAND_CR): Replace with...
660 (PPC_OPERAND_CR_BIT): ...this and
661 (PPC_OPERAND_CR_REG): ...this.
662
663
f6c1a2d5
NC		 6642012-05-03 Sean Keys <skeys@ipdatasys.com>
665
666 * xgate.h: Header file for XGATE assembler.
667
ec668d69
DM		 6682012-04-27 David S. Miller <davem@davemloft.net>
669
6cda1326
DM		 670 * sparc.h: Document new arg code' )' for crypto RS3
671 immediates.
672
ec668d69
DM		 673 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
674 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
675 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
676 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
677 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
678 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
679 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
680 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
681 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
682 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
683 HWCAP_CBCOND, HWCAP_CRC32): New defines.
684
aea77599
AM		 6852012-03-10 Edmar Wienskoski <edmar@freescale.com>
686
687 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
688
1f42f8b3
AM		 6892012-02-27 Alan Modra <amodra@gmail.com>
690
691 * crx.h (cst4_map): Update declaration.
692
6f7be959
WL		 6932012-02-25 Walter Lee <walt@tilera.com>
694
695 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
696 TILEGX_OPC_LD_TLS.
697 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
698 TILEPRO_OPC_LW_TLS_SN.
699
42164a71
L		 7002012-02-08 H.J. Lu <hongjiu.lu@intel.com>
701
702 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
703 (XRELEASE_PREFIX_OPCODE): Likewise.
704
432233b3 7052011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 706 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 707
708 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
709 (INSN_OCTEON2): New macro.
710 (CPU_OCTEON2): New macro.
711 (OPCODE_IS_MEMBER): Add Octeon2.
712
dd6a37e7
AP		 7132011-11-29 Andrew Pinski <apinski@cavium.com>
714
715 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
716 (INSN_OCTEONP): New macro.
717 (CPU_OCTEONP): New macro.
718 (OPCODE_IS_MEMBER): Add Octeon+.
719 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
720
99c513f6
DD		 7212011-11-01 DJ Delorie <dj@redhat.com>
722
723 * rl78.h: New file.
724
26f85d7a
MR		 7252011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
726
727 * mips.h: Fix a typo in description.
728
9e8c70f9
DM		 7292011-09-21 David S. Miller <davem@davemloft.net>
730
731 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
732 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
733 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
734 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
735
dec0624d 7362011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 737 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 738
739 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
740 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
741 (INSN_ASE_MASK): Add the MCU bit.
742 (INSN_MCU): New macro.
743 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
744 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
745
2b0c8b40
MR		 7462011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
747
748 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
749 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
750 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
751 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
752 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
753 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
754 (INSN2_READ_GPR_MMN): Likewise.
755 (INSN2_READ_FPR_D): Change the bit used.
756 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
757 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
758 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
759 (INSN2_COND_BRANCH): Likewise.
760 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
761 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
762 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
763 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
764 (INSN2_MOD_GPR_MN): Likewise.
765
ea783ef3
DM		 7662011-08-05 David S. Miller <davem@davemloft.net>
767
768 * sparc.h: Document new format codes '4', '5', and '('.
769 (OPF_LOW4, RS3): New macros.
770
7c176fa8
MR		 7712011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
772
773 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
774 order of flags documented.
775
2309ddf2
MR		 7762011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
777
778 * mips.h: Clarify the description of microMIPS instruction
779 manipulation macros.
780 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
781
df58fc94 7822011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 783 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 784
785 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
786 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
787 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
788 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
789 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
790 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
791 (OP_MASK_RS3, OP_SH_RS3): Likewise.
792 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
793 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
794 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
795 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
796 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
797 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
798 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
799 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
800 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
801 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
802 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
803 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
804 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
805 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
806 (INSN_WRITE_GPR_S): New macro.
807 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
808 (INSN2_READ_FPR_D): Likewise.
809 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
810 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
811 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
812 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
813 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
814 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
815 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
816 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
817 (CPU_MICROMIPS): New macro.
818 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
819 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
820 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
821 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
822 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
823 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
824 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
825 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
826 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
827 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
828 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
829 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
830 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
831 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
832 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
833 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
834 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
835 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
836 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
837 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
838 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
839 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
840 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
841 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
842 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
843 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
844 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
845 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
846 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
847 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
848 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
849 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
850 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
851 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
852 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
853 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
854 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
855 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
856 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
857 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
858 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
859 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
860 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
861 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
862 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
863 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
864 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
865 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
866 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
867 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
868 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
869 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
870 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
871 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
872 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
873 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
874 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
875 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
876 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
877 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
878 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
879 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
880 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
881 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
882 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
883 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
884 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
885 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
886 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
887 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
888 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
889 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
890 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
891 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
892 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
893 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
894 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
895 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
896 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
897 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
898 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
899 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
900 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
901 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
902 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
903 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
904 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
905 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
906 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
907 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
908 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
909 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
910 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
911 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
912 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
913 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
914 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
915 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
916 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
917 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
918 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
919 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
920 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
921 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
922 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
923 (micromips_opcodes): New declaration.
924 (bfd_micromips_num_opcodes): Likewise.
925
bcd530a7
RS		 9262011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
927
928 * mips.h (INSN_TRAP): Rename to...
929 (INSN_NO_DELAY_SLOT): ... this.
930 (INSN_SYNC): Remove macro.
931
2dad5a91
EW		 9322011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
933
934 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
935 a duplicate of AVR_ISA_SPM.
936
5d73b1f1
NC		 9372011-07-01 Nick Clifton <nickc@redhat.com>
938
939 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
940
ef26d60e
MF		 9412011-06-18 Robin Getz <robin.getz@analog.com>
942
943 * bfin.h (is_macmod_signed): New func
944
8fb8dca7
MF		 9452011-06-18 Mike Frysinger <vapier@gentoo.org>
946
947 * bfin.h (is_macmod_pmove): Add missing space before func args.
948 (is_macmod_hmove): Likewise.
949
aa137e4d
NC		 9502011-06-13 Walter Lee <walt@tilera.com>
951
952 * tilegx.h: New file.
953 * tilepro.h: New file.
954
3b2f0793
PB		 9552011-05-31 Paul Brook <paul@codesourcery.com>
956
aa137e4d
NC		 957 * arm.h (ARM_ARCH_V7R_IDIV): Define.
958
9592011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
960
961 * s390.h: Replace S390_OPERAND_REG_EVEN with
962 S390_OPERAND_REG_PAIR.
963
9642011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
965
966 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 967
ac7f631b
NC		 9682011-04-18 Julian Brown <julian@codesourcery.com>
969
970 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
971
84701018
NC		 9722011-04-11 Dan McDonald <dan@wellkeeper.com>
973
974 PR gas/12296
975 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
976
8cc66334
EW		 9772011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
978
979 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
980 New instruction set flags.
981 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
982
3eebd5eb
MR		 9832011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
984
985 * mips.h (M_PREF_AB): New enum value.
986
26bb3ddd
MF		 9872011-02-12 Mike Frysinger <vapier@gentoo.org>
988
89c0d58c
MR		 989 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
990 M_IU): Define.
991 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 992
dd76fcb8
MF		 9932011-02-11 Mike Frysinger <vapier@gentoo.org>
994
995 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
996
98d23bef
BS		 9972011-02-04 Bernd Schmidt <bernds@codesourcery.com>
998
999 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1000 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1001
3c853d93
DA		 10022010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1003
1004 PR gas/11395
1005 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1006 "bb" entries.
1007
79676006
DA		 10082010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1009
1010 PR gas/11395
1011 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1012
1bec78e9
RS		 10132010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1014
1015 * mips.h: Update commentary after last commit.
1016
98675402
RS		 10172010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1018
1019 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1020 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1021 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1022
aa137e4d
NC		 10232010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1024
1025 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1026
435b94a4
RS		 10272010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1028
1029 * mips.h: Fix previous commit.
1030
d051516a
NC		 10312010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1032
1033 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1034 (INSN_LOONGSON_3A): Clear bit 31.
1035
251665fc
MGD		 10362010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1037
1038 PR gas/12198
1039 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1040 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1041 (ARM_ARCH_V6M_ONLY): New define.
1042
fd503541
NC		 10432010-11-11 Mingming Sun <mingm.sun@gmail.com>
1044
1045 * mips.h (INSN_LOONGSON_3A): Defined.
1046 (CPU_LOONGSON_3A): Defined.
1047 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1048
4469d2be
AM		 10492010-10-09 Matt Rice <ratmice@gmail.com>
1050
1051 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1052 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1053
90ec0d68
MGD		 10542010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1055
1056 * arm.h (ARM_EXT_VIRT): New define.
1057 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1058 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1059 Extensions.
1060
eea54501 10612010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1062
eea54501
MGD		 1063 * arm.h (ARM_AEXT_ADIV): New define.
1064 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1065
b2a5fbdc
MGD		 10662010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1067
1068 * arm.h (ARM_EXT_OS): New define.
1069 (ARM_AEXT_V6SM): Likewise.
1070 (ARM_ARCH_V6SM): Likewise.
1071
60e5ef9f
MGD		 10722010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1073
1074 * arm.h (ARM_EXT_MP): Add.
1075 (ARM_ARCH_V7A_MP): Likewise.
1076
73a63ccf
MF		 10772010-09-22 Mike Frysinger <vapier@gentoo.org>
1078
1079 * bfin.h: Declare pseudoChr structs/defines.
1080
ee99860a
MF		 10812010-09-21 Mike Frysinger <vapier@gentoo.org>
1082
1083 * bfin.h: Strip trailing whitespace.
1084
f9c7014e
DD		 10852010-07-29 DJ Delorie <dj@redhat.com>
1086
1087 * rx.h (RX_Operand_Type): Add TwoReg.
1088 (RX_Opcode_ID): Remove ediv and ediv2.
1089
93378652
DD		 10902010-07-27 DJ Delorie <dj@redhat.com>
1091
1092 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1093
1cd986c5
NC		 10942010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1095 Ina Pandit <ina.pandit@kpitcummins.com>
1096
1097 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1098 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1099 PROCESSOR_V850E2_ALL.
1100 Remove PROCESSOR_V850EA support.
1101 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1102 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1103 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1104 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1105 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1106 V850_OPERAND_PERCENT.
1107 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1108 V850_NOT_R0.
1109 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1110 and V850E_PUSH_POP
1111
9a2c7088
MR		 11122010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1113
1114 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1115 (MIPS16_INSN_BRANCH): Rename to...
1116 (MIPS16_INSN_COND_BRANCH): ... this.
1117
bdc70b4a
AM		 11182010-07-03 Alan Modra <amodra@gmail.com>
1119
1120 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1121 Renumber other PPC_OPCODE defines.
1122
f2bae120
AM		 11232010-07-03 Alan Modra <amodra@gmail.com>
1124
1125 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1126
360cfc9c
AM		 11272010-06-29 Alan Modra <amodra@gmail.com>
1128
1129 * maxq.h: Delete file.
1130
e01d869a
AM		 11312010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1132
1133 * ppc.h (PPC_OPCODE_E500): Define.
1134
f79e2745
CM		 11352010-05-26 Catherine Moore <clm@codesourcery.com>
1136
1137 * opcode/mips.h (INSN_MIPS16): Remove.
1138
2462afa1
JM		 11392010-04-21 Joseph Myers <joseph@codesourcery.com>
1140
1141 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1142
e4e42b45
NC		 11432010-04-15 Nick Clifton <nickc@redhat.com>
1144
1145 * alpha.h: Update copyright notice to use GPLv3.
1146 * arc.h: Likewise.
1147 * arm.h: Likewise.
1148 * avr.h: Likewise.
1149 * bfin.h: Likewise.
1150 * cgen.h: Likewise.
1151 * convex.h: Likewise.
1152 * cr16.h: Likewise.
1153 * cris.h: Likewise.
1154 * crx.h: Likewise.
1155 * d10v.h: Likewise.
1156 * d30v.h: Likewise.
1157 * dlx.h: Likewise.
1158 * h8300.h: Likewise.
1159 * hppa.h: Likewise.
1160 * i370.h: Likewise.
1161 * i386.h: Likewise.
1162 * i860.h: Likewise.
1163 * i960.h: Likewise.
1164 * ia64.h: Likewise.
1165 * m68hc11.h: Likewise.
1166 * m68k.h: Likewise.
1167 * m88k.h: Likewise.
1168 * maxq.h: Likewise.
1169 * mips.h: Likewise.
1170 * mmix.h: Likewise.
1171 * mn10200.h: Likewise.
1172 * mn10300.h: Likewise.
1173 * msp430.h: Likewise.
1174 * np1.h: Likewise.
1175 * ns32k.h: Likewise.
1176 * or32.h: Likewise.
1177 * pdp11.h: Likewise.
1178 * pj.h: Likewise.
1179 * pn.h: Likewise.
1180 * ppc.h: Likewise.
1181 * pyr.h: Likewise.
1182 * rx.h: Likewise.
1183 * s390.h: Likewise.
1184 * score-datadep.h: Likewise.
1185 * score-inst.h: Likewise.
1186 * sparc.h: Likewise.
1187 * spu-insns.h: Likewise.
1188 * spu.h: Likewise.
1189 * tic30.h: Likewise.
1190 * tic4x.h: Likewise.
1191 * tic54x.h: Likewise.
1192 * tic80.h: Likewise.
1193 * v850.h: Likewise.
1194 * vax.h: Likewise.
1195
40b36596
JM		 11962010-03-25 Joseph Myers <joseph@codesourcery.com>
1197
1198 * tic6x-control-registers.h, tic6x-insn-formats.h,
1199 tic6x-opcode-table.h, tic6x.h: New.
1200
c67a084a
NC		 12012010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1202
1203 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1204
466ef64f
AM		 12052010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1206
1207 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1208
1319d143
L		 12092010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1210
1211 * ia64.h (ia64_find_opcode): Remove argument name.
1212 (ia64_find_next_opcode): Likewise.
1213 (ia64_dis_opcode): Likewise.
1214 (ia64_free_opcode): Likewise.
1215 (ia64_find_dependency): Likewise.
1216
1fbb9298
DE		 12172009-11-22 Doug Evans <dje@sebabeach.org>
1218
1219 * cgen.h: Include bfd_stdint.h.
1220 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1221
ada65aa3
PB		 12222009-11-18 Paul Brook <paul@codesourcery.com>
1223
1224 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1225
9e3c6df6
PB		 12262009-11-17 Paul Brook <paul@codesourcery.com>
1227 Daniel Jacobowitz <dan@codesourcery.com>
1228
1229 * arm.h (ARM_EXT_V6_DSP): Define.
1230 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1231 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1232
0d734b5d
DD		 12332009-11-04 DJ Delorie <dj@redhat.com>
1234
1235 * rx.h (rx_decode_opcode) (mvtipl): Add.
1236 (mvtcp, mvfcp, opecp): Remove.
1237
62f3b8c8
PB		 12382009-11-02 Paul Brook <paul@codesourcery.com>
1239
1240 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1241 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1242 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1243 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1244 FPU_ARCH_NEON_VFP_V4): Define.
1245
ac1e9eca
DE		 12462009-10-23 Doug Evans <dje@sebabeach.org>
1247
1248 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1249 * cgen.h: Update. Improve multi-inclusion macro name.
1250
9fe54b1c
PB		 12512009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1252
1253 * ppc.h (PPC_OPCODE_476): Define.
1254
634b50f2
PB		 12552009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1256
1257 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1258
c7927a3c
NC		 12592009-09-29 DJ Delorie <dj@redhat.com>
1260
1261 * rx.h: New file.
1262
b961e85b
AM		 12632009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1264
1265 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1266
e0d602ec
BE		 12672009-09-21 Ben Elliston <bje@au.ibm.com>
1268
1269 * ppc.h (PPC_OPCODE_PPCA2): New.
1270
96d56e9f
NC		 12712009-09-05 Martin Thuresson <martin@mtme.org>
1272
1273 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1274
d3ce72d0
NC		 12752009-08-29 Martin Thuresson <martin@mtme.org>
1276
1277 * tic30.h (template): Rename type template to
1278 insn_template. Updated code to use new name.
1279 * tic54x.h (template): Rename type template to
1280 insn_template.
1281
824b28db
NH		 12822009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1283
1284 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1285
f865a31d
AG		 12862009-06-11 Anthony Green <green@moxielogic.com>
1287
1288 * moxie.h (MOXIE_F3_PCREL): Define.
1289 (moxie_form3_opc_info): Grow.
1290
0e7c7f11
AG		 12912009-06-06 Anthony Green <green@moxielogic.com>
1292
1293 * moxie.h (MOXIE_F1_M): Define.
1294
20135e4c
NC		 12952009-04-15 Anthony Green <green@moxielogic.com>
1296
1297 * moxie.h: Created.
1298
bcb012d3
DD		 12992009-04-06 DJ Delorie <dj@redhat.com>
1300
1301 * h8300.h: Add relaxation attributes to MOVA opcodes.
1302
69fe9ce5
AM		 13032009-03-10 Alan Modra <amodra@bigpond.net.au>
1304
1305 * ppc.h (ppc_parse_cpu): Declare.
1306
c3b7224a
NC		 13072009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1308
1309 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1310 and _IMM11 for mbitclr and mbitset.
1311 * score-datadep.h: Update dependency information.
1312
066be9f7
PB		 13132009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1314
1315 * ppc.h (PPC_OPCODE_POWER7): New.
1316
fedc618e
DE		 13172009-02-06 Doug Evans <dje@google.com>
1318
1319 * i386.h: Add comment regarding sse* insns and prefixes.
1320
52b6b6b9
JM		 13212009-02-03 Sandip Matte <sandip@rmicorp.com>
1322
1323 * mips.h (INSN_XLR): Define.
1324 (INSN_CHIP_MASK): Update.
1325 (CPU_XLR): Define.
1326 (OPCODE_IS_MEMBER): Update.
1327 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1328
35669430
DE		 13292009-01-28 Doug Evans <dje@google.com>
1330
1331 * opcode/i386.h: Add multiple inclusion protection.
1332 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1333 (EDI_REG_NUM): New macros.
1334 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1335 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1336 (REX_PREFIX_P): New macro.
35669430 1337
1cb0a767
PB		 13382009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1339
1340 * ppc.h (struct powerpc_opcode): New field "deprecated".
1341 (PPC_OPCODE_NOPOWER4): Delete.
1342
3aa3176b
TS		 13432008-11-28 Joshua Kinard <kumba@gentoo.org>
1344
1345 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1346 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1347
8e79c3df
CM		 13482008-11-18 Catherine Moore <clm@codesourcery.com>
1349
1350 * arm.h (FPU_NEON_FP16): New.
1351 (FPU_ARCH_NEON_FP16): New.
1352
de9a3e51
CF		 13532008-11-06 Chao-ying Fu <fu@mips.com>
1354
1355 * mips.h: Doucument '1' for 5-bit sync type.
1356
1ca35711
L		 13572008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1358
1359 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1360 IA64_RS_CR.
1361
9b4e5766
PB		 13622008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1363
1364 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1365
081ba1b3
AM		 13662008-07-30 Michael J. Eager <eager@eagercon.com>
1367
1368 * ppc.h (PPC_OPCODE_405): Define.
1369 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1370
fa452fa6
PB		 13712008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1372
1373 * ppc.h (ppc_cpu_t): New typedef.
1374 (struct powerpc_opcode <flags>): Use it.
1375 (struct powerpc_operand <insert, extract>): Likewise.
1376 (struct powerpc_macro <flags>): Likewise.
1377
bb35fb24
NC		 13782008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1379
1380 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1381 Update comment before MIPS16 field descriptors to mention MIPS16.
1382 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1383 BBIT.
1384 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1385 New bit masks and shift counts for cins and exts.
1386
dd3cbb7e
NC		 1387 * mips.h: Document new field descriptors +Q.
1388 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1389
d0799671
AN		 13902008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1391
9aff4b7a 1392 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1393 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1394
19a6653c
AM		 13952008-04-14 Edmar Wienskoski <edmar@freescale.com>
1396
1397 * ppc.h: (PPC_OPCODE_E500MC): New.
1398
c0f3af97
L		 13992008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1400
1401 * i386.h (MAX_OPERANDS): Set to 5.
1402 (MAX_MNEM_SIZE): Changed to 20.
1403
e210c36b
NC		 14042008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1405
1406 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1407
b1cc4aeb
PB		 14082008-03-09 Paul Brook <paul@codesourcery.com>
1409
1410 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1411
7e806470
PB		 14122008-03-04 Paul Brook <paul@codesourcery.com>
1413
1414 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1415 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1416 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1417
7b2185f9 14182008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1419 Nick Clifton <nickc@redhat.com>
1420
1421 PR 3134
1422 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1423 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1424 set.
af7329f0 1425
796d5313
NC		 14262008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1427
1428 * cr16.h (cr16_num_optab): Declared.
1429
d669d37f
NC		 14302008-02-14 Hakan Ardo <hakan@debian.org>
1431
1432 PR gas/2626
1433 * avr.h (AVR_ISA_2xxe): Define.
1434
e6429699
AN		 14352008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1436
1437 * mips.h: Update copyright.
1438 (INSN_CHIP_MASK): New macro.
1439 (INSN_OCTEON): New macro.
1440 (CPU_OCTEON): New macro.
1441 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1442
e210c36b
NC		 14432008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1444
1445 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1446
14472008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1448
1449 * avr.h (AVR_ISA_USB162): Add new opcode set.
1450 (AVR_ISA_AVR3): Likewise.
1451
350cc38d
MS		 14522007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1453
1454 * mips.h (INSN_LOONGSON_2E): New.
1455 (INSN_LOONGSON_2F): New.
1456 (CPU_LOONGSON_2E): New.
1457 (CPU_LOONGSON_2F): New.
1458 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1459
56950294
MS		 14602007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1461
1462 * mips.h (INSN_ISA*): Redefine certain values as an
1463 enumeration. Update comments.
1464 (mips_isa_table): New.
1465 (ISA_MIPS*): Redefine to match enumeration.
1466 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1467 values.
1468
c3d65c1c
BE		 14692007-08-08 Ben Elliston <bje@au.ibm.com>
1470
1471 * ppc.h (PPC_OPCODE_PPCPS): New.
1472
0fdaa005
L		 14732007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1474
1475 * m68k.h: Document j K & E.
1476
14772007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1478
1479 * cr16.h: New file for CR16 target.
1480
3896c469
AM		 14812007-05-02 Alan Modra <amodra@bigpond.net.au>
1482
1483 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1484
9a2e615a
NS		 14852007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1486
1487 * m68k.h (mcfisa_c): New.
1488 (mcfusp, mcf_mask): Adjust.
1489
b84bf58a
AM		 14902007-04-20 Alan Modra <amodra@bigpond.net.au>
1491
1492 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1493 (num_powerpc_operands): Declare.
1494 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1495 (PPC_OPERAND_PLUS1): Define.
1496
831480e9 14972007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1498
1499 * i386.h (REX_MODE64): Renamed to ...
1500 (REX_W): This.
1501 (REX_EXTX): Renamed to ...
1502 (REX_R): This.
1503 (REX_EXTY): Renamed to ...
1504 (REX_X): This.
1505 (REX_EXTZ): Renamed to ...
1506 (REX_B): This.
1507
0b1cf022
L		 15082007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1509
1510 * i386.h: Add entries from config/tc-i386.h and move tables
1511 to opcodes/i386-opc.h.
1512
d796c0ad
L		 15132007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1514
1515 * i386.h (FloatDR): Removed.
1516 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1517
30ac7323
AM		 15182007-03-01 Alan Modra <amodra@bigpond.net.au>
1519
1520 * spu-insns.h: Add soma double-float insns.
1521
8b082fb1 15222007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1523 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1524
1525 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1526 (INSN_DSPR2): Add flag for DSP R2 instructions.
1527 (M_BALIGN): New macro.
1528
4eed87de
AM		 15292007-02-14 Alan Modra <amodra@bigpond.net.au>
1530
1531 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1532 and Seg3ShortFrom with Shortform.
1533
fda592e8
L		 15342007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1535
1536 PR gas/4027
1537 * i386.h (i386_optab): Put the real "test" before the pseudo
1538 one.
1539
3bdcfdf4
KH		 15402007-01-08 Kazu Hirata <kazu@codesourcery.com>
1541
1542 * m68k.h (m68010up): OR fido_a.
1543
9840d27e
KH		 15442006-12-25 Kazu Hirata <kazu@codesourcery.com>
1545
1546 * m68k.h (fido_a): New.
1547
c629cdac
KH		 15482006-12-24 Kazu Hirata <kazu@codesourcery.com>
1549
1550 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1551 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1552 values.
1553
b7d9ef37
L		 15542006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1555
1556 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1557
b138abaa
NC		 15582006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1559
1560 * score-inst.h (enum score_insn_type): Add Insn_internal.
1561
e9f53129
AM		 15622006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1563 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1564 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1565 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1566 Alan Modra <amodra@bigpond.net.au>
1567
1568 * spu-insns.h: New file.
1569 * spu.h: New file.
1570
ede602d7
AM		 15712006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1572
1573 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1574
7918206c
MM		 15752006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1576
e4e42b45 1577 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1578 in amdfam10 architecture.
1579
ef05d495
L		 15802006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1581
1582 * i386.h: Replace CpuMNI with CpuSSSE3.
1583
2d447fca 15842006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1585 Joseph Myers <joseph@codesourcery.com>
1586 Ian Lance Taylor <ian@wasabisystems.com>
1587 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1588
1589 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1590
1c0d3aa6
NC		 15912006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1592
1593 * score-datadep.h: New file.
1594 * score-inst.h: New file.
1595
c2f0420e
L		 15962006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1597
1598 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1599 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1600 movdq2q and movq2dq.
1601
050dfa73
MM		 16022006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1603 Michael Meissner <michael.meissner@amd.com>
1604
1605 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1606
15965411
L		 16072006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1608
1609 * i386.h (i386_optab): Add "nop" with memory reference.
1610
46e883c5
L		 16112006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1612
1613 * i386.h (i386_optab): Update comment for 64bit NOP.
1614
9622b051
AM		 16152006-06-06 Ben Elliston <bje@au.ibm.com>
1616 Anton Blanchard <anton@samba.org>
1617
1618 * ppc.h (PPC_OPCODE_POWER6): Define.
1619 Adjust whitespace.
1620
a9e24354
TS		 16212006-06-05 Thiemo Seufer <ths@mips.com>
1622
e4e42b45 1623 * mips.h: Improve description of MT flags.
a9e24354 1624
a596001e
RS		 16252006-05-25 Richard Sandiford <richard@codesourcery.com>
1626
1627 * m68k.h (mcf_mask): Define.
1628
d43b4baf 16292006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1630 David Ung <davidu@mips.com>
d43b4baf
TS		 1631
1632 * mips.h (enum): Add macro M_CACHE_AB.
1633
39a7806d 16342006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1635 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1636 David Ung <davidu@mips.com>
1637
1638 * mips.h: Add INSN_SMARTMIPS define.
1639
9bcd4f99 16402006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1641 David Ung <davidu@mips.com>
9bcd4f99
TS		 1642
1643 * mips.h: Defines udi bits and masks. Add description of
1644 characters which may appear in the args field of udi
1645 instructions.
1646
ef0ee844
TS		 16472006-04-26 Thiemo Seufer <ths@networkno.de>
1648
1649 * mips.h: Improve comments describing the bitfield instruction
1650 fields.
1651
f7675147
L		 16522006-04-26 Julian Brown <julian@codesourcery.com>
1653
1654 * arm.h (FPU_VFP_EXT_V3): Define constant.
1655 (FPU_NEON_EXT_V1): Likewise.
1656 (FPU_VFP_HARD): Update.
1657 (FPU_VFP_V3): Define macro.
1658 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1659
ef0ee844 16602006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1661
1662 * avr.h (AVR_ISA_PWMx): New.
1663
2da12c60
NS		 16642006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1665
1666 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1667 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1668 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1669 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1670 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1671
0715c387
PB		 16722006-03-10 Paul Brook <paul@codesourcery.com>
1673
1674 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1675
34bdd094
DA		 16762006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1677
1678 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1679 first. Correct mask of bb "B" opcode.
1680
331d2d0d
L		 16812006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1682
1683 * i386.h (i386_optab): Support Intel Merom New Instructions.
1684
62b3e311
PB		 16852006-02-24 Paul Brook <paul@codesourcery.com>
1686
1687 * arm.h: Add V7 feature bits.
1688
59cf82fe
L		 16892006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1690
1691 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1692
e74cfd16
PB		 16932006-01-31 Paul Brook <paul@codesourcery.com>
1694 Richard Earnshaw <rearnsha@arm.com>
1695
1696 * arm.h: Use ARM_CPU_FEATURE.
1697 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1698 (arm_feature_set): Change to a structure.
1699 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1700 ARM_FEATURE): New macros.
1701
5b3f8a92
HPN		 17022005-12-07 Hans-Peter Nilsson <hp@axis.com>
1703
1704 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1705 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1706 (ADD_PC_INCR_OPCODE): Don't define.
1707
cb712a9e
L		 17082005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1709
1710 PR gas/1874
1711 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1712
0499d65b
TS		 17132005-11-14 David Ung <davidu@mips.com>
1714
1715 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1716 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1717 save/restore encoding of the args field.
1718
ea5ca089
DB		 17192005-10-28 Dave Brolley <brolley@redhat.com>
1720
1721 Contribute the following changes:
1722 2005-02-16 Dave Brolley <brolley@redhat.com>
1723
1724 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1725 cgen_isa_mask_* to cgen_bitset_*.
1726 * cgen.h: Likewise.
1727
16175d96
DB		 1728 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1729
1730 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1731 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1732 (CGEN_CPU_TABLE): Make isas a ponter.
1733
1734 2003-09-29 Dave Brolley <brolley@redhat.com>
1735
1736 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1737 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1738 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1739
1740 2002-12-13 Dave Brolley <brolley@redhat.com>
1741
1742 * cgen.h (symcat.h): #include it.
1743 (cgen-bitset.h): #include it.
1744 (CGEN_ATTR_VALUE_TYPE): Now a union.
1745 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1746 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1747 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1748 * cgen-bitset.h: New file.
1749
3c9b82ba
NC		 17502005-09-30 Catherine Moore <clm@cm00re.com>
1751
1752 * bfin.h: New file.
1753
6a2375c6
JB		 17542005-10-24 Jan Beulich <jbeulich@novell.com>
1755
1756 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1757 indirect operands.
1758
c06a12f8
DA		 17592005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1760
1761 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1762 Add FLAG_STRICT to pa10 ftest opcode.
1763
4d443107
DA		 17642005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1765
1766 * hppa.h (pa_opcodes): Remove lha entries.
1767
f0a3b40f
DA		 17682005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1769
1770 * hppa.h (FLAG_STRICT): Revise comment.
1771 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1772 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1773 entries for "fdc".
1774
e210c36b
NC		 17752005-09-30 Catherine Moore <clm@cm00re.com>
1776
1777 * bfin.h: New file.
1778
1b7e1362
DA		 17792005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1780
1781 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1782
089b39de
CF		 17832005-09-06 Chao-ying Fu <fu@mips.com>
1784
1785 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1786 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1787 define.
1788 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1789 (INSN_ASE_MASK): Update to include INSN_MT.
1790 (INSN_MT): New define for MT ASE.
1791
93c34b9b
CF		 17922005-08-25 Chao-ying Fu <fu@mips.com>
1793
1794 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1795 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1796 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1797 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1798 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1799 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1800 instructions.
1801 (INSN_DSP): New define for DSP ASE.
1802
848cf006
AM		 18032005-08-18 Alan Modra <amodra@bigpond.net.au>
1804
1805 * a29k.h: Delete.
1806
36ae0db3
DJ		 18072005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1808
1809 * ppc.h (PPC_OPCODE_E300): Define.
1810
8c929562
MS		 18112005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1812
1813 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1814
f7b8cccc
DA		 18152005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1816
1817 PR gas/336
1818 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1819 and pitlb.
1820
8b5328ac
JB		 18212005-07-27 Jan Beulich <jbeulich@novell.com>
1822
1823 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1824 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1825 Add movq-s as 64-bit variants of movd-s.
1826
f417d200
DA		 18272005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1828
18b3bdfc
DA		 1829 * hppa.h: Fix punctuation in comment.
1830
f417d200
DA		 1831 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1832 implicit space-register addressing. Set space-register bits on opcodes
1833 using implicit space-register addressing. Add various missing pa20
1834 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1835 space-register addressing. Use "fE" instead of "fe" in various
1836 fstw opcodes.
1837
9a145ce6
JB		 18382005-07-18 Jan Beulich <jbeulich@novell.com>
1839
1840 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1841
90700ea2
L		 18422007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1843
1844 * i386.h (i386_optab): Support Intel VMX Instructions.
1845
48f130a8
DA		 18462005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1847
1848 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1849
30123838
JB		 18502005-07-05 Jan Beulich <jbeulich@novell.com>
1851
1852 * i386.h (i386_optab): Add new insns.
1853
47b0e7ad
NC		 18542005-07-01 Nick Clifton <nickc@redhat.com>
1855
1856 * sparc.h: Add typedefs to structure declarations.
1857
b300c311
L		 18582005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1859
1860 PR 1013
1861 * i386.h (i386_optab): Update comments for 64bit addressing on
1862 mov. Allow 64bit addressing for mov and movq.
1863
2db495be
DA		 18642005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1865
1866 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1867 respectively, in various floating-point load and store patterns.
1868
caa05036
DA		 18692005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1870
1871 * hppa.h (FLAG_STRICT): Correct comment.
1872 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1873 PA 2.0 mneumonics when equivalent. Entries with cache control
1874 completers now require PA 1.1. Adjust whitespace.
1875
f4411256
AM		 18762005-05-19 Anton Blanchard <anton@samba.org>
1877
1878 * ppc.h (PPC_OPCODE_POWER5): Define.
1879
e172dbf8
NC		 18802005-05-10 Nick Clifton <nickc@redhat.com>
1881
1882 * Update the address and phone number of the FSF organization in
1883 the GPL notices in the following files:
1884 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1885 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1886 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1887 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1888 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1889 tic54x.h, tic80.h, v850.h, vax.h
1890
e44823cf
JB		 18912005-05-09 Jan Beulich <jbeulich@novell.com>
1892
1893 * i386.h (i386_optab): Add ht and hnt.
1894
791fe849
MK		 18952005-04-18 Mark Kettenis <kettenis@gnu.org>
1896
1897 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1898 Add xcrypt-ctr. Provide aliases without hyphens.
1899
faa7ef87
L		 19002005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1901
a63027e5
L		 1902 Moved from ../ChangeLog
1903
faa7ef87
L		 1904 2005-04-12 Paul Brook <paul@codesourcery.com>
1905 * m88k.h: Rename psr macros to avoid conflicts.
1906
1907 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1908 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1909 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1910 and ARM_ARCH_V6ZKT2.
1911
1912 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1913 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1914 Remove redundant instruction types.
1915 (struct argument): X_op - new field.
1916 (struct cst4_entry): Remove.
1917 (no_op_insn): Declare.
1918
1919 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1920 * crx.h (enum argtype): Rename types, remove unused types.
1921
1922 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1923 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1924 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1925 (enum operand_type): Rearrange operands, edit comments.
1926 replace us<N> with ui<N> for unsigned immediate.
1927 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1928 displacements (respectively).
1929 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1930 (instruction type): Add NO_TYPE_INS.
1931 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1932 (operand_entry): New field - 'flags'.
1933 (operand flags): New.
1934
1935 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1936 * crx.h (operand_type): Remove redundant types i3, i4,
1937 i5, i8, i12.
1938 Add new unsigned immediate types us3, us4, us5, us16.
1939
bc4bd9ab
MK		 19402005-04-12 Mark Kettenis <kettenis@gnu.org>
1941
1942 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1943 adjust them accordingly.
1944
373ff435
JB		 19452005-04-01 Jan Beulich <jbeulich@novell.com>
1946
1947 * i386.h (i386_optab): Add rdtscp.
1948
4cc91dba
L		 19492005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1950
1951 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1952 between memory and segment register. Allow movq for moving between
1953 general-purpose register and segment register.
4cc91dba 1954
9ae09ff9
JB		 19552005-02-09 Jan Beulich <jbeulich@novell.com>
1956
1957 PR gas/707
1958 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1959 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1960 fnstsw.
1961
638e7a64
NS		 19622006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1963
1964 * m68k.h (m68008, m68ec030, m68882): Remove.
1965 (m68k_mask): New.
1966 (cpu_m68k, cpu_cf): New.
1967 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1968 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1969
90219bd0
AO		 19702005-01-25 Alexandre Oliva <aoliva@redhat.com>
1971
1972 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1973 * cgen.h (enum cgen_parse_operand_type): Add
1974 CGEN_PARSE_OPERAND_SYMBOLIC.
1975
239cb185
FF		 19762005-01-21 Fred Fish <fnf@specifixinc.com>
1977
1978 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1979 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1980 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1981
dc9a9f39
FF		 19822005-01-19 Fred Fish <fnf@specifixinc.com>
1983
1984 * mips.h (struct mips_opcode): Add new pinfo2 member.
1985 (INSN_ALIAS): New define for opcode table entries that are
1986 specific instances of another entry, such as 'move' for an 'or'
1987 with a zero operand.
1988 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1989 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1990
98e7aba8
ILT		 19912004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1992
1993 * mips.h (CPU_RM9000): Define.
1994 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1995
37edbb65
JB		 19962004-11-25 Jan Beulich <jbeulich@novell.com>
1997
1998 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1999 to/from test registers are illegal in 64-bit mode. Add missing
2000 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2001 (previously one had to explicitly encode a rex64 prefix). Re-enable
2002 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2003 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2004
20052004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2006
2007 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2008 available only with SSE2. Change the MMX additions introduced by SSE
2009 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2010 instructions by their now designated identifier (since combining i686
2011 and 3DNow! does not really imply 3DNow!A).
2012
f5c7edf4
AM		 20132004-11-19 Alan Modra <amodra@bigpond.net.au>
2014
2015 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2016 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2017
7499d566
NC		 20182004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2019 Vineet Sharma <vineets@noida.hcltech.com>
2020
2021 * maxq.h: New file: Disassembly information for the maxq port.
2022
bcb9eebe
L		 20232004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2024
2025 * i386.h (i386_optab): Put back "movzb".
2026
94bb3d38
HPN		 20272004-11-04 Hans-Peter Nilsson <hp@axis.com>
2028
2029 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2030 comments. Remove member cris_ver_sim. Add members
2031 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2032 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2033 (struct cris_support_reg, struct cris_cond15): New types.
2034 (cris_conds15): Declare.
2035 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2036 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2037 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2038 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2039 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2040 SIZE_FIELD_UNSIGNED.
2041
37edbb65 20422004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2043
2044 * i386.h (sldx_Suf): Remove.
2045 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2046 (q_FP): Define, implying no REX64.
2047 (x_FP, sl_FP): Imply FloatMF.
2048 (i386_optab): Split reg and mem forms of moving from segment registers
2049 so that the memory forms can ignore the 16-/32-bit operand size
2050 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2051 all non-floating-point instructions. Unite 32- and 64-bit forms of
2052 movsx, movzx, and movd. Adjust floating point operations for the above
2053 changes to the *FP macros. Add DefaultSize to floating point control
2054 insns operating on larger memory ranges. Remove left over comments
2055 hinting at certain insns being Intel-syntax ones where the ones
2056 actually meant are already gone.
2057
48c9f030
NC		 20582004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2059
2060 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2061 instruction type.
2062
0dd132b6
NC		 20632004-09-30 Paul Brook <paul@codesourcery.com>
2064
2065 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2066 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2067
23794b24
MM		 20682004-09-11 Theodore A. Roth <troth@openavr.org>
2069
2070 * avr.h: Add support for
2071 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2072
2a309db0
AM		 20732004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2074
2075 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2076
b18c562e
NC		 20772004-08-24 Dmitry Diky <diwil@spec.ru>
2078
2079 * msp430.h (msp430_opc): Add new instructions.
2080 (msp430_rcodes): Declare new instructions.
2081 (msp430_hcodes): Likewise..
2082
45d313cd
NC		 20832004-08-13 Nick Clifton <nickc@redhat.com>
2084
2085 PR/301
2086 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2087 processors.
2088
30d1c836
ML		 20892004-08-30 Michal Ludvig <mludvig@suse.cz>
2090
2091 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2092
9a45f1c2
L		 20932004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2094
2095 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2096
543613e9
NC		 20972004-07-21 Jan Beulich <jbeulich@novell.com>
2098
2099 * i386.h: Adjust instruction descriptions to better match the
2100 specification.
2101
b781e558
RE		 21022004-07-16 Richard Earnshaw <rearnsha@arm.com>
2103
2104 * arm.h: Remove all old content. Replace with architecture defines
2105 from gas/config/tc-arm.c.
2106
8577e690
AS		 21072004-07-09 Andreas Schwab <schwab@suse.de>
2108
2109 * m68k.h: Fix comment.
2110
1fe1f39c
NC		 21112004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2112
2113 * crx.h: New file.
2114
1d9f512f
AM		 21152004-06-24 Alan Modra <amodra@bigpond.net.au>
2116
2117 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2118
be8c092b
NC		 21192004-05-24 Peter Barada <peter@the-baradas.com>
2120
2121 * m68k.h: Add 'size' to m68k_opcode.
2122
6b6e92f4
NC		 21232004-05-05 Peter Barada <peter@the-baradas.com>
2124
2125 * m68k.h: Switch from ColdFire chip name to core variant.
2126
21272004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2128
2129 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2130 descriptions for new EMAC cases.
2131 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2132 handle Motorola MAC syntax.
2133 Allow disassembly of ColdFire V4e object files.
2134
fdd12ef3
AM		 21352004-03-16 Alan Modra <amodra@bigpond.net.au>
2136
2137 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2138
3922a64c
L		 21392004-03-12 Jakub Jelinek <jakub@redhat.com>
2140
2141 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2142
1f45d988
ML		 21432004-03-12 Michal Ludvig <mludvig@suse.cz>
2144
2145 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2146
0f10071e
ML		 21472004-03-12 Michal Ludvig <mludvig@suse.cz>
2148
2149 * i386.h (i386_optab): Added xstore/xcrypt insns.
2150
3255318a
NC		 21512004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2152
2153 * h8300.h (32bit ldc/stc): Add relaxing support.
2154
ca9a79a1 21552004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2156
ca9a79a1
NC		 2157 * h8300.h (BITOP): Pass MEMRELAX flag.
2158
875a0b14
NC		 21592004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2160
2161 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2162 except for the H8S.
252b5132 2163
c9e214e5 2164For older changes see ChangeLog-9103
252b5132 2165\f
b90efa5b 2166Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2167
2168Copying and distribution of this file, with or without modification,
2169are permitted in any medium without royalty provided the copyright
2170notice and this notice are preserved.
2171
252b5132 2172Local Variables:
c9e214e5
AM		 2173mode: change-log
2174left-margin: 8
2175fill-column: 74
252b5132
RH		 2176version-control: never
2177End:
GDB Binutils - Deliverables
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