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mach-o: display data_in_code.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
4b95cf5c
AM		 12014-03-05 Alan Modra <amodra@gmail.com>
2
3 Update copyright years.
4
e269fea7
AB		 52013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
6
7 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
8 microMIPS.
9
35c08157
KLC		 102013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
11 Wei-Cheng Wang <cole945@gmail.com>
12
13 * nds32.h: New file for Andes NDS32.
14
594d8fa8
MF		 152013-12-07 Mike Frysinger <vapier@gentoo.org>
16
17 * bfin.h: Remove +x file mode.
18
87b8eed7
YZ		 192013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
20
21 * aarch64.h (aarch64_pstatefields): Change element type to
22 aarch64_sys_reg.
23
c9fb6e58
YZ		 242013-11-18 Renlin Li <Renlin.Li@arm.com>
25
26 * arm.h (ARM_AEXT_V7VE): New define.
27 (ARM_ARCH_V7VE): New define.
28 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
29
a203d9b7
YZ		 302013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
31
32 Revert
33
34 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
35
36 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
37 (aarch64_sys_reg_writeonly_p): Ditto.
38
75468c93
YZ		 392013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
40
41 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
42 (aarch64_sys_reg_writeonly_p): Ditto.
43
49eec193
YZ		 442013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
45
46 * aarch64.h (aarch64_sys_reg): New typedef.
47 (aarch64_sys_regs): Change to define with the new type.
48 (aarch64_sys_reg_deprecated_p): Declare.
49
68a64283
YZ		 502013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
51
52 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
53 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
54
387a82f1
CF		 552013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
56
57 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
58 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
59 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
60 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
61 For MIPS, update extension character sequences after +.
62 (ASE_MSA): New define.
63 (ASE_MSA64): New define.
64 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
65 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
66 For microMIPS, update extension character sequences after +.
67
9aff4b7a
NC		 682013-08-23 Yuri Chornoivan <yurchor@ukr.net>
69
70 PR binutils/15834
71 * i960.h: Fix typos.
72
e423441d
RS		 732013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
74
75 * mips.h: Remove references to "+I" and imm2_expr.
76
5e0dc5ba
RS		 772013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
78
79 * mips.h (M_DEXT, M_DINS): Delete.
80
0f35dbc4
RS		 812013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
82
83 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
84 (mips_optional_operand_p): New function.
85
14daeee3
RS		 862013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
87 Richard Sandiford <rdsandiford@googlemail.com>
88
89 * mips.h: Document new VU0 operand characters.
90 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
91 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
92 (OP_REG_R5900_ACC): New mips_reg_operand_types.
93 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
94 (mips_vu0_channel_mask): Declare.
95
3ccad066
RS		 962013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
97
98 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
99 (mips_int_operand_min, mips_int_operand_max): New functions.
100 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
101
fc76e730
RS		 1022013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
103
104 * mips.h (mips_decode_reg_operand): New function.
105 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
106 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
107 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
108 New macros.
109 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
110 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
111 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
112 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
113 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
114 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
115 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
116 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
117 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
118 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
119 macros to cover the gaps.
120 (INSN2_MOD_SP): Replace with...
121 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
122 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
123 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
124 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
125 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
126 Delete.
127
26545944
RS		 1282013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
129
130 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
131 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
132 (MIPS16_INSN_COND_BRANCH): Delete.
133
7e8b059b
L		 1342013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
135 Kirill Yukhin <kirill.yukhin@intel.com>
136 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
137
138 * i386.h (BND_PREFIX_OPCODE): New.
139
c3c07478
RS		 1402013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
141
142 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
143 OP_SAVE_RESTORE_LIST.
144 (decode_mips16_operand): Declare.
145
ab902481
RS		 1462013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
147
148 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
149 (mips_operand, mips_int_operand, mips_mapped_int_operand)
150 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
151 (mips_pcrel_operand): New structures.
152 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
153 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
154 (decode_mips_operand, decode_micromips_operand): Declare.
155
cc537e56
RS		 1562013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
157
158 * mips.h: Document MIPS16 "I" opcode.
159
f2ae14a1
RS		 1602013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
161
162 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
163 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
164 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
165 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
166 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
167 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
168 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
169 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
170 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
171 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
172 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
173 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
174 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
175 Rename to...
176 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
177 (M_USD_AB): ...these.
178
5c324c16
RS		 1792013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
180
181 * mips.h: Remove documentation of "[" and "]". Update documentation
182 of "k" and the MDMX formats.
183
23e69e47
RS		 1842013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
185
186 * mips.h: Update documentation of "+s" and "+S".
187
27c5c572
RS		 1882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
189
190 * mips.h: Document "+i".
191
e76ff5ab
RS		 1922013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
193
194 * mips.h: Remove "mi" documentation. Update "mh" documentation.
195 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
196 Delete.
197 (INSN2_WRITE_GPR_MHI): Rename to...
198 (INSN2_WRITE_GPR_MH): ...this.
199
fa7616a4
RS		 2002013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
201
202 * mips.h: Remove documentation of "+D" and "+T".
203
18870af7
RS		 2042013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
205
206 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
207 Use "source" rather than "destination" for microMIPS "G".
208
833794fc
MR		 2092013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
210
211 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
212 values.
213
c3678916
RS		 2142013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
215
216 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
217
7f3c4072
CM		 2182013-06-17 Catherine Moore <clm@codesourcery.com>
219 Maciej W. Rozycki <macro@codesourcery.com>
220 Chao-Ying Fu <fu@mips.com>
221
222 * mips.h (OP_SH_EVAOFFSET): Define.
223 (OP_MASK_EVAOFFSET): Define.
224 (INSN_ASE_MASK): Delete.
225 (ASE_EVA): Define.
226 (M_CACHEE_AB, M_CACHEE_OB): New.
227 (M_LBE_OB, M_LBE_AB): New.
228 (M_LBUE_OB, M_LBUE_AB): New.
229 (M_LHE_OB, M_LHE_AB): New.
230 (M_LHUE_OB, M_LHUE_AB): New.
231 (M_LLE_AB, M_LLE_OB): New.
232 (M_LWE_OB, M_LWE_AB): New.
233 (M_LWLE_AB, M_LWLE_OB): New.
234 (M_LWRE_AB, M_LWRE_OB): New.
235 (M_PREFE_AB, M_PREFE_OB): New.
236 (M_SCE_AB, M_SCE_OB): New.
237 (M_SBE_OB, M_SBE_AB): New.
238 (M_SHE_OB, M_SHE_AB): New.
239 (M_SWE_OB, M_SWE_AB): New.
240 (M_SWLE_AB, M_SWLE_OB): New.
241 (M_SWRE_AB, M_SWRE_OB): New.
242 (MICROMIPSOP_SH_EVAOFFSET): Define.
243 (MICROMIPSOP_MASK_EVAOFFSET): Define.
244
0c8fe7cf
SL		 2452013-06-12 Sandra Loosemore <sandra@codesourcery.com>
246
247 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
248
c77c0862
RS		 2492013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
250
251 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
252
b015e599
AP		 2532013-05-09 Andrew Pinski <apinski@cavium.com>
254
255 * mips.h (OP_MASK_CODE10): Correct definition.
256 (OP_SH_CODE10): Likewise.
257 Add a comment that "+J" is used now for OP_*CODE10.
258 (INSN_ASE_MASK): Update.
259 (INSN_VIRT): New macro.
260 (INSN_VIRT64): New macro
261
13761a11
NC		 2622013-05-02 Nick Clifton <nickc@redhat.com>
263
264 * msp430.h: Add patterns for MSP430X instructions.
265
0afd1215
DM		 2662013-04-06 David S. Miller <davem@davemloft.net>
267
268 * sparc.h (F_PREFERRED): Define.
269 (F_PREF_ALIAS): Define.
270
41702d50
NC		 2712013-04-03 Nick Clifton <nickc@redhat.com>
272
273 * v850.h (V850_INVERSE_PCREL): Define.
274
e21e1a51
NC		 2752013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
276
277 PR binutils/15068
278 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
279
51dcdd4d
NC		 2802013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
281
282 PR binutils/15068
283 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
284 Add 16-bit opcodes.
285 * tic6xc-opcode-table.h: Add 16-bit insns.
286 * tic6x.h: Add support for 16-bit insns.
287
81f5558e
NC		 2882013-03-21 Michael Schewe <michael.schewe@gmx.net>
289
290 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
291 and mov.b/w/l Rs,@(d:32,ERd).
292
165546ad
NC		 2932013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
294
295 PR gas/15082
296 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
297 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
298 tic6x_operand_xregpair operand coding type.
299 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
300 opcode field, usu ORXREGD1324 for the src2 operand and remove the
301 TIC6X_FLAG_NO_CROSS.
302
795b8e6b
NC		 3032013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
304
305 PR gas/15095
306 * tic6x.h (enum tic6x_coding_method): Add
307 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
308 separately the msb and lsb of a register pair. This is needed to
309 encode the opcodes in the same way as TI assembler does.
310 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
311 and rsqrdp opcodes to use the new field coding types.
312
dd5181d5
KT		 3132013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
314
315 * arm.h (CRC_EXT_ARMV8): New constant.
316 (ARCH_CRC_ARMV8): New macro.
317
e60bb1dd
YZ		 3182013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
319
320 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
321
36591ba1
SL		 3222013-02-06 Sandra Loosemore <sandra@codesourcery.com>
323 Andrew Jenner <andrew@codesourcery.com>
324
325 Based on patches from Altera Corporation.
326
327 * nios2.h: New file.
328
e30181a5
YZ		 3292013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
330
331 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
332
0c9573f4
NC		 3332013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
334
335 PR gas/15069
336 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
337
981dc7f1
NC		 3382013-01-24 Nick Clifton <nickc@redhat.com>
339
340 * v850.h: Add e3v5 support.
341
f5555712
YZ		 3422013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
343
344 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
345
5817ffd1
PB		 3462013-01-10 Peter Bergner <bergner@vnet.ibm.com>
347
348 * ppc.h (PPC_OPCODE_POWER8): New define.
349 (PPC_OPCODE_HTM): Likewise.
350
a3c62988
NC		 3512013-01-10 Will Newton <will.newton@imgtec.com>
352
353 * metag.h: New file.
354
73335eae
NC		 3552013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
356
357 * cr16.h (make_instruction): Rename to cr16_make_instruction.
358 (match_opcode): Rename to cr16_match_opcode.
359
e407c74b
NC		 3602013-01-04 Juergen Urban <JuergenUrban@gmx.de>
361
362 * mips.h: Add support for r5900 instructions including lq and sq.
363
bab4becb
NC		 3642013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
365
366 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
367 (make_instruction,match_opcode): Added function prototypes.
368 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
369
776fc418
AM		 3702012-11-23 Alan Modra <amodra@gmail.com>
371
372 * ppc.h (ppc_parse_cpu): Update prototype.
373
f05682d4
DA		 3742012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
375
376 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
377 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
378
cfc72779
AK		 3792012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
380
381 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
382
b3e14eda
L		 3832012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
384
385 * ia64.h (ia64_opnd): Add new operand types.
386
2c63854f
DM		 3872012-08-21 David S. Miller <davem@davemloft.net>
388
389 * sparc.h (F3F4): New macro.
390
a06ea964 3912012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 392 Laurent Desnogues <laurent.desnogues@arm.com>
393 Jim MacArthur <jim.macarthur@arm.com>
394 Marcus Shawcroft <marcus.shawcroft@arm.com>
395 Nigel Stephens <nigel.stephens@arm.com>
396 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
397 Richard Earnshaw <rearnsha@arm.com>
398 Sofiane Naci <sofiane.naci@arm.com>
399 Tejas Belagod <tejas.belagod@arm.com>
400 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 401
402 * aarch64.h: New file.
403
35d0a169 4042012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 405 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 406
407 * mips.h (mips_opcode): Add the exclusions field.
408 (OPCODE_IS_MEMBER): Remove macro.
409 (cpu_is_member): New inline function.
410 (opcode_is_member): Likewise.
411
03f66e8a 4122012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 413 Catherine Moore <clm@codesourcery.com>
414 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 415
416 * mips.h: Document microMIPS DSP ASE usage.
417 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
418 microMIPS DSP ASE support.
419 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
420 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
421 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
422 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
423 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
424 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
425 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
426
9d7b4c23
MR		 4272012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
428
429 * mips.h: Fix a typo in description.
430
76e879f8
NC		 4312012-06-07 Georg-Johann Lay <avr@gjlay.de>
432
433 * avr.h: (AVR_ISA_XCH): New define.
434 (AVR_ISA_XMEGA): Use it.
435 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
436
6927f982
NC		 4372012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
438
439 * m68hc11.h: Add XGate definitions.
440 (struct m68hc11_opcode): Add xg_mask field.
441
b9c361e0
JL		 4422012-05-14 Catherine Moore <clm@codesourcery.com>
443 Maciej W. Rozycki <macro@codesourcery.com>
444 Rhonda Wittels <rhonda@codesourcery.com>
445
6927f982 446 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 447 (PPC_OP_SA): New macro.
448 (PPC_OP_SE_VLE): New macro.
449 (PPC_OP): Use a variable shift amount.
450 (powerpc_operand): Update comments.
451 (PPC_OPSHIFT_INV): New macro.
452 (PPC_OPERAND_CR): Replace with...
453 (PPC_OPERAND_CR_BIT): ...this and
454 (PPC_OPERAND_CR_REG): ...this.
455
456
f6c1a2d5
NC		 4572012-05-03 Sean Keys <skeys@ipdatasys.com>
458
459 * xgate.h: Header file for XGATE assembler.
460
ec668d69
DM		 4612012-04-27 David S. Miller <davem@davemloft.net>
462
6cda1326
DM		 463 * sparc.h: Document new arg code' )' for crypto RS3
464 immediates.
465
ec668d69
DM		 466 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
467 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
468 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
469 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
470 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
471 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
472 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
473 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
474 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
475 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
476 HWCAP_CBCOND, HWCAP_CRC32): New defines.
477
aea77599
AM		 4782012-03-10 Edmar Wienskoski <edmar@freescale.com>
479
480 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
481
1f42f8b3
AM		 4822012-02-27 Alan Modra <amodra@gmail.com>
483
484 * crx.h (cst4_map): Update declaration.
485
6f7be959
WL		 4862012-02-25 Walter Lee <walt@tilera.com>
487
488 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
489 TILEGX_OPC_LD_TLS.
490 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
491 TILEPRO_OPC_LW_TLS_SN.
492
42164a71
L		 4932012-02-08 H.J. Lu <hongjiu.lu@intel.com>
494
495 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
496 (XRELEASE_PREFIX_OPCODE): Likewise.
497
432233b3 4982011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 499 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 500
501 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
502 (INSN_OCTEON2): New macro.
503 (CPU_OCTEON2): New macro.
504 (OPCODE_IS_MEMBER): Add Octeon2.
505
dd6a37e7
AP		 5062011-11-29 Andrew Pinski <apinski@cavium.com>
507
508 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
509 (INSN_OCTEONP): New macro.
510 (CPU_OCTEONP): New macro.
511 (OPCODE_IS_MEMBER): Add Octeon+.
512 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
513
99c513f6
DD		 5142011-11-01 DJ Delorie <dj@redhat.com>
515
516 * rl78.h: New file.
517
26f85d7a
MR		 5182011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
519
520 * mips.h: Fix a typo in description.
521
9e8c70f9
DM		 5222011-09-21 David S. Miller <davem@davemloft.net>
523
524 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
525 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
526 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
527 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
528
dec0624d 5292011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 530 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 531
532 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
533 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
534 (INSN_ASE_MASK): Add the MCU bit.
535 (INSN_MCU): New macro.
536 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
537 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
538
2b0c8b40
MR		 5392011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
540
541 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
542 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
543 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
544 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
545 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
546 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
547 (INSN2_READ_GPR_MMN): Likewise.
548 (INSN2_READ_FPR_D): Change the bit used.
549 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
550 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
551 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
552 (INSN2_COND_BRANCH): Likewise.
553 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
554 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
555 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
556 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
557 (INSN2_MOD_GPR_MN): Likewise.
558
ea783ef3
DM		 5592011-08-05 David S. Miller <davem@davemloft.net>
560
561 * sparc.h: Document new format codes '4', '5', and '('.
562 (OPF_LOW4, RS3): New macros.
563
7c176fa8
MR		 5642011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
565
566 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
567 order of flags documented.
568
2309ddf2
MR		 5692011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
570
571 * mips.h: Clarify the description of microMIPS instruction
572 manipulation macros.
573 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
574
df58fc94 5752011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 576 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 577
578 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
579 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
580 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
581 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
582 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
583 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
584 (OP_MASK_RS3, OP_SH_RS3): Likewise.
585 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
586 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
587 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
588 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
589 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
590 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
591 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
592 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
593 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
594 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
595 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
596 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
597 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
598 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
599 (INSN_WRITE_GPR_S): New macro.
600 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
601 (INSN2_READ_FPR_D): Likewise.
602 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
603 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
604 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
605 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
606 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
607 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
608 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
609 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
610 (CPU_MICROMIPS): New macro.
611 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
612 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
613 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
614 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
615 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
616 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
617 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
618 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
619 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
620 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
621 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
622 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
623 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
624 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
625 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
626 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
627 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
628 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
629 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
630 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
631 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
632 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
633 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
634 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
635 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
636 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
637 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
638 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
639 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
640 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
641 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
642 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
643 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
644 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
645 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
646 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
647 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
648 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
649 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
650 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
651 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
652 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
653 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
654 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
655 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
656 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
657 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
658 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
659 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
660 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
661 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
662 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
663 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
664 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
665 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
666 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
667 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
668 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
669 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
670 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
671 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
672 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
673 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
674 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
675 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
676 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
677 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
678 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
679 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
680 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
681 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
682 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
683 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
684 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
685 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
686 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
687 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
688 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
689 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
690 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
691 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
692 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
693 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
694 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
695 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
696 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
697 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
698 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
699 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
700 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
701 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
702 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
703 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
704 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
705 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
706 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
707 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
708 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
709 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
710 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
711 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
712 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
713 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
714 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
715 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
716 (micromips_opcodes): New declaration.
717 (bfd_micromips_num_opcodes): Likewise.
718
bcd530a7
RS		 7192011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
720
721 * mips.h (INSN_TRAP): Rename to...
722 (INSN_NO_DELAY_SLOT): ... this.
723 (INSN_SYNC): Remove macro.
724
2dad5a91
EW		 7252011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
726
727 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
728 a duplicate of AVR_ISA_SPM.
729
5d73b1f1
NC		 7302011-07-01 Nick Clifton <nickc@redhat.com>
731
732 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
733
ef26d60e
MF		 7342011-06-18 Robin Getz <robin.getz@analog.com>
735
736 * bfin.h (is_macmod_signed): New func
737
8fb8dca7
MF		 7382011-06-18 Mike Frysinger <vapier@gentoo.org>
739
740 * bfin.h (is_macmod_pmove): Add missing space before func args.
741 (is_macmod_hmove): Likewise.
742
aa137e4d
NC		 7432011-06-13 Walter Lee <walt@tilera.com>
744
745 * tilegx.h: New file.
746 * tilepro.h: New file.
747
3b2f0793
PB		 7482011-05-31 Paul Brook <paul@codesourcery.com>
749
aa137e4d
NC		 750 * arm.h (ARM_ARCH_V7R_IDIV): Define.
751
7522011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
753
754 * s390.h: Replace S390_OPERAND_REG_EVEN with
755 S390_OPERAND_REG_PAIR.
756
7572011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
758
759 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 760
ac7f631b
NC		 7612011-04-18 Julian Brown <julian@codesourcery.com>
762
763 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
764
84701018
NC		 7652011-04-11 Dan McDonald <dan@wellkeeper.com>
766
767 PR gas/12296
768 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
769
8cc66334
EW		 7702011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
771
772 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
773 New instruction set flags.
774 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
775
3eebd5eb
MR		 7762011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
777
778 * mips.h (M_PREF_AB): New enum value.
779
26bb3ddd
MF		 7802011-02-12 Mike Frysinger <vapier@gentoo.org>
781
89c0d58c
MR		 782 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
783 M_IU): Define.
784 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 785
dd76fcb8
MF		 7862011-02-11 Mike Frysinger <vapier@gentoo.org>
787
788 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
789
98d23bef
BS		 7902011-02-04 Bernd Schmidt <bernds@codesourcery.com>
791
792 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
793 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
794
3c853d93
DA		 7952010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
796
797 PR gas/11395
798 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
799 "bb" entries.
800
79676006
DA		 8012010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
802
803 PR gas/11395
804 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
805
1bec78e9
RS		 8062010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
807
808 * mips.h: Update commentary after last commit.
809
98675402
RS		 8102010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
811
812 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
813 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
814 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
815
aa137e4d
NC		 8162010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
817
818 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
819
435b94a4
RS		 8202010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
821
822 * mips.h: Fix previous commit.
823
d051516a
NC		 8242010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
825
826 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
827 (INSN_LOONGSON_3A): Clear bit 31.
828
251665fc
MGD		 8292010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
830
831 PR gas/12198
832 * arm.h (ARM_AEXT_V6M_ONLY): New define.
833 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
834 (ARM_ARCH_V6M_ONLY): New define.
835
fd503541
NC		 8362010-11-11 Mingming Sun <mingm.sun@gmail.com>
837
838 * mips.h (INSN_LOONGSON_3A): Defined.
839 (CPU_LOONGSON_3A): Defined.
840 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
841
4469d2be
AM		 8422010-10-09 Matt Rice <ratmice@gmail.com>
843
844 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
845 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
846
90ec0d68
MGD		 8472010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
848
849 * arm.h (ARM_EXT_VIRT): New define.
850 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
851 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
852 Extensions.
853
eea54501 8542010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 855
eea54501
MGD		 856 * arm.h (ARM_AEXT_ADIV): New define.
857 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
858
b2a5fbdc
MGD		 8592010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
860
861 * arm.h (ARM_EXT_OS): New define.
862 (ARM_AEXT_V6SM): Likewise.
863 (ARM_ARCH_V6SM): Likewise.
864
60e5ef9f
MGD		 8652010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
866
867 * arm.h (ARM_EXT_MP): Add.
868 (ARM_ARCH_V7A_MP): Likewise.
869
73a63ccf
MF		 8702010-09-22 Mike Frysinger <vapier@gentoo.org>
871
872 * bfin.h: Declare pseudoChr structs/defines.
873
ee99860a
MF		 8742010-09-21 Mike Frysinger <vapier@gentoo.org>
875
876 * bfin.h: Strip trailing whitespace.
877
f9c7014e
DD		 8782010-07-29 DJ Delorie <dj@redhat.com>
879
880 * rx.h (RX_Operand_Type): Add TwoReg.
881 (RX_Opcode_ID): Remove ediv and ediv2.
882
93378652
DD		 8832010-07-27 DJ Delorie <dj@redhat.com>
884
885 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
886
1cd986c5
NC		 8872010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
888 Ina Pandit <ina.pandit@kpitcummins.com>
889
890 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
891 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
892 PROCESSOR_V850E2_ALL.
893 Remove PROCESSOR_V850EA support.
894 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
895 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
896 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
897 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
898 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
899 V850_OPERAND_PERCENT.
900 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
901 V850_NOT_R0.
902 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
903 and V850E_PUSH_POP
904
9a2c7088
MR		 9052010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
906
907 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
908 (MIPS16_INSN_BRANCH): Rename to...
909 (MIPS16_INSN_COND_BRANCH): ... this.
910
bdc70b4a
AM		 9112010-07-03 Alan Modra <amodra@gmail.com>
912
913 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
914 Renumber other PPC_OPCODE defines.
915
f2bae120
AM		 9162010-07-03 Alan Modra <amodra@gmail.com>
917
918 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
919
360cfc9c
AM		 9202010-06-29 Alan Modra <amodra@gmail.com>
921
922 * maxq.h: Delete file.
923
e01d869a
AM		 9242010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
925
926 * ppc.h (PPC_OPCODE_E500): Define.
927
f79e2745
CM		 9282010-05-26 Catherine Moore <clm@codesourcery.com>
929
930 * opcode/mips.h (INSN_MIPS16): Remove.
931
2462afa1
JM		 9322010-04-21 Joseph Myers <joseph@codesourcery.com>
933
934 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
935
e4e42b45
NC		 9362010-04-15 Nick Clifton <nickc@redhat.com>
937
938 * alpha.h: Update copyright notice to use GPLv3.
939 * arc.h: Likewise.
940 * arm.h: Likewise.
941 * avr.h: Likewise.
942 * bfin.h: Likewise.
943 * cgen.h: Likewise.
944 * convex.h: Likewise.
945 * cr16.h: Likewise.
946 * cris.h: Likewise.
947 * crx.h: Likewise.
948 * d10v.h: Likewise.
949 * d30v.h: Likewise.
950 * dlx.h: Likewise.
951 * h8300.h: Likewise.
952 * hppa.h: Likewise.
953 * i370.h: Likewise.
954 * i386.h: Likewise.
955 * i860.h: Likewise.
956 * i960.h: Likewise.
957 * ia64.h: Likewise.
958 * m68hc11.h: Likewise.
959 * m68k.h: Likewise.
960 * m88k.h: Likewise.
961 * maxq.h: Likewise.
962 * mips.h: Likewise.
963 * mmix.h: Likewise.
964 * mn10200.h: Likewise.
965 * mn10300.h: Likewise.
966 * msp430.h: Likewise.
967 * np1.h: Likewise.
968 * ns32k.h: Likewise.
969 * or32.h: Likewise.
970 * pdp11.h: Likewise.
971 * pj.h: Likewise.
972 * pn.h: Likewise.
973 * ppc.h: Likewise.
974 * pyr.h: Likewise.
975 * rx.h: Likewise.
976 * s390.h: Likewise.
977 * score-datadep.h: Likewise.
978 * score-inst.h: Likewise.
979 * sparc.h: Likewise.
980 * spu-insns.h: Likewise.
981 * spu.h: Likewise.
982 * tic30.h: Likewise.
983 * tic4x.h: Likewise.
984 * tic54x.h: Likewise.
985 * tic80.h: Likewise.
986 * v850.h: Likewise.
987 * vax.h: Likewise.
988
40b36596
JM		 9892010-03-25 Joseph Myers <joseph@codesourcery.com>
990
991 * tic6x-control-registers.h, tic6x-insn-formats.h,
992 tic6x-opcode-table.h, tic6x.h: New.
993
c67a084a
NC		 9942010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
995
996 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
997
466ef64f
AM		 9982010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
999
1000 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1001
1319d143
L		 10022010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1003
1004 * ia64.h (ia64_find_opcode): Remove argument name.
1005 (ia64_find_next_opcode): Likewise.
1006 (ia64_dis_opcode): Likewise.
1007 (ia64_free_opcode): Likewise.
1008 (ia64_find_dependency): Likewise.
1009
1fbb9298
DE		 10102009-11-22 Doug Evans <dje@sebabeach.org>
1011
1012 * cgen.h: Include bfd_stdint.h.
1013 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1014
ada65aa3
PB		 10152009-11-18 Paul Brook <paul@codesourcery.com>
1016
1017 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1018
9e3c6df6
PB		 10192009-11-17 Paul Brook <paul@codesourcery.com>
1020 Daniel Jacobowitz <dan@codesourcery.com>
1021
1022 * arm.h (ARM_EXT_V6_DSP): Define.
1023 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1024 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1025
0d734b5d
DD		 10262009-11-04 DJ Delorie <dj@redhat.com>
1027
1028 * rx.h (rx_decode_opcode) (mvtipl): Add.
1029 (mvtcp, mvfcp, opecp): Remove.
1030
62f3b8c8
PB		 10312009-11-02 Paul Brook <paul@codesourcery.com>
1032
1033 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1034 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1035 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1036 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1037 FPU_ARCH_NEON_VFP_V4): Define.
1038
ac1e9eca
DE		 10392009-10-23 Doug Evans <dje@sebabeach.org>
1040
1041 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1042 * cgen.h: Update. Improve multi-inclusion macro name.
1043
9fe54b1c
PB		 10442009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1045
1046 * ppc.h (PPC_OPCODE_476): Define.
1047
634b50f2
PB		 10482009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1049
1050 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1051
c7927a3c
NC		 10522009-09-29 DJ Delorie <dj@redhat.com>
1053
1054 * rx.h: New file.
1055
b961e85b
AM		 10562009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1057
1058 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1059
e0d602ec
BE		 10602009-09-21 Ben Elliston <bje@au.ibm.com>
1061
1062 * ppc.h (PPC_OPCODE_PPCA2): New.
1063
96d56e9f
NC		 10642009-09-05 Martin Thuresson <martin@mtme.org>
1065
1066 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1067
d3ce72d0
NC		 10682009-08-29 Martin Thuresson <martin@mtme.org>
1069
1070 * tic30.h (template): Rename type template to
1071 insn_template. Updated code to use new name.
1072 * tic54x.h (template): Rename type template to
1073 insn_template.
1074
824b28db
NH		 10752009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1076
1077 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1078
f865a31d
AG		 10792009-06-11 Anthony Green <green@moxielogic.com>
1080
1081 * moxie.h (MOXIE_F3_PCREL): Define.
1082 (moxie_form3_opc_info): Grow.
1083
0e7c7f11
AG		 10842009-06-06 Anthony Green <green@moxielogic.com>
1085
1086 * moxie.h (MOXIE_F1_M): Define.
1087
20135e4c
NC		 10882009-04-15 Anthony Green <green@moxielogic.com>
1089
1090 * moxie.h: Created.
1091
bcb012d3
DD		 10922009-04-06 DJ Delorie <dj@redhat.com>
1093
1094 * h8300.h: Add relaxation attributes to MOVA opcodes.
1095
69fe9ce5
AM		 10962009-03-10 Alan Modra <amodra@bigpond.net.au>
1097
1098 * ppc.h (ppc_parse_cpu): Declare.
1099
c3b7224a
NC		 11002009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1101
1102 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1103 and _IMM11 for mbitclr and mbitset.
1104 * score-datadep.h: Update dependency information.
1105
066be9f7
PB		 11062009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1107
1108 * ppc.h (PPC_OPCODE_POWER7): New.
1109
fedc618e
DE		 11102009-02-06 Doug Evans <dje@google.com>
1111
1112 * i386.h: Add comment regarding sse* insns and prefixes.
1113
52b6b6b9
JM		 11142009-02-03 Sandip Matte <sandip@rmicorp.com>
1115
1116 * mips.h (INSN_XLR): Define.
1117 (INSN_CHIP_MASK): Update.
1118 (CPU_XLR): Define.
1119 (OPCODE_IS_MEMBER): Update.
1120 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1121
35669430
DE		 11222009-01-28 Doug Evans <dje@google.com>
1123
1124 * opcode/i386.h: Add multiple inclusion protection.
1125 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1126 (EDI_REG_NUM): New macros.
1127 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1128 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1129 (REX_PREFIX_P): New macro.
35669430 1130
1cb0a767
PB		 11312009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1132
1133 * ppc.h (struct powerpc_opcode): New field "deprecated".
1134 (PPC_OPCODE_NOPOWER4): Delete.
1135
3aa3176b
TS		 11362008-11-28 Joshua Kinard <kumba@gentoo.org>
1137
1138 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1139 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1140
8e79c3df
CM		 11412008-11-18 Catherine Moore <clm@codesourcery.com>
1142
1143 * arm.h (FPU_NEON_FP16): New.
1144 (FPU_ARCH_NEON_FP16): New.
1145
de9a3e51
CF		 11462008-11-06 Chao-ying Fu <fu@mips.com>
1147
1148 * mips.h: Doucument '1' for 5-bit sync type.
1149
1ca35711
L		 11502008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1151
1152 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1153 IA64_RS_CR.
1154
9b4e5766
PB		 11552008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1156
1157 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1158
081ba1b3
AM		 11592008-07-30 Michael J. Eager <eager@eagercon.com>
1160
1161 * ppc.h (PPC_OPCODE_405): Define.
1162 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1163
fa452fa6
PB		 11642008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1165
1166 * ppc.h (ppc_cpu_t): New typedef.
1167 (struct powerpc_opcode <flags>): Use it.
1168 (struct powerpc_operand <insert, extract>): Likewise.
1169 (struct powerpc_macro <flags>): Likewise.
1170
bb35fb24
NC		 11712008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1172
1173 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1174 Update comment before MIPS16 field descriptors to mention MIPS16.
1175 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1176 BBIT.
1177 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1178 New bit masks and shift counts for cins and exts.
1179
dd3cbb7e
NC		 1180 * mips.h: Document new field descriptors +Q.
1181 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1182
d0799671
AN		 11832008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1184
9aff4b7a 1185 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1186 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1187
19a6653c
AM		 11882008-04-14 Edmar Wienskoski <edmar@freescale.com>
1189
1190 * ppc.h: (PPC_OPCODE_E500MC): New.
1191
c0f3af97
L		 11922008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1193
1194 * i386.h (MAX_OPERANDS): Set to 5.
1195 (MAX_MNEM_SIZE): Changed to 20.
1196
e210c36b
NC		 11972008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1198
1199 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1200
b1cc4aeb
PB		 12012008-03-09 Paul Brook <paul@codesourcery.com>
1202
1203 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1204
7e806470
PB		 12052008-03-04 Paul Brook <paul@codesourcery.com>
1206
1207 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1208 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1209 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1210
7b2185f9 12112008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1212 Nick Clifton <nickc@redhat.com>
1213
1214 PR 3134
1215 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1216 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1217 set.
af7329f0 1218
796d5313
NC		 12192008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1220
1221 * cr16.h (cr16_num_optab): Declared.
1222
d669d37f
NC		 12232008-02-14 Hakan Ardo <hakan@debian.org>
1224
1225 PR gas/2626
1226 * avr.h (AVR_ISA_2xxe): Define.
1227
e6429699
AN		 12282008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1229
1230 * mips.h: Update copyright.
1231 (INSN_CHIP_MASK): New macro.
1232 (INSN_OCTEON): New macro.
1233 (CPU_OCTEON): New macro.
1234 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1235
e210c36b
NC		 12362008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1237
1238 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1239
12402008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1241
1242 * avr.h (AVR_ISA_USB162): Add new opcode set.
1243 (AVR_ISA_AVR3): Likewise.
1244
350cc38d
MS		 12452007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1246
1247 * mips.h (INSN_LOONGSON_2E): New.
1248 (INSN_LOONGSON_2F): New.
1249 (CPU_LOONGSON_2E): New.
1250 (CPU_LOONGSON_2F): New.
1251 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1252
56950294
MS		 12532007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1254
1255 * mips.h (INSN_ISA*): Redefine certain values as an
1256 enumeration. Update comments.
1257 (mips_isa_table): New.
1258 (ISA_MIPS*): Redefine to match enumeration.
1259 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1260 values.
1261
c3d65c1c
BE		 12622007-08-08 Ben Elliston <bje@au.ibm.com>
1263
1264 * ppc.h (PPC_OPCODE_PPCPS): New.
1265
0fdaa005
L		 12662007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1267
1268 * m68k.h: Document j K & E.
1269
12702007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1271
1272 * cr16.h: New file for CR16 target.
1273
3896c469
AM		 12742007-05-02 Alan Modra <amodra@bigpond.net.au>
1275
1276 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1277
9a2e615a
NS		 12782007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1279
1280 * m68k.h (mcfisa_c): New.
1281 (mcfusp, mcf_mask): Adjust.
1282
b84bf58a
AM		 12832007-04-20 Alan Modra <amodra@bigpond.net.au>
1284
1285 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1286 (num_powerpc_operands): Declare.
1287 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1288 (PPC_OPERAND_PLUS1): Define.
1289
831480e9 12902007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1291
1292 * i386.h (REX_MODE64): Renamed to ...
1293 (REX_W): This.
1294 (REX_EXTX): Renamed to ...
1295 (REX_R): This.
1296 (REX_EXTY): Renamed to ...
1297 (REX_X): This.
1298 (REX_EXTZ): Renamed to ...
1299 (REX_B): This.
1300
0b1cf022
L		 13012007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1302
1303 * i386.h: Add entries from config/tc-i386.h and move tables
1304 to opcodes/i386-opc.h.
1305
d796c0ad
L		 13062007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1307
1308 * i386.h (FloatDR): Removed.
1309 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1310
30ac7323
AM		 13112007-03-01 Alan Modra <amodra@bigpond.net.au>
1312
1313 * spu-insns.h: Add soma double-float insns.
1314
8b082fb1 13152007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1316 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1317
1318 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1319 (INSN_DSPR2): Add flag for DSP R2 instructions.
1320 (M_BALIGN): New macro.
1321
4eed87de
AM		 13222007-02-14 Alan Modra <amodra@bigpond.net.au>
1323
1324 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1325 and Seg3ShortFrom with Shortform.
1326
fda592e8
L		 13272007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1328
1329 PR gas/4027
1330 * i386.h (i386_optab): Put the real "test" before the pseudo
1331 one.
1332
3bdcfdf4
KH		 13332007-01-08 Kazu Hirata <kazu@codesourcery.com>
1334
1335 * m68k.h (m68010up): OR fido_a.
1336
9840d27e
KH		 13372006-12-25 Kazu Hirata <kazu@codesourcery.com>
1338
1339 * m68k.h (fido_a): New.
1340
c629cdac
KH		 13412006-12-24 Kazu Hirata <kazu@codesourcery.com>
1342
1343 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1344 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1345 values.
1346
b7d9ef37
L		 13472006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1348
1349 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1350
b138abaa
NC		 13512006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1352
1353 * score-inst.h (enum score_insn_type): Add Insn_internal.
1354
e9f53129
AM		 13552006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1356 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1357 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1358 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1359 Alan Modra <amodra@bigpond.net.au>
1360
1361 * spu-insns.h: New file.
1362 * spu.h: New file.
1363
ede602d7
AM		 13642006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1365
1366 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1367
7918206c
MM		 13682006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1369
e4e42b45 1370 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1371 in amdfam10 architecture.
1372
ef05d495
L		 13732006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1374
1375 * i386.h: Replace CpuMNI with CpuSSSE3.
1376
2d447fca 13772006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1378 Joseph Myers <joseph@codesourcery.com>
1379 Ian Lance Taylor <ian@wasabisystems.com>
1380 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1381
1382 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1383
1c0d3aa6
NC		 13842006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1385
1386 * score-datadep.h: New file.
1387 * score-inst.h: New file.
1388
c2f0420e
L		 13892006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1390
1391 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1392 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1393 movdq2q and movq2dq.
1394
050dfa73
MM		 13952006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1396 Michael Meissner <michael.meissner@amd.com>
1397
1398 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1399
15965411
L		 14002006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1401
1402 * i386.h (i386_optab): Add "nop" with memory reference.
1403
46e883c5
L		 14042006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1405
1406 * i386.h (i386_optab): Update comment for 64bit NOP.
1407
9622b051
AM		 14082006-06-06 Ben Elliston <bje@au.ibm.com>
1409 Anton Blanchard <anton@samba.org>
1410
1411 * ppc.h (PPC_OPCODE_POWER6): Define.
1412 Adjust whitespace.
1413
a9e24354
TS		 14142006-06-05 Thiemo Seufer <ths@mips.com>
1415
e4e42b45 1416 * mips.h: Improve description of MT flags.
a9e24354 1417
a596001e
RS		 14182006-05-25 Richard Sandiford <richard@codesourcery.com>
1419
1420 * m68k.h (mcf_mask): Define.
1421
d43b4baf 14222006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1423 David Ung <davidu@mips.com>
d43b4baf
TS		 1424
1425 * mips.h (enum): Add macro M_CACHE_AB.
1426
39a7806d 14272006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1428 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1429 David Ung <davidu@mips.com>
1430
1431 * mips.h: Add INSN_SMARTMIPS define.
1432
9bcd4f99 14332006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1434 David Ung <davidu@mips.com>
9bcd4f99
TS		 1435
1436 * mips.h: Defines udi bits and masks. Add description of
1437 characters which may appear in the args field of udi
1438 instructions.
1439
ef0ee844
TS		 14402006-04-26 Thiemo Seufer <ths@networkno.de>
1441
1442 * mips.h: Improve comments describing the bitfield instruction
1443 fields.
1444
f7675147
L		 14452006-04-26 Julian Brown <julian@codesourcery.com>
1446
1447 * arm.h (FPU_VFP_EXT_V3): Define constant.
1448 (FPU_NEON_EXT_V1): Likewise.
1449 (FPU_VFP_HARD): Update.
1450 (FPU_VFP_V3): Define macro.
1451 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1452
ef0ee844 14532006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1454
1455 * avr.h (AVR_ISA_PWMx): New.
1456
2da12c60
NS		 14572006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1458
1459 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1460 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1461 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1462 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1463 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1464
0715c387
PB		 14652006-03-10 Paul Brook <paul@codesourcery.com>
1466
1467 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1468
34bdd094
DA		 14692006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1470
1471 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1472 first. Correct mask of bb "B" opcode.
1473
331d2d0d
L		 14742006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1475
1476 * i386.h (i386_optab): Support Intel Merom New Instructions.
1477
62b3e311
PB		 14782006-02-24 Paul Brook <paul@codesourcery.com>
1479
1480 * arm.h: Add V7 feature bits.
1481
59cf82fe
L		 14822006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1483
1484 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1485
e74cfd16
PB		 14862006-01-31 Paul Brook <paul@codesourcery.com>
1487 Richard Earnshaw <rearnsha@arm.com>
1488
1489 * arm.h: Use ARM_CPU_FEATURE.
1490 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1491 (arm_feature_set): Change to a structure.
1492 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1493 ARM_FEATURE): New macros.
1494
5b3f8a92
HPN		 14952005-12-07 Hans-Peter Nilsson <hp@axis.com>
1496
1497 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1498 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1499 (ADD_PC_INCR_OPCODE): Don't define.
1500
cb712a9e
L		 15012005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1502
1503 PR gas/1874
1504 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1505
0499d65b
TS		 15062005-11-14 David Ung <davidu@mips.com>
1507
1508 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1509 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1510 save/restore encoding of the args field.
1511
ea5ca089
DB		 15122005-10-28 Dave Brolley <brolley@redhat.com>
1513
1514 Contribute the following changes:
1515 2005-02-16 Dave Brolley <brolley@redhat.com>
1516
1517 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1518 cgen_isa_mask_* to cgen_bitset_*.
1519 * cgen.h: Likewise.
1520
16175d96
DB		 1521 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1522
1523 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1524 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1525 (CGEN_CPU_TABLE): Make isas a ponter.
1526
1527 2003-09-29 Dave Brolley <brolley@redhat.com>
1528
1529 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1530 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1531 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1532
1533 2002-12-13 Dave Brolley <brolley@redhat.com>
1534
1535 * cgen.h (symcat.h): #include it.
1536 (cgen-bitset.h): #include it.
1537 (CGEN_ATTR_VALUE_TYPE): Now a union.
1538 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1539 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1540 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1541 * cgen-bitset.h: New file.
1542
3c9b82ba
NC		 15432005-09-30 Catherine Moore <clm@cm00re.com>
1544
1545 * bfin.h: New file.
1546
6a2375c6
JB		 15472005-10-24 Jan Beulich <jbeulich@novell.com>
1548
1549 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1550 indirect operands.
1551
c06a12f8
DA		 15522005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1553
1554 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1555 Add FLAG_STRICT to pa10 ftest opcode.
1556
4d443107
DA		 15572005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1558
1559 * hppa.h (pa_opcodes): Remove lha entries.
1560
f0a3b40f
DA		 15612005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1562
1563 * hppa.h (FLAG_STRICT): Revise comment.
1564 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1565 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1566 entries for "fdc".
1567
e210c36b
NC		 15682005-09-30 Catherine Moore <clm@cm00re.com>
1569
1570 * bfin.h: New file.
1571
1b7e1362
DA		 15722005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1573
1574 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1575
089b39de
CF		 15762005-09-06 Chao-ying Fu <fu@mips.com>
1577
1578 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1579 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1580 define.
1581 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1582 (INSN_ASE_MASK): Update to include INSN_MT.
1583 (INSN_MT): New define for MT ASE.
1584
93c34b9b
CF		 15852005-08-25 Chao-ying Fu <fu@mips.com>
1586
1587 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1588 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1589 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1590 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1591 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1592 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1593 instructions.
1594 (INSN_DSP): New define for DSP ASE.
1595
848cf006
AM		 15962005-08-18 Alan Modra <amodra@bigpond.net.au>
1597
1598 * a29k.h: Delete.
1599
36ae0db3
DJ		 16002005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1601
1602 * ppc.h (PPC_OPCODE_E300): Define.
1603
8c929562
MS		 16042005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1605
1606 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1607
f7b8cccc
DA		 16082005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1609
1610 PR gas/336
1611 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1612 and pitlb.
1613
8b5328ac
JB		 16142005-07-27 Jan Beulich <jbeulich@novell.com>
1615
1616 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1617 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1618 Add movq-s as 64-bit variants of movd-s.
1619
f417d200
DA		 16202005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1621
18b3bdfc
DA		 1622 * hppa.h: Fix punctuation in comment.
1623
f417d200
DA		 1624 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1625 implicit space-register addressing. Set space-register bits on opcodes
1626 using implicit space-register addressing. Add various missing pa20
1627 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1628 space-register addressing. Use "fE" instead of "fe" in various
1629 fstw opcodes.
1630
9a145ce6
JB		 16312005-07-18 Jan Beulich <jbeulich@novell.com>
1632
1633 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1634
90700ea2
L		 16352007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1636
1637 * i386.h (i386_optab): Support Intel VMX Instructions.
1638
48f130a8
DA		 16392005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1640
1641 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1642
30123838
JB		 16432005-07-05 Jan Beulich <jbeulich@novell.com>
1644
1645 * i386.h (i386_optab): Add new insns.
1646
47b0e7ad
NC		 16472005-07-01 Nick Clifton <nickc@redhat.com>
1648
1649 * sparc.h: Add typedefs to structure declarations.
1650
b300c311
L		 16512005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1652
1653 PR 1013
1654 * i386.h (i386_optab): Update comments for 64bit addressing on
1655 mov. Allow 64bit addressing for mov and movq.
1656
2db495be
DA		 16572005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1658
1659 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1660 respectively, in various floating-point load and store patterns.
1661
caa05036
DA		 16622005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1663
1664 * hppa.h (FLAG_STRICT): Correct comment.
1665 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1666 PA 2.0 mneumonics when equivalent. Entries with cache control
1667 completers now require PA 1.1. Adjust whitespace.
1668
f4411256
AM		 16692005-05-19 Anton Blanchard <anton@samba.org>
1670
1671 * ppc.h (PPC_OPCODE_POWER5): Define.
1672
e172dbf8
NC		 16732005-05-10 Nick Clifton <nickc@redhat.com>
1674
1675 * Update the address and phone number of the FSF organization in
1676 the GPL notices in the following files:
1677 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1678 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1679 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1680 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1681 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1682 tic54x.h, tic80.h, v850.h, vax.h
1683
e44823cf
JB		 16842005-05-09 Jan Beulich <jbeulich@novell.com>
1685
1686 * i386.h (i386_optab): Add ht and hnt.
1687
791fe849
MK		 16882005-04-18 Mark Kettenis <kettenis@gnu.org>
1689
1690 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1691 Add xcrypt-ctr. Provide aliases without hyphens.
1692
faa7ef87
L		 16932005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1694
a63027e5
L		 1695 Moved from ../ChangeLog
1696
faa7ef87
L		 1697 2005-04-12 Paul Brook <paul@codesourcery.com>
1698 * m88k.h: Rename psr macros to avoid conflicts.
1699
1700 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1701 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1702 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1703 and ARM_ARCH_V6ZKT2.
1704
1705 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1706 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1707 Remove redundant instruction types.
1708 (struct argument): X_op - new field.
1709 (struct cst4_entry): Remove.
1710 (no_op_insn): Declare.
1711
1712 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1713 * crx.h (enum argtype): Rename types, remove unused types.
1714
1715 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1716 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1717 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1718 (enum operand_type): Rearrange operands, edit comments.
1719 replace us<N> with ui<N> for unsigned immediate.
1720 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1721 displacements (respectively).
1722 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1723 (instruction type): Add NO_TYPE_INS.
1724 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1725 (operand_entry): New field - 'flags'.
1726 (operand flags): New.
1727
1728 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1729 * crx.h (operand_type): Remove redundant types i3, i4,
1730 i5, i8, i12.
1731 Add new unsigned immediate types us3, us4, us5, us16.
1732
bc4bd9ab
MK		 17332005-04-12 Mark Kettenis <kettenis@gnu.org>
1734
1735 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1736 adjust them accordingly.
1737
373ff435
JB		 17382005-04-01 Jan Beulich <jbeulich@novell.com>
1739
1740 * i386.h (i386_optab): Add rdtscp.
1741
4cc91dba
L		 17422005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1743
1744 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1745 between memory and segment register. Allow movq for moving between
1746 general-purpose register and segment register.
4cc91dba 1747
9ae09ff9
JB		 17482005-02-09 Jan Beulich <jbeulich@novell.com>
1749
1750 PR gas/707
1751 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1752 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1753 fnstsw.
1754
638e7a64
NS		 17552006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1756
1757 * m68k.h (m68008, m68ec030, m68882): Remove.
1758 (m68k_mask): New.
1759 (cpu_m68k, cpu_cf): New.
1760 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1761 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1762
90219bd0
AO		 17632005-01-25 Alexandre Oliva <aoliva@redhat.com>
1764
1765 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1766 * cgen.h (enum cgen_parse_operand_type): Add
1767 CGEN_PARSE_OPERAND_SYMBOLIC.
1768
239cb185
FF		 17692005-01-21 Fred Fish <fnf@specifixinc.com>
1770
1771 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1772 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1773 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1774
dc9a9f39
FF		 17752005-01-19 Fred Fish <fnf@specifixinc.com>
1776
1777 * mips.h (struct mips_opcode): Add new pinfo2 member.
1778 (INSN_ALIAS): New define for opcode table entries that are
1779 specific instances of another entry, such as 'move' for an 'or'
1780 with a zero operand.
1781 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1782 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1783
98e7aba8
ILT		 17842004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1785
1786 * mips.h (CPU_RM9000): Define.
1787 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1788
37edbb65
JB		 17892004-11-25 Jan Beulich <jbeulich@novell.com>
1790
1791 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1792 to/from test registers are illegal in 64-bit mode. Add missing
1793 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1794 (previously one had to explicitly encode a rex64 prefix). Re-enable
1795 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1796 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1797
17982004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1799
1800 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1801 available only with SSE2. Change the MMX additions introduced by SSE
1802 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1803 instructions by their now designated identifier (since combining i686
1804 and 3DNow! does not really imply 3DNow!A).
1805
f5c7edf4
AM		 18062004-11-19 Alan Modra <amodra@bigpond.net.au>
1807
1808 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1809 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1810
7499d566
NC		 18112004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1812 Vineet Sharma <vineets@noida.hcltech.com>
1813
1814 * maxq.h: New file: Disassembly information for the maxq port.
1815
bcb9eebe
L		 18162004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1817
1818 * i386.h (i386_optab): Put back "movzb".
1819
94bb3d38
HPN		 18202004-11-04 Hans-Peter Nilsson <hp@axis.com>
1821
1822 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1823 comments. Remove member cris_ver_sim. Add members
1824 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1825 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1826 (struct cris_support_reg, struct cris_cond15): New types.
1827 (cris_conds15): Declare.
1828 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1829 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1830 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1831 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1832 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1833 SIZE_FIELD_UNSIGNED.
1834
37edbb65 18352004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1836
1837 * i386.h (sldx_Suf): Remove.
1838 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1839 (q_FP): Define, implying no REX64.
1840 (x_FP, sl_FP): Imply FloatMF.
1841 (i386_optab): Split reg and mem forms of moving from segment registers
1842 so that the memory forms can ignore the 16-/32-bit operand size
1843 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1844 all non-floating-point instructions. Unite 32- and 64-bit forms of
1845 movsx, movzx, and movd. Adjust floating point operations for the above
1846 changes to the *FP macros. Add DefaultSize to floating point control
1847 insns operating on larger memory ranges. Remove left over comments
1848 hinting at certain insns being Intel-syntax ones where the ones
1849 actually meant are already gone.
1850
48c9f030
NC		 18512004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1852
1853 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1854 instruction type.
1855
0dd132b6
NC		 18562004-09-30 Paul Brook <paul@codesourcery.com>
1857
1858 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1859 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1860
23794b24
MM		 18612004-09-11 Theodore A. Roth <troth@openavr.org>
1862
1863 * avr.h: Add support for
1864 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1865
2a309db0
AM		 18662004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1867
1868 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1869
b18c562e
NC		 18702004-08-24 Dmitry Diky <diwil@spec.ru>
1871
1872 * msp430.h (msp430_opc): Add new instructions.
1873 (msp430_rcodes): Declare new instructions.
1874 (msp430_hcodes): Likewise..
1875
45d313cd
NC		 18762004-08-13 Nick Clifton <nickc@redhat.com>
1877
1878 PR/301
1879 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1880 processors.
1881
30d1c836
ML		 18822004-08-30 Michal Ludvig <mludvig@suse.cz>
1883
1884 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1885
9a45f1c2
L		 18862004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1887
1888 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1889
543613e9
NC		 18902004-07-21 Jan Beulich <jbeulich@novell.com>
1891
1892 * i386.h: Adjust instruction descriptions to better match the
1893 specification.
1894
b781e558
RE		 18952004-07-16 Richard Earnshaw <rearnsha@arm.com>
1896
1897 * arm.h: Remove all old content. Replace with architecture defines
1898 from gas/config/tc-arm.c.
1899
8577e690
AS		 19002004-07-09 Andreas Schwab <schwab@suse.de>
1901
1902 * m68k.h: Fix comment.
1903
1fe1f39c
NC		 19042004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1905
1906 * crx.h: New file.
1907
1d9f512f
AM		 19082004-06-24 Alan Modra <amodra@bigpond.net.au>
1909
1910 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1911
be8c092b
NC		 19122004-05-24 Peter Barada <peter@the-baradas.com>
1913
1914 * m68k.h: Add 'size' to m68k_opcode.
1915
6b6e92f4
NC		 19162004-05-05 Peter Barada <peter@the-baradas.com>
1917
1918 * m68k.h: Switch from ColdFire chip name to core variant.
1919
19202004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1921
1922 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1923 descriptions for new EMAC cases.
1924 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1925 handle Motorola MAC syntax.
1926 Allow disassembly of ColdFire V4e object files.
1927
fdd12ef3
AM		 19282004-03-16 Alan Modra <amodra@bigpond.net.au>
1929
1930 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1931
3922a64c
L		 19322004-03-12 Jakub Jelinek <jakub@redhat.com>
1933
1934 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1935
1f45d988
ML		 19362004-03-12 Michal Ludvig <mludvig@suse.cz>
1937
1938 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1939
0f10071e
ML		 19402004-03-12 Michal Ludvig <mludvig@suse.cz>
1941
1942 * i386.h (i386_optab): Added xstore/xcrypt insns.
1943
3255318a
NC		 19442004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1945
1946 * h8300.h (32bit ldc/stc): Add relaxing support.
1947
ca9a79a1 19482004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1949
ca9a79a1
NC		 1950 * h8300.h (BITOP): Pass MEMRELAX flag.
1951
875a0b14
NC		 19522004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1953
1954 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1955 except for the H8S.
252b5132 1956
c9e214e5 1957For older changes see ChangeLog-9103
252b5132 1958\f
4b95cf5c 1959Copyright (C) 2004-2014 Free Software Foundation, Inc.
752937aa
NC		 1960
1961Copying and distribution of this file, with or without modification,
1962are permitted in any medium without royalty provided the copyright
1963notice and this notice are preserved.
1964
252b5132 1965Local Variables:
c9e214e5
AM		 1966mode: change-log
1967left-margin: 8
1968fill-column: 74
252b5132
RH		 1969version-control: never
1970End:
GDB Binutils - Deliverables
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