(enum reg): Rearrange registers, remove 'ccfg' and 'pc'.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
48c9f030
NC
12004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2
3 * crx.h: Add COPS_REG_INS - Coprocessor Special register
4 instruction type.
5
0dd132b6
NC
62004-09-30 Paul Brook <paul@codesourcery.com>
7
8 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
9 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
10
23794b24
MM
112004-09-11 Theodore A. Roth <troth@openavr.org>
12
13 * avr.h: Add support for
14 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
15
2a309db0
AM
162004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
17
18 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
19
b18c562e
NC
202004-08-24 Dmitry Diky <diwil@spec.ru>
21
22 * msp430.h (msp430_opc): Add new instructions.
23 (msp430_rcodes): Declare new instructions.
24 (msp430_hcodes): Likewise..
25
45d313cd
NC
262004-08-13 Nick Clifton <nickc@redhat.com>
27
28 PR/301
29 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
30 processors.
31
30d1c836
ML
322004-08-30 Michal Ludvig <mludvig@suse.cz>
33
34 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
35
9a45f1c2
L
362004-07-22 H.J. Lu <hongjiu.lu@intel.com>
37
38 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
39
543613e9
NC
402004-07-21 Jan Beulich <jbeulich@novell.com>
41
42 * i386.h: Adjust instruction descriptions to better match the
43 specification.
44
b781e558
RE
452004-07-16 Richard Earnshaw <rearnsha@arm.com>
46
47 * arm.h: Remove all old content. Replace with architecture defines
48 from gas/config/tc-arm.c.
49
8577e690
AS
502004-07-09 Andreas Schwab <schwab@suse.de>
51
52 * m68k.h: Fix comment.
53
1fe1f39c
NC
542004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
55
56 * crx.h: New file.
57
1d9f512f
AM
582004-06-24 Alan Modra <amodra@bigpond.net.au>
59
60 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
61
be8c092b
NC
622004-05-24 Peter Barada <peter@the-baradas.com>
63
64 * m68k.h: Add 'size' to m68k_opcode.
65
6b6e92f4
NC
662004-05-05 Peter Barada <peter@the-baradas.com>
67
68 * m68k.h: Switch from ColdFire chip name to core variant.
69
702004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC
71
72 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
73 descriptions for new EMAC cases.
74 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
75 handle Motorola MAC syntax.
76 Allow disassembly of ColdFire V4e object files.
77
fdd12ef3
AM
782004-03-16 Alan Modra <amodra@bigpond.net.au>
79
80 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
81
3922a64c
L
822004-03-12 Jakub Jelinek <jakub@redhat.com>
83
84 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
85
1f45d988
ML
862004-03-12 Michal Ludvig <mludvig@suse.cz>
87
88 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
89
0f10071e
ML
902004-03-12 Michal Ludvig <mludvig@suse.cz>
91
92 * i386.h (i386_optab): Added xstore/xcrypt insns.
93
3255318a
NC
942004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
95
96 * h8300.h (32bit ldc/stc): Add relaxing support.
97
ca9a79a1 982004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 99
ca9a79a1
NC
100 * h8300.h (BITOP): Pass MEMRELAX flag.
101
875a0b14
NC
1022004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
103
104 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
105 except for the H8S.
252b5132 106
c9e214e5 107For older changes see ChangeLog-9103
252b5132
RH
108\f
109Local Variables:
c9e214e5
AM
110mode: change-log
111left-margin: 8
112fill-column: 74
252b5132
RH
113version-control: never
114End:
This page took 0.229509 seconds and 4 git commands to generate.