[deliverable/binutils-gdb.git] / include / opcode / ChangeLog

2005-09-06  Chao-ying Fu  <fu@mips.com>

	* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
	OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
	define.
	Document !, $, *, &, g, +t, +T operand formats for MT instructions.
	(INSN_ASE_MASK): Update to include INSN_MT.
	(INSN_MT): New define for MT ASE.

2005-08-25  Chao-ying Fu  <fu@mips.com>

	* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
	OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
	OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
	OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
	OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
	Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
	instructions.
	(INSN_DSP): New define for DSP ASE.

2005-08-18  Alan Modra  <amodra@bigpond.net.au>

	* a29k.h: Delete.

2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>

	* ppc.h (PPC_OPCODE_E300): Define.

2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>

	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.

2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	PR gas/336
 	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	and pitlb.

2005-07-27  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	Add movq-s as 64-bit variants of movd-s.

2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h: Fix punctuation in comment.

	* hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
	implicit space-register addressing.  Set space-register bits on opcodes
	using implicit space-register addressing.  Add various missing pa20
	long-immediate opcodes.  Remove various opcodes using implicit 3-bit
	space-register addressing.  Use "fE" instead of "fe" in various
	fstw opcodes.

2005-07-18  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Operands of aam and aad are unsigned.

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel VMX Instructions.

2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.

2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add new insns.

2005-07-01  Nick Clifton  <nickc@redhat.com>

	* sparc.h: Add typedefs to structure declarations.

2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR 1013
	* i386.h (i386_optab): Update comments for 64bit addressing on
	mov. Allow 64bit addressing for mov and movq.

2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	respectively, in various floating-point load and store patterns.

2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (FLAG_STRICT): Correct comment.
	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	PA 2.0 mneumonics when equivalent.  Entries with cache control
	completers now require PA 1.1.  Adjust whitespace.

2005-05-19  Anton Blanchard  <anton@samba.org>

	* ppc.h (PPC_OPCODE_POWER5): Define.

2005-05-10  Nick Clifton  <nickc@redhat.com>

	* Update the address and phone number of the FSF organization in
	the GPL notices in the following files:
	a29k.h,	alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	tic54x.h, tic80.h, v850.h, vax.h

2005-05-09  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add ht and hnt.

2005-04-18  Mark Kettenis  <kettenis@gnu.org>

	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	Add xcrypt-ctr.  Provide aliases without hyphens.

2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>

	Moved from ../ChangeLog

	2005-04-12  Paul Brook  <paul@codesourcery.com>
	* m88k.h: Rename psr macros to avoid conflicts.

	2005-03-12  Zack Weinberg  <zack@codesourcery.com>
	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	and ARM_ARCH_V6ZKT2.

	2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	Remove redundant instruction types.
	(struct argument): X_op - new field.
	(struct cst4_entry): Remove.
	(no_op_insn): Declare.

	2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum argtype): Rename types, remove unused types.

	2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	(enum operand_type): Rearrange operands, edit comments.
	replace us<N> with ui<N> for unsigned immediate.
	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	displacements (respectively).
	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	(instruction type): Add NO_TYPE_INS.
	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	(operand_entry): New field - 'flags'.
	(operand flags): New.

	2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (operand_type): Remove redundant types i3, i4,
	i5, i8, i12.
	Add new unsigned immediate types us3, us4, us5, us16.

2005-04-12  Mark Kettenis  <kettenis@gnu.org>

	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	adjust them accordingly.

2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add rdtscp.

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Don't allow the `l' suffix for moving
	between memory and segment register. Allow movq for moving between
	general-purpose register and segment register.

2005-02-09  Jan Beulich  <jbeulich@novell.com>

	PR gas/707
	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	fnstsw.

2005-01-25  Alexandre Oliva  <aoliva@redhat.com>

	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
	* cgen.h (enum cgen_parse_operand_type): Add
	CGEN_PARSE_OPERAND_SYMBOLIC.

2005-01-21  Fred Fish  <fnf@specifixinc.com>

	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.

2005-01-19  Fred Fish  <fnf@specifixinc.com>

	* mips.h (struct mips_opcode): Add new pinfo2 member.
	(INSN_ALIAS): New define for opcode table entries that are
	specific instances of another entry, such as 'move' for an 'or'
	with a zero operand.
	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.

2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>

	* mips.h (CPU_RM9000): Define.
	(OPCODE_IS_MEMBER): Handle CPU_RM9000.

2004-11-25 Jan Beulich  <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.

2004-11-23 Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).

2004-11-19  Alan Modra  <amodra@bigpond.net.au>

	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.

2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
	    Vineet Sharma      <vineets@noida.hcltech.com>

	* maxq.h: New file: Disassembly information for the maxq port.

2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Put back "movzb".

2004-11-04  Hans-Peter Nilsson  <hp@axis.com>

	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	comments.  Remove member cris_ver_sim.  Add members
	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	(struct cris_support_reg, struct cris_cond15): New types.
	(cris_conds15): Declare.
	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	SIZE_FIELD_UNSIGNED.

2004-11-04 Jan Beulich  <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	instruction type.

2004-09-30  Paul Brook  <paul@codesourcery.com>

	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.

2004-09-11  Theodore A. Roth  <troth@openavr.org>

	* avr.h: Add support for
	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.

2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>

	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.

2004-08-24  Dmitry Diky  <diwil@spec.ru>

	* msp430.h (msp430_opc): Add new instructions.
	(msp430_rcodes): Declare new instructions.
	(msp430_hcodes): Likewise..

2004-08-13  Nick Clifton  <nickc@redhat.com>

	PR/301
	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	processors.

2004-08-30  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

2004-07-21  Jan Beulich  <jbeulich@novell.com>

	* i386.h: Adjust instruction descriptions to better match the
	specification.

2004-07-16  Richard Earnshaw  <rearnsha@arm.com>

	* arm.h: Remove all old content.  Replace with architecture defines
	from gas/config/tc-arm.c.

2004-07-09  Andreas Schwab  <schwab@suse.de>

	* m68k.h: Fix comment.

2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: New file.

2004-06-24  Alan Modra  <amodra@bigpond.net.au>

	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

2004-05-24  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add 'size' to m68k_opcode.

2004-05-05  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Switch from ColdFire chip name to core variant.

2004-04-22  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
	descriptions for new EMAC cases.
	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	handle Motorola MAC syntax.
	Allow disassembly of ColdFire V4e object files.

2004-03-16  Alan Modra  <amodra@bigpond.net.au>

	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

2004-03-12  Jakub Jelinek  <jakub@redhat.com>

	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore as an alias for xstorerng.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore/xcrypt insns.

2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (32bit ldc/stc): Add relaxing support.

2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Pass MEMRELAX flag.

2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	except for the H8S.

For older changes see ChangeLog-9103
\f
Local Variables:
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Commit	Line	Data
089b39de CF	1	2005-09-06 Chao-ying Fu <fu@mips.com>
	2
	3	* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
	4	OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
	5	define.
	6	Document !, $, *, &, g, +t, +T operand formats for MT instructions.
	7	(INSN_ASE_MASK): Update to include INSN_MT.
	8	(INSN_MT): New define for MT ASE.
	9
93c34b9b CF	10	2005-08-25 Chao-ying Fu <fu@mips.com>
	11
	12	* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
	13	OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
	14	OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
	15	OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
	16	OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
	17	Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
	18	instructions.
	19	(INSN_DSP): New define for DSP ASE.
	20
848cf006 AM	21	2005-08-18 Alan Modra <amodra@bigpond.net.au>
	22
	23	* a29k.h: Delete.
	24
36ae0db3 DJ	25	2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
	26
	27	* ppc.h (PPC_OPCODE_E300): Define.
	28
8c929562 MS	29	2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
	30
	31	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
	32
f7b8cccc DA	33	2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	34
	35	PR gas/336
	36	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	37	and pitlb.
	38
8b5328ac JB	39	2005-07-27 Jan Beulich <jbeulich@novell.com>
	40
	41	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	42	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	43	Add movq-s as 64-bit variants of movd-s.
	44
f417d200 DA	45	2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
f417d200 DA	46
18b3bdfc DA	47	* hppa.h: Fix punctuation in comment.
18b3bdfc DA	48
f417d200 DA	49	* hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
	50	implicit space-register addressing. Set space-register bits on opcodes
	51	using implicit space-register addressing. Add various missing pa20
	52	long-immediate opcodes. Remove various opcodes using implicit 3-bit
	53	space-register addressing. Use "fE" instead of "fe" in various
	54	fstw opcodes.
	55
9a145ce6 JB	56	2005-07-18 Jan Beulich <jbeulich@novell.com>
	57
	58	* i386.h (i386_optab): Operands of aam and aad are unsigned.
	59
90700ea2 L	60	2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
	61
	62	* i386.h (i386_optab): Support Intel VMX Instructions.
	63
48f130a8 DA	64	2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	65
	66	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
	67
30123838 JB	68	2005-07-05 Jan Beulich <jbeulich@novell.com>
	69
	70	* i386.h (i386_optab): Add new insns.
	71
47b0e7ad NC	72	2005-07-01 Nick Clifton <nickc@redhat.com>
	73
	74	* sparc.h: Add typedefs to structure declarations.
	75
b300c311 L	76	2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
	77
	78	PR 1013
	79	* i386.h (i386_optab): Update comments for 64bit addressing on
	80	mov. Allow 64bit addressing for mov and movq.
	81
2db495be DA	82	2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	83
	84	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	85	respectively, in various floating-point load and store patterns.
	86
caa05036 DA	87	2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	88
	89	* hppa.h (FLAG_STRICT): Correct comment.
	90	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	91	PA 2.0 mneumonics when equivalent. Entries with cache control
	92	completers now require PA 1.1. Adjust whitespace.
	93
f4411256 AM	94	2005-05-19 Anton Blanchard <anton@samba.org>
	95
	96	* ppc.h (PPC_OPCODE_POWER5): Define.
	97
e172dbf8 NC	98	2005-05-10 Nick Clifton <nickc@redhat.com>
	99
	100	* Update the address and phone number of the FSF organization in
	101	the GPL notices in the following files:
	102	a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	103	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	104	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	105	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	106	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	107	tic54x.h, tic80.h, v850.h, vax.h
	108
e44823cf JB	109	2005-05-09 Jan Beulich <jbeulich@novell.com>
	110
	111	* i386.h (i386_optab): Add ht and hnt.
	112
791fe849 MK	113	2005-04-18 Mark Kettenis <kettenis@gnu.org>
	114
	115	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	116	Add xcrypt-ctr. Provide aliases without hyphens.
	117
faa7ef87 L	118	2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
faa7ef87 L	119
a63027e5 L	120	Moved from ../ChangeLog
a63027e5 L	121
faa7ef87 L	122	2005-04-12 Paul Brook <paul@codesourcery.com>
	123	* m88k.h: Rename psr macros to avoid conflicts.
	124
	125	2005-03-12 Zack Weinberg <zack@codesourcery.com>
	126	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	127	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	128	and ARM_ARCH_V6ZKT2.
	129
	130	2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
	131	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	132	Remove redundant instruction types.
	133	(struct argument): X_op - new field.
	134	(struct cst4_entry): Remove.
	135	(no_op_insn): Declare.
	136
	137	2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
	138	* crx.h (enum argtype): Rename types, remove unused types.
	139
	140	2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
	141	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	142	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	143	(enum operand_type): Rearrange operands, edit comments.
	144	replace us<N> with ui<N> for unsigned immediate.
	145	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	146	displacements (respectively).
	147	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	148	(instruction type): Add NO_TYPE_INS.
	149	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	150	(operand_entry): New field - 'flags'.
	151	(operand flags): New.
	152
	153	2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
	154	* crx.h (operand_type): Remove redundant types i3, i4,
	155	i5, i8, i12.
	156	Add new unsigned immediate types us3, us4, us5, us16.
	157
bc4bd9ab MK	158	2005-04-12 Mark Kettenis <kettenis@gnu.org>
	159
	160	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	161	adjust them accordingly.
	162
373ff435 JB	163	2005-04-01 Jan Beulich <jbeulich@novell.com>
	164
	165	* i386.h (i386_optab): Add rdtscp.
	166
4cc91dba L	167	2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
	168
	169	* i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca AS	170	between memory and segment register. Allow movq for moving between
418a8fca AS	171	general-purpose register and segment register.
4cc91dba	172
9ae09ff9 JB	173	2005-02-09 Jan Beulich <jbeulich@novell.com>
	174
	175	PR gas/707
	176	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	177	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	178	fnstsw.
	179
90219bd0 AO	180	2005-01-25 Alexandre Oliva <aoliva@redhat.com>
	181
	182	2004-11-10 Alexandre Oliva <aoliva@redhat.com>
	183	* cgen.h (enum cgen_parse_operand_type): Add
	184	CGEN_PARSE_OPERAND_SYMBOLIC.
	185
239cb185 FF	186	2005-01-21 Fred Fish <fnf@specifixinc.com>
	187
	188	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	189	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	190	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
	191
dc9a9f39 FF	192	2005-01-19 Fred Fish <fnf@specifixinc.com>
	193
	194	* mips.h (struct mips_opcode): Add new pinfo2 member.
	195	(INSN_ALIAS): New define for opcode table entries that are
	196	specific instances of another entry, such as 'move' for an 'or'
	197	with a zero operand.
	198	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	199	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
	200
98e7aba8 ILT	201	2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
	202
	203	* mips.h (CPU_RM9000): Define.
	204	(OPCODE_IS_MEMBER): Handle CPU_RM9000.
	205
37edbb65 JB	206	2004-11-25 Jan Beulich <jbeulich@novell.com>
	207
	208	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	209	to/from test registers are illegal in 64-bit mode. Add missing
	210	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	211	(previously one had to explicitly encode a rex64 prefix). Re-enable
	212	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	213	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
	214
	215	2004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e JB	216
	217	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	218	available only with SSE2. Change the MMX additions introduced by SSE
	219	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	220	instructions by their now designated identifier (since combining i686
	221	and 3DNow! does not really imply 3DNow!A).
	222
f5c7edf4 AM	223	2004-11-19 Alan Modra <amodra@bigpond.net.au>
	224
	225	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	226	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
	227
7499d566 NC	228	2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
	229	Vineet Sharma <vineets@noida.hcltech.com>
	230
	231	* maxq.h: New file: Disassembly information for the maxq port.
	232
bcb9eebe L	233	2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
	234
	235	* i386.h (i386_optab): Put back "movzb".
	236
94bb3d38 HPN	237	2004-11-04 Hans-Peter Nilsson <hp@axis.com>
	238
	239	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	240	comments. Remove member cris_ver_sim. Add members
	241	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	242	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	243	(struct cris_support_reg, struct cris_cond15): New types.
	244	(cris_conds15): Declare.
	245	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	246	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	247	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	248	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	249	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	250	SIZE_FIELD_UNSIGNED.
	251
37edbb65	252	2004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a JB	253
	254	* i386.h (sldx_Suf): Remove.
	255	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	256	(q_FP): Define, implying no REX64.
	257	(x_FP, sl_FP): Imply FloatMF.
	258	(i386_optab): Split reg and mem forms of moving from segment registers
	259	so that the memory forms can ignore the 16-/32-bit operand size
	260	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	261	all non-floating-point instructions. Unite 32- and 64-bit forms of
	262	movsx, movzx, and movd. Adjust floating point operations for the above
	263	changes to the *FP macros. Add DefaultSize to floating point control
	264	insns operating on larger memory ranges. Remove left over comments
	265	hinting at certain insns being Intel-syntax ones where the ones
	266	actually meant are already gone.
	267
48c9f030 NC	268	2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
	269
	270	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	271	instruction type.
	272
0dd132b6 NC	273	2004-09-30 Paul Brook <paul@codesourcery.com>
	274
	275	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	276	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
	277
23794b24 MM	278	2004-09-11 Theodore A. Roth <troth@openavr.org>
	279
	280	* avr.h: Add support for
	281	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
	282
2a309db0 AM	283	2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
	284
	285	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
	286
b18c562e NC	287	2004-08-24 Dmitry Diky <diwil@spec.ru>
	288
	289	* msp430.h (msp430_opc): Add new instructions.
	290	(msp430_rcodes): Declare new instructions.
	291	(msp430_hcodes): Likewise..
	292
45d313cd NC	293	2004-08-13 Nick Clifton <nickc@redhat.com>
	294
	295	PR/301
	296	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	297	processors.
	298
30d1c836 ML	299	2004-08-30 Michal Ludvig <mludvig@suse.cz>
	300
	301	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
	302
9a45f1c2 L	303	2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
	304
	305	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
	306
543613e9 NC	307	2004-07-21 Jan Beulich <jbeulich@novell.com>
	308
	309	* i386.h: Adjust instruction descriptions to better match the
	310	specification.
	311
b781e558 RE	312	2004-07-16 Richard Earnshaw <rearnsha@arm.com>
	313
	314	* arm.h: Remove all old content. Replace with architecture defines
	315	from gas/config/tc-arm.c.
	316
8577e690 AS	317	2004-07-09 Andreas Schwab <schwab@suse.de>
	318
	319	* m68k.h: Fix comment.
	320
1fe1f39c NC	321	2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
	322
	323	* crx.h: New file.
	324
1d9f512f AM	325	2004-06-24 Alan Modra <amodra@bigpond.net.au>
	326
	327	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
	328
be8c092b NC	329	2004-05-24 Peter Barada <peter@the-baradas.com>
	330
	331	* m68k.h: Add 'size' to m68k_opcode.
	332
6b6e92f4 NC	333	2004-05-05 Peter Barada <peter@the-baradas.com>
	334
	335	* m68k.h: Switch from ColdFire chip name to core variant.
	336
	337	2004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b NC	338
	339	* m68k.h: Add mcfmac/mcfemac definitions. Update operand
	340	descriptions for new EMAC cases.
	341	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	342	handle Motorola MAC syntax.
	343	Allow disassembly of ColdFire V4e object files.
	344
fdd12ef3 AM	345	2004-03-16 Alan Modra <amodra@bigpond.net.au>
	346
	347	* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
	348
3922a64c L	349	2004-03-12 Jakub Jelinek <jakub@redhat.com>
	350
	351	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
	352
1f45d988 ML	353	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	354
	355	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
	356
0f10071e ML	357	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	358
	359	* i386.h (i386_optab): Added xstore/xcrypt insns.
	360
3255318a NC	361	2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
	362
	363	* h8300.h (32bit ldc/stc): Add relaxing support.
	364
ca9a79a1	365	2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3	366
ca9a79a1 NC	367	* h8300.h (BITOP): Pass MEMRELAX flag.
ca9a79a1 NC	368
875a0b14 NC	369	2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
	370
	371	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	372	except for the H8S.
252b5132	373
c9e214e5	374	For older changes see ChangeLog-9103
252b5132 RH	375	\f
252b5132 RH	376	Local Variables:
c9e214e5 AM	377	mode: change-log
	378	left-margin: 8
	379	fill-column: 74
252b5132 RH	380	version-control: never
252b5132 RH	381	End: