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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
9e8c70f9
DM		 12011-09-21 David S. Miller <davem@davemloft.net>
2
3 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
4 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
5 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
6 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
7
dec0624d
MR		 82011-08-09 Chao-ying Fu <fu@mips.com>
9 Maciej W. Rozycki <macro@codesourcery.com>
10
11 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
12 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
13 (INSN_ASE_MASK): Add the MCU bit.
14 (INSN_MCU): New macro.
15 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
16 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
17
2b0c8b40
MR		 182011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
19
20 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
21 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
22 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
23 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
24 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
25 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
26 (INSN2_READ_GPR_MMN): Likewise.
27 (INSN2_READ_FPR_D): Change the bit used.
28 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
29 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
30 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
31 (INSN2_COND_BRANCH): Likewise.
32 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
33 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
34 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
35 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
36 (INSN2_MOD_GPR_MN): Likewise.
37
ea783ef3
DM		 382011-08-05 David S. Miller <davem@davemloft.net>
39
40 * sparc.h: Document new format codes '4', '5', and '('.
41 (OPF_LOW4, RS3): New macros.
42
7c176fa8
MR		 432011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
44
45 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
46 order of flags documented.
47
2309ddf2
MR		 482011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
49
50 * mips.h: Clarify the description of microMIPS instruction
51 manipulation macros.
52 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
53
df58fc94
RS		 542011-07-24 Chao-ying Fu <fu@mips.com>
55 Maciej W. Rozycki <macro@codesourcery.com>
56
57 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
58 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
59 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
60 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
61 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
62 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
63 (OP_MASK_RS3, OP_SH_RS3): Likewise.
64 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
65 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
66 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
67 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
68 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
69 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
70 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
71 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
72 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
73 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
74 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
75 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
76 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
77 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
78 (INSN_WRITE_GPR_S): New macro.
79 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
80 (INSN2_READ_FPR_D): Likewise.
81 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
82 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
83 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
84 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
85 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
86 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
87 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
88 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
89 (CPU_MICROMIPS): New macro.
90 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
91 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
92 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
93 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
94 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
95 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
96 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
97 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
98 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
99 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
100 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
101 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
102 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
103 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
104 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
105 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
106 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
107 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
108 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
109 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
110 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
111 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
112 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
113 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
114 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
115 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
116 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
117 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
118 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
119 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
120 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
121 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
122 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
123 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
124 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
125 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
126 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
127 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
128 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
129 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
130 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
131 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
132 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
133 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
134 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
135 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
136 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
137 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
138 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
139 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
140 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
141 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
142 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
143 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
144 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
145 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
146 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
147 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
148 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
149 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
150 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
151 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
152 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
153 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
154 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
155 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
156 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
157 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
158 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
159 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
160 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
161 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
162 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
163 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
164 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
165 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
166 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
167 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
168 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
169 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
170 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
171 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
172 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
173 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
174 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
175 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
176 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
177 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
178 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
179 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
180 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
181 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
182 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
183 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
184 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
185 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
186 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
187 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
188 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
189 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
190 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
191 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
192 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
193 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
194 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
195 (micromips_opcodes): New declaration.
196 (bfd_micromips_num_opcodes): Likewise.
197
bcd530a7
RS		 1982011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
199
200 * mips.h (INSN_TRAP): Rename to...
201 (INSN_NO_DELAY_SLOT): ... this.
202 (INSN_SYNC): Remove macro.
203
2dad5a91
EW		 2042011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
205
206 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
207 a duplicate of AVR_ISA_SPM.
208
5d73b1f1
NC		 2092011-07-01 Nick Clifton <nickc@redhat.com>
210
211 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
212
ef26d60e
MF		 2132011-06-18 Robin Getz <robin.getz@analog.com>
214
215 * bfin.h (is_macmod_signed): New func
216
8fb8dca7
MF		 2172011-06-18 Mike Frysinger <vapier@gentoo.org>
218
219 * bfin.h (is_macmod_pmove): Add missing space before func args.
220 (is_macmod_hmove): Likewise.
221
aa137e4d
NC		 2222011-06-13 Walter Lee <walt@tilera.com>
223
224 * tilegx.h: New file.
225 * tilepro.h: New file.
226
3b2f0793
PB		 2272011-05-31 Paul Brook <paul@codesourcery.com>
228
aa137e4d
NC		 229 * arm.h (ARM_ARCH_V7R_IDIV): Define.
230
2312011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
232
233 * s390.h: Replace S390_OPERAND_REG_EVEN with
234 S390_OPERAND_REG_PAIR.
235
2362011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
237
238 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 239
ac7f631b
NC		 2402011-04-18 Julian Brown <julian@codesourcery.com>
241
242 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
243
84701018
NC		 2442011-04-11 Dan McDonald <dan@wellkeeper.com>
245
246 PR gas/12296
247 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
248
8cc66334
EW		 2492011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
250
251 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
252 New instruction set flags.
253 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
254
3eebd5eb
MR		 2552011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
256
257 * mips.h (M_PREF_AB): New enum value.
258
26bb3ddd
MF		 2592011-02-12 Mike Frysinger <vapier@gentoo.org>
260
89c0d58c
MR		 261 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
262 M_IU): Define.
263 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 264
dd76fcb8
MF		 2652011-02-11 Mike Frysinger <vapier@gentoo.org>
266
267 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
268
98d23bef
BS		 2692011-02-04 Bernd Schmidt <bernds@codesourcery.com>
270
271 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
272 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
273
3c853d93
DA		 2742010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
275
276 PR gas/11395
277 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
278 "bb" entries.
279
79676006
DA		 2802010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
281
282 PR gas/11395
283 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
284
1bec78e9
RS		 2852010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
286
287 * mips.h: Update commentary after last commit.
288
98675402
RS		 2892010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
290
291 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
292 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
293 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
294
aa137e4d
NC		 2952010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
296
297 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
298
435b94a4
RS		 2992010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
300
301 * mips.h: Fix previous commit.
302
d051516a
NC		 3032010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
304
305 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
306 (INSN_LOONGSON_3A): Clear bit 31.
307
251665fc
MGD		 3082010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
309
310 PR gas/12198
311 * arm.h (ARM_AEXT_V6M_ONLY): New define.
312 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
313 (ARM_ARCH_V6M_ONLY): New define.
314
fd503541
NC		 3152010-11-11 Mingming Sun <mingm.sun@gmail.com>
316
317 * mips.h (INSN_LOONGSON_3A): Defined.
318 (CPU_LOONGSON_3A): Defined.
319 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
320
4469d2be
AM		 3212010-10-09 Matt Rice <ratmice@gmail.com>
322
323 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
324 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
325
90ec0d68
MGD		 3262010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
327
328 * arm.h (ARM_EXT_VIRT): New define.
329 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
330 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
331 Extensions.
332
eea54501 3332010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 334
eea54501
MGD		 335 * arm.h (ARM_AEXT_ADIV): New define.
336 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
337
b2a5fbdc
MGD		 3382010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
339
340 * arm.h (ARM_EXT_OS): New define.
341 (ARM_AEXT_V6SM): Likewise.
342 (ARM_ARCH_V6SM): Likewise.
343
60e5ef9f
MGD		 3442010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
345
346 * arm.h (ARM_EXT_MP): Add.
347 (ARM_ARCH_V7A_MP): Likewise.
348
73a63ccf
MF		 3492010-09-22 Mike Frysinger <vapier@gentoo.org>
350
351 * bfin.h: Declare pseudoChr structs/defines.
352
ee99860a
MF		 3532010-09-21 Mike Frysinger <vapier@gentoo.org>
354
355 * bfin.h: Strip trailing whitespace.
356
f9c7014e
DD		 3572010-07-29 DJ Delorie <dj@redhat.com>
358
359 * rx.h (RX_Operand_Type): Add TwoReg.
360 (RX_Opcode_ID): Remove ediv and ediv2.
361
93378652
DD		 3622010-07-27 DJ Delorie <dj@redhat.com>
363
364 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
365
1cd986c5
NC		 3662010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
367 Ina Pandit <ina.pandit@kpitcummins.com>
368
369 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
370 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
371 PROCESSOR_V850E2_ALL.
372 Remove PROCESSOR_V850EA support.
373 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
374 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
375 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
376 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
377 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
378 V850_OPERAND_PERCENT.
379 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
380 V850_NOT_R0.
381 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
382 and V850E_PUSH_POP
383
9a2c7088
MR		 3842010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
385
386 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
387 (MIPS16_INSN_BRANCH): Rename to...
388 (MIPS16_INSN_COND_BRANCH): ... this.
389
bdc70b4a
AM		 3902010-07-03 Alan Modra <amodra@gmail.com>
391
392 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
393 Renumber other PPC_OPCODE defines.
394
f2bae120
AM		 3952010-07-03 Alan Modra <amodra@gmail.com>
396
397 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
398
360cfc9c
AM		 3992010-06-29 Alan Modra <amodra@gmail.com>
400
401 * maxq.h: Delete file.
402
e01d869a
AM		 4032010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
404
405 * ppc.h (PPC_OPCODE_E500): Define.
406
f79e2745
CM		 4072010-05-26 Catherine Moore <clm@codesourcery.com>
408
409 * opcode/mips.h (INSN_MIPS16): Remove.
410
2462afa1
JM		 4112010-04-21 Joseph Myers <joseph@codesourcery.com>
412
413 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
414
e4e42b45
NC		 4152010-04-15 Nick Clifton <nickc@redhat.com>
416
417 * alpha.h: Update copyright notice to use GPLv3.
418 * arc.h: Likewise.
419 * arm.h: Likewise.
420 * avr.h: Likewise.
421 * bfin.h: Likewise.
422 * cgen.h: Likewise.
423 * convex.h: Likewise.
424 * cr16.h: Likewise.
425 * cris.h: Likewise.
426 * crx.h: Likewise.
427 * d10v.h: Likewise.
428 * d30v.h: Likewise.
429 * dlx.h: Likewise.
430 * h8300.h: Likewise.
431 * hppa.h: Likewise.
432 * i370.h: Likewise.
433 * i386.h: Likewise.
434 * i860.h: Likewise.
435 * i960.h: Likewise.
436 * ia64.h: Likewise.
437 * m68hc11.h: Likewise.
438 * m68k.h: Likewise.
439 * m88k.h: Likewise.
440 * maxq.h: Likewise.
441 * mips.h: Likewise.
442 * mmix.h: Likewise.
443 * mn10200.h: Likewise.
444 * mn10300.h: Likewise.
445 * msp430.h: Likewise.
446 * np1.h: Likewise.
447 * ns32k.h: Likewise.
448 * or32.h: Likewise.
449 * pdp11.h: Likewise.
450 * pj.h: Likewise.
451 * pn.h: Likewise.
452 * ppc.h: Likewise.
453 * pyr.h: Likewise.
454 * rx.h: Likewise.
455 * s390.h: Likewise.
456 * score-datadep.h: Likewise.
457 * score-inst.h: Likewise.
458 * sparc.h: Likewise.
459 * spu-insns.h: Likewise.
460 * spu.h: Likewise.
461 * tic30.h: Likewise.
462 * tic4x.h: Likewise.
463 * tic54x.h: Likewise.
464 * tic80.h: Likewise.
465 * v850.h: Likewise.
466 * vax.h: Likewise.
467
40b36596
JM		 4682010-03-25 Joseph Myers <joseph@codesourcery.com>
469
470 * tic6x-control-registers.h, tic6x-insn-formats.h,
471 tic6x-opcode-table.h, tic6x.h: New.
472
c67a084a
NC		 4732010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
474
475 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
476
466ef64f
AM		 4772010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
478
479 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
480
1319d143
L		 4812010-01-14 H.J. Lu <hongjiu.lu@intel.com>
482
483 * ia64.h (ia64_find_opcode): Remove argument name.
484 (ia64_find_next_opcode): Likewise.
485 (ia64_dis_opcode): Likewise.
486 (ia64_free_opcode): Likewise.
487 (ia64_find_dependency): Likewise.
488
1fbb9298
DE		 4892009-11-22 Doug Evans <dje@sebabeach.org>
490
491 * cgen.h: Include bfd_stdint.h.
492 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
493
ada65aa3
PB		 4942009-11-18 Paul Brook <paul@codesourcery.com>
495
496 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
497
9e3c6df6
PB		 4982009-11-17 Paul Brook <paul@codesourcery.com>
499 Daniel Jacobowitz <dan@codesourcery.com>
500
501 * arm.h (ARM_EXT_V6_DSP): Define.
502 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
503 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
504
0d734b5d
DD		 5052009-11-04 DJ Delorie <dj@redhat.com>
506
507 * rx.h (rx_decode_opcode) (mvtipl): Add.
508 (mvtcp, mvfcp, opecp): Remove.
509
62f3b8c8
PB		 5102009-11-02 Paul Brook <paul@codesourcery.com>
511
512 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
513 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
514 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
515 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
516 FPU_ARCH_NEON_VFP_V4): Define.
517
ac1e9eca
DE		 5182009-10-23 Doug Evans <dje@sebabeach.org>
519
520 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
521 * cgen.h: Update. Improve multi-inclusion macro name.
522
9fe54b1c
PB		 5232009-10-02 Peter Bergner <bergner@vnet.ibm.com>
524
525 * ppc.h (PPC_OPCODE_476): Define.
526
634b50f2
PB		 5272009-10-01 Peter Bergner <bergner@vnet.ibm.com>
528
529 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
530
c7927a3c
NC		 5312009-09-29 DJ Delorie <dj@redhat.com>
532
533 * rx.h: New file.
534
b961e85b
AM		 5352009-09-22 Peter Bergner <bergner@vnet.ibm.com>
536
537 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
538
e0d602ec
BE		 5392009-09-21 Ben Elliston <bje@au.ibm.com>
540
541 * ppc.h (PPC_OPCODE_PPCA2): New.
542
96d56e9f
NC		 5432009-09-05 Martin Thuresson <martin@mtme.org>
544
545 * ia64.h (struct ia64_operand): Renamed member class to op_class.
546
d3ce72d0
NC		 5472009-08-29 Martin Thuresson <martin@mtme.org>
548
549 * tic30.h (template): Rename type template to
550 insn_template. Updated code to use new name.
551 * tic54x.h (template): Rename type template to
552 insn_template.
553
824b28db
NH		 5542009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
555
556 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
557
f865a31d
AG		 5582009-06-11 Anthony Green <green@moxielogic.com>
559
560 * moxie.h (MOXIE_F3_PCREL): Define.
561 (moxie_form3_opc_info): Grow.
562
0e7c7f11
AG		 5632009-06-06 Anthony Green <green@moxielogic.com>
564
565 * moxie.h (MOXIE_F1_M): Define.
566
20135e4c
NC		 5672009-04-15 Anthony Green <green@moxielogic.com>
568
569 * moxie.h: Created.
570
bcb012d3
DD		 5712009-04-06 DJ Delorie <dj@redhat.com>
572
573 * h8300.h: Add relaxation attributes to MOVA opcodes.
574
69fe9ce5
AM		 5752009-03-10 Alan Modra <amodra@bigpond.net.au>
576
577 * ppc.h (ppc_parse_cpu): Declare.
578
c3b7224a
NC		 5792009-03-02 Qinwei <qinwei@sunnorth.com.cn>
580
581 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
582 and _IMM11 for mbitclr and mbitset.
583 * score-datadep.h: Update dependency information.
584
066be9f7
PB		 5852009-02-26 Peter Bergner <bergner@vnet.ibm.com>
586
587 * ppc.h (PPC_OPCODE_POWER7): New.
588
fedc618e
DE		 5892009-02-06 Doug Evans <dje@google.com>
590
591 * i386.h: Add comment regarding sse* insns and prefixes.
592
52b6b6b9
JM		 5932009-02-03 Sandip Matte <sandip@rmicorp.com>
594
595 * mips.h (INSN_XLR): Define.
596 (INSN_CHIP_MASK): Update.
597 (CPU_XLR): Define.
598 (OPCODE_IS_MEMBER): Update.
599 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
600
35669430
DE		 6012009-01-28 Doug Evans <dje@google.com>
602
603 * opcode/i386.h: Add multiple inclusion protection.
604 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
605 (EDI_REG_NUM): New macros.
606 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
607 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 608 (REX_PREFIX_P): New macro.
35669430 609
1cb0a767
PB		 6102009-01-09 Peter Bergner <bergner@vnet.ibm.com>
611
612 * ppc.h (struct powerpc_opcode): New field "deprecated".
613 (PPC_OPCODE_NOPOWER4): Delete.
614
3aa3176b
TS		 6152008-11-28 Joshua Kinard <kumba@gentoo.org>
616
617 * mips.h: Define CPU_R14000, CPU_R16000.
618 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
619
8e79c3df
CM		 6202008-11-18 Catherine Moore <clm@codesourcery.com>
621
622 * arm.h (FPU_NEON_FP16): New.
623 (FPU_ARCH_NEON_FP16): New.
624
de9a3e51
CF		 6252008-11-06 Chao-ying Fu <fu@mips.com>
626
627 * mips.h: Doucument '1' for 5-bit sync type.
628
1ca35711
L		 6292008-08-28 H.J. Lu <hongjiu.lu@intel.com>
630
631 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
632 IA64_RS_CR.
633
9b4e5766
PB		 6342008-08-01 Peter Bergner <bergner@vnet.ibm.com>
635
636 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
637
081ba1b3
AM		 6382008-07-30 Michael J. Eager <eager@eagercon.com>
639
640 * ppc.h (PPC_OPCODE_405): Define.
641 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
642
fa452fa6
PB		 6432008-06-13 Peter Bergner <bergner@vnet.ibm.com>
644
645 * ppc.h (ppc_cpu_t): New typedef.
646 (struct powerpc_opcode <flags>): Use it.
647 (struct powerpc_operand <insert, extract>): Likewise.
648 (struct powerpc_macro <flags>): Likewise.
649
bb35fb24
NC		 6502008-06-12 Adam Nemet <anemet@caviumnetworks.com>
651
652 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
653 Update comment before MIPS16 field descriptors to mention MIPS16.
654 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
655 BBIT.
656 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
657 New bit masks and shift counts for cins and exts.
658
dd3cbb7e
NC		 659 * mips.h: Document new field descriptors +Q.
660 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
661
d0799671
AN		 6622008-04-28 Adam Nemet <anemet@caviumnetworks.com>
663
664 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
665 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
666
19a6653c
AM		 6672008-04-14 Edmar Wienskoski <edmar@freescale.com>
668
669 * ppc.h: (PPC_OPCODE_E500MC): New.
670
c0f3af97
L		 6712008-04-03 H.J. Lu <hongjiu.lu@intel.com>
672
673 * i386.h (MAX_OPERANDS): Set to 5.
674 (MAX_MNEM_SIZE): Changed to 20.
675
e210c36b
NC		 6762008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
677
678 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
679
b1cc4aeb
PB		 6802008-03-09 Paul Brook <paul@codesourcery.com>
681
682 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
683
7e806470
PB		 6842008-03-04 Paul Brook <paul@codesourcery.com>
685
686 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
687 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
688 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
689
7b2185f9 6902008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 691 Nick Clifton <nickc@redhat.com>
692
693 PR 3134
694 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
695 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 696 set.
af7329f0 697
796d5313
NC		 6982008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
699
700 * cr16.h (cr16_num_optab): Declared.
701
d669d37f
NC		 7022008-02-14 Hakan Ardo <hakan@debian.org>
703
704 PR gas/2626
705 * avr.h (AVR_ISA_2xxe): Define.
706
e6429699
AN		 7072008-02-04 Adam Nemet <anemet@caviumnetworks.com>
708
709 * mips.h: Update copyright.
710 (INSN_CHIP_MASK): New macro.
711 (INSN_OCTEON): New macro.
712 (CPU_OCTEON): New macro.
713 (OPCODE_IS_MEMBER): Handle Octeon instructions.
714
e210c36b
NC		 7152008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
716
717 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
718
7192008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
720
721 * avr.h (AVR_ISA_USB162): Add new opcode set.
722 (AVR_ISA_AVR3): Likewise.
723
350cc38d
MS		 7242007-11-29 Mark Shinwell <shinwell@codesourcery.com>
725
726 * mips.h (INSN_LOONGSON_2E): New.
727 (INSN_LOONGSON_2F): New.
728 (CPU_LOONGSON_2E): New.
729 (CPU_LOONGSON_2F): New.
730 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
731
56950294
MS		 7322007-11-29 Mark Shinwell <shinwell@codesourcery.com>
733
734 * mips.h (INSN_ISA*): Redefine certain values as an
735 enumeration. Update comments.
736 (mips_isa_table): New.
737 (ISA_MIPS*): Redefine to match enumeration.
738 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
739 values.
740
c3d65c1c
BE		 7412007-08-08 Ben Elliston <bje@au.ibm.com>
742
743 * ppc.h (PPC_OPCODE_PPCPS): New.
744
0fdaa005
L		 7452007-07-03 Nathan Sidwell <nathan@codesourcery.com>
746
747 * m68k.h: Document j K & E.
748
7492007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 750
751 * cr16.h: New file for CR16 target.
752
3896c469
AM		 7532007-05-02 Alan Modra <amodra@bigpond.net.au>
754
755 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
756
9a2e615a
NS		 7572007-04-23 Nathan Sidwell <nathan@codesourcery.com>
758
759 * m68k.h (mcfisa_c): New.
760 (mcfusp, mcf_mask): Adjust.
761
b84bf58a
AM		 7622007-04-20 Alan Modra <amodra@bigpond.net.au>
763
764 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
765 (num_powerpc_operands): Declare.
766 (PPC_OPERAND_SIGNED et al): Redefine as hex.
767 (PPC_OPERAND_PLUS1): Define.
768
831480e9 7692007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 770
771 * i386.h (REX_MODE64): Renamed to ...
772 (REX_W): This.
773 (REX_EXTX): Renamed to ...
774 (REX_R): This.
775 (REX_EXTY): Renamed to ...
776 (REX_X): This.
777 (REX_EXTZ): Renamed to ...
778 (REX_B): This.
779
0b1cf022
L		 7802007-03-15 H.J. Lu <hongjiu.lu@intel.com>
781
782 * i386.h: Add entries from config/tc-i386.h and move tables
783 to opcodes/i386-opc.h.
784
d796c0ad
L		 7852007-03-13 H.J. Lu <hongjiu.lu@intel.com>
786
787 * i386.h (FloatDR): Removed.
788 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
789
30ac7323
AM		 7902007-03-01 Alan Modra <amodra@bigpond.net.au>
791
792 * spu-insns.h: Add soma double-float insns.
793
8b082fb1 7942007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 795 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 796
797 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
798 (INSN_DSPR2): Add flag for DSP R2 instructions.
799 (M_BALIGN): New macro.
800
4eed87de
AM		 8012007-02-14 Alan Modra <amodra@bigpond.net.au>
802
803 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
804 and Seg3ShortFrom with Shortform.
805
fda592e8
L		 8062007-02-11 H.J. Lu <hongjiu.lu@intel.com>
807
808 PR gas/4027
809 * i386.h (i386_optab): Put the real "test" before the pseudo
810 one.
811
3bdcfdf4
KH		 8122007-01-08 Kazu Hirata <kazu@codesourcery.com>
813
814 * m68k.h (m68010up): OR fido_a.
815
9840d27e
KH		 8162006-12-25 Kazu Hirata <kazu@codesourcery.com>
817
818 * m68k.h (fido_a): New.
819
c629cdac
KH		 8202006-12-24 Kazu Hirata <kazu@codesourcery.com>
821
822 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
823 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
824 values.
825
b7d9ef37
L		 8262006-11-08 H.J. Lu <hongjiu.lu@intel.com>
827
828 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
829
b138abaa
NC		 8302006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
831
832 * score-inst.h (enum score_insn_type): Add Insn_internal.
833
e9f53129
AM		 8342006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
835 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
836 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
837 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
838 Alan Modra <amodra@bigpond.net.au>
839
840 * spu-insns.h: New file.
841 * spu.h: New file.
842
ede602d7
AM		 8432006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
844
845 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 846
7918206c
MM		 8472006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
848
e4e42b45 849 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 850 in amdfam10 architecture.
851
ef05d495
L		 8522006-09-28 H.J. Lu <hongjiu.lu@intel.com>
853
854 * i386.h: Replace CpuMNI with CpuSSSE3.
855
2d447fca
JM		 8562006-09-26 Mark Shinwell <shinwell@codesourcery.com>
857 Joseph Myers <joseph@codesourcery.com>
858 Ian Lance Taylor <ian@wasabisystems.com>
859 Ben Elliston <bje@wasabisystems.com>
860
861 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
862
1c0d3aa6
NC		 8632006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
864
865 * score-datadep.h: New file.
866 * score-inst.h: New file.
867
c2f0420e
L		 8682006-07-14 H.J. Lu <hongjiu.lu@intel.com>
869
870 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
871 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
872 movdq2q and movq2dq.
873
050dfa73
MM		 8742006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
875 Michael Meissner <michael.meissner@amd.com>
876
877 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
878
15965411
L		 8792006-06-12 H.J. Lu <hongjiu.lu@intel.com>
880
881 * i386.h (i386_optab): Add "nop" with memory reference.
882
46e883c5
L		 8832006-06-12 H.J. Lu <hongjiu.lu@intel.com>
884
885 * i386.h (i386_optab): Update comment for 64bit NOP.
886
9622b051
AM		 8872006-06-06 Ben Elliston <bje@au.ibm.com>
888 Anton Blanchard <anton@samba.org>
889
890 * ppc.h (PPC_OPCODE_POWER6): Define.
891 Adjust whitespace.
892
a9e24354
TS		 8932006-06-05 Thiemo Seufer <ths@mips.com>
894
e4e42b45 895 * mips.h: Improve description of MT flags.
a9e24354 896
a596001e
RS		 8972006-05-25 Richard Sandiford <richard@codesourcery.com>
898
899 * m68k.h (mcf_mask): Define.
900
d43b4baf
TS		 9012006-05-05 Thiemo Seufer <ths@mips.com>
902 David Ung <davidu@mips.com>
903
904 * mips.h (enum): Add macro M_CACHE_AB.
905
39a7806d
TS		 9062006-05-04 Thiemo Seufer <ths@mips.com>
907 Nigel Stephens <nigel@mips.com>
908 David Ung <davidu@mips.com>
909
910 * mips.h: Add INSN_SMARTMIPS define.
911
9bcd4f99
TS		 9122006-04-30 Thiemo Seufer <ths@mips.com>
913 David Ung <davidu@mips.com>
914
915 * mips.h: Defines udi bits and masks. Add description of
916 characters which may appear in the args field of udi
917 instructions.
918
ef0ee844
TS		 9192006-04-26 Thiemo Seufer <ths@networkno.de>
920
921 * mips.h: Improve comments describing the bitfield instruction
922 fields.
923
f7675147
L		 9242006-04-26 Julian Brown <julian@codesourcery.com>
925
926 * arm.h (FPU_VFP_EXT_V3): Define constant.
927 (FPU_NEON_EXT_V1): Likewise.
928 (FPU_VFP_HARD): Update.
929 (FPU_VFP_V3): Define macro.
930 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
931
ef0ee844 9322006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 933
934 * avr.h (AVR_ISA_PWMx): New.
935
2da12c60
NS		 9362006-03-28 Nathan Sidwell <nathan@codesourcery.com>
937
938 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
939 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
940 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
941 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
942 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
943
0715c387
PB		 9442006-03-10 Paul Brook <paul@codesourcery.com>
945
946 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
947
34bdd094
DA		 9482006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
949
950 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
951 first. Correct mask of bb "B" opcode.
952
331d2d0d
L		 9532006-02-27 H.J. Lu <hongjiu.lu@intel.com>
954
955 * i386.h (i386_optab): Support Intel Merom New Instructions.
956
62b3e311
PB		 9572006-02-24 Paul Brook <paul@codesourcery.com>
958
959 * arm.h: Add V7 feature bits.
960
59cf82fe
L		 9612006-02-23 H.J. Lu <hongjiu.lu@intel.com>
962
963 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
964
e74cfd16
PB		 9652006-01-31 Paul Brook <paul@codesourcery.com>
966 Richard Earnshaw <rearnsha@arm.com>
967
968 * arm.h: Use ARM_CPU_FEATURE.
969 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
970 (arm_feature_set): Change to a structure.
971 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
972 ARM_FEATURE): New macros.
973
5b3f8a92
HPN		 9742005-12-07 Hans-Peter Nilsson <hp@axis.com>
975
976 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
977 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
978 (ADD_PC_INCR_OPCODE): Don't define.
979
cb712a9e
L		 9802005-12-06 H.J. Lu <hongjiu.lu@intel.com>
981
982 PR gas/1874
983 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
984
0499d65b
TS		 9852005-11-14 David Ung <davidu@mips.com>
986
987 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
988 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
989 save/restore encoding of the args field.
990
ea5ca089
DB		 9912005-10-28 Dave Brolley <brolley@redhat.com>
992
993 Contribute the following changes:
994 2005-02-16 Dave Brolley <brolley@redhat.com>
995
996 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
997 cgen_isa_mask_* to cgen_bitset_*.
998 * cgen.h: Likewise.
999
16175d96
DB		 1000 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1001
1002 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1003 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1004 (CGEN_CPU_TABLE): Make isas a ponter.
1005
1006 2003-09-29 Dave Brolley <brolley@redhat.com>
1007
1008 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1009 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1010 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1011
1012 2002-12-13 Dave Brolley <brolley@redhat.com>
1013
1014 * cgen.h (symcat.h): #include it.
1015 (cgen-bitset.h): #include it.
1016 (CGEN_ATTR_VALUE_TYPE): Now a union.
1017 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1018 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1019 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1020 * cgen-bitset.h: New file.
1021
3c9b82ba
NC		 10222005-09-30 Catherine Moore <clm@cm00re.com>
1023
1024 * bfin.h: New file.
1025
6a2375c6
JB		 10262005-10-24 Jan Beulich <jbeulich@novell.com>
1027
1028 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1029 indirect operands.
1030
c06a12f8
DA		 10312005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1032
1033 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1034 Add FLAG_STRICT to pa10 ftest opcode.
1035
4d443107
DA		 10362005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1037
1038 * hppa.h (pa_opcodes): Remove lha entries.
1039
f0a3b40f
DA		 10402005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1041
1042 * hppa.h (FLAG_STRICT): Revise comment.
1043 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1044 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1045 entries for "fdc".
1046
e210c36b
NC		 10472005-09-30 Catherine Moore <clm@cm00re.com>
1048
1049 * bfin.h: New file.
1050
1b7e1362
DA		 10512005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1052
1053 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1054
089b39de
CF		 10552005-09-06 Chao-ying Fu <fu@mips.com>
1056
1057 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1058 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1059 define.
1060 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1061 (INSN_ASE_MASK): Update to include INSN_MT.
1062 (INSN_MT): New define for MT ASE.
1063
93c34b9b
CF		 10642005-08-25 Chao-ying Fu <fu@mips.com>
1065
1066 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1067 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1068 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1069 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1070 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1071 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1072 instructions.
1073 (INSN_DSP): New define for DSP ASE.
1074
848cf006
AM		 10752005-08-18 Alan Modra <amodra@bigpond.net.au>
1076
1077 * a29k.h: Delete.
1078
36ae0db3
DJ		 10792005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1080
1081 * ppc.h (PPC_OPCODE_E300): Define.
1082
8c929562
MS		 10832005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1084
1085 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1086
f7b8cccc
DA		 10872005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1088
1089 PR gas/336
1090 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1091 and pitlb.
1092
8b5328ac
JB		 10932005-07-27 Jan Beulich <jbeulich@novell.com>
1094
1095 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1096 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1097 Add movq-s as 64-bit variants of movd-s.
1098
f417d200
DA		 10992005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1100
18b3bdfc
DA		 1101 * hppa.h: Fix punctuation in comment.
1102
f417d200
DA		 1103 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1104 implicit space-register addressing. Set space-register bits on opcodes
1105 using implicit space-register addressing. Add various missing pa20
1106 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1107 space-register addressing. Use "fE" instead of "fe" in various
1108 fstw opcodes.
1109
9a145ce6
JB		 11102005-07-18 Jan Beulich <jbeulich@novell.com>
1111
1112 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1113
90700ea2
L		 11142007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1115
1116 * i386.h (i386_optab): Support Intel VMX Instructions.
1117
48f130a8
DA		 11182005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1119
1120 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1121
30123838
JB		 11222005-07-05 Jan Beulich <jbeulich@novell.com>
1123
1124 * i386.h (i386_optab): Add new insns.
1125
47b0e7ad
NC		 11262005-07-01 Nick Clifton <nickc@redhat.com>
1127
1128 * sparc.h: Add typedefs to structure declarations.
1129
b300c311
L		 11302005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1131
1132 PR 1013
1133 * i386.h (i386_optab): Update comments for 64bit addressing on
1134 mov. Allow 64bit addressing for mov and movq.
1135
2db495be
DA		 11362005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1137
1138 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1139 respectively, in various floating-point load and store patterns.
1140
caa05036
DA		 11412005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1142
1143 * hppa.h (FLAG_STRICT): Correct comment.
1144 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1145 PA 2.0 mneumonics when equivalent. Entries with cache control
1146 completers now require PA 1.1. Adjust whitespace.
1147
f4411256
AM		 11482005-05-19 Anton Blanchard <anton@samba.org>
1149
1150 * ppc.h (PPC_OPCODE_POWER5): Define.
1151
e172dbf8
NC		 11522005-05-10 Nick Clifton <nickc@redhat.com>
1153
1154 * Update the address and phone number of the FSF organization in
1155 the GPL notices in the following files:
1156 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1157 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1158 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1159 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1160 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1161 tic54x.h, tic80.h, v850.h, vax.h
1162
e44823cf
JB		 11632005-05-09 Jan Beulich <jbeulich@novell.com>
1164
1165 * i386.h (i386_optab): Add ht and hnt.
1166
791fe849
MK		 11672005-04-18 Mark Kettenis <kettenis@gnu.org>
1168
1169 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1170 Add xcrypt-ctr. Provide aliases without hyphens.
1171
faa7ef87
L		 11722005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1173
a63027e5
L		 1174 Moved from ../ChangeLog
1175
faa7ef87
L		 1176 2005-04-12 Paul Brook <paul@codesourcery.com>
1177 * m88k.h: Rename psr macros to avoid conflicts.
1178
1179 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1180 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1181 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1182 and ARM_ARCH_V6ZKT2.
1183
1184 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1185 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1186 Remove redundant instruction types.
1187 (struct argument): X_op - new field.
1188 (struct cst4_entry): Remove.
1189 (no_op_insn): Declare.
1190
1191 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1192 * crx.h (enum argtype): Rename types, remove unused types.
1193
1194 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1195 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1196 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1197 (enum operand_type): Rearrange operands, edit comments.
1198 replace us<N> with ui<N> for unsigned immediate.
1199 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1200 displacements (respectively).
1201 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1202 (instruction type): Add NO_TYPE_INS.
1203 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1204 (operand_entry): New field - 'flags'.
1205 (operand flags): New.
1206
1207 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1208 * crx.h (operand_type): Remove redundant types i3, i4,
1209 i5, i8, i12.
1210 Add new unsigned immediate types us3, us4, us5, us16.
1211
bc4bd9ab
MK		 12122005-04-12 Mark Kettenis <kettenis@gnu.org>
1213
1214 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1215 adjust them accordingly.
1216
373ff435
JB		 12172005-04-01 Jan Beulich <jbeulich@novell.com>
1218
1219 * i386.h (i386_optab): Add rdtscp.
1220
4cc91dba
L		 12212005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1222
1223 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1224 between memory and segment register. Allow movq for moving between
1225 general-purpose register and segment register.
4cc91dba 1226
9ae09ff9
JB		 12272005-02-09 Jan Beulich <jbeulich@novell.com>
1228
1229 PR gas/707
1230 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1231 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1232 fnstsw.
1233
638e7a64
NS		 12342006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1235
1236 * m68k.h (m68008, m68ec030, m68882): Remove.
1237 (m68k_mask): New.
1238 (cpu_m68k, cpu_cf): New.
1239 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1240 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1241
90219bd0
AO		 12422005-01-25 Alexandre Oliva <aoliva@redhat.com>
1243
1244 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1245 * cgen.h (enum cgen_parse_operand_type): Add
1246 CGEN_PARSE_OPERAND_SYMBOLIC.
1247
239cb185
FF		 12482005-01-21 Fred Fish <fnf@specifixinc.com>
1249
1250 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1251 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1252 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1253
dc9a9f39
FF		 12542005-01-19 Fred Fish <fnf@specifixinc.com>
1255
1256 * mips.h (struct mips_opcode): Add new pinfo2 member.
1257 (INSN_ALIAS): New define for opcode table entries that are
1258 specific instances of another entry, such as 'move' for an 'or'
1259 with a zero operand.
1260 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1261 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1262
98e7aba8
ILT		 12632004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1264
1265 * mips.h (CPU_RM9000): Define.
1266 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1267
37edbb65
JB		 12682004-11-25 Jan Beulich <jbeulich@novell.com>
1269
1270 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1271 to/from test registers are illegal in 64-bit mode. Add missing
1272 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1273 (previously one had to explicitly encode a rex64 prefix). Re-enable
1274 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1275 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1276
12772004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1278
1279 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1280 available only with SSE2. Change the MMX additions introduced by SSE
1281 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1282 instructions by their now designated identifier (since combining i686
1283 and 3DNow! does not really imply 3DNow!A).
1284
f5c7edf4
AM		 12852004-11-19 Alan Modra <amodra@bigpond.net.au>
1286
1287 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1288 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1289
7499d566
NC		 12902004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1291 Vineet Sharma <vineets@noida.hcltech.com>
1292
1293 * maxq.h: New file: Disassembly information for the maxq port.
1294
bcb9eebe
L		 12952004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1296
1297 * i386.h (i386_optab): Put back "movzb".
1298
94bb3d38
HPN		 12992004-11-04 Hans-Peter Nilsson <hp@axis.com>
1300
1301 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1302 comments. Remove member cris_ver_sim. Add members
1303 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1304 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1305 (struct cris_support_reg, struct cris_cond15): New types.
1306 (cris_conds15): Declare.
1307 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1308 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1309 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1310 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1311 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1312 SIZE_FIELD_UNSIGNED.
1313
37edbb65 13142004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1315
1316 * i386.h (sldx_Suf): Remove.
1317 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1318 (q_FP): Define, implying no REX64.
1319 (x_FP, sl_FP): Imply FloatMF.
1320 (i386_optab): Split reg and mem forms of moving from segment registers
1321 so that the memory forms can ignore the 16-/32-bit operand size
1322 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1323 all non-floating-point instructions. Unite 32- and 64-bit forms of
1324 movsx, movzx, and movd. Adjust floating point operations for the above
1325 changes to the *FP macros. Add DefaultSize to floating point control
1326 insns operating on larger memory ranges. Remove left over comments
1327 hinting at certain insns being Intel-syntax ones where the ones
1328 actually meant are already gone.
1329
48c9f030
NC		 13302004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1331
1332 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1333 instruction type.
1334
0dd132b6
NC		 13352004-09-30 Paul Brook <paul@codesourcery.com>
1336
1337 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1338 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1339
23794b24
MM		 13402004-09-11 Theodore A. Roth <troth@openavr.org>
1341
1342 * avr.h: Add support for
1343 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1344
2a309db0
AM		 13452004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1346
1347 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1348
b18c562e
NC		 13492004-08-24 Dmitry Diky <diwil@spec.ru>
1350
1351 * msp430.h (msp430_opc): Add new instructions.
1352 (msp430_rcodes): Declare new instructions.
1353 (msp430_hcodes): Likewise..
1354
45d313cd
NC		 13552004-08-13 Nick Clifton <nickc@redhat.com>
1356
1357 PR/301
1358 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1359 processors.
1360
30d1c836
ML		 13612004-08-30 Michal Ludvig <mludvig@suse.cz>
1362
1363 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1364
9a45f1c2
L		 13652004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1366
1367 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1368
543613e9
NC		 13692004-07-21 Jan Beulich <jbeulich@novell.com>
1370
1371 * i386.h: Adjust instruction descriptions to better match the
1372 specification.
1373
b781e558
RE		 13742004-07-16 Richard Earnshaw <rearnsha@arm.com>
1375
1376 * arm.h: Remove all old content. Replace with architecture defines
1377 from gas/config/tc-arm.c.
1378
8577e690
AS		 13792004-07-09 Andreas Schwab <schwab@suse.de>
1380
1381 * m68k.h: Fix comment.
1382
1fe1f39c
NC		 13832004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1384
1385 * crx.h: New file.
1386
1d9f512f
AM		 13872004-06-24 Alan Modra <amodra@bigpond.net.au>
1388
1389 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1390
be8c092b
NC		 13912004-05-24 Peter Barada <peter@the-baradas.com>
1392
1393 * m68k.h: Add 'size' to m68k_opcode.
1394
6b6e92f4
NC		 13952004-05-05 Peter Barada <peter@the-baradas.com>
1396
1397 * m68k.h: Switch from ColdFire chip name to core variant.
1398
13992004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1400
1401 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1402 descriptions for new EMAC cases.
1403 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1404 handle Motorola MAC syntax.
1405 Allow disassembly of ColdFire V4e object files.
1406
fdd12ef3
AM		 14072004-03-16 Alan Modra <amodra@bigpond.net.au>
1408
1409 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1410
3922a64c
L		 14112004-03-12 Jakub Jelinek <jakub@redhat.com>
1412
1413 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1414
1f45d988
ML		 14152004-03-12 Michal Ludvig <mludvig@suse.cz>
1416
1417 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1418
0f10071e
ML		 14192004-03-12 Michal Ludvig <mludvig@suse.cz>
1420
1421 * i386.h (i386_optab): Added xstore/xcrypt insns.
1422
3255318a
NC		 14232004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1424
1425 * h8300.h (32bit ldc/stc): Add relaxing support.
1426
ca9a79a1 14272004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1428
ca9a79a1
NC		 1429 * h8300.h (BITOP): Pass MEMRELAX flag.
1430
875a0b14
NC		 14312004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1432
1433 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1434 except for the H8S.
252b5132 1435
c9e214e5 1436For older changes see ChangeLog-9103
252b5132
RH		 1437\f
1438Local Variables:
c9e214e5
AM		 1439mode: change-log
1440left-margin: 8
1441fill-column: 74
252b5132
RH		 1442version-control: never
1443End:
GDB Binutils - Deliverables
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