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[gdb/doc] Stack, Examining the Stack: Reorder menu
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
24b368f8
CZ		 12015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
2
3 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
4
d685192a
MW		 52015-11-27 Matthew Wahab <matthew.wahab@arm.com>
6
7 * aarch64.h (aarch64_op): Add OP_BFC.
8
87018195
MW		 92015-11-27 Matthew Wahab <matthew.wahab@arm.com>
10
11 * aarch64.h (AARCH64_FEATURE_F16): New.
12 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
13 features.
14
250aafa4
MW		 152015-11-20 Matthew Wahab <matthew.wahab@arm.com>
16
17 * aarch64.h (AARCH64_FEATURE_V8_1): New.
18 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
19
56a1b672
MW		 202015-11-19 Matthew Wahab <matthew.wahab@arm.com>
21
22 * arm.h (ARM_EXT2_V8_2A): New.
23 (ARM_ARCH_V8_2A): New.
24
acb787b0
MW		 252015-11-19 Matthew Wahab <matthew.wahab@arm.com>
26
27 * aarch64.h (AARCH64_FEATURE_V8_2): New.
28 (AARCH64_ARCH_V8_2): New.
29
a680de9a
PB		 302015-11-11 Alan Modra <amodra@gmail.com>
31 Peter Bergner <bergner@vnet.ibm.com>
32
33 * ppc.h (PPC_OPCODE_POWER9): New define.
34 (PPC_OPCODE_VSX3): Likewise.
35
854eb72b
NC		 362015-11-02 Nick Clifton <nickc@redhat.com>
37
38 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
39
e292aa7a
NC		 402015-11-02 Nick Clifton <nickc@redhat.com>
41
42 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
43
43cdf5ae
YQ		 442015-10-28 Yao Qi <yao.qi@linaro.org>
45
46 * aarch64.h (aarch64_decode_insn): Update declaration.
47
875880c6
YQ		 482015-10-07 Yao Qi <yao.qi@linaro.org>
49
50 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
51 <name>: New field.
52
d3e12b29
YQ		 532015-10-07 Yao Qi <yao.qi@linaro.org>
54
55 * aarch64.h [__cplusplus]: Wrap in extern "C".
56
886a2506
NC		 572015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
58 Cupertino Miranda <cmiranda@synopsys.com>
59
60 * arc-func.h: New file.
61 * arc.h: Likewise.
62
e141d84e
YQ		 632015-10-02 Yao Qi <yao.qi@linaro.org>
64
65 * aarch64.h (aarch64_zero_register_p): Move the declaration
66 to column one.
67
36f4aab1
YQ		 682015-10-02 Yao Qi <yao.qi@linaro.org>
69
70 * aarch64.h (aarch64_decode_insn): Declare it.
71
7ecc513a
DV		 722015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
73
74 * s390.h (S390_INSTR_FLAG_HTM): New flag.
75 (S390_INSTR_FLAG_VX): New flag.
76 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
77
b6518b38
NC		 782015-09-23 Nick Clifton <nickc@redhat.com>
79
80 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
81 shifting.
82
f04265ec
NC		 832015-09-22 Nick Clifton <nickc@redhat.com>
84
85 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
86
7bdf96ef
NC		 872015-09-09 Daniel Santos <daniel.santos@pobox.com>
88
89 * visium.h (gen_reg_table): Make static.
90 (fp_reg_table): Likewise.
91 (cc_table): Likewise.
92
f33026a9
MW		 932015-07-20 Matthew Wahab <matthew.wahab@arm.com>
94
95 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
96 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
97 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
98 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
99
ef5a96d5
AM		 1002015-07-03 Alan Modra <amodra@gmail.com>
101
102 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
103
c8c8175b
SL		 1042015-07-01 Sandra Loosemore <sandra@codesourcery.com>
105 Cesar Philippidis <cesar@codesourcery.com>
106
107 * nios2.h (enum iw_format_type): Add R2 formats.
108 (enum overflow_type): Add signed_immed12_overflow and
109 enumeration_overflow for R2.
110 (struct nios2_opcode): Document new argument letters for R2.
111 (REG_3BIT, REG_LDWM, REG_POP): Define.
112 (includes): Include nios2r2.h.
113 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
114 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
115 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
116 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
117 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
118 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
119 Declare.
120 * nios2r2.h: New file.
121
11a0cf2e
PB		 1222015-06-19 Peter Bergner <bergner@vnet.ibm.com>
123
124 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
125 (ppc_optional_operand_value): New inline function.
126
88f0ea34
MW		 1272015-06-04 Matthew Wahab <matthew.wahab@arm.com>
128
129 * aarch64.h (AARCH64_V8_1): New.
130
a5932920
MW		 1312015-06-03 Matthew Wahab <matthew.wahab@arm.com>
132
133 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
134 (ARM_ARCH_V8_1A): New.
135 (ARM_ARCH_V8_1A_FP): New.
136 (ARM_ARCH_V8_1A_SIMD): New.
137 (ARM_ARCH_V8_1A_CRYPTOV1): New.
138 (ARM_FEATURE_CORE): New.
139
ddfded2f
MW		 1402015-06-02 Matthew Wahab <matthew.wahab@arm.com>
141
142 * arm.h (ARM_EXT2_PAN): New.
143 (ARM_FEATURE_CORE_HIGH): New.
144
1af1dd51
MW		 1452015-06-02 Matthew Wahab <matthew.wahab@arm.com>
146
147 * arm.h (ARM_FEATURE_ALL): New.
148
9e1f0fa7
MW		 1492015-06-02 Matthew Wahab <matthew.wahab@arm.com>
150
151 * aarch64.h (AARCH64_FEATURE_RDMA): New.
152
290806fd
MW		 1532015-06-02 Matthew Wahab <matthew.wahab@arm.com>
154
155 * aarch64.h (AARCH64_FEATURE_LOR): New.
156
f21cce2c
MW		 1572015-06-01 Matthew Wahab <matthew.wahab@arm.com>
158
159 * aarch64.h (AARCH64_FEATURE_PAN): New.
160 (aarch64_sys_reg_supported_p): Declare.
161 (aarch64_pstatefield_supported_p): Declare.
162
0952813b
DD		 1632015-04-30 DJ Delorie <dj@redhat.com>
164
165 * rl78.h (RL78_Dis_Isa): New.
166 (rl78_decode_opcode): Add ISA parameter.
167
823d2571
TG		 1682015-03-24 Terry Guo <terry.guo@arm.com>
169
170 * arm.h (arm_feature_set): Extended to provide more available bits.
171 (ARM_ANY): Updated to follow above new definition.
172 (ARM_CPU_HAS_FEATURE): Likewise.
173 (ARM_CPU_IS_ANY): Likewise.
174 (ARM_MERGE_FEATURE_SETS): Likewise.
175 (ARM_CLEAR_FEATURE): Likewise.
176 (ARM_FEATURE): Likewise.
177 (ARM_FEATURE_COPY): New macro.
178 (ARM_FEATURE_EQUAL): Likewise.
179 (ARM_FEATURE_ZERO): Likewise.
180 (ARM_FEATURE_CORE_EQUAL): Likewise.
181 (ARM_FEATURE_LOW): Likewise.
182 (ARM_FEATURE_CORE_LOW): Likewise.
183 (ARM_FEATURE_CORE_COPROC): Likewise.
184
f63c1776
PA		 1852015-02-19 Pedro Alves <palves@redhat.com>
186
187 * cgen.h [__cplusplus]: Wrap in extern "C".
188 * msp430-decode.h [__cplusplus]: Likewise.
189 * nios2.h [__cplusplus]: Likewise.
190 * rl78.h [__cplusplus]: Likewise.
191 * rx.h [__cplusplus]: Likewise.
192 * tilegx.h [__cplusplus]: Likewise.
193
3f8107ab
AM		 1942015-01-28 James Bowman <james.bowman@ftdichip.com>
195
196 * ft32.h: New file.
197
1e2e8c52
AK		 1982015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
199
200 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
201
b90efa5b
AM		 2022015-01-01 Alan Modra <amodra@gmail.com>
203
204 Update year range in copyright notice of all files.
205
bffb6004
AG		 2062014-12-27 Anthony Green <green@moxielogic.com>
207
208 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
209 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
210
1945cfa5
EB		 2112014-12-06 Eric Botcazou <ebotcazou@adacore.com>
212
213 * visium.h: New file.
214
d306ce58
SL		 2152014-11-28 Sandra Loosemore <sandra@codesourcery.com>
216
217 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
218 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
219 (NIOS2_INSN_OPTARG): Renumber.
220
b4714c7c
SL		 2212014-11-06 Sandra Loosemore <sandra@codesourcery.com>
222
223 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
224 declaration. Fix obsolete comment.
225
96ba4233
SL		 2262014-10-23 Sandra Loosemore <sandra@codesourcery.com>
227
228 * nios2.h (enum iw_format_type): New.
229 (struct nios2_opcode): Update comments. Add size and format fields.
230 (NIOS2_INSN_OPTARG): New.
231 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
232 (struct nios2_reg): Add regtype field.
233 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
234 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
235 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
236 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
237 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
238 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
239 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
240 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
241 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
242 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
243 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
244 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
245 (OP_MASK_OP, OP_SH_OP): Delete.
246 (OP_MASK_IOP, OP_SH_IOP): Delete.
247 (OP_MASK_IRD, OP_SH_IRD): Delete.
248 (OP_MASK_IRT, OP_SH_IRT): Delete.
249 (OP_MASK_IRS, OP_SH_IRS): Delete.
250 (OP_MASK_ROP, OP_SH_ROP): Delete.
251 (OP_MASK_RRD, OP_SH_RRD): Delete.
252 (OP_MASK_RRT, OP_SH_RRT): Delete.
253 (OP_MASK_RRS, OP_SH_RRS): Delete.
254 (OP_MASK_JOP, OP_SH_JOP): Delete.
255 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
256 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
257 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
258 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
259 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
260 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
261 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
262 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
263 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
264 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
265 (OP_MASK_<insn>, OP_MASK): Delete.
266 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
267 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
268 Include nios2r1.h to define new instruction opcode constants
269 and accessors.
270 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
271 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
272 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
273 (NUMOPCODES, NUMREGISTERS): Delete.
274 * nios2r1.h: New file.
275
0b6be415
JM		 2762014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
277
278 * sparc.h (HWCAP2_VIS3B): Documentation improved.
279
3d68f91c
JM		 2802014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
281
282 * sparc.h (sparc_opcode): new field `hwcaps2'.
283 (HWCAP2_FJATHPLUS): New define.
284 (HWCAP2_VIS3B): Likewise.
285 (HWCAP2_ADP): Likewise.
286 (HWCAP2_SPARC5): Likewise.
287 (HWCAP2_MWAIT): Likewise.
288 (HWCAP2_XMPMUL): Likewise.
289 (HWCAP2_XMONT): Likewise.
290 (HWCAP2_NSEC): Likewise.
291 (HWCAP2_FJATHHPC): Likewise.
292 (HWCAP2_FJDES): Likewise.
293 (HWCAP2_FJAES): Likewise.
294 Document the new operand kind `{', corresponding to the mcdper
295 ancillary state register.
296 Document the new operand kind }, which represents frsd floating
297 point registers (double precision) which must be the same than
298 frs1 in its containing instruction.
299
40c7a7cb
KLC		 3002014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
301
72f4393d 302 * nds32.h: Add new opcode declaration.
40c7a7cb 303
7361da2c
AB		 3042014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
305 Matthew Fortune <matthew.fortune@imgtec.com>
306
307 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
308 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
309 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
310 +I, +O, +R, +:, +\, +", +;
311 (mips_check_prev_operand): New struct.
312 (INSN2_FORBIDDEN_SLOT): New define.
313 (INSN_ISA32R6): New define.
314 (INSN_ISA64R6): New define.
315 (INSN_UPTO32R6): New define.
316 (INSN_UPTO64R6): New define.
317 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
318 (ISA_MIPS32R6): New define.
319 (ISA_MIPS64R6): New define.
320 (CPU_MIPS32R6): New define.
321 (CPU_MIPS64R6): New define.
322 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
323
ee804238
JW		 3242014-09-03 Jiong Wang <jiong.wang@arm.com>
325
326 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
327 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
328 (aarch64_insn_class): Add lse_atomic.
329 (F_LSE_SZ): New field added.
330 (opcode_has_special_coder): Recognize F_LSE_SZ.
331
5575639b
MR		 3322014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
333
334 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
335 over to `+J'.
336
43885403
MF		 3372014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
338
339 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
340 (INSN_LOAD_COPROC): New define.
341 (INSN_COPROC_MOVE_DELAY): Rename to...
342 (INSN_COPROC_MOVE): New define.
343
f36e8886 3442014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 345 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
346 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
347 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 348
349 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
350 (AVR_ISA_2xxxa): Define ISA without LPM.
351 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
352 Add doc for contraint used in 16 bit lds/sts.
353 Adjust ISA group for icall, ijmp, pop and push.
354 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
355
00b32ff2
NC		 3562014-05-19 Nick Clifton <nickc@redhat.com>
357
358 * msp430.h (struct msp430_operand_s): Add vshift field.
359
ae52f483
AB		 3602014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
361
362 * mips.h (INSN_ISA_MASK): Updated.
363 (INSN_ISA32R3): New define.
364 (INSN_ISA32R5): New define.
365 (INSN_ISA64R3): New define.
366 (INSN_ISA64R5): New define.
367 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
368 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
369 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
370 mips64r5.
371 (INSN_UPTO32R3): New define.
372 (INSN_UPTO32R5): New define.
373 (INSN_UPTO64R3): New define.
374 (INSN_UPTO64R5): New define.
375 (ISA_MIPS32R3): New define.
376 (ISA_MIPS32R5): New define.
377 (ISA_MIPS64R3): New define.
378 (ISA_MIPS64R5): New define.
379 (CPU_MIPS32R3): New define.
380 (CPU_MIPS32R5): New define.
381 (CPU_MIPS64R3): New define.
382 (CPU_MIPS64R5): New define.
383
3efe9ec5
RS		 3842014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
385
386 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
387
73589c9d
CS		 3882014-04-22 Christian Svensson <blue@cmd.nu>
389
390 * or32.h: Delete.
391
4b95cf5c
AM		 3922014-03-05 Alan Modra <amodra@gmail.com>
393
394 Update copyright years.
395
e269fea7
AB		 3962013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
397
398 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
399 microMIPS.
400
35c08157
KLC		 4012013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
402 Wei-Cheng Wang <cole945@gmail.com>
403
404 * nds32.h: New file for Andes NDS32.
405
594d8fa8
MF		 4062013-12-07 Mike Frysinger <vapier@gentoo.org>
407
408 * bfin.h: Remove +x file mode.
409
87b8eed7
YZ		 4102013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
411
412 * aarch64.h (aarch64_pstatefields): Change element type to
413 aarch64_sys_reg.
414
c9fb6e58
YZ		 4152013-11-18 Renlin Li <Renlin.Li@arm.com>
416
417 * arm.h (ARM_AEXT_V7VE): New define.
418 (ARM_ARCH_V7VE): New define.
419 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
420
a203d9b7
YZ		 4212013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
422
423 Revert
424
425 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
426
427 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
428 (aarch64_sys_reg_writeonly_p): Ditto.
429
75468c93
YZ		 4302013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
431
432 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
433 (aarch64_sys_reg_writeonly_p): Ditto.
434
49eec193
YZ		 4352013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
436
437 * aarch64.h (aarch64_sys_reg): New typedef.
438 (aarch64_sys_regs): Change to define with the new type.
439 (aarch64_sys_reg_deprecated_p): Declare.
440
68a64283
YZ		 4412013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
442
443 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
444 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
445
387a82f1
CF		 4462013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
447
448 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
449 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
450 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
451 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
452 For MIPS, update extension character sequences after +.
453 (ASE_MSA): New define.
454 (ASE_MSA64): New define.
455 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
456 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
457 For microMIPS, update extension character sequences after +.
458
9aff4b7a
NC		 4592013-08-23 Yuri Chornoivan <yurchor@ukr.net>
460
461 PR binutils/15834
462 * i960.h: Fix typos.
463
e423441d
RS		 4642013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
465
466 * mips.h: Remove references to "+I" and imm2_expr.
467
5e0dc5ba
RS		 4682013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
469
470 * mips.h (M_DEXT, M_DINS): Delete.
471
0f35dbc4
RS		 4722013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
473
474 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
475 (mips_optional_operand_p): New function.
476
14daeee3
RS		 4772013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
478 Richard Sandiford <rdsandiford@googlemail.com>
479
480 * mips.h: Document new VU0 operand characters.
481 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
482 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
483 (OP_REG_R5900_ACC): New mips_reg_operand_types.
484 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
485 (mips_vu0_channel_mask): Declare.
486
3ccad066
RS		 4872013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
488
489 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
490 (mips_int_operand_min, mips_int_operand_max): New functions.
491 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
492
fc76e730
RS		 4932013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
494
495 * mips.h (mips_decode_reg_operand): New function.
496 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
497 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
498 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
499 New macros.
500 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
501 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
502 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
503 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
504 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
505 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
506 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
507 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
508 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
509 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
510 macros to cover the gaps.
511 (INSN2_MOD_SP): Replace with...
512 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
513 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
514 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
515 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
516 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
517 Delete.
518
26545944
RS		 5192013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
520
521 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
522 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
523 (MIPS16_INSN_COND_BRANCH): Delete.
524
7e8b059b
L		 5252013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
526 Kirill Yukhin <kirill.yukhin@intel.com>
527 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
528
529 * i386.h (BND_PREFIX_OPCODE): New.
530
c3c07478
RS		 5312013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
532
533 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
534 OP_SAVE_RESTORE_LIST.
535 (decode_mips16_operand): Declare.
536
ab902481
RS		 5372013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
538
539 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
540 (mips_operand, mips_int_operand, mips_mapped_int_operand)
541 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
542 (mips_pcrel_operand): New structures.
543 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
544 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
545 (decode_mips_operand, decode_micromips_operand): Declare.
546
cc537e56
RS		 5472013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
548
549 * mips.h: Document MIPS16 "I" opcode.
550
f2ae14a1
RS		 5512013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
552
553 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
554 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
555 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
556 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
557 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
558 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
559 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
560 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
561 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
562 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
563 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
564 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
565 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
566 Rename to...
567 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
568 (M_USD_AB): ...these.
569
5c324c16
RS		 5702013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
571
572 * mips.h: Remove documentation of "[" and "]". Update documentation
573 of "k" and the MDMX formats.
574
23e69e47
RS		 5752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
576
577 * mips.h: Update documentation of "+s" and "+S".
578
27c5c572
RS		 5792013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
580
581 * mips.h: Document "+i".
582
e76ff5ab
RS		 5832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
584
585 * mips.h: Remove "mi" documentation. Update "mh" documentation.
586 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
587 Delete.
588 (INSN2_WRITE_GPR_MHI): Rename to...
589 (INSN2_WRITE_GPR_MH): ...this.
590
fa7616a4
RS		 5912013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
592
593 * mips.h: Remove documentation of "+D" and "+T".
594
18870af7
RS		 5952013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
596
597 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
598 Use "source" rather than "destination" for microMIPS "G".
599
833794fc
MR		 6002013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
601
602 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
603 values.
604
c3678916
RS		 6052013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
606
607 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
608
7f3c4072
CM		 6092013-06-17 Catherine Moore <clm@codesourcery.com>
610 Maciej W. Rozycki <macro@codesourcery.com>
611 Chao-Ying Fu <fu@mips.com>
612
613 * mips.h (OP_SH_EVAOFFSET): Define.
614 (OP_MASK_EVAOFFSET): Define.
615 (INSN_ASE_MASK): Delete.
616 (ASE_EVA): Define.
617 (M_CACHEE_AB, M_CACHEE_OB): New.
618 (M_LBE_OB, M_LBE_AB): New.
619 (M_LBUE_OB, M_LBUE_AB): New.
620 (M_LHE_OB, M_LHE_AB): New.
621 (M_LHUE_OB, M_LHUE_AB): New.
622 (M_LLE_AB, M_LLE_OB): New.
623 (M_LWE_OB, M_LWE_AB): New.
624 (M_LWLE_AB, M_LWLE_OB): New.
625 (M_LWRE_AB, M_LWRE_OB): New.
626 (M_PREFE_AB, M_PREFE_OB): New.
627 (M_SCE_AB, M_SCE_OB): New.
628 (M_SBE_OB, M_SBE_AB): New.
629 (M_SHE_OB, M_SHE_AB): New.
630 (M_SWE_OB, M_SWE_AB): New.
631 (M_SWLE_AB, M_SWLE_OB): New.
632 (M_SWRE_AB, M_SWRE_OB): New.
633 (MICROMIPSOP_SH_EVAOFFSET): Define.
634 (MICROMIPSOP_MASK_EVAOFFSET): Define.
635
0c8fe7cf
SL		 6362013-06-12 Sandra Loosemore <sandra@codesourcery.com>
637
638 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
639
c77c0862
RS		 6402013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
641
642 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
643
b015e599
AP		 6442013-05-09 Andrew Pinski <apinski@cavium.com>
645
646 * mips.h (OP_MASK_CODE10): Correct definition.
647 (OP_SH_CODE10): Likewise.
648 Add a comment that "+J" is used now for OP_*CODE10.
649 (INSN_ASE_MASK): Update.
650 (INSN_VIRT): New macro.
651 (INSN_VIRT64): New macro
652
13761a11
NC		 6532013-05-02 Nick Clifton <nickc@redhat.com>
654
655 * msp430.h: Add patterns for MSP430X instructions.
656
0afd1215
DM		 6572013-04-06 David S. Miller <davem@davemloft.net>
658
659 * sparc.h (F_PREFERRED): Define.
660 (F_PREF_ALIAS): Define.
661
41702d50
NC		 6622013-04-03 Nick Clifton <nickc@redhat.com>
663
664 * v850.h (V850_INVERSE_PCREL): Define.
665
e21e1a51
NC		 6662013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
667
668 PR binutils/15068
669 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
670
51dcdd4d
NC		 6712013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
672
673 PR binutils/15068
674 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
675 Add 16-bit opcodes.
676 * tic6xc-opcode-table.h: Add 16-bit insns.
677 * tic6x.h: Add support for 16-bit insns.
678
81f5558e
NC		 6792013-03-21 Michael Schewe <michael.schewe@gmx.net>
680
681 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
682 and mov.b/w/l Rs,@(d:32,ERd).
683
165546ad
NC		 6842013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
685
686 PR gas/15082
687 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
688 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
689 tic6x_operand_xregpair operand coding type.
690 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
691 opcode field, usu ORXREGD1324 for the src2 operand and remove the
692 TIC6X_FLAG_NO_CROSS.
693
795b8e6b
NC		 6942013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
695
696 PR gas/15095
697 * tic6x.h (enum tic6x_coding_method): Add
698 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
699 separately the msb and lsb of a register pair. This is needed to
700 encode the opcodes in the same way as TI assembler does.
701 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
702 and rsqrdp opcodes to use the new field coding types.
703
dd5181d5
KT		 7042013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
705
706 * arm.h (CRC_EXT_ARMV8): New constant.
707 (ARCH_CRC_ARMV8): New macro.
708
e60bb1dd
YZ		 7092013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
710
711 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
712
36591ba1 7132013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 714 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 715
716 Based on patches from Altera Corporation.
717
718 * nios2.h: New file.
719
e30181a5
YZ		 7202013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
721
722 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
723
0c9573f4
NC		 7242013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
725
726 PR gas/15069
727 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
728
981dc7f1
NC		 7292013-01-24 Nick Clifton <nickc@redhat.com>
730
731 * v850.h: Add e3v5 support.
732
f5555712
YZ		 7332013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
734
735 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
736
5817ffd1
PB		 7372013-01-10 Peter Bergner <bergner@vnet.ibm.com>
738
739 * ppc.h (PPC_OPCODE_POWER8): New define.
740 (PPC_OPCODE_HTM): Likewise.
741
a3c62988
NC		 7422013-01-10 Will Newton <will.newton@imgtec.com>
743
744 * metag.h: New file.
745
73335eae
NC		 7462013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
747
748 * cr16.h (make_instruction): Rename to cr16_make_instruction.
749 (match_opcode): Rename to cr16_match_opcode.
750
e407c74b
NC		 7512013-01-04 Juergen Urban <JuergenUrban@gmx.de>
752
753 * mips.h: Add support for r5900 instructions including lq and sq.
754
bab4becb
NC		 7552013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
756
757 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
758 (make_instruction,match_opcode): Added function prototypes.
759 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
760
776fc418
AM		 7612012-11-23 Alan Modra <amodra@gmail.com>
762
763 * ppc.h (ppc_parse_cpu): Update prototype.
764
f05682d4
DA		 7652012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
766
767 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
768 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
769
cfc72779
AK		 7702012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
771
772 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
773
b3e14eda
L		 7742012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
775
776 * ia64.h (ia64_opnd): Add new operand types.
777
2c63854f
DM		 7782012-08-21 David S. Miller <davem@davemloft.net>
779
780 * sparc.h (F3F4): New macro.
781
a06ea964 7822012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 783 Laurent Desnogues <laurent.desnogues@arm.com>
784 Jim MacArthur <jim.macarthur@arm.com>
785 Marcus Shawcroft <marcus.shawcroft@arm.com>
786 Nigel Stephens <nigel.stephens@arm.com>
787 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
788 Richard Earnshaw <rearnsha@arm.com>
789 Sofiane Naci <sofiane.naci@arm.com>
790 Tejas Belagod <tejas.belagod@arm.com>
791 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 792
793 * aarch64.h: New file.
794
35d0a169 7952012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 796 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 797
798 * mips.h (mips_opcode): Add the exclusions field.
799 (OPCODE_IS_MEMBER): Remove macro.
800 (cpu_is_member): New inline function.
801 (opcode_is_member): Likewise.
802
03f66e8a 8032012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 804 Catherine Moore <clm@codesourcery.com>
805 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 806
807 * mips.h: Document microMIPS DSP ASE usage.
808 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
809 microMIPS DSP ASE support.
810 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
811 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
812 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
813 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
814 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
815 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
816 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
817
9d7b4c23
MR		 8182012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
819
820 * mips.h: Fix a typo in description.
821
76e879f8
NC		 8222012-06-07 Georg-Johann Lay <avr@gjlay.de>
823
824 * avr.h: (AVR_ISA_XCH): New define.
825 (AVR_ISA_XMEGA): Use it.
826 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
827
6927f982
NC		 8282012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
829
830 * m68hc11.h: Add XGate definitions.
831 (struct m68hc11_opcode): Add xg_mask field.
832
b9c361e0
JL		 8332012-05-14 Catherine Moore <clm@codesourcery.com>
834 Maciej W. Rozycki <macro@codesourcery.com>
835 Rhonda Wittels <rhonda@codesourcery.com>
836
6927f982 837 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 838 (PPC_OP_SA): New macro.
839 (PPC_OP_SE_VLE): New macro.
840 (PPC_OP): Use a variable shift amount.
841 (powerpc_operand): Update comments.
842 (PPC_OPSHIFT_INV): New macro.
843 (PPC_OPERAND_CR): Replace with...
844 (PPC_OPERAND_CR_BIT): ...this and
845 (PPC_OPERAND_CR_REG): ...this.
846
847
f6c1a2d5
NC		 8482012-05-03 Sean Keys <skeys@ipdatasys.com>
849
850 * xgate.h: Header file for XGATE assembler.
851
ec668d69
DM		 8522012-04-27 David S. Miller <davem@davemloft.net>
853
6cda1326
DM		 854 * sparc.h: Document new arg code' )' for crypto RS3
855 immediates.
856
ec668d69
DM		 857 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
858 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
859 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
860 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
861 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
862 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
863 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
864 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
865 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
866 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
867 HWCAP_CBCOND, HWCAP_CRC32): New defines.
868
aea77599
AM		 8692012-03-10 Edmar Wienskoski <edmar@freescale.com>
870
871 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
872
1f42f8b3
AM		 8732012-02-27 Alan Modra <amodra@gmail.com>
874
875 * crx.h (cst4_map): Update declaration.
876
6f7be959
WL		 8772012-02-25 Walter Lee <walt@tilera.com>
878
879 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
880 TILEGX_OPC_LD_TLS.
881 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
882 TILEPRO_OPC_LW_TLS_SN.
883
42164a71
L		 8842012-02-08 H.J. Lu <hongjiu.lu@intel.com>
885
886 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
887 (XRELEASE_PREFIX_OPCODE): Likewise.
888
432233b3 8892011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 890 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 891
892 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
893 (INSN_OCTEON2): New macro.
894 (CPU_OCTEON2): New macro.
895 (OPCODE_IS_MEMBER): Add Octeon2.
896
dd6a37e7
AP		 8972011-11-29 Andrew Pinski <apinski@cavium.com>
898
899 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
900 (INSN_OCTEONP): New macro.
901 (CPU_OCTEONP): New macro.
902 (OPCODE_IS_MEMBER): Add Octeon+.
903 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
904
99c513f6
DD		 9052011-11-01 DJ Delorie <dj@redhat.com>
906
907 * rl78.h: New file.
908
26f85d7a
MR		 9092011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
910
911 * mips.h: Fix a typo in description.
912
9e8c70f9
DM		 9132011-09-21 David S. Miller <davem@davemloft.net>
914
915 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
916 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
917 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
918 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
919
dec0624d 9202011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 921 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 922
923 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
924 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
925 (INSN_ASE_MASK): Add the MCU bit.
926 (INSN_MCU): New macro.
927 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
928 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
929
2b0c8b40
MR		 9302011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
931
932 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
933 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
934 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
935 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
936 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
937 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
938 (INSN2_READ_GPR_MMN): Likewise.
939 (INSN2_READ_FPR_D): Change the bit used.
940 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
941 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
942 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
943 (INSN2_COND_BRANCH): Likewise.
944 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
945 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
946 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
947 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
948 (INSN2_MOD_GPR_MN): Likewise.
949
ea783ef3
DM		 9502011-08-05 David S. Miller <davem@davemloft.net>
951
952 * sparc.h: Document new format codes '4', '5', and '('.
953 (OPF_LOW4, RS3): New macros.
954
7c176fa8
MR		 9552011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
956
957 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
958 order of flags documented.
959
2309ddf2
MR		 9602011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
961
962 * mips.h: Clarify the description of microMIPS instruction
963 manipulation macros.
964 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
965
df58fc94 9662011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 967 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 968
969 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
970 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
971 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
972 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
973 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
974 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
975 (OP_MASK_RS3, OP_SH_RS3): Likewise.
976 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
977 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
978 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
979 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
980 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
981 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
982 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
983 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
984 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
985 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
986 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
987 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
988 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
989 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
990 (INSN_WRITE_GPR_S): New macro.
991 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
992 (INSN2_READ_FPR_D): Likewise.
993 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
994 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
995 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
996 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
997 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
998 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
999 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1000 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1001 (CPU_MICROMIPS): New macro.
1002 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1003 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1004 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1005 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1006 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1007 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1008 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1009 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1010 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1011 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1012 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1013 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1014 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1015 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1016 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1017 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1018 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1019 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1020 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1021 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1022 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1023 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1024 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1025 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1026 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1027 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1028 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1029 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1030 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1031 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1032 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1033 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1034 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1035 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1036 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1037 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1038 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1039 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1040 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1041 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1042 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1043 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1044 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1045 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1046 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1047 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1048 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1049 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1050 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1051 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1052 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1053 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1054 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1055 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1056 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1057 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1058 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1059 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1060 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1061 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1062 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1063 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1064 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1065 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1066 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1067 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1068 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1069 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1070 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1071 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1072 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1073 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1074 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1075 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1076 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1077 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1078 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1079 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1080 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1081 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1082 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1083 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1084 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1085 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1086 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1087 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1088 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1089 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1090 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1091 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1092 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1093 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1094 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1095 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1096 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1097 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1098 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1099 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1100 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1101 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1102 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1103 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1104 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1105 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1106 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1107 (micromips_opcodes): New declaration.
1108 (bfd_micromips_num_opcodes): Likewise.
1109
bcd530a7
RS		 11102011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1111
1112 * mips.h (INSN_TRAP): Rename to...
1113 (INSN_NO_DELAY_SLOT): ... this.
1114 (INSN_SYNC): Remove macro.
1115
2dad5a91
EW		 11162011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1117
1118 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1119 a duplicate of AVR_ISA_SPM.
1120
5d73b1f1
NC		 11212011-07-01 Nick Clifton <nickc@redhat.com>
1122
1123 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1124
ef26d60e
MF		 11252011-06-18 Robin Getz <robin.getz@analog.com>
1126
1127 * bfin.h (is_macmod_signed): New func
1128
8fb8dca7
MF		 11292011-06-18 Mike Frysinger <vapier@gentoo.org>
1130
1131 * bfin.h (is_macmod_pmove): Add missing space before func args.
1132 (is_macmod_hmove): Likewise.
1133
aa137e4d
NC		 11342011-06-13 Walter Lee <walt@tilera.com>
1135
1136 * tilegx.h: New file.
1137 * tilepro.h: New file.
1138
3b2f0793
PB		 11392011-05-31 Paul Brook <paul@codesourcery.com>
1140
aa137e4d
NC		 1141 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1142
11432011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1144
1145 * s390.h: Replace S390_OPERAND_REG_EVEN with
1146 S390_OPERAND_REG_PAIR.
1147
11482011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1149
1150 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1151
ac7f631b
NC		 11522011-04-18 Julian Brown <julian@codesourcery.com>
1153
1154 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1155
84701018
NC		 11562011-04-11 Dan McDonald <dan@wellkeeper.com>
1157
1158 PR gas/12296
1159 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1160
8cc66334
EW		 11612011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1162
1163 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1164 New instruction set flags.
1165 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1166
3eebd5eb
MR		 11672011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1168
1169 * mips.h (M_PREF_AB): New enum value.
1170
26bb3ddd
MF		 11712011-02-12 Mike Frysinger <vapier@gentoo.org>
1172
89c0d58c
MR		 1173 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1174 M_IU): Define.
1175 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1176
dd76fcb8
MF		 11772011-02-11 Mike Frysinger <vapier@gentoo.org>
1178
1179 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1180
98d23bef
BS		 11812011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1182
1183 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1184 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1185
3c853d93
DA		 11862010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1187
1188 PR gas/11395
1189 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1190 "bb" entries.
1191
79676006
DA		 11922010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1193
1194 PR gas/11395
1195 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1196
1bec78e9
RS		 11972010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1198
1199 * mips.h: Update commentary after last commit.
1200
98675402
RS		 12012010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1202
1203 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1204 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1205 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1206
aa137e4d
NC		 12072010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1208
1209 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1210
435b94a4
RS		 12112010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1212
1213 * mips.h: Fix previous commit.
1214
d051516a
NC		 12152010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1216
1217 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1218 (INSN_LOONGSON_3A): Clear bit 31.
1219
251665fc
MGD		 12202010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1221
1222 PR gas/12198
1223 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1224 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1225 (ARM_ARCH_V6M_ONLY): New define.
1226
fd503541
NC		 12272010-11-11 Mingming Sun <mingm.sun@gmail.com>
1228
1229 * mips.h (INSN_LOONGSON_3A): Defined.
1230 (CPU_LOONGSON_3A): Defined.
1231 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1232
4469d2be
AM		 12332010-10-09 Matt Rice <ratmice@gmail.com>
1234
1235 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1236 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1237
90ec0d68
MGD		 12382010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1239
1240 * arm.h (ARM_EXT_VIRT): New define.
1241 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1242 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1243 Extensions.
1244
eea54501 12452010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1246
eea54501
MGD		 1247 * arm.h (ARM_AEXT_ADIV): New define.
1248 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1249
b2a5fbdc
MGD		 12502010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1251
1252 * arm.h (ARM_EXT_OS): New define.
1253 (ARM_AEXT_V6SM): Likewise.
1254 (ARM_ARCH_V6SM): Likewise.
1255
60e5ef9f
MGD		 12562010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1257
1258 * arm.h (ARM_EXT_MP): Add.
1259 (ARM_ARCH_V7A_MP): Likewise.
1260
73a63ccf
MF		 12612010-09-22 Mike Frysinger <vapier@gentoo.org>
1262
1263 * bfin.h: Declare pseudoChr structs/defines.
1264
ee99860a
MF		 12652010-09-21 Mike Frysinger <vapier@gentoo.org>
1266
1267 * bfin.h: Strip trailing whitespace.
1268
f9c7014e
DD		 12692010-07-29 DJ Delorie <dj@redhat.com>
1270
1271 * rx.h (RX_Operand_Type): Add TwoReg.
1272 (RX_Opcode_ID): Remove ediv and ediv2.
1273
93378652
DD		 12742010-07-27 DJ Delorie <dj@redhat.com>
1275
1276 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1277
1cd986c5
NC		 12782010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1279 Ina Pandit <ina.pandit@kpitcummins.com>
1280
1281 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1282 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1283 PROCESSOR_V850E2_ALL.
1284 Remove PROCESSOR_V850EA support.
1285 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1286 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1287 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1288 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1289 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1290 V850_OPERAND_PERCENT.
1291 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1292 V850_NOT_R0.
1293 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1294 and V850E_PUSH_POP
1295
9a2c7088
MR		 12962010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1297
1298 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1299 (MIPS16_INSN_BRANCH): Rename to...
1300 (MIPS16_INSN_COND_BRANCH): ... this.
1301
bdc70b4a
AM		 13022010-07-03 Alan Modra <amodra@gmail.com>
1303
1304 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1305 Renumber other PPC_OPCODE defines.
1306
f2bae120
AM		 13072010-07-03 Alan Modra <amodra@gmail.com>
1308
1309 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1310
360cfc9c
AM		 13112010-06-29 Alan Modra <amodra@gmail.com>
1312
1313 * maxq.h: Delete file.
1314
e01d869a
AM		 13152010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1316
1317 * ppc.h (PPC_OPCODE_E500): Define.
1318
f79e2745
CM		 13192010-05-26 Catherine Moore <clm@codesourcery.com>
1320
1321 * opcode/mips.h (INSN_MIPS16): Remove.
1322
2462afa1
JM		 13232010-04-21 Joseph Myers <joseph@codesourcery.com>
1324
1325 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1326
e4e42b45
NC		 13272010-04-15 Nick Clifton <nickc@redhat.com>
1328
1329 * alpha.h: Update copyright notice to use GPLv3.
1330 * arc.h: Likewise.
1331 * arm.h: Likewise.
1332 * avr.h: Likewise.
1333 * bfin.h: Likewise.
1334 * cgen.h: Likewise.
1335 * convex.h: Likewise.
1336 * cr16.h: Likewise.
1337 * cris.h: Likewise.
1338 * crx.h: Likewise.
1339 * d10v.h: Likewise.
1340 * d30v.h: Likewise.
1341 * dlx.h: Likewise.
1342 * h8300.h: Likewise.
1343 * hppa.h: Likewise.
1344 * i370.h: Likewise.
1345 * i386.h: Likewise.
1346 * i860.h: Likewise.
1347 * i960.h: Likewise.
1348 * ia64.h: Likewise.
1349 * m68hc11.h: Likewise.
1350 * m68k.h: Likewise.
1351 * m88k.h: Likewise.
1352 * maxq.h: Likewise.
1353 * mips.h: Likewise.
1354 * mmix.h: Likewise.
1355 * mn10200.h: Likewise.
1356 * mn10300.h: Likewise.
1357 * msp430.h: Likewise.
1358 * np1.h: Likewise.
1359 * ns32k.h: Likewise.
1360 * or32.h: Likewise.
1361 * pdp11.h: Likewise.
1362 * pj.h: Likewise.
1363 * pn.h: Likewise.
1364 * ppc.h: Likewise.
1365 * pyr.h: Likewise.
1366 * rx.h: Likewise.
1367 * s390.h: Likewise.
1368 * score-datadep.h: Likewise.
1369 * score-inst.h: Likewise.
1370 * sparc.h: Likewise.
1371 * spu-insns.h: Likewise.
1372 * spu.h: Likewise.
1373 * tic30.h: Likewise.
1374 * tic4x.h: Likewise.
1375 * tic54x.h: Likewise.
1376 * tic80.h: Likewise.
1377 * v850.h: Likewise.
1378 * vax.h: Likewise.
1379
40b36596
JM		 13802010-03-25 Joseph Myers <joseph@codesourcery.com>
1381
1382 * tic6x-control-registers.h, tic6x-insn-formats.h,
1383 tic6x-opcode-table.h, tic6x.h: New.
1384
c67a084a
NC		 13852010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1386
1387 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1388
466ef64f
AM		 13892010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1390
1391 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1392
1319d143
L		 13932010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1394
1395 * ia64.h (ia64_find_opcode): Remove argument name.
1396 (ia64_find_next_opcode): Likewise.
1397 (ia64_dis_opcode): Likewise.
1398 (ia64_free_opcode): Likewise.
1399 (ia64_find_dependency): Likewise.
1400
1fbb9298
DE		 14012009-11-22 Doug Evans <dje@sebabeach.org>
1402
1403 * cgen.h: Include bfd_stdint.h.
1404 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1405
ada65aa3
PB		 14062009-11-18 Paul Brook <paul@codesourcery.com>
1407
1408 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1409
9e3c6df6
PB		 14102009-11-17 Paul Brook <paul@codesourcery.com>
1411 Daniel Jacobowitz <dan@codesourcery.com>
1412
1413 * arm.h (ARM_EXT_V6_DSP): Define.
1414 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1415 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1416
0d734b5d
DD		 14172009-11-04 DJ Delorie <dj@redhat.com>
1418
1419 * rx.h (rx_decode_opcode) (mvtipl): Add.
1420 (mvtcp, mvfcp, opecp): Remove.
1421
62f3b8c8
PB		 14222009-11-02 Paul Brook <paul@codesourcery.com>
1423
1424 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1425 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1426 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1427 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1428 FPU_ARCH_NEON_VFP_V4): Define.
1429
ac1e9eca
DE		 14302009-10-23 Doug Evans <dje@sebabeach.org>
1431
1432 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1433 * cgen.h: Update. Improve multi-inclusion macro name.
1434
9fe54b1c
PB		 14352009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1436
1437 * ppc.h (PPC_OPCODE_476): Define.
1438
634b50f2
PB		 14392009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1440
1441 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1442
c7927a3c
NC		 14432009-09-29 DJ Delorie <dj@redhat.com>
1444
1445 * rx.h: New file.
1446
b961e85b
AM		 14472009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1448
1449 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1450
e0d602ec
BE		 14512009-09-21 Ben Elliston <bje@au.ibm.com>
1452
1453 * ppc.h (PPC_OPCODE_PPCA2): New.
1454
96d56e9f
NC		 14552009-09-05 Martin Thuresson <martin@mtme.org>
1456
1457 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1458
d3ce72d0
NC		 14592009-08-29 Martin Thuresson <martin@mtme.org>
1460
1461 * tic30.h (template): Rename type template to
1462 insn_template. Updated code to use new name.
1463 * tic54x.h (template): Rename type template to
1464 insn_template.
1465
824b28db
NH		 14662009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1467
1468 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1469
f865a31d
AG		 14702009-06-11 Anthony Green <green@moxielogic.com>
1471
1472 * moxie.h (MOXIE_F3_PCREL): Define.
1473 (moxie_form3_opc_info): Grow.
1474
0e7c7f11
AG		 14752009-06-06 Anthony Green <green@moxielogic.com>
1476
1477 * moxie.h (MOXIE_F1_M): Define.
1478
20135e4c
NC		 14792009-04-15 Anthony Green <green@moxielogic.com>
1480
1481 * moxie.h: Created.
1482
bcb012d3
DD		 14832009-04-06 DJ Delorie <dj@redhat.com>
1484
1485 * h8300.h: Add relaxation attributes to MOVA opcodes.
1486
69fe9ce5
AM		 14872009-03-10 Alan Modra <amodra@bigpond.net.au>
1488
1489 * ppc.h (ppc_parse_cpu): Declare.
1490
c3b7224a
NC		 14912009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1492
1493 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1494 and _IMM11 for mbitclr and mbitset.
1495 * score-datadep.h: Update dependency information.
1496
066be9f7
PB		 14972009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1498
1499 * ppc.h (PPC_OPCODE_POWER7): New.
1500
fedc618e
DE		 15012009-02-06 Doug Evans <dje@google.com>
1502
1503 * i386.h: Add comment regarding sse* insns and prefixes.
1504
52b6b6b9
JM		 15052009-02-03 Sandip Matte <sandip@rmicorp.com>
1506
1507 * mips.h (INSN_XLR): Define.
1508 (INSN_CHIP_MASK): Update.
1509 (CPU_XLR): Define.
1510 (OPCODE_IS_MEMBER): Update.
1511 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1512
35669430
DE		 15132009-01-28 Doug Evans <dje@google.com>
1514
1515 * opcode/i386.h: Add multiple inclusion protection.
1516 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1517 (EDI_REG_NUM): New macros.
1518 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1519 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1520 (REX_PREFIX_P): New macro.
35669430 1521
1cb0a767
PB		 15222009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1523
1524 * ppc.h (struct powerpc_opcode): New field "deprecated".
1525 (PPC_OPCODE_NOPOWER4): Delete.
1526
3aa3176b
TS		 15272008-11-28 Joshua Kinard <kumba@gentoo.org>
1528
1529 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1530 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1531
8e79c3df
CM		 15322008-11-18 Catherine Moore <clm@codesourcery.com>
1533
1534 * arm.h (FPU_NEON_FP16): New.
1535 (FPU_ARCH_NEON_FP16): New.
1536
de9a3e51
CF		 15372008-11-06 Chao-ying Fu <fu@mips.com>
1538
1539 * mips.h: Doucument '1' for 5-bit sync type.
1540
1ca35711
L		 15412008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1542
1543 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1544 IA64_RS_CR.
1545
9b4e5766
PB		 15462008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1547
1548 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1549
081ba1b3
AM		 15502008-07-30 Michael J. Eager <eager@eagercon.com>
1551
1552 * ppc.h (PPC_OPCODE_405): Define.
1553 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1554
fa452fa6
PB		 15552008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1556
1557 * ppc.h (ppc_cpu_t): New typedef.
1558 (struct powerpc_opcode <flags>): Use it.
1559 (struct powerpc_operand <insert, extract>): Likewise.
1560 (struct powerpc_macro <flags>): Likewise.
1561
bb35fb24
NC		 15622008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1563
1564 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1565 Update comment before MIPS16 field descriptors to mention MIPS16.
1566 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1567 BBIT.
1568 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1569 New bit masks and shift counts for cins and exts.
1570
dd3cbb7e
NC		 1571 * mips.h: Document new field descriptors +Q.
1572 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1573
d0799671
AN		 15742008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1575
9aff4b7a 1576 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1577 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1578
19a6653c
AM		 15792008-04-14 Edmar Wienskoski <edmar@freescale.com>
1580
1581 * ppc.h: (PPC_OPCODE_E500MC): New.
1582
c0f3af97
L		 15832008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1584
1585 * i386.h (MAX_OPERANDS): Set to 5.
1586 (MAX_MNEM_SIZE): Changed to 20.
1587
e210c36b
NC		 15882008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1589
1590 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1591
b1cc4aeb
PB		 15922008-03-09 Paul Brook <paul@codesourcery.com>
1593
1594 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1595
7e806470
PB		 15962008-03-04 Paul Brook <paul@codesourcery.com>
1597
1598 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1599 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1600 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1601
7b2185f9 16022008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1603 Nick Clifton <nickc@redhat.com>
1604
1605 PR 3134
1606 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1607 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1608 set.
af7329f0 1609
796d5313
NC		 16102008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1611
1612 * cr16.h (cr16_num_optab): Declared.
1613
d669d37f
NC		 16142008-02-14 Hakan Ardo <hakan@debian.org>
1615
1616 PR gas/2626
1617 * avr.h (AVR_ISA_2xxe): Define.
1618
e6429699
AN		 16192008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1620
1621 * mips.h: Update copyright.
1622 (INSN_CHIP_MASK): New macro.
1623 (INSN_OCTEON): New macro.
1624 (CPU_OCTEON): New macro.
1625 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1626
e210c36b
NC		 16272008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1628
1629 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1630
16312008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1632
1633 * avr.h (AVR_ISA_USB162): Add new opcode set.
1634 (AVR_ISA_AVR3): Likewise.
1635
350cc38d
MS		 16362007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1637
1638 * mips.h (INSN_LOONGSON_2E): New.
1639 (INSN_LOONGSON_2F): New.
1640 (CPU_LOONGSON_2E): New.
1641 (CPU_LOONGSON_2F): New.
1642 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1643
56950294
MS		 16442007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1645
1646 * mips.h (INSN_ISA*): Redefine certain values as an
1647 enumeration. Update comments.
1648 (mips_isa_table): New.
1649 (ISA_MIPS*): Redefine to match enumeration.
1650 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1651 values.
1652
c3d65c1c
BE		 16532007-08-08 Ben Elliston <bje@au.ibm.com>
1654
1655 * ppc.h (PPC_OPCODE_PPCPS): New.
1656
0fdaa005
L		 16572007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1658
1659 * m68k.h: Document j K & E.
1660
16612007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1662
1663 * cr16.h: New file for CR16 target.
1664
3896c469
AM		 16652007-05-02 Alan Modra <amodra@bigpond.net.au>
1666
1667 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1668
9a2e615a
NS		 16692007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1670
1671 * m68k.h (mcfisa_c): New.
1672 (mcfusp, mcf_mask): Adjust.
1673
b84bf58a
AM		 16742007-04-20 Alan Modra <amodra@bigpond.net.au>
1675
1676 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1677 (num_powerpc_operands): Declare.
1678 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1679 (PPC_OPERAND_PLUS1): Define.
1680
831480e9 16812007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1682
1683 * i386.h (REX_MODE64): Renamed to ...
1684 (REX_W): This.
1685 (REX_EXTX): Renamed to ...
1686 (REX_R): This.
1687 (REX_EXTY): Renamed to ...
1688 (REX_X): This.
1689 (REX_EXTZ): Renamed to ...
1690 (REX_B): This.
1691
0b1cf022
L		 16922007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1693
1694 * i386.h: Add entries from config/tc-i386.h and move tables
1695 to opcodes/i386-opc.h.
1696
d796c0ad
L		 16972007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1698
1699 * i386.h (FloatDR): Removed.
1700 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1701
30ac7323
AM		 17022007-03-01 Alan Modra <amodra@bigpond.net.au>
1703
1704 * spu-insns.h: Add soma double-float insns.
1705
8b082fb1 17062007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1707 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1708
1709 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1710 (INSN_DSPR2): Add flag for DSP R2 instructions.
1711 (M_BALIGN): New macro.
1712
4eed87de
AM		 17132007-02-14 Alan Modra <amodra@bigpond.net.au>
1714
1715 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1716 and Seg3ShortFrom with Shortform.
1717
fda592e8
L		 17182007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1719
1720 PR gas/4027
1721 * i386.h (i386_optab): Put the real "test" before the pseudo
1722 one.
1723
3bdcfdf4
KH		 17242007-01-08 Kazu Hirata <kazu@codesourcery.com>
1725
1726 * m68k.h (m68010up): OR fido_a.
1727
9840d27e
KH		 17282006-12-25 Kazu Hirata <kazu@codesourcery.com>
1729
1730 * m68k.h (fido_a): New.
1731
c629cdac
KH		 17322006-12-24 Kazu Hirata <kazu@codesourcery.com>
1733
1734 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1735 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1736 values.
1737
b7d9ef37
L		 17382006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1739
1740 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1741
b138abaa
NC		 17422006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1743
1744 * score-inst.h (enum score_insn_type): Add Insn_internal.
1745
e9f53129
AM		 17462006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1747 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1748 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1749 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1750 Alan Modra <amodra@bigpond.net.au>
1751
1752 * spu-insns.h: New file.
1753 * spu.h: New file.
1754
ede602d7
AM		 17552006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1756
1757 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1758
7918206c
MM		 17592006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1760
e4e42b45 1761 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1762 in amdfam10 architecture.
1763
ef05d495
L		 17642006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1765
1766 * i386.h: Replace CpuMNI with CpuSSSE3.
1767
2d447fca 17682006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1769 Joseph Myers <joseph@codesourcery.com>
1770 Ian Lance Taylor <ian@wasabisystems.com>
1771 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1772
1773 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1774
1c0d3aa6
NC		 17752006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1776
1777 * score-datadep.h: New file.
1778 * score-inst.h: New file.
1779
c2f0420e
L		 17802006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1781
1782 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1783 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1784 movdq2q and movq2dq.
1785
050dfa73
MM		 17862006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1787 Michael Meissner <michael.meissner@amd.com>
1788
1789 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1790
15965411
L		 17912006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1792
1793 * i386.h (i386_optab): Add "nop" with memory reference.
1794
46e883c5
L		 17952006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1796
1797 * i386.h (i386_optab): Update comment for 64bit NOP.
1798
9622b051
AM		 17992006-06-06 Ben Elliston <bje@au.ibm.com>
1800 Anton Blanchard <anton@samba.org>
1801
1802 * ppc.h (PPC_OPCODE_POWER6): Define.
1803 Adjust whitespace.
1804
a9e24354
TS		 18052006-06-05 Thiemo Seufer <ths@mips.com>
1806
e4e42b45 1807 * mips.h: Improve description of MT flags.
a9e24354 1808
a596001e
RS		 18092006-05-25 Richard Sandiford <richard@codesourcery.com>
1810
1811 * m68k.h (mcf_mask): Define.
1812
d43b4baf 18132006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1814 David Ung <davidu@mips.com>
d43b4baf
TS		 1815
1816 * mips.h (enum): Add macro M_CACHE_AB.
1817
39a7806d 18182006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1819 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1820 David Ung <davidu@mips.com>
1821
1822 * mips.h: Add INSN_SMARTMIPS define.
1823
9bcd4f99 18242006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1825 David Ung <davidu@mips.com>
9bcd4f99
TS		 1826
1827 * mips.h: Defines udi bits and masks. Add description of
1828 characters which may appear in the args field of udi
1829 instructions.
1830
ef0ee844
TS		 18312006-04-26 Thiemo Seufer <ths@networkno.de>
1832
1833 * mips.h: Improve comments describing the bitfield instruction
1834 fields.
1835
f7675147
L		 18362006-04-26 Julian Brown <julian@codesourcery.com>
1837
1838 * arm.h (FPU_VFP_EXT_V3): Define constant.
1839 (FPU_NEON_EXT_V1): Likewise.
1840 (FPU_VFP_HARD): Update.
1841 (FPU_VFP_V3): Define macro.
1842 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1843
ef0ee844 18442006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1845
1846 * avr.h (AVR_ISA_PWMx): New.
1847
2da12c60
NS		 18482006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1849
1850 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1851 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1852 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1853 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1854 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1855
0715c387
PB		 18562006-03-10 Paul Brook <paul@codesourcery.com>
1857
1858 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1859
34bdd094
DA		 18602006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1861
1862 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1863 first. Correct mask of bb "B" opcode.
1864
331d2d0d
L		 18652006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1866
1867 * i386.h (i386_optab): Support Intel Merom New Instructions.
1868
62b3e311
PB		 18692006-02-24 Paul Brook <paul@codesourcery.com>
1870
1871 * arm.h: Add V7 feature bits.
1872
59cf82fe
L		 18732006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1874
1875 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1876
e74cfd16
PB		 18772006-01-31 Paul Brook <paul@codesourcery.com>
1878 Richard Earnshaw <rearnsha@arm.com>
1879
1880 * arm.h: Use ARM_CPU_FEATURE.
1881 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1882 (arm_feature_set): Change to a structure.
1883 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1884 ARM_FEATURE): New macros.
1885
5b3f8a92
HPN		 18862005-12-07 Hans-Peter Nilsson <hp@axis.com>
1887
1888 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1889 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1890 (ADD_PC_INCR_OPCODE): Don't define.
1891
cb712a9e
L		 18922005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1893
1894 PR gas/1874
1895 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1896
0499d65b
TS		 18972005-11-14 David Ung <davidu@mips.com>
1898
1899 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1900 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1901 save/restore encoding of the args field.
1902
ea5ca089
DB		 19032005-10-28 Dave Brolley <brolley@redhat.com>
1904
1905 Contribute the following changes:
1906 2005-02-16 Dave Brolley <brolley@redhat.com>
1907
1908 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1909 cgen_isa_mask_* to cgen_bitset_*.
1910 * cgen.h: Likewise.
1911
16175d96
DB		 1912 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1913
1914 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1915 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1916 (CGEN_CPU_TABLE): Make isas a ponter.
1917
1918 2003-09-29 Dave Brolley <brolley@redhat.com>
1919
1920 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1921 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1922 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1923
1924 2002-12-13 Dave Brolley <brolley@redhat.com>
1925
1926 * cgen.h (symcat.h): #include it.
1927 (cgen-bitset.h): #include it.
1928 (CGEN_ATTR_VALUE_TYPE): Now a union.
1929 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1930 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1931 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1932 * cgen-bitset.h: New file.
1933
3c9b82ba
NC		 19342005-09-30 Catherine Moore <clm@cm00re.com>
1935
1936 * bfin.h: New file.
1937
6a2375c6
JB		 19382005-10-24 Jan Beulich <jbeulich@novell.com>
1939
1940 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1941 indirect operands.
1942
c06a12f8
DA		 19432005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1944
1945 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1946 Add FLAG_STRICT to pa10 ftest opcode.
1947
4d443107
DA		 19482005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1949
1950 * hppa.h (pa_opcodes): Remove lha entries.
1951
f0a3b40f
DA		 19522005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1953
1954 * hppa.h (FLAG_STRICT): Revise comment.
1955 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1956 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1957 entries for "fdc".
1958
e210c36b
NC		 19592005-09-30 Catherine Moore <clm@cm00re.com>
1960
1961 * bfin.h: New file.
1962
1b7e1362
DA		 19632005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1964
1965 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1966
089b39de
CF		 19672005-09-06 Chao-ying Fu <fu@mips.com>
1968
1969 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1970 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1971 define.
1972 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1973 (INSN_ASE_MASK): Update to include INSN_MT.
1974 (INSN_MT): New define for MT ASE.
1975
93c34b9b
CF		 19762005-08-25 Chao-ying Fu <fu@mips.com>
1977
1978 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1979 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1980 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1981 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1982 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1983 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1984 instructions.
1985 (INSN_DSP): New define for DSP ASE.
1986
848cf006
AM		 19872005-08-18 Alan Modra <amodra@bigpond.net.au>
1988
1989 * a29k.h: Delete.
1990
36ae0db3
DJ		 19912005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1992
1993 * ppc.h (PPC_OPCODE_E300): Define.
1994
8c929562
MS		 19952005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1996
1997 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1998
f7b8cccc
DA		 19992005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2000
2001 PR gas/336
2002 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2003 and pitlb.
2004
8b5328ac
JB		 20052005-07-27 Jan Beulich <jbeulich@novell.com>
2006
2007 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2008 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2009 Add movq-s as 64-bit variants of movd-s.
2010
f417d200
DA		 20112005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2012
18b3bdfc
DA		 2013 * hppa.h: Fix punctuation in comment.
2014
f417d200
DA		 2015 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2016 implicit space-register addressing. Set space-register bits on opcodes
2017 using implicit space-register addressing. Add various missing pa20
2018 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2019 space-register addressing. Use "fE" instead of "fe" in various
2020 fstw opcodes.
2021
9a145ce6
JB		 20222005-07-18 Jan Beulich <jbeulich@novell.com>
2023
2024 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2025
90700ea2
L		 20262007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2027
2028 * i386.h (i386_optab): Support Intel VMX Instructions.
2029
48f130a8
DA		 20302005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2031
2032 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2033
30123838
JB		 20342005-07-05 Jan Beulich <jbeulich@novell.com>
2035
2036 * i386.h (i386_optab): Add new insns.
2037
47b0e7ad
NC		 20382005-07-01 Nick Clifton <nickc@redhat.com>
2039
2040 * sparc.h: Add typedefs to structure declarations.
2041
b300c311
L		 20422005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2043
2044 PR 1013
2045 * i386.h (i386_optab): Update comments for 64bit addressing on
2046 mov. Allow 64bit addressing for mov and movq.
2047
2db495be
DA		 20482005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2049
2050 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2051 respectively, in various floating-point load and store patterns.
2052
caa05036
DA		 20532005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2054
2055 * hppa.h (FLAG_STRICT): Correct comment.
2056 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2057 PA 2.0 mneumonics when equivalent. Entries with cache control
2058 completers now require PA 1.1. Adjust whitespace.
2059
f4411256
AM		 20602005-05-19 Anton Blanchard <anton@samba.org>
2061
2062 * ppc.h (PPC_OPCODE_POWER5): Define.
2063
e172dbf8
NC		 20642005-05-10 Nick Clifton <nickc@redhat.com>
2065
2066 * Update the address and phone number of the FSF organization in
2067 the GPL notices in the following files:
2068 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2069 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2070 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2071 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2072 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2073 tic54x.h, tic80.h, v850.h, vax.h
2074
e44823cf
JB		 20752005-05-09 Jan Beulich <jbeulich@novell.com>
2076
2077 * i386.h (i386_optab): Add ht and hnt.
2078
791fe849
MK		 20792005-04-18 Mark Kettenis <kettenis@gnu.org>
2080
2081 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2082 Add xcrypt-ctr. Provide aliases without hyphens.
2083
faa7ef87
L		 20842005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2085
a63027e5
L		 2086 Moved from ../ChangeLog
2087
faa7ef87
L		 2088 2005-04-12 Paul Brook <paul@codesourcery.com>
2089 * m88k.h: Rename psr macros to avoid conflicts.
2090
2091 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2092 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2093 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2094 and ARM_ARCH_V6ZKT2.
2095
2096 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2097 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2098 Remove redundant instruction types.
2099 (struct argument): X_op - new field.
2100 (struct cst4_entry): Remove.
2101 (no_op_insn): Declare.
2102
2103 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2104 * crx.h (enum argtype): Rename types, remove unused types.
2105
2106 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2107 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2108 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2109 (enum operand_type): Rearrange operands, edit comments.
2110 replace us<N> with ui<N> for unsigned immediate.
2111 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2112 displacements (respectively).
2113 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2114 (instruction type): Add NO_TYPE_INS.
2115 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2116 (operand_entry): New field - 'flags'.
2117 (operand flags): New.
2118
2119 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2120 * crx.h (operand_type): Remove redundant types i3, i4,
2121 i5, i8, i12.
2122 Add new unsigned immediate types us3, us4, us5, us16.
2123
bc4bd9ab
MK		 21242005-04-12 Mark Kettenis <kettenis@gnu.org>
2125
2126 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2127 adjust them accordingly.
2128
373ff435
JB		 21292005-04-01 Jan Beulich <jbeulich@novell.com>
2130
2131 * i386.h (i386_optab): Add rdtscp.
2132
4cc91dba
L		 21332005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2134
2135 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2136 between memory and segment register. Allow movq for moving between
2137 general-purpose register and segment register.
4cc91dba 2138
9ae09ff9
JB		 21392005-02-09 Jan Beulich <jbeulich@novell.com>
2140
2141 PR gas/707
2142 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2143 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2144 fnstsw.
2145
638e7a64
NS		 21462006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2147
2148 * m68k.h (m68008, m68ec030, m68882): Remove.
2149 (m68k_mask): New.
2150 (cpu_m68k, cpu_cf): New.
2151 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2152 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2153
90219bd0
AO		 21542005-01-25 Alexandre Oliva <aoliva@redhat.com>
2155
2156 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2157 * cgen.h (enum cgen_parse_operand_type): Add
2158 CGEN_PARSE_OPERAND_SYMBOLIC.
2159
239cb185
FF		 21602005-01-21 Fred Fish <fnf@specifixinc.com>
2161
2162 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2163 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2164 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2165
dc9a9f39
FF		 21662005-01-19 Fred Fish <fnf@specifixinc.com>
2167
2168 * mips.h (struct mips_opcode): Add new pinfo2 member.
2169 (INSN_ALIAS): New define for opcode table entries that are
2170 specific instances of another entry, such as 'move' for an 'or'
2171 with a zero operand.
2172 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2173 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2174
98e7aba8
ILT		 21752004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2176
2177 * mips.h (CPU_RM9000): Define.
2178 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2179
37edbb65
JB		 21802004-11-25 Jan Beulich <jbeulich@novell.com>
2181
2182 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2183 to/from test registers are illegal in 64-bit mode. Add missing
2184 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2185 (previously one had to explicitly encode a rex64 prefix). Re-enable
2186 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2187 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2188
21892004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2190
2191 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2192 available only with SSE2. Change the MMX additions introduced by SSE
2193 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2194 instructions by their now designated identifier (since combining i686
2195 and 3DNow! does not really imply 3DNow!A).
2196
f5c7edf4
AM		 21972004-11-19 Alan Modra <amodra@bigpond.net.au>
2198
2199 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2200 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2201
7499d566
NC		 22022004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2203 Vineet Sharma <vineets@noida.hcltech.com>
2204
2205 * maxq.h: New file: Disassembly information for the maxq port.
2206
bcb9eebe
L		 22072004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2208
2209 * i386.h (i386_optab): Put back "movzb".
2210
94bb3d38
HPN		 22112004-11-04 Hans-Peter Nilsson <hp@axis.com>
2212
2213 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2214 comments. Remove member cris_ver_sim. Add members
2215 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2216 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2217 (struct cris_support_reg, struct cris_cond15): New types.
2218 (cris_conds15): Declare.
2219 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2220 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2221 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2222 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2223 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2224 SIZE_FIELD_UNSIGNED.
2225
37edbb65 22262004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2227
2228 * i386.h (sldx_Suf): Remove.
2229 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2230 (q_FP): Define, implying no REX64.
2231 (x_FP, sl_FP): Imply FloatMF.
2232 (i386_optab): Split reg and mem forms of moving from segment registers
2233 so that the memory forms can ignore the 16-/32-bit operand size
2234 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2235 all non-floating-point instructions. Unite 32- and 64-bit forms of
2236 movsx, movzx, and movd. Adjust floating point operations for the above
2237 changes to the *FP macros. Add DefaultSize to floating point control
2238 insns operating on larger memory ranges. Remove left over comments
2239 hinting at certain insns being Intel-syntax ones where the ones
2240 actually meant are already gone.
2241
48c9f030
NC		 22422004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2243
2244 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2245 instruction type.
2246
0dd132b6
NC		 22472004-09-30 Paul Brook <paul@codesourcery.com>
2248
2249 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2250 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2251
23794b24
MM		 22522004-09-11 Theodore A. Roth <troth@openavr.org>
2253
2254 * avr.h: Add support for
2255 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2256
2a309db0
AM		 22572004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2258
2259 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2260
b18c562e
NC		 22612004-08-24 Dmitry Diky <diwil@spec.ru>
2262
2263 * msp430.h (msp430_opc): Add new instructions.
2264 (msp430_rcodes): Declare new instructions.
2265 (msp430_hcodes): Likewise..
2266
45d313cd
NC		 22672004-08-13 Nick Clifton <nickc@redhat.com>
2268
2269 PR/301
2270 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2271 processors.
2272
30d1c836
ML		 22732004-08-30 Michal Ludvig <mludvig@suse.cz>
2274
2275 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2276
9a45f1c2
L		 22772004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2278
2279 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2280
543613e9
NC		 22812004-07-21 Jan Beulich <jbeulich@novell.com>
2282
2283 * i386.h: Adjust instruction descriptions to better match the
2284 specification.
2285
b781e558
RE		 22862004-07-16 Richard Earnshaw <rearnsha@arm.com>
2287
2288 * arm.h: Remove all old content. Replace with architecture defines
2289 from gas/config/tc-arm.c.
2290
8577e690
AS		 22912004-07-09 Andreas Schwab <schwab@suse.de>
2292
2293 * m68k.h: Fix comment.
2294
1fe1f39c
NC		 22952004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2296
2297 * crx.h: New file.
2298
1d9f512f
AM		 22992004-06-24 Alan Modra <amodra@bigpond.net.au>
2300
2301 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2302
be8c092b
NC		 23032004-05-24 Peter Barada <peter@the-baradas.com>
2304
2305 * m68k.h: Add 'size' to m68k_opcode.
2306
6b6e92f4
NC		 23072004-05-05 Peter Barada <peter@the-baradas.com>
2308
2309 * m68k.h: Switch from ColdFire chip name to core variant.
2310
23112004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2312
2313 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2314 descriptions for new EMAC cases.
2315 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2316 handle Motorola MAC syntax.
2317 Allow disassembly of ColdFire V4e object files.
2318
fdd12ef3
AM		 23192004-03-16 Alan Modra <amodra@bigpond.net.au>
2320
2321 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2322
3922a64c
L		 23232004-03-12 Jakub Jelinek <jakub@redhat.com>
2324
2325 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2326
1f45d988
ML		 23272004-03-12 Michal Ludvig <mludvig@suse.cz>
2328
2329 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2330
0f10071e
ML		 23312004-03-12 Michal Ludvig <mludvig@suse.cz>
2332
2333 * i386.h (i386_optab): Added xstore/xcrypt insns.
2334
3255318a
NC		 23352004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2336
2337 * h8300.h (32bit ldc/stc): Add relaxing support.
2338
ca9a79a1 23392004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2340
ca9a79a1
NC		 2341 * h8300.h (BITOP): Pass MEMRELAX flag.
2342
875a0b14
NC		 23432004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2344
2345 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2346 except for the H8S.
252b5132 2347
c9e214e5 2348For older changes see ChangeLog-9103
252b5132 2349\f
b90efa5b 2350Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2351
2352Copying and distribution of this file, with or without modification,
2353are permitted in any medium without royalty provided the copyright
2354notice and this notice are preserved.
2355
252b5132 2356Local Variables:
c9e214e5
AM		 2357mode: change-log
2358left-margin: 8
2359fill-column: 74
252b5132
RH		 2360version-control: never
2361End:
GDB Binutils - Deliverables
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