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Allow for optional operands with non-zero default values.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
11a0cf2e
PB		 12015-06-19 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
4 (ppc_optional_operand_value): New inline function.
5
88f0ea34
MW		 62015-06-04 Matthew Wahab <matthew.wahab@arm.com>
7
8 * aarch64.h (AARCH64_V8_1): New.
9
a5932920
MW		 102015-06-03 Matthew Wahab <matthew.wahab@arm.com>
11
12 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
13 (ARM_ARCH_V8_1A): New.
14 (ARM_ARCH_V8_1A_FP): New.
15 (ARM_ARCH_V8_1A_SIMD): New.
16 (ARM_ARCH_V8_1A_CRYPTOV1): New.
17 (ARM_FEATURE_CORE): New.
18
ddfded2f
MW		 192015-06-02 Matthew Wahab <matthew.wahab@arm.com>
20
21 * arm.h (ARM_EXT2_PAN): New.
22 (ARM_FEATURE_CORE_HIGH): New.
23
1af1dd51
MW		 242015-06-02 Matthew Wahab <matthew.wahab@arm.com>
25
26 * arm.h (ARM_FEATURE_ALL): New.
27
9e1f0fa7
MW		 282015-06-02 Matthew Wahab <matthew.wahab@arm.com>
29
30 * aarch64.h (AARCH64_FEATURE_RDMA): New.
31
290806fd
MW		 322015-06-02 Matthew Wahab <matthew.wahab@arm.com>
33
34 * aarch64.h (AARCH64_FEATURE_LOR): New.
35
f21cce2c
MW		 362015-06-01 Matthew Wahab <matthew.wahab@arm.com>
37
38 * aarch64.h (AARCH64_FEATURE_PAN): New.
39 (aarch64_sys_reg_supported_p): Declare.
40 (aarch64_pstatefield_supported_p): Declare.
41
0952813b
DD		 422015-04-30 DJ Delorie <dj@redhat.com>
43
44 * rl78.h (RL78_Dis_Isa): New.
45 (rl78_decode_opcode): Add ISA parameter.
46
823d2571
TG		 472015-03-24 Terry Guo <terry.guo@arm.com>
48
49 * arm.h (arm_feature_set): Extended to provide more available bits.
50 (ARM_ANY): Updated to follow above new definition.
51 (ARM_CPU_HAS_FEATURE): Likewise.
52 (ARM_CPU_IS_ANY): Likewise.
53 (ARM_MERGE_FEATURE_SETS): Likewise.
54 (ARM_CLEAR_FEATURE): Likewise.
55 (ARM_FEATURE): Likewise.
56 (ARM_FEATURE_COPY): New macro.
57 (ARM_FEATURE_EQUAL): Likewise.
58 (ARM_FEATURE_ZERO): Likewise.
59 (ARM_FEATURE_CORE_EQUAL): Likewise.
60 (ARM_FEATURE_LOW): Likewise.
61 (ARM_FEATURE_CORE_LOW): Likewise.
62 (ARM_FEATURE_CORE_COPROC): Likewise.
63
f63c1776
PA		 642015-02-19 Pedro Alves <palves@redhat.com>
65
66 * cgen.h [__cplusplus]: Wrap in extern "C".
67 * msp430-decode.h [__cplusplus]: Likewise.
68 * nios2.h [__cplusplus]: Likewise.
69 * rl78.h [__cplusplus]: Likewise.
70 * rx.h [__cplusplus]: Likewise.
71 * tilegx.h [__cplusplus]: Likewise.
72
3f8107ab
AM		 732015-01-28 James Bowman <james.bowman@ftdichip.com>
74
75 * ft32.h: New file.
76
1e2e8c52
AK		 772015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
78
79 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
80
b90efa5b
AM		 812015-01-01 Alan Modra <amodra@gmail.com>
82
83 Update year range in copyright notice of all files.
84
bffb6004
AG		 852014-12-27 Anthony Green <green@moxielogic.com>
86
87 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
88 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
89
1945cfa5
EB		 902014-12-06 Eric Botcazou <ebotcazou@adacore.com>
91
92 * visium.h: New file.
93
d306ce58
SL		 942014-11-28 Sandra Loosemore <sandra@codesourcery.com>
95
96 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
97 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
98 (NIOS2_INSN_OPTARG): Renumber.
99
b4714c7c
SL		 1002014-11-06 Sandra Loosemore <sandra@codesourcery.com>
101
102 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
103 declaration. Fix obsolete comment.
104
96ba4233
SL		 1052014-10-23 Sandra Loosemore <sandra@codesourcery.com>
106
107 * nios2.h (enum iw_format_type): New.
108 (struct nios2_opcode): Update comments. Add size and format fields.
109 (NIOS2_INSN_OPTARG): New.
110 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
111 (struct nios2_reg): Add regtype field.
112 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
113 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
114 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
115 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
116 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
117 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
118 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
119 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
120 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
121 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
122 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
123 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
124 (OP_MASK_OP, OP_SH_OP): Delete.
125 (OP_MASK_IOP, OP_SH_IOP): Delete.
126 (OP_MASK_IRD, OP_SH_IRD): Delete.
127 (OP_MASK_IRT, OP_SH_IRT): Delete.
128 (OP_MASK_IRS, OP_SH_IRS): Delete.
129 (OP_MASK_ROP, OP_SH_ROP): Delete.
130 (OP_MASK_RRD, OP_SH_RRD): Delete.
131 (OP_MASK_RRT, OP_SH_RRT): Delete.
132 (OP_MASK_RRS, OP_SH_RRS): Delete.
133 (OP_MASK_JOP, OP_SH_JOP): Delete.
134 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
135 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
136 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
137 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
138 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
139 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
140 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
141 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
142 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
143 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
144 (OP_MASK_<insn>, OP_MASK): Delete.
145 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
146 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
147 Include nios2r1.h to define new instruction opcode constants
148 and accessors.
149 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
150 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
151 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
152 (NUMOPCODES, NUMREGISTERS): Delete.
153 * nios2r1.h: New file.
154
0b6be415
JM		 1552014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
156
157 * sparc.h (HWCAP2_VIS3B): Documentation improved.
158
3d68f91c
JM		 1592014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
160
161 * sparc.h (sparc_opcode): new field `hwcaps2'.
162 (HWCAP2_FJATHPLUS): New define.
163 (HWCAP2_VIS3B): Likewise.
164 (HWCAP2_ADP): Likewise.
165 (HWCAP2_SPARC5): Likewise.
166 (HWCAP2_MWAIT): Likewise.
167 (HWCAP2_XMPMUL): Likewise.
168 (HWCAP2_XMONT): Likewise.
169 (HWCAP2_NSEC): Likewise.
170 (HWCAP2_FJATHHPC): Likewise.
171 (HWCAP2_FJDES): Likewise.
172 (HWCAP2_FJAES): Likewise.
173 Document the new operand kind `{', corresponding to the mcdper
174 ancillary state register.
175 Document the new operand kind }, which represents frsd floating
176 point registers (double precision) which must be the same than
177 frs1 in its containing instruction.
178
40c7a7cb
KLC		 1792014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
180
181 * nds32.h: Add new opcode declaration.
182
7361da2c
AB		 1832014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
184 Matthew Fortune <matthew.fortune@imgtec.com>
185
186 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
187 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
188 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
189 +I, +O, +R, +:, +\, +", +;
190 (mips_check_prev_operand): New struct.
191 (INSN2_FORBIDDEN_SLOT): New define.
192 (INSN_ISA32R6): New define.
193 (INSN_ISA64R6): New define.
194 (INSN_UPTO32R6): New define.
195 (INSN_UPTO64R6): New define.
196 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
197 (ISA_MIPS32R6): New define.
198 (ISA_MIPS64R6): New define.
199 (CPU_MIPS32R6): New define.
200 (CPU_MIPS64R6): New define.
201 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
202
ee804238
JW		 2032014-09-03 Jiong Wang <jiong.wang@arm.com>
204
205 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
206 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
207 (aarch64_insn_class): Add lse_atomic.
208 (F_LSE_SZ): New field added.
209 (opcode_has_special_coder): Recognize F_LSE_SZ.
210
5575639b
MR		 2112014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
212
213 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
214 over to `+J'.
215
43885403
MF		 2162014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
217
218 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
219 (INSN_LOAD_COPROC): New define.
220 (INSN_COPROC_MOVE_DELAY): Rename to...
221 (INSN_COPROC_MOVE): New define.
222
f36e8886
BS		 2232014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
224 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
225 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
226 Soundararajan <Sounderarajan.D@atmel.com>
227
228 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
229 (AVR_ISA_2xxxa): Define ISA without LPM.
230 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
231 Add doc for contraint used in 16 bit lds/sts.
232 Adjust ISA group for icall, ijmp, pop and push.
233 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
234
00b32ff2
NC		 2352014-05-19 Nick Clifton <nickc@redhat.com>
236
237 * msp430.h (struct msp430_operand_s): Add vshift field.
238
ae52f483
AB		 2392014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
240
241 * mips.h (INSN_ISA_MASK): Updated.
242 (INSN_ISA32R3): New define.
243 (INSN_ISA32R5): New define.
244 (INSN_ISA64R3): New define.
245 (INSN_ISA64R5): New define.
246 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
247 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
248 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
249 mips64r5.
250 (INSN_UPTO32R3): New define.
251 (INSN_UPTO32R5): New define.
252 (INSN_UPTO64R3): New define.
253 (INSN_UPTO64R5): New define.
254 (ISA_MIPS32R3): New define.
255 (ISA_MIPS32R5): New define.
256 (ISA_MIPS64R3): New define.
257 (ISA_MIPS64R5): New define.
258 (CPU_MIPS32R3): New define.
259 (CPU_MIPS32R5): New define.
260 (CPU_MIPS64R3): New define.
261 (CPU_MIPS64R5): New define.
262
3efe9ec5
RS		 2632014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
264
265 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
266
73589c9d
CS		 2672014-04-22 Christian Svensson <blue@cmd.nu>
268
269 * or32.h: Delete.
270
4b95cf5c
AM		 2712014-03-05 Alan Modra <amodra@gmail.com>
272
273 Update copyright years.
274
e269fea7
AB		 2752013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
276
277 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
278 microMIPS.
279
35c08157
KLC		 2802013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
281 Wei-Cheng Wang <cole945@gmail.com>
282
283 * nds32.h: New file for Andes NDS32.
284
594d8fa8
MF		 2852013-12-07 Mike Frysinger <vapier@gentoo.org>
286
287 * bfin.h: Remove +x file mode.
288
87b8eed7
YZ		 2892013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
290
291 * aarch64.h (aarch64_pstatefields): Change element type to
292 aarch64_sys_reg.
293
c9fb6e58
YZ		 2942013-11-18 Renlin Li <Renlin.Li@arm.com>
295
296 * arm.h (ARM_AEXT_V7VE): New define.
297 (ARM_ARCH_V7VE): New define.
298 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
299
a203d9b7
YZ		 3002013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
301
302 Revert
303
304 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
305
306 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
307 (aarch64_sys_reg_writeonly_p): Ditto.
308
75468c93
YZ		 3092013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
310
311 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
312 (aarch64_sys_reg_writeonly_p): Ditto.
313
49eec193
YZ		 3142013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
315
316 * aarch64.h (aarch64_sys_reg): New typedef.
317 (aarch64_sys_regs): Change to define with the new type.
318 (aarch64_sys_reg_deprecated_p): Declare.
319
68a64283
YZ		 3202013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
321
322 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
323 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
324
387a82f1
CF		 3252013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
326
327 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
328 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
329 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
330 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
331 For MIPS, update extension character sequences after +.
332 (ASE_MSA): New define.
333 (ASE_MSA64): New define.
334 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
335 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
336 For microMIPS, update extension character sequences after +.
337
9aff4b7a
NC		 3382013-08-23 Yuri Chornoivan <yurchor@ukr.net>
339
340 PR binutils/15834
341 * i960.h: Fix typos.
342
e423441d
RS		 3432013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
344
345 * mips.h: Remove references to "+I" and imm2_expr.
346
5e0dc5ba
RS		 3472013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
348
349 * mips.h (M_DEXT, M_DINS): Delete.
350
0f35dbc4
RS		 3512013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
352
353 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
354 (mips_optional_operand_p): New function.
355
14daeee3
RS		 3562013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
357 Richard Sandiford <rdsandiford@googlemail.com>
358
359 * mips.h: Document new VU0 operand characters.
360 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
361 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
362 (OP_REG_R5900_ACC): New mips_reg_operand_types.
363 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
364 (mips_vu0_channel_mask): Declare.
365
3ccad066
RS		 3662013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
367
368 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
369 (mips_int_operand_min, mips_int_operand_max): New functions.
370 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
371
fc76e730
RS		 3722013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
373
374 * mips.h (mips_decode_reg_operand): New function.
375 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
376 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
377 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
378 New macros.
379 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
380 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
381 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
382 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
383 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
384 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
385 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
386 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
387 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
388 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
389 macros to cover the gaps.
390 (INSN2_MOD_SP): Replace with...
391 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
392 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
393 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
394 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
395 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
396 Delete.
397
26545944
RS		 3982013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
399
400 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
401 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
402 (MIPS16_INSN_COND_BRANCH): Delete.
403
7e8b059b
L		 4042013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
405 Kirill Yukhin <kirill.yukhin@intel.com>
406 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
407
408 * i386.h (BND_PREFIX_OPCODE): New.
409
c3c07478
RS		 4102013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
411
412 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
413 OP_SAVE_RESTORE_LIST.
414 (decode_mips16_operand): Declare.
415
ab902481
RS		 4162013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
417
418 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
419 (mips_operand, mips_int_operand, mips_mapped_int_operand)
420 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
421 (mips_pcrel_operand): New structures.
422 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
423 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
424 (decode_mips_operand, decode_micromips_operand): Declare.
425
cc537e56
RS		 4262013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
427
428 * mips.h: Document MIPS16 "I" opcode.
429
f2ae14a1
RS		 4302013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
431
432 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
433 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
434 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
435 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
436 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
437 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
438 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
439 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
440 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
441 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
442 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
443 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
444 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
445 Rename to...
446 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
447 (M_USD_AB): ...these.
448
5c324c16
RS		 4492013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
450
451 * mips.h: Remove documentation of "[" and "]". Update documentation
452 of "k" and the MDMX formats.
453
23e69e47
RS		 4542013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
455
456 * mips.h: Update documentation of "+s" and "+S".
457
27c5c572
RS		 4582013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
459
460 * mips.h: Document "+i".
461
e76ff5ab
RS		 4622013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
463
464 * mips.h: Remove "mi" documentation. Update "mh" documentation.
465 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
466 Delete.
467 (INSN2_WRITE_GPR_MHI): Rename to...
468 (INSN2_WRITE_GPR_MH): ...this.
469
fa7616a4
RS		 4702013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
471
472 * mips.h: Remove documentation of "+D" and "+T".
473
18870af7
RS		 4742013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
475
476 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
477 Use "source" rather than "destination" for microMIPS "G".
478
833794fc
MR		 4792013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
480
481 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
482 values.
483
c3678916
RS		 4842013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
485
486 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
487
7f3c4072
CM		 4882013-06-17 Catherine Moore <clm@codesourcery.com>
489 Maciej W. Rozycki <macro@codesourcery.com>
490 Chao-Ying Fu <fu@mips.com>
491
492 * mips.h (OP_SH_EVAOFFSET): Define.
493 (OP_MASK_EVAOFFSET): Define.
494 (INSN_ASE_MASK): Delete.
495 (ASE_EVA): Define.
496 (M_CACHEE_AB, M_CACHEE_OB): New.
497 (M_LBE_OB, M_LBE_AB): New.
498 (M_LBUE_OB, M_LBUE_AB): New.
499 (M_LHE_OB, M_LHE_AB): New.
500 (M_LHUE_OB, M_LHUE_AB): New.
501 (M_LLE_AB, M_LLE_OB): New.
502 (M_LWE_OB, M_LWE_AB): New.
503 (M_LWLE_AB, M_LWLE_OB): New.
504 (M_LWRE_AB, M_LWRE_OB): New.
505 (M_PREFE_AB, M_PREFE_OB): New.
506 (M_SCE_AB, M_SCE_OB): New.
507 (M_SBE_OB, M_SBE_AB): New.
508 (M_SHE_OB, M_SHE_AB): New.
509 (M_SWE_OB, M_SWE_AB): New.
510 (M_SWLE_AB, M_SWLE_OB): New.
511 (M_SWRE_AB, M_SWRE_OB): New.
512 (MICROMIPSOP_SH_EVAOFFSET): Define.
513 (MICROMIPSOP_MASK_EVAOFFSET): Define.
514
0c8fe7cf
SL		 5152013-06-12 Sandra Loosemore <sandra@codesourcery.com>
516
517 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
518
c77c0862
RS		 5192013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
520
521 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
522
b015e599
AP		 5232013-05-09 Andrew Pinski <apinski@cavium.com>
524
525 * mips.h (OP_MASK_CODE10): Correct definition.
526 (OP_SH_CODE10): Likewise.
527 Add a comment that "+J" is used now for OP_*CODE10.
528 (INSN_ASE_MASK): Update.
529 (INSN_VIRT): New macro.
530 (INSN_VIRT64): New macro
531
13761a11
NC		 5322013-05-02 Nick Clifton <nickc@redhat.com>
533
534 * msp430.h: Add patterns for MSP430X instructions.
535
0afd1215
DM		 5362013-04-06 David S. Miller <davem@davemloft.net>
537
538 * sparc.h (F_PREFERRED): Define.
539 (F_PREF_ALIAS): Define.
540
41702d50
NC		 5412013-04-03 Nick Clifton <nickc@redhat.com>
542
543 * v850.h (V850_INVERSE_PCREL): Define.
544
e21e1a51
NC		 5452013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
546
547 PR binutils/15068
548 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
549
51dcdd4d
NC		 5502013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
551
552 PR binutils/15068
553 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
554 Add 16-bit opcodes.
555 * tic6xc-opcode-table.h: Add 16-bit insns.
556 * tic6x.h: Add support for 16-bit insns.
557
81f5558e
NC		 5582013-03-21 Michael Schewe <michael.schewe@gmx.net>
559
560 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
561 and mov.b/w/l Rs,@(d:32,ERd).
562
165546ad
NC		 5632013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
564
565 PR gas/15082
566 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
567 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
568 tic6x_operand_xregpair operand coding type.
569 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
570 opcode field, usu ORXREGD1324 for the src2 operand and remove the
571 TIC6X_FLAG_NO_CROSS.
572
795b8e6b
NC		 5732013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
574
575 PR gas/15095
576 * tic6x.h (enum tic6x_coding_method): Add
577 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
578 separately the msb and lsb of a register pair. This is needed to
579 encode the opcodes in the same way as TI assembler does.
580 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
581 and rsqrdp opcodes to use the new field coding types.
582
dd5181d5
KT		 5832013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
584
585 * arm.h (CRC_EXT_ARMV8): New constant.
586 (ARCH_CRC_ARMV8): New macro.
587
e60bb1dd
YZ		 5882013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
589
590 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
591
36591ba1
SL		 5922013-02-06 Sandra Loosemore <sandra@codesourcery.com>
593 Andrew Jenner <andrew@codesourcery.com>
594
595 Based on patches from Altera Corporation.
596
597 * nios2.h: New file.
598
e30181a5
YZ		 5992013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
600
601 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
602
0c9573f4
NC		 6032013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
604
605 PR gas/15069
606 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
607
981dc7f1
NC		 6082013-01-24 Nick Clifton <nickc@redhat.com>
609
610 * v850.h: Add e3v5 support.
611
f5555712
YZ		 6122013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
613
614 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
615
5817ffd1
PB		 6162013-01-10 Peter Bergner <bergner@vnet.ibm.com>
617
618 * ppc.h (PPC_OPCODE_POWER8): New define.
619 (PPC_OPCODE_HTM): Likewise.
620
a3c62988
NC		 6212013-01-10 Will Newton <will.newton@imgtec.com>
622
623 * metag.h: New file.
624
73335eae
NC		 6252013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
626
627 * cr16.h (make_instruction): Rename to cr16_make_instruction.
628 (match_opcode): Rename to cr16_match_opcode.
629
e407c74b
NC		 6302013-01-04 Juergen Urban <JuergenUrban@gmx.de>
631
632 * mips.h: Add support for r5900 instructions including lq and sq.
633
bab4becb
NC		 6342013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
635
636 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
637 (make_instruction,match_opcode): Added function prototypes.
638 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
639
776fc418
AM		 6402012-11-23 Alan Modra <amodra@gmail.com>
641
642 * ppc.h (ppc_parse_cpu): Update prototype.
643
f05682d4
DA		 6442012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
645
646 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
647 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
648
cfc72779
AK		 6492012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
650
651 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
652
b3e14eda
L		 6532012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
654
655 * ia64.h (ia64_opnd): Add new operand types.
656
2c63854f
DM		 6572012-08-21 David S. Miller <davem@davemloft.net>
658
659 * sparc.h (F3F4): New macro.
660
a06ea964 6612012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 662 Laurent Desnogues <laurent.desnogues@arm.com>
663 Jim MacArthur <jim.macarthur@arm.com>
664 Marcus Shawcroft <marcus.shawcroft@arm.com>
665 Nigel Stephens <nigel.stephens@arm.com>
666 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
667 Richard Earnshaw <rearnsha@arm.com>
668 Sofiane Naci <sofiane.naci@arm.com>
669 Tejas Belagod <tejas.belagod@arm.com>
670 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 671
672 * aarch64.h: New file.
673
35d0a169 6742012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 675 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 676
677 * mips.h (mips_opcode): Add the exclusions field.
678 (OPCODE_IS_MEMBER): Remove macro.
679 (cpu_is_member): New inline function.
680 (opcode_is_member): Likewise.
681
03f66e8a 6822012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 683 Catherine Moore <clm@codesourcery.com>
684 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 685
686 * mips.h: Document microMIPS DSP ASE usage.
687 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
688 microMIPS DSP ASE support.
689 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
690 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
691 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
692 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
693 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
694 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
695 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
696
9d7b4c23
MR		 6972012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
698
699 * mips.h: Fix a typo in description.
700
76e879f8
NC		 7012012-06-07 Georg-Johann Lay <avr@gjlay.de>
702
703 * avr.h: (AVR_ISA_XCH): New define.
704 (AVR_ISA_XMEGA): Use it.
705 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
706
6927f982
NC		 7072012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
708
709 * m68hc11.h: Add XGate definitions.
710 (struct m68hc11_opcode): Add xg_mask field.
711
b9c361e0
JL		 7122012-05-14 Catherine Moore <clm@codesourcery.com>
713 Maciej W. Rozycki <macro@codesourcery.com>
714 Rhonda Wittels <rhonda@codesourcery.com>
715
6927f982 716 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 717 (PPC_OP_SA): New macro.
718 (PPC_OP_SE_VLE): New macro.
719 (PPC_OP): Use a variable shift amount.
720 (powerpc_operand): Update comments.
721 (PPC_OPSHIFT_INV): New macro.
722 (PPC_OPERAND_CR): Replace with...
723 (PPC_OPERAND_CR_BIT): ...this and
724 (PPC_OPERAND_CR_REG): ...this.
725
726
f6c1a2d5
NC		 7272012-05-03 Sean Keys <skeys@ipdatasys.com>
728
729 * xgate.h: Header file for XGATE assembler.
730
ec668d69
DM		 7312012-04-27 David S. Miller <davem@davemloft.net>
732
6cda1326
DM		 733 * sparc.h: Document new arg code' )' for crypto RS3
734 immediates.
735
ec668d69
DM		 736 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
737 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
738 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
739 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
740 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
741 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
742 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
743 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
744 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
745 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
746 HWCAP_CBCOND, HWCAP_CRC32): New defines.
747
aea77599
AM		 7482012-03-10 Edmar Wienskoski <edmar@freescale.com>
749
750 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
751
1f42f8b3
AM		 7522012-02-27 Alan Modra <amodra@gmail.com>
753
754 * crx.h (cst4_map): Update declaration.
755
6f7be959
WL		 7562012-02-25 Walter Lee <walt@tilera.com>
757
758 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
759 TILEGX_OPC_LD_TLS.
760 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
761 TILEPRO_OPC_LW_TLS_SN.
762
42164a71
L		 7632012-02-08 H.J. Lu <hongjiu.lu@intel.com>
764
765 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
766 (XRELEASE_PREFIX_OPCODE): Likewise.
767
432233b3 7682011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 769 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 770
771 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
772 (INSN_OCTEON2): New macro.
773 (CPU_OCTEON2): New macro.
774 (OPCODE_IS_MEMBER): Add Octeon2.
775
dd6a37e7
AP		 7762011-11-29 Andrew Pinski <apinski@cavium.com>
777
778 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
779 (INSN_OCTEONP): New macro.
780 (CPU_OCTEONP): New macro.
781 (OPCODE_IS_MEMBER): Add Octeon+.
782 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
783
99c513f6
DD		 7842011-11-01 DJ Delorie <dj@redhat.com>
785
786 * rl78.h: New file.
787
26f85d7a
MR		 7882011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
789
790 * mips.h: Fix a typo in description.
791
9e8c70f9
DM		 7922011-09-21 David S. Miller <davem@davemloft.net>
793
794 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
795 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
796 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
797 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
798
dec0624d 7992011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 800 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 801
802 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
803 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
804 (INSN_ASE_MASK): Add the MCU bit.
805 (INSN_MCU): New macro.
806 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
807 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
808
2b0c8b40
MR		 8092011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
810
811 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
812 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
813 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
814 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
815 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
816 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
817 (INSN2_READ_GPR_MMN): Likewise.
818 (INSN2_READ_FPR_D): Change the bit used.
819 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
820 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
821 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
822 (INSN2_COND_BRANCH): Likewise.
823 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
824 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
825 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
826 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
827 (INSN2_MOD_GPR_MN): Likewise.
828
ea783ef3
DM		 8292011-08-05 David S. Miller <davem@davemloft.net>
830
831 * sparc.h: Document new format codes '4', '5', and '('.
832 (OPF_LOW4, RS3): New macros.
833
7c176fa8
MR		 8342011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
835
836 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
837 order of flags documented.
838
2309ddf2
MR		 8392011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
840
841 * mips.h: Clarify the description of microMIPS instruction
842 manipulation macros.
843 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
844
df58fc94 8452011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 846 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 847
848 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
849 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
850 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
851 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
852 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
853 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
854 (OP_MASK_RS3, OP_SH_RS3): Likewise.
855 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
856 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
857 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
858 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
859 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
860 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
861 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
862 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
863 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
864 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
865 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
866 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
867 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
868 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
869 (INSN_WRITE_GPR_S): New macro.
870 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
871 (INSN2_READ_FPR_D): Likewise.
872 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
873 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
874 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
875 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
876 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
877 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
878 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
879 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
880 (CPU_MICROMIPS): New macro.
881 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
882 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
883 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
884 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
885 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
886 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
887 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
888 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
889 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
890 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
891 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
892 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
893 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
894 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
895 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
896 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
897 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
898 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
899 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
900 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
901 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
902 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
903 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
904 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
905 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
906 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
907 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
908 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
909 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
910 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
911 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
912 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
913 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
914 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
915 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
916 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
917 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
918 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
919 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
920 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
921 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
922 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
923 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
924 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
925 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
926 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
927 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
928 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
929 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
930 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
931 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
932 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
933 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
934 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
935 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
936 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
937 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
938 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
939 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
940 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
941 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
942 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
943 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
944 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
945 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
946 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
947 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
948 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
949 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
950 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
951 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
952 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
953 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
954 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
955 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
956 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
957 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
958 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
959 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
960 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
961 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
962 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
963 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
964 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
965 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
966 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
967 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
968 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
969 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
970 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
971 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
972 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
973 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
974 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
975 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
976 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
977 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
978 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
979 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
980 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
981 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
982 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
983 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
984 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
985 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
986 (micromips_opcodes): New declaration.
987 (bfd_micromips_num_opcodes): Likewise.
988
bcd530a7
RS		 9892011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
990
991 * mips.h (INSN_TRAP): Rename to...
992 (INSN_NO_DELAY_SLOT): ... this.
993 (INSN_SYNC): Remove macro.
994
2dad5a91
EW		 9952011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
996
997 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
998 a duplicate of AVR_ISA_SPM.
999
5d73b1f1
NC		 10002011-07-01 Nick Clifton <nickc@redhat.com>
1001
1002 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1003
ef26d60e
MF		 10042011-06-18 Robin Getz <robin.getz@analog.com>
1005
1006 * bfin.h (is_macmod_signed): New func
1007
8fb8dca7
MF		 10082011-06-18 Mike Frysinger <vapier@gentoo.org>
1009
1010 * bfin.h (is_macmod_pmove): Add missing space before func args.
1011 (is_macmod_hmove): Likewise.
1012
aa137e4d
NC		 10132011-06-13 Walter Lee <walt@tilera.com>
1014
1015 * tilegx.h: New file.
1016 * tilepro.h: New file.
1017
3b2f0793
PB		 10182011-05-31 Paul Brook <paul@codesourcery.com>
1019
aa137e4d
NC		 1020 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1021
10222011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1023
1024 * s390.h: Replace S390_OPERAND_REG_EVEN with
1025 S390_OPERAND_REG_PAIR.
1026
10272011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1028
1029 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1030
ac7f631b
NC		 10312011-04-18 Julian Brown <julian@codesourcery.com>
1032
1033 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1034
84701018
NC		 10352011-04-11 Dan McDonald <dan@wellkeeper.com>
1036
1037 PR gas/12296
1038 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1039
8cc66334
EW		 10402011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1041
1042 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1043 New instruction set flags.
1044 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1045
3eebd5eb
MR		 10462011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1047
1048 * mips.h (M_PREF_AB): New enum value.
1049
26bb3ddd
MF		 10502011-02-12 Mike Frysinger <vapier@gentoo.org>
1051
89c0d58c
MR		 1052 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1053 M_IU): Define.
1054 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1055
dd76fcb8
MF		 10562011-02-11 Mike Frysinger <vapier@gentoo.org>
1057
1058 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1059
98d23bef
BS		 10602011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1061
1062 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1063 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1064
3c853d93
DA		 10652010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1066
1067 PR gas/11395
1068 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1069 "bb" entries.
1070
79676006
DA		 10712010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1072
1073 PR gas/11395
1074 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1075
1bec78e9
RS		 10762010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1077
1078 * mips.h: Update commentary after last commit.
1079
98675402
RS		 10802010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1081
1082 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1083 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1084 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1085
aa137e4d
NC		 10862010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1087
1088 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1089
435b94a4
RS		 10902010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1091
1092 * mips.h: Fix previous commit.
1093
d051516a
NC		 10942010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1095
1096 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1097 (INSN_LOONGSON_3A): Clear bit 31.
1098
251665fc
MGD		 10992010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1100
1101 PR gas/12198
1102 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1103 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1104 (ARM_ARCH_V6M_ONLY): New define.
1105
fd503541
NC		 11062010-11-11 Mingming Sun <mingm.sun@gmail.com>
1107
1108 * mips.h (INSN_LOONGSON_3A): Defined.
1109 (CPU_LOONGSON_3A): Defined.
1110 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1111
4469d2be
AM		 11122010-10-09 Matt Rice <ratmice@gmail.com>
1113
1114 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1115 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1116
90ec0d68
MGD		 11172010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1118
1119 * arm.h (ARM_EXT_VIRT): New define.
1120 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1121 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1122 Extensions.
1123
eea54501 11242010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1125
eea54501
MGD		 1126 * arm.h (ARM_AEXT_ADIV): New define.
1127 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1128
b2a5fbdc
MGD		 11292010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1130
1131 * arm.h (ARM_EXT_OS): New define.
1132 (ARM_AEXT_V6SM): Likewise.
1133 (ARM_ARCH_V6SM): Likewise.
1134
60e5ef9f
MGD		 11352010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1136
1137 * arm.h (ARM_EXT_MP): Add.
1138 (ARM_ARCH_V7A_MP): Likewise.
1139
73a63ccf
MF		 11402010-09-22 Mike Frysinger <vapier@gentoo.org>
1141
1142 * bfin.h: Declare pseudoChr structs/defines.
1143
ee99860a
MF		 11442010-09-21 Mike Frysinger <vapier@gentoo.org>
1145
1146 * bfin.h: Strip trailing whitespace.
1147
f9c7014e
DD		 11482010-07-29 DJ Delorie <dj@redhat.com>
1149
1150 * rx.h (RX_Operand_Type): Add TwoReg.
1151 (RX_Opcode_ID): Remove ediv and ediv2.
1152
93378652
DD		 11532010-07-27 DJ Delorie <dj@redhat.com>
1154
1155 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1156
1cd986c5
NC		 11572010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1158 Ina Pandit <ina.pandit@kpitcummins.com>
1159
1160 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1161 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1162 PROCESSOR_V850E2_ALL.
1163 Remove PROCESSOR_V850EA support.
1164 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1165 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1166 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1167 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1168 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1169 V850_OPERAND_PERCENT.
1170 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1171 V850_NOT_R0.
1172 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1173 and V850E_PUSH_POP
1174
9a2c7088
MR		 11752010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1176
1177 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1178 (MIPS16_INSN_BRANCH): Rename to...
1179 (MIPS16_INSN_COND_BRANCH): ... this.
1180
bdc70b4a
AM		 11812010-07-03 Alan Modra <amodra@gmail.com>
1182
1183 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1184 Renumber other PPC_OPCODE defines.
1185
f2bae120
AM		 11862010-07-03 Alan Modra <amodra@gmail.com>
1187
1188 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1189
360cfc9c
AM		 11902010-06-29 Alan Modra <amodra@gmail.com>
1191
1192 * maxq.h: Delete file.
1193
e01d869a
AM		 11942010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1195
1196 * ppc.h (PPC_OPCODE_E500): Define.
1197
f79e2745
CM		 11982010-05-26 Catherine Moore <clm@codesourcery.com>
1199
1200 * opcode/mips.h (INSN_MIPS16): Remove.
1201
2462afa1
JM		 12022010-04-21 Joseph Myers <joseph@codesourcery.com>
1203
1204 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1205
e4e42b45
NC		 12062010-04-15 Nick Clifton <nickc@redhat.com>
1207
1208 * alpha.h: Update copyright notice to use GPLv3.
1209 * arc.h: Likewise.
1210 * arm.h: Likewise.
1211 * avr.h: Likewise.
1212 * bfin.h: Likewise.
1213 * cgen.h: Likewise.
1214 * convex.h: Likewise.
1215 * cr16.h: Likewise.
1216 * cris.h: Likewise.
1217 * crx.h: Likewise.
1218 * d10v.h: Likewise.
1219 * d30v.h: Likewise.
1220 * dlx.h: Likewise.
1221 * h8300.h: Likewise.
1222 * hppa.h: Likewise.
1223 * i370.h: Likewise.
1224 * i386.h: Likewise.
1225 * i860.h: Likewise.
1226 * i960.h: Likewise.
1227 * ia64.h: Likewise.
1228 * m68hc11.h: Likewise.
1229 * m68k.h: Likewise.
1230 * m88k.h: Likewise.
1231 * maxq.h: Likewise.
1232 * mips.h: Likewise.
1233 * mmix.h: Likewise.
1234 * mn10200.h: Likewise.
1235 * mn10300.h: Likewise.
1236 * msp430.h: Likewise.
1237 * np1.h: Likewise.
1238 * ns32k.h: Likewise.
1239 * or32.h: Likewise.
1240 * pdp11.h: Likewise.
1241 * pj.h: Likewise.
1242 * pn.h: Likewise.
1243 * ppc.h: Likewise.
1244 * pyr.h: Likewise.
1245 * rx.h: Likewise.
1246 * s390.h: Likewise.
1247 * score-datadep.h: Likewise.
1248 * score-inst.h: Likewise.
1249 * sparc.h: Likewise.
1250 * spu-insns.h: Likewise.
1251 * spu.h: Likewise.
1252 * tic30.h: Likewise.
1253 * tic4x.h: Likewise.
1254 * tic54x.h: Likewise.
1255 * tic80.h: Likewise.
1256 * v850.h: Likewise.
1257 * vax.h: Likewise.
1258
40b36596
JM		 12592010-03-25 Joseph Myers <joseph@codesourcery.com>
1260
1261 * tic6x-control-registers.h, tic6x-insn-formats.h,
1262 tic6x-opcode-table.h, tic6x.h: New.
1263
c67a084a
NC		 12642010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1265
1266 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1267
466ef64f
AM		 12682010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1269
1270 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1271
1319d143
L		 12722010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1273
1274 * ia64.h (ia64_find_opcode): Remove argument name.
1275 (ia64_find_next_opcode): Likewise.
1276 (ia64_dis_opcode): Likewise.
1277 (ia64_free_opcode): Likewise.
1278 (ia64_find_dependency): Likewise.
1279
1fbb9298
DE		 12802009-11-22 Doug Evans <dje@sebabeach.org>
1281
1282 * cgen.h: Include bfd_stdint.h.
1283 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1284
ada65aa3
PB		 12852009-11-18 Paul Brook <paul@codesourcery.com>
1286
1287 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1288
9e3c6df6
PB		 12892009-11-17 Paul Brook <paul@codesourcery.com>
1290 Daniel Jacobowitz <dan@codesourcery.com>
1291
1292 * arm.h (ARM_EXT_V6_DSP): Define.
1293 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1294 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1295
0d734b5d
DD		 12962009-11-04 DJ Delorie <dj@redhat.com>
1297
1298 * rx.h (rx_decode_opcode) (mvtipl): Add.
1299 (mvtcp, mvfcp, opecp): Remove.
1300
62f3b8c8
PB		 13012009-11-02 Paul Brook <paul@codesourcery.com>
1302
1303 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1304 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1305 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1306 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1307 FPU_ARCH_NEON_VFP_V4): Define.
1308
ac1e9eca
DE		 13092009-10-23 Doug Evans <dje@sebabeach.org>
1310
1311 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1312 * cgen.h: Update. Improve multi-inclusion macro name.
1313
9fe54b1c
PB		 13142009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1315
1316 * ppc.h (PPC_OPCODE_476): Define.
1317
634b50f2
PB		 13182009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1319
1320 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1321
c7927a3c
NC		 13222009-09-29 DJ Delorie <dj@redhat.com>
1323
1324 * rx.h: New file.
1325
b961e85b
AM		 13262009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1327
1328 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1329
e0d602ec
BE		 13302009-09-21 Ben Elliston <bje@au.ibm.com>
1331
1332 * ppc.h (PPC_OPCODE_PPCA2): New.
1333
96d56e9f
NC		 13342009-09-05 Martin Thuresson <martin@mtme.org>
1335
1336 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1337
d3ce72d0
NC		 13382009-08-29 Martin Thuresson <martin@mtme.org>
1339
1340 * tic30.h (template): Rename type template to
1341 insn_template. Updated code to use new name.
1342 * tic54x.h (template): Rename type template to
1343 insn_template.
1344
824b28db
NH		 13452009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1346
1347 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1348
f865a31d
AG		 13492009-06-11 Anthony Green <green@moxielogic.com>
1350
1351 * moxie.h (MOXIE_F3_PCREL): Define.
1352 (moxie_form3_opc_info): Grow.
1353
0e7c7f11
AG		 13542009-06-06 Anthony Green <green@moxielogic.com>
1355
1356 * moxie.h (MOXIE_F1_M): Define.
1357
20135e4c
NC		 13582009-04-15 Anthony Green <green@moxielogic.com>
1359
1360 * moxie.h: Created.
1361
bcb012d3
DD		 13622009-04-06 DJ Delorie <dj@redhat.com>
1363
1364 * h8300.h: Add relaxation attributes to MOVA opcodes.
1365
69fe9ce5
AM		 13662009-03-10 Alan Modra <amodra@bigpond.net.au>
1367
1368 * ppc.h (ppc_parse_cpu): Declare.
1369
c3b7224a
NC		 13702009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1371
1372 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1373 and _IMM11 for mbitclr and mbitset.
1374 * score-datadep.h: Update dependency information.
1375
066be9f7
PB		 13762009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1377
1378 * ppc.h (PPC_OPCODE_POWER7): New.
1379
fedc618e
DE		 13802009-02-06 Doug Evans <dje@google.com>
1381
1382 * i386.h: Add comment regarding sse* insns and prefixes.
1383
52b6b6b9
JM		 13842009-02-03 Sandip Matte <sandip@rmicorp.com>
1385
1386 * mips.h (INSN_XLR): Define.
1387 (INSN_CHIP_MASK): Update.
1388 (CPU_XLR): Define.
1389 (OPCODE_IS_MEMBER): Update.
1390 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1391
35669430
DE		 13922009-01-28 Doug Evans <dje@google.com>
1393
1394 * opcode/i386.h: Add multiple inclusion protection.
1395 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1396 (EDI_REG_NUM): New macros.
1397 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1398 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1399 (REX_PREFIX_P): New macro.
35669430 1400
1cb0a767
PB		 14012009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1402
1403 * ppc.h (struct powerpc_opcode): New field "deprecated".
1404 (PPC_OPCODE_NOPOWER4): Delete.
1405
3aa3176b
TS		 14062008-11-28 Joshua Kinard <kumba@gentoo.org>
1407
1408 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1409 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1410
8e79c3df
CM		 14112008-11-18 Catherine Moore <clm@codesourcery.com>
1412
1413 * arm.h (FPU_NEON_FP16): New.
1414 (FPU_ARCH_NEON_FP16): New.
1415
de9a3e51
CF		 14162008-11-06 Chao-ying Fu <fu@mips.com>
1417
1418 * mips.h: Doucument '1' for 5-bit sync type.
1419
1ca35711
L		 14202008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1421
1422 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1423 IA64_RS_CR.
1424
9b4e5766
PB		 14252008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1426
1427 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1428
081ba1b3
AM		 14292008-07-30 Michael J. Eager <eager@eagercon.com>
1430
1431 * ppc.h (PPC_OPCODE_405): Define.
1432 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1433
fa452fa6
PB		 14342008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1435
1436 * ppc.h (ppc_cpu_t): New typedef.
1437 (struct powerpc_opcode <flags>): Use it.
1438 (struct powerpc_operand <insert, extract>): Likewise.
1439 (struct powerpc_macro <flags>): Likewise.
1440
bb35fb24
NC		 14412008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1442
1443 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1444 Update comment before MIPS16 field descriptors to mention MIPS16.
1445 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1446 BBIT.
1447 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1448 New bit masks and shift counts for cins and exts.
1449
dd3cbb7e
NC		 1450 * mips.h: Document new field descriptors +Q.
1451 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1452
d0799671
AN		 14532008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1454
9aff4b7a 1455 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1456 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1457
19a6653c
AM		 14582008-04-14 Edmar Wienskoski <edmar@freescale.com>
1459
1460 * ppc.h: (PPC_OPCODE_E500MC): New.
1461
c0f3af97
L		 14622008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1463
1464 * i386.h (MAX_OPERANDS): Set to 5.
1465 (MAX_MNEM_SIZE): Changed to 20.
1466
e210c36b
NC		 14672008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1468
1469 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1470
b1cc4aeb
PB		 14712008-03-09 Paul Brook <paul@codesourcery.com>
1472
1473 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1474
7e806470
PB		 14752008-03-04 Paul Brook <paul@codesourcery.com>
1476
1477 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1478 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1479 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1480
7b2185f9 14812008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1482 Nick Clifton <nickc@redhat.com>
1483
1484 PR 3134
1485 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1486 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1487 set.
af7329f0 1488
796d5313
NC		 14892008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1490
1491 * cr16.h (cr16_num_optab): Declared.
1492
d669d37f
NC		 14932008-02-14 Hakan Ardo <hakan@debian.org>
1494
1495 PR gas/2626
1496 * avr.h (AVR_ISA_2xxe): Define.
1497
e6429699
AN		 14982008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1499
1500 * mips.h: Update copyright.
1501 (INSN_CHIP_MASK): New macro.
1502 (INSN_OCTEON): New macro.
1503 (CPU_OCTEON): New macro.
1504 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1505
e210c36b
NC		 15062008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1507
1508 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1509
15102008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1511
1512 * avr.h (AVR_ISA_USB162): Add new opcode set.
1513 (AVR_ISA_AVR3): Likewise.
1514
350cc38d
MS		 15152007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1516
1517 * mips.h (INSN_LOONGSON_2E): New.
1518 (INSN_LOONGSON_2F): New.
1519 (CPU_LOONGSON_2E): New.
1520 (CPU_LOONGSON_2F): New.
1521 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1522
56950294
MS		 15232007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1524
1525 * mips.h (INSN_ISA*): Redefine certain values as an
1526 enumeration. Update comments.
1527 (mips_isa_table): New.
1528 (ISA_MIPS*): Redefine to match enumeration.
1529 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1530 values.
1531
c3d65c1c
BE		 15322007-08-08 Ben Elliston <bje@au.ibm.com>
1533
1534 * ppc.h (PPC_OPCODE_PPCPS): New.
1535
0fdaa005
L		 15362007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1537
1538 * m68k.h: Document j K & E.
1539
15402007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1541
1542 * cr16.h: New file for CR16 target.
1543
3896c469
AM		 15442007-05-02 Alan Modra <amodra@bigpond.net.au>
1545
1546 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1547
9a2e615a
NS		 15482007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1549
1550 * m68k.h (mcfisa_c): New.
1551 (mcfusp, mcf_mask): Adjust.
1552
b84bf58a
AM		 15532007-04-20 Alan Modra <amodra@bigpond.net.au>
1554
1555 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1556 (num_powerpc_operands): Declare.
1557 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1558 (PPC_OPERAND_PLUS1): Define.
1559
831480e9 15602007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1561
1562 * i386.h (REX_MODE64): Renamed to ...
1563 (REX_W): This.
1564 (REX_EXTX): Renamed to ...
1565 (REX_R): This.
1566 (REX_EXTY): Renamed to ...
1567 (REX_X): This.
1568 (REX_EXTZ): Renamed to ...
1569 (REX_B): This.
1570
0b1cf022
L		 15712007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1572
1573 * i386.h: Add entries from config/tc-i386.h and move tables
1574 to opcodes/i386-opc.h.
1575
d796c0ad
L		 15762007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1577
1578 * i386.h (FloatDR): Removed.
1579 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1580
30ac7323
AM		 15812007-03-01 Alan Modra <amodra@bigpond.net.au>
1582
1583 * spu-insns.h: Add soma double-float insns.
1584
8b082fb1 15852007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1586 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1587
1588 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1589 (INSN_DSPR2): Add flag for DSP R2 instructions.
1590 (M_BALIGN): New macro.
1591
4eed87de
AM		 15922007-02-14 Alan Modra <amodra@bigpond.net.au>
1593
1594 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1595 and Seg3ShortFrom with Shortform.
1596
fda592e8
L		 15972007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1598
1599 PR gas/4027
1600 * i386.h (i386_optab): Put the real "test" before the pseudo
1601 one.
1602
3bdcfdf4
KH		 16032007-01-08 Kazu Hirata <kazu@codesourcery.com>
1604
1605 * m68k.h (m68010up): OR fido_a.
1606
9840d27e
KH		 16072006-12-25 Kazu Hirata <kazu@codesourcery.com>
1608
1609 * m68k.h (fido_a): New.
1610
c629cdac
KH		 16112006-12-24 Kazu Hirata <kazu@codesourcery.com>
1612
1613 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1614 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1615 values.
1616
b7d9ef37
L		 16172006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1618
1619 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1620
b138abaa
NC		 16212006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1622
1623 * score-inst.h (enum score_insn_type): Add Insn_internal.
1624
e9f53129
AM		 16252006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1626 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1627 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1628 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1629 Alan Modra <amodra@bigpond.net.au>
1630
1631 * spu-insns.h: New file.
1632 * spu.h: New file.
1633
ede602d7
AM		 16342006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1635
1636 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1637
7918206c
MM		 16382006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1639
e4e42b45 1640 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1641 in amdfam10 architecture.
1642
ef05d495
L		 16432006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1644
1645 * i386.h: Replace CpuMNI with CpuSSSE3.
1646
2d447fca 16472006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1648 Joseph Myers <joseph@codesourcery.com>
1649 Ian Lance Taylor <ian@wasabisystems.com>
1650 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1651
1652 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1653
1c0d3aa6
NC		 16542006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1655
1656 * score-datadep.h: New file.
1657 * score-inst.h: New file.
1658
c2f0420e
L		 16592006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1660
1661 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1662 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1663 movdq2q and movq2dq.
1664
050dfa73
MM		 16652006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1666 Michael Meissner <michael.meissner@amd.com>
1667
1668 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1669
15965411
L		 16702006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1671
1672 * i386.h (i386_optab): Add "nop" with memory reference.
1673
46e883c5
L		 16742006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1675
1676 * i386.h (i386_optab): Update comment for 64bit NOP.
1677
9622b051
AM		 16782006-06-06 Ben Elliston <bje@au.ibm.com>
1679 Anton Blanchard <anton@samba.org>
1680
1681 * ppc.h (PPC_OPCODE_POWER6): Define.
1682 Adjust whitespace.
1683
a9e24354
TS		 16842006-06-05 Thiemo Seufer <ths@mips.com>
1685
e4e42b45 1686 * mips.h: Improve description of MT flags.
a9e24354 1687
a596001e
RS		 16882006-05-25 Richard Sandiford <richard@codesourcery.com>
1689
1690 * m68k.h (mcf_mask): Define.
1691
d43b4baf 16922006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1693 David Ung <davidu@mips.com>
d43b4baf
TS		 1694
1695 * mips.h (enum): Add macro M_CACHE_AB.
1696
39a7806d 16972006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1698 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1699 David Ung <davidu@mips.com>
1700
1701 * mips.h: Add INSN_SMARTMIPS define.
1702
9bcd4f99 17032006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1704 David Ung <davidu@mips.com>
9bcd4f99
TS		 1705
1706 * mips.h: Defines udi bits and masks. Add description of
1707 characters which may appear in the args field of udi
1708 instructions.
1709
ef0ee844
TS		 17102006-04-26 Thiemo Seufer <ths@networkno.de>
1711
1712 * mips.h: Improve comments describing the bitfield instruction
1713 fields.
1714
f7675147
L		 17152006-04-26 Julian Brown <julian@codesourcery.com>
1716
1717 * arm.h (FPU_VFP_EXT_V3): Define constant.
1718 (FPU_NEON_EXT_V1): Likewise.
1719 (FPU_VFP_HARD): Update.
1720 (FPU_VFP_V3): Define macro.
1721 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1722
ef0ee844 17232006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1724
1725 * avr.h (AVR_ISA_PWMx): New.
1726
2da12c60
NS		 17272006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1728
1729 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1730 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1731 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1732 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1733 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1734
0715c387
PB		 17352006-03-10 Paul Brook <paul@codesourcery.com>
1736
1737 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1738
34bdd094
DA		 17392006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1740
1741 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1742 first. Correct mask of bb "B" opcode.
1743
331d2d0d
L		 17442006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1745
1746 * i386.h (i386_optab): Support Intel Merom New Instructions.
1747
62b3e311
PB		 17482006-02-24 Paul Brook <paul@codesourcery.com>
1749
1750 * arm.h: Add V7 feature bits.
1751
59cf82fe
L		 17522006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1753
1754 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1755
e74cfd16
PB		 17562006-01-31 Paul Brook <paul@codesourcery.com>
1757 Richard Earnshaw <rearnsha@arm.com>
1758
1759 * arm.h: Use ARM_CPU_FEATURE.
1760 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1761 (arm_feature_set): Change to a structure.
1762 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1763 ARM_FEATURE): New macros.
1764
5b3f8a92
HPN		 17652005-12-07 Hans-Peter Nilsson <hp@axis.com>
1766
1767 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1768 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1769 (ADD_PC_INCR_OPCODE): Don't define.
1770
cb712a9e
L		 17712005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1772
1773 PR gas/1874
1774 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1775
0499d65b
TS		 17762005-11-14 David Ung <davidu@mips.com>
1777
1778 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1779 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1780 save/restore encoding of the args field.
1781
ea5ca089
DB		 17822005-10-28 Dave Brolley <brolley@redhat.com>
1783
1784 Contribute the following changes:
1785 2005-02-16 Dave Brolley <brolley@redhat.com>
1786
1787 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1788 cgen_isa_mask_* to cgen_bitset_*.
1789 * cgen.h: Likewise.
1790
16175d96
DB		 1791 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1792
1793 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1794 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1795 (CGEN_CPU_TABLE): Make isas a ponter.
1796
1797 2003-09-29 Dave Brolley <brolley@redhat.com>
1798
1799 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1800 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1801 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1802
1803 2002-12-13 Dave Brolley <brolley@redhat.com>
1804
1805 * cgen.h (symcat.h): #include it.
1806 (cgen-bitset.h): #include it.
1807 (CGEN_ATTR_VALUE_TYPE): Now a union.
1808 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1809 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1810 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1811 * cgen-bitset.h: New file.
1812
3c9b82ba
NC		 18132005-09-30 Catherine Moore <clm@cm00re.com>
1814
1815 * bfin.h: New file.
1816
6a2375c6
JB		 18172005-10-24 Jan Beulich <jbeulich@novell.com>
1818
1819 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1820 indirect operands.
1821
c06a12f8
DA		 18222005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1823
1824 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1825 Add FLAG_STRICT to pa10 ftest opcode.
1826
4d443107
DA		 18272005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1828
1829 * hppa.h (pa_opcodes): Remove lha entries.
1830
f0a3b40f
DA		 18312005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1832
1833 * hppa.h (FLAG_STRICT): Revise comment.
1834 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1835 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1836 entries for "fdc".
1837
e210c36b
NC		 18382005-09-30 Catherine Moore <clm@cm00re.com>
1839
1840 * bfin.h: New file.
1841
1b7e1362
DA		 18422005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1843
1844 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1845
089b39de
CF		 18462005-09-06 Chao-ying Fu <fu@mips.com>
1847
1848 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1849 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1850 define.
1851 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1852 (INSN_ASE_MASK): Update to include INSN_MT.
1853 (INSN_MT): New define for MT ASE.
1854
93c34b9b
CF		 18552005-08-25 Chao-ying Fu <fu@mips.com>
1856
1857 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1858 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1859 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1860 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1861 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1862 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1863 instructions.
1864 (INSN_DSP): New define for DSP ASE.
1865
848cf006
AM		 18662005-08-18 Alan Modra <amodra@bigpond.net.au>
1867
1868 * a29k.h: Delete.
1869
36ae0db3
DJ		 18702005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1871
1872 * ppc.h (PPC_OPCODE_E300): Define.
1873
8c929562
MS		 18742005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1875
1876 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1877
f7b8cccc
DA		 18782005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1879
1880 PR gas/336
1881 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1882 and pitlb.
1883
8b5328ac
JB		 18842005-07-27 Jan Beulich <jbeulich@novell.com>
1885
1886 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1887 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1888 Add movq-s as 64-bit variants of movd-s.
1889
f417d200
DA		 18902005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1891
18b3bdfc
DA		 1892 * hppa.h: Fix punctuation in comment.
1893
f417d200
DA		 1894 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1895 implicit space-register addressing. Set space-register bits on opcodes
1896 using implicit space-register addressing. Add various missing pa20
1897 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1898 space-register addressing. Use "fE" instead of "fe" in various
1899 fstw opcodes.
1900
9a145ce6
JB		 19012005-07-18 Jan Beulich <jbeulich@novell.com>
1902
1903 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1904
90700ea2
L		 19052007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1906
1907 * i386.h (i386_optab): Support Intel VMX Instructions.
1908
48f130a8
DA		 19092005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1910
1911 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1912
30123838
JB		 19132005-07-05 Jan Beulich <jbeulich@novell.com>
1914
1915 * i386.h (i386_optab): Add new insns.
1916
47b0e7ad
NC		 19172005-07-01 Nick Clifton <nickc@redhat.com>
1918
1919 * sparc.h: Add typedefs to structure declarations.
1920
b300c311
L		 19212005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1922
1923 PR 1013
1924 * i386.h (i386_optab): Update comments for 64bit addressing on
1925 mov. Allow 64bit addressing for mov and movq.
1926
2db495be
DA		 19272005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1928
1929 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1930 respectively, in various floating-point load and store patterns.
1931
caa05036
DA		 19322005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1933
1934 * hppa.h (FLAG_STRICT): Correct comment.
1935 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1936 PA 2.0 mneumonics when equivalent. Entries with cache control
1937 completers now require PA 1.1. Adjust whitespace.
1938
f4411256
AM		 19392005-05-19 Anton Blanchard <anton@samba.org>
1940
1941 * ppc.h (PPC_OPCODE_POWER5): Define.
1942
e172dbf8
NC		 19432005-05-10 Nick Clifton <nickc@redhat.com>
1944
1945 * Update the address and phone number of the FSF organization in
1946 the GPL notices in the following files:
1947 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1948 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1949 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1950 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1951 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1952 tic54x.h, tic80.h, v850.h, vax.h
1953
e44823cf
JB		 19542005-05-09 Jan Beulich <jbeulich@novell.com>
1955
1956 * i386.h (i386_optab): Add ht and hnt.
1957
791fe849
MK		 19582005-04-18 Mark Kettenis <kettenis@gnu.org>
1959
1960 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1961 Add xcrypt-ctr. Provide aliases without hyphens.
1962
faa7ef87
L		 19632005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1964
a63027e5
L		 1965 Moved from ../ChangeLog
1966
faa7ef87
L		 1967 2005-04-12 Paul Brook <paul@codesourcery.com>
1968 * m88k.h: Rename psr macros to avoid conflicts.
1969
1970 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1971 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1972 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1973 and ARM_ARCH_V6ZKT2.
1974
1975 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1976 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1977 Remove redundant instruction types.
1978 (struct argument): X_op - new field.
1979 (struct cst4_entry): Remove.
1980 (no_op_insn): Declare.
1981
1982 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1983 * crx.h (enum argtype): Rename types, remove unused types.
1984
1985 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1986 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1987 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1988 (enum operand_type): Rearrange operands, edit comments.
1989 replace us<N> with ui<N> for unsigned immediate.
1990 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1991 displacements (respectively).
1992 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1993 (instruction type): Add NO_TYPE_INS.
1994 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1995 (operand_entry): New field - 'flags'.
1996 (operand flags): New.
1997
1998 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1999 * crx.h (operand_type): Remove redundant types i3, i4,
2000 i5, i8, i12.
2001 Add new unsigned immediate types us3, us4, us5, us16.
2002
bc4bd9ab
MK		 20032005-04-12 Mark Kettenis <kettenis@gnu.org>
2004
2005 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2006 adjust them accordingly.
2007
373ff435
JB		 20082005-04-01 Jan Beulich <jbeulich@novell.com>
2009
2010 * i386.h (i386_optab): Add rdtscp.
2011
4cc91dba
L		 20122005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2013
2014 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2015 between memory and segment register. Allow movq for moving between
2016 general-purpose register and segment register.
4cc91dba 2017
9ae09ff9
JB		 20182005-02-09 Jan Beulich <jbeulich@novell.com>
2019
2020 PR gas/707
2021 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2022 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2023 fnstsw.
2024
638e7a64
NS		 20252006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2026
2027 * m68k.h (m68008, m68ec030, m68882): Remove.
2028 (m68k_mask): New.
2029 (cpu_m68k, cpu_cf): New.
2030 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2031 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2032
90219bd0
AO		 20332005-01-25 Alexandre Oliva <aoliva@redhat.com>
2034
2035 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2036 * cgen.h (enum cgen_parse_operand_type): Add
2037 CGEN_PARSE_OPERAND_SYMBOLIC.
2038
239cb185
FF		 20392005-01-21 Fred Fish <fnf@specifixinc.com>
2040
2041 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2042 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2043 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2044
dc9a9f39
FF		 20452005-01-19 Fred Fish <fnf@specifixinc.com>
2046
2047 * mips.h (struct mips_opcode): Add new pinfo2 member.
2048 (INSN_ALIAS): New define for opcode table entries that are
2049 specific instances of another entry, such as 'move' for an 'or'
2050 with a zero operand.
2051 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2052 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2053
98e7aba8
ILT		 20542004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2055
2056 * mips.h (CPU_RM9000): Define.
2057 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2058
37edbb65
JB		 20592004-11-25 Jan Beulich <jbeulich@novell.com>
2060
2061 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2062 to/from test registers are illegal in 64-bit mode. Add missing
2063 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2064 (previously one had to explicitly encode a rex64 prefix). Re-enable
2065 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2066 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2067
20682004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2069
2070 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2071 available only with SSE2. Change the MMX additions introduced by SSE
2072 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2073 instructions by their now designated identifier (since combining i686
2074 and 3DNow! does not really imply 3DNow!A).
2075
f5c7edf4
AM		 20762004-11-19 Alan Modra <amodra@bigpond.net.au>
2077
2078 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2079 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2080
7499d566
NC		 20812004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2082 Vineet Sharma <vineets@noida.hcltech.com>
2083
2084 * maxq.h: New file: Disassembly information for the maxq port.
2085
bcb9eebe
L		 20862004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2087
2088 * i386.h (i386_optab): Put back "movzb".
2089
94bb3d38
HPN		 20902004-11-04 Hans-Peter Nilsson <hp@axis.com>
2091
2092 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2093 comments. Remove member cris_ver_sim. Add members
2094 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2095 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2096 (struct cris_support_reg, struct cris_cond15): New types.
2097 (cris_conds15): Declare.
2098 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2099 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2100 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2101 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2102 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2103 SIZE_FIELD_UNSIGNED.
2104
37edbb65 21052004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2106
2107 * i386.h (sldx_Suf): Remove.
2108 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2109 (q_FP): Define, implying no REX64.
2110 (x_FP, sl_FP): Imply FloatMF.
2111 (i386_optab): Split reg and mem forms of moving from segment registers
2112 so that the memory forms can ignore the 16-/32-bit operand size
2113 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2114 all non-floating-point instructions. Unite 32- and 64-bit forms of
2115 movsx, movzx, and movd. Adjust floating point operations for the above
2116 changes to the *FP macros. Add DefaultSize to floating point control
2117 insns operating on larger memory ranges. Remove left over comments
2118 hinting at certain insns being Intel-syntax ones where the ones
2119 actually meant are already gone.
2120
48c9f030
NC		 21212004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2122
2123 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2124 instruction type.
2125
0dd132b6
NC		 21262004-09-30 Paul Brook <paul@codesourcery.com>
2127
2128 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2129 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2130
23794b24
MM		 21312004-09-11 Theodore A. Roth <troth@openavr.org>
2132
2133 * avr.h: Add support for
2134 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2135
2a309db0
AM		 21362004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2137
2138 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2139
b18c562e
NC		 21402004-08-24 Dmitry Diky <diwil@spec.ru>
2141
2142 * msp430.h (msp430_opc): Add new instructions.
2143 (msp430_rcodes): Declare new instructions.
2144 (msp430_hcodes): Likewise..
2145
45d313cd
NC		 21462004-08-13 Nick Clifton <nickc@redhat.com>
2147
2148 PR/301
2149 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2150 processors.
2151
30d1c836
ML		 21522004-08-30 Michal Ludvig <mludvig@suse.cz>
2153
2154 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2155
9a45f1c2
L		 21562004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2157
2158 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2159
543613e9
NC		 21602004-07-21 Jan Beulich <jbeulich@novell.com>
2161
2162 * i386.h: Adjust instruction descriptions to better match the
2163 specification.
2164
b781e558
RE		 21652004-07-16 Richard Earnshaw <rearnsha@arm.com>
2166
2167 * arm.h: Remove all old content. Replace with architecture defines
2168 from gas/config/tc-arm.c.
2169
8577e690
AS		 21702004-07-09 Andreas Schwab <schwab@suse.de>
2171
2172 * m68k.h: Fix comment.
2173
1fe1f39c
NC		 21742004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2175
2176 * crx.h: New file.
2177
1d9f512f
AM		 21782004-06-24 Alan Modra <amodra@bigpond.net.au>
2179
2180 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2181
be8c092b
NC		 21822004-05-24 Peter Barada <peter@the-baradas.com>
2183
2184 * m68k.h: Add 'size' to m68k_opcode.
2185
6b6e92f4
NC		 21862004-05-05 Peter Barada <peter@the-baradas.com>
2187
2188 * m68k.h: Switch from ColdFire chip name to core variant.
2189
21902004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2191
2192 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2193 descriptions for new EMAC cases.
2194 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2195 handle Motorola MAC syntax.
2196 Allow disassembly of ColdFire V4e object files.
2197
fdd12ef3
AM		 21982004-03-16 Alan Modra <amodra@bigpond.net.au>
2199
2200 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2201
3922a64c
L		 22022004-03-12 Jakub Jelinek <jakub@redhat.com>
2203
2204 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2205
1f45d988
ML		 22062004-03-12 Michal Ludvig <mludvig@suse.cz>
2207
2208 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2209
0f10071e
ML		 22102004-03-12 Michal Ludvig <mludvig@suse.cz>
2211
2212 * i386.h (i386_optab): Added xstore/xcrypt insns.
2213
3255318a
NC		 22142004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2215
2216 * h8300.h (32bit ldc/stc): Add relaxing support.
2217
ca9a79a1 22182004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2219
ca9a79a1
NC		 2220 * h8300.h (BITOP): Pass MEMRELAX flag.
2221
875a0b14
NC		 22222004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2223
2224 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2225 except for the H8S.
252b5132 2226
c9e214e5 2227For older changes see ChangeLog-9103
252b5132 2228\f
b90efa5b 2229Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2230
2231Copying and distribution of this file, with or without modification,
2232are permitted in any medium without royalty provided the copyright
2233notice and this notice are preserved.
2234
252b5132 2235Local Variables:
c9e214e5
AM		 2236mode: change-log
2237left-margin: 8
2238fill-column: 74
252b5132
RH		 2239version-control: never
2240End:
GDB Binutils - Deliverables
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