projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 161a04f6 L |
1 | 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> |
| 2 | ||
| 3 | * i386.h (REX_MODE64): Renamed to ... | |
| 4 | (REX_W): This. | |
| 5 | (REX_EXTX): Renamed to ... | |
| 6 | (REX_R): This. | |
| 7 | (REX_EXTY): Renamed to ... | |
| 8 | (REX_X): This. | |
| 9 | (REX_EXTZ): Renamed to ... | |
| 10 | (REX_B): This. | |
| 11 | ||
| 0b1cf022 L |
12 | 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> |
| 13 | ||
| 14 | * i386.h: Add entries from config/tc-i386.h and move tables | |
| 15 | to opcodes/i386-opc.h. | |
| 16 | ||
| d796c0ad L |
17 | 2007-03-13 H.J. Lu <hongjiu.lu@intel.com> |
| 18 | ||
| 19 | * i386.h (FloatDR): Removed. | |
| 20 | (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. | |
| 21 | ||
| 30ac7323 AM |
22 | 2007-03-01 Alan Modra <amodra@bigpond.net.au> |
| 23 | ||
| 24 | * spu-insns.h: Add soma double-float insns. | |
| 25 | ||
| 8b082fb1 | 26 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
| d796c0ad | 27 | Chao-Ying Fu <fu@mips.com> |
| 8b082fb1 TS |
28 | |
| 29 | * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. | |
| 30 | (INSN_DSPR2): Add flag for DSP R2 instructions. | |
| 31 | (M_BALIGN): New macro. | |
| 32 | ||
| 4eed87de AM |
33 | 2007-02-14 Alan Modra <amodra@bigpond.net.au> |
| 34 | ||
| 35 | * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm | |
| 36 | and Seg3ShortFrom with Shortform. | |
| 37 | ||
| fda592e8 L |
38 | 2007-02-11 H.J. Lu <hongjiu.lu@intel.com> |
| 39 | ||
| 40 | PR gas/4027 | |
| 41 | * i386.h (i386_optab): Put the real "test" before the pseudo | |
| 42 | one. | |
| 43 | ||
| 3bdcfdf4 KH |
44 | 2007-01-08 Kazu Hirata <kazu@codesourcery.com> |
| 45 | ||
| 46 | * m68k.h (m68010up): OR fido_a. | |
| 47 | ||
| 9840d27e KH |
48 | 2006-12-25 Kazu Hirata <kazu@codesourcery.com> |
| 49 | ||
| 50 | * m68k.h (fido_a): New. | |
| 51 | ||
| c629cdac KH |
52 | 2006-12-24 Kazu Hirata <kazu@codesourcery.com> |
| 53 | ||
| 54 | * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, | |
| 55 | mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined | |
| 56 | values. | |
| 57 | ||
| b7d9ef37 L |
58 | 2006-11-08 H.J. Lu <hongjiu.lu@intel.com> |
| 59 | ||
| 60 | * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. | |
| 61 | ||
| b138abaa NC |
62 | 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> |
| 63 | ||
| 64 | * score-inst.h (enum score_insn_type): Add Insn_internal. | |
| 65 | ||
| e9f53129 AM |
66 | 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> |
| 67 | Yukishige Shibata <shibata@rd.scei.sony.co.jp> | |
| 68 | Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> | |
| 69 | Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> | |
| 70 | Alan Modra <amodra@bigpond.net.au> | |
| 71 | ||
| 72 | * spu-insns.h: New file. | |
| 73 | * spu.h: New file. | |
| 74 | ||
| ede602d7 AM |
75 | 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> |
| 76 | ||
| 77 | * ppc.h (PPC_OPCODE_CELL): Define. | |
| 78 | ||
| 7918206c MM |
79 | 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
| 80 | ||
| 81 | * i386.h : Modify opcode to support for the change in POPCNT opcode | |
| 82 | in amdfam10 architecture. | |
| 83 | ||
| ef05d495 L |
84 | 2006-09-28 H.J. Lu <hongjiu.lu@intel.com> |
| 85 | ||
| 86 | * i386.h: Replace CpuMNI with CpuSSSE3. | |
| 87 | ||
| 2d447fca JM |
88 | 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> |
| 89 | Joseph Myers <joseph@codesourcery.com> | |
| 90 | Ian Lance Taylor <ian@wasabisystems.com> | |
| 91 | Ben Elliston <bje@wasabisystems.com> | |
| 92 | ||
| 93 | * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. | |
| 94 | ||
| 1c0d3aa6 NC |
95 | 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> |
| 96 | ||
| 97 | * score-datadep.h: New file. | |
| 98 | * score-inst.h: New file. | |
| 99 | ||
| c2f0420e L |
100 | 2006-07-14 H.J. Lu <hongjiu.lu@intel.com> |
| 101 | ||
| 102 | * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, | |
| 103 | movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, | |
| 104 | movdq2q and movq2dq. | |
| 105 | ||
| 050dfa73 MM |
106 | 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
| 107 | Michael Meissner <michael.meissner@amd.com> | |
| 108 | ||
| 109 | * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). | |
| 110 | ||
| 15965411 L |
111 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
| 112 | ||
| 113 | * i386.h (i386_optab): Add "nop" with memory reference. | |
| 114 | ||
| 46e883c5 L |
115 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
| 116 | ||
| 117 | * i386.h (i386_optab): Update comment for 64bit NOP. | |
| 118 | ||
| 9622b051 AM |
119 | 2006-06-06 Ben Elliston <bje@au.ibm.com> |
| 120 | Anton Blanchard <anton@samba.org> | |
| 121 | ||
| 122 | * ppc.h (PPC_OPCODE_POWER6): Define. | |
| 123 | Adjust whitespace. | |
| 124 | ||
| a9e24354 TS |
125 | 2006-06-05 Thiemo Seufer <ths@mips.com> |
| 126 | ||
| 127 | * mips.h: Improve description of MT flags. | |
| 128 | ||
| a596001e RS |
129 | 2006-05-25 Richard Sandiford <richard@codesourcery.com> |
| 130 | ||
| 131 | * m68k.h (mcf_mask): Define. | |
| 132 | ||
| d43b4baf TS |
133 | 2006-05-05 Thiemo Seufer <ths@mips.com> |
| 134 | David Ung <davidu@mips.com> | |
| 135 | ||
| 136 | * mips.h (enum): Add macro M_CACHE_AB. | |
| 137 | ||
| 39a7806d TS |
138 | 2006-05-04 Thiemo Seufer <ths@mips.com> |
| 139 | Nigel Stephens <nigel@mips.com> | |
| 140 | David Ung <davidu@mips.com> | |
| 141 | ||
| 142 | * mips.h: Add INSN_SMARTMIPS define. | |
| 143 | ||
| 9bcd4f99 TS |
144 | 2006-04-30 Thiemo Seufer <ths@mips.com> |
| 145 | David Ung <davidu@mips.com> | |
| 146 | ||
| 147 | * mips.h: Defines udi bits and masks. Add description of | |
| 148 | characters which may appear in the args field of udi | |
| 149 | instructions. | |
| 150 | ||
| ef0ee844 TS |
151 | 2006-04-26 Thiemo Seufer <ths@networkno.de> |
| 152 | ||
| 153 | * mips.h: Improve comments describing the bitfield instruction | |
| 154 | fields. | |
| 155 | ||
| f7675147 L |
156 | 2006-04-26 Julian Brown <julian@codesourcery.com> |
| 157 | ||
| 158 | * arm.h (FPU_VFP_EXT_V3): Define constant. | |
| 159 | (FPU_NEON_EXT_V1): Likewise. | |
| 160 | (FPU_VFP_HARD): Update. | |
| 161 | (FPU_VFP_V3): Define macro. | |
| 162 | (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. | |
| 163 | ||
| ef0ee844 | 164 | 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> |
| d727e8c2 NC |
165 | |
| 166 | * avr.h (AVR_ISA_PWMx): New. | |
| 167 | ||
| 2da12c60 NS |
168 | 2006-03-28 Nathan Sidwell <nathan@codesourcery.com> |
| 169 | ||
| 170 | * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, | |
| 171 | cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, | |
| 172 | cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, | |
| 173 | cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, | |
| 174 | cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. | |
| 175 | ||
| 0715c387 PB |
176 | 2006-03-10 Paul Brook <paul@codesourcery.com> |
| 177 | ||
| 178 | * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. | |
| 179 | ||
| 34bdd094 DA |
180 | 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 181 | ||
| 182 | * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come | |
| 183 | first. Correct mask of bb "B" opcode. | |
| 184 | ||
| 331d2d0d L |
185 | 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> |
| 186 | ||
| 187 | * i386.h (i386_optab): Support Intel Merom New Instructions. | |
| 188 | ||
| 62b3e311 PB |
189 | 2006-02-24 Paul Brook <paul@codesourcery.com> |
| 190 | ||
| 191 | * arm.h: Add V7 feature bits. | |
| 192 | ||
| 59cf82fe L |
193 | 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> |
| 194 | ||
| 195 | * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. | |
| 196 | ||
| e74cfd16 PB |
197 | 2006-01-31 Paul Brook <paul@codesourcery.com> |
| 198 | Richard Earnshaw <rearnsha@arm.com> | |
| 199 | ||
| 200 | * arm.h: Use ARM_CPU_FEATURE. | |
| 201 | (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. | |
| 202 | (arm_feature_set): Change to a structure. | |
| 203 | (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, | |
| 204 | ARM_FEATURE): New macros. | |
| 205 | ||
| 5b3f8a92 HPN |
206 | 2005-12-07 Hans-Peter Nilsson <hp@axis.com> |
| 207 | ||
| 208 | * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) | |
| 209 | (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. | |
| 210 | (ADD_PC_INCR_OPCODE): Don't define. | |
| 211 | ||
| cb712a9e L |
212 | 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> |
| 213 | ||
| 214 | PR gas/1874 | |
| 215 | * i386.h (i386_optab): Add 64bit support for monitor and mwait. | |
| 216 | ||
| 0499d65b TS |
217 | 2005-11-14 David Ung <davidu@mips.com> |
| 218 | ||
| 219 | * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore | |
| 220 | instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for | |
| 221 | save/restore encoding of the args field. | |
| 222 | ||
| ea5ca089 DB |
223 | 2005-10-28 Dave Brolley <brolley@redhat.com> |
| 224 | ||
| 225 | Contribute the following changes: | |
| 226 | 2005-02-16 Dave Brolley <brolley@redhat.com> | |
| 227 | ||
| 228 | * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename | |
| 229 | cgen_isa_mask_* to cgen_bitset_*. | |
| 230 | * cgen.h: Likewise. | |
| 231 | ||
| 16175d96 DB |
232 | 2003-10-21 Richard Sandiford <rsandifo@redhat.com> |
| 233 | ||
| 234 | * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. | |
| 235 | (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". | |
| 236 | (CGEN_CPU_TABLE): Make isas a ponter. | |
| 237 | ||
| 238 | 2003-09-29 Dave Brolley <brolley@redhat.com> | |
| 239 | ||
| 240 | * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. | |
| 241 | (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. | |
| 242 | (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. | |
| 243 | ||
| 244 | 2002-12-13 Dave Brolley <brolley@redhat.com> | |
| 245 | ||
| 246 | * cgen.h (symcat.h): #include it. | |
| 247 | (cgen-bitset.h): #include it. | |
| 248 | (CGEN_ATTR_VALUE_TYPE): Now a union. | |
| 249 | (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. | |
| 250 | (CGEN_ATTR_ENTRY): 'value' now unsigned. | |
| 251 | (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). | |
| 252 | * cgen-bitset.h: New file. | |
| 253 | ||
| 3c9b82ba NC |
254 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
| 255 | ||
| 256 | * bfin.h: New file. | |
| 257 | ||
| 6a2375c6 JB |
258 | 2005-10-24 Jan Beulich <jbeulich@novell.com> |
| 259 | ||
| 260 | * ia64.h (enum ia64_opnd): Move memory operand out of set of | |
| 261 | indirect operands. | |
| 262 | ||
| c06a12f8 DA |
263 | 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 264 | ||
| 265 | * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. | |
| 266 | Add FLAG_STRICT to pa10 ftest opcode. | |
| 267 | ||
| 4d443107 DA |
268 | 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 269 | ||
| 270 | * hppa.h (pa_opcodes): Remove lha entries. | |
| 271 | ||
| f0a3b40f DA |
272 | 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 273 | ||
| 274 | * hppa.h (FLAG_STRICT): Revise comment. | |
| 275 | (pa_opcode): Revise ordering rules. Add/move strict pa10 variants | |
| 276 | before corresponding pa11 opcodes. Add strict pa10 register-immediate | |
| 277 | entries for "fdc". | |
| 278 | ||
| 1b7e1362 DA |
279 | 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 280 | ||
| 281 | * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. | |
| 282 | ||
| 089b39de CF |
283 | 2005-09-06 Chao-ying Fu <fu@mips.com> |
| 284 | ||
| 285 | * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, | |
| 286 | OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New | |
| 287 | define. | |
| 288 | Document !, $, *, &, g, +t, +T operand formats for MT instructions. | |
| 289 | (INSN_ASE_MASK): Update to include INSN_MT. | |
| 290 | (INSN_MT): New define for MT ASE. | |
| 291 | ||
| 93c34b9b CF |
292 | 2005-08-25 Chao-ying Fu <fu@mips.com> |
| 293 | ||
| 294 | * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, | |
| 295 | OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, | |
| 296 | OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, | |
| 297 | OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, | |
| 298 | OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. | |
| 299 | Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP | |
| 300 | instructions. | |
| 301 | (INSN_DSP): New define for DSP ASE. | |
| 302 | ||
| 848cf006 AM |
303 | 2005-08-18 Alan Modra <amodra@bigpond.net.au> |
| 304 | ||
| 305 | * a29k.h: Delete. | |
| 306 | ||
| 36ae0db3 DJ |
307 | 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> |
| 308 | ||
| 309 | * ppc.h (PPC_OPCODE_E300): Define. | |
| 310 | ||
| 8c929562 MS |
311 | 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> |
| 312 | ||
| 313 | * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. | |
| 314 | ||
| f7b8cccc DA |
315 | 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 316 | ||
| 317 | PR gas/336 | |
| 318 | * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb | |
| 319 | and pitlb. | |
| 320 | ||
| 8b5328ac JB |
321 | 2005-07-27 Jan Beulich <jbeulich@novell.com> |
| 322 | ||
| 323 | * i386.h (i386_optab): Add comment to movd. Use LongMem for all | |
| 324 | movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. | |
| 325 | Add movq-s as 64-bit variants of movd-s. | |
| 326 | ||
| f417d200 DA |
327 | 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 328 | ||
| 18b3bdfc DA |
329 | * hppa.h: Fix punctuation in comment. |
| 330 | ||
| f417d200 DA |
331 | * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for |
| 332 | implicit space-register addressing. Set space-register bits on opcodes | |
| 333 | using implicit space-register addressing. Add various missing pa20 | |
| 334 | long-immediate opcodes. Remove various opcodes using implicit 3-bit | |
| 335 | space-register addressing. Use "fE" instead of "fe" in various | |
| 336 | fstw opcodes. | |
| 337 | ||
| 9a145ce6 JB |
338 | 2005-07-18 Jan Beulich <jbeulich@novell.com> |
| 339 | ||
| 340 | * i386.h (i386_optab): Operands of aam and aad are unsigned. | |
| 341 | ||
| 90700ea2 L |
342 | 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> |
| 343 | ||
| 344 | * i386.h (i386_optab): Support Intel VMX Instructions. | |
| 345 | ||
| 48f130a8 DA |
346 | 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 347 | ||
| 348 | * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. | |
| 349 | ||
| 30123838 JB |
350 | 2005-07-05 Jan Beulich <jbeulich@novell.com> |
| 351 | ||
| 352 | * i386.h (i386_optab): Add new insns. | |
| 353 | ||
| 47b0e7ad NC |
354 | 2005-07-01 Nick Clifton <nickc@redhat.com> |
| 355 | ||
| 356 | * sparc.h: Add typedefs to structure declarations. | |
| 357 | ||
| b300c311 L |
358 | 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> |
| 359 | ||
| 360 | PR 1013 | |
| 361 | * i386.h (i386_optab): Update comments for 64bit addressing on | |
| 362 | mov. Allow 64bit addressing for mov and movq. | |
| 363 | ||
| 2db495be DA |
364 | 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 365 | ||
| 366 | * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, | |
| 367 | respectively, in various floating-point load and store patterns. | |
| 368 | ||
| caa05036 DA |
369 | 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 370 | ||
| 371 | * hppa.h (FLAG_STRICT): Correct comment. | |
| 372 | (pa_opcodes): Update load and store entries to allow both PA 1.X and | |
| 373 | PA 2.0 mneumonics when equivalent. Entries with cache control | |
| 374 | completers now require PA 1.1. Adjust whitespace. | |
| 375 | ||
| f4411256 AM |
376 | 2005-05-19 Anton Blanchard <anton@samba.org> |
| 377 | ||
| 378 | * ppc.h (PPC_OPCODE_POWER5): Define. | |
| 379 | ||
| e172dbf8 NC |
380 | 2005-05-10 Nick Clifton <nickc@redhat.com> |
| 381 | ||
| 382 | * Update the address and phone number of the FSF organization in | |
| 383 | the GPL notices in the following files: | |
| 384 | a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, | |
| 385 | crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, | |
| 386 | i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, | |
| 387 | mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, | |
| 388 | pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, | |
| 389 | tic54x.h, tic80.h, v850.h, vax.h | |
| 390 | ||
| e44823cf JB |
391 | 2005-05-09 Jan Beulich <jbeulich@novell.com> |
| 392 | ||
| 393 | * i386.h (i386_optab): Add ht and hnt. | |
| 394 | ||
| 791fe849 MK |
395 | 2005-04-18 Mark Kettenis <kettenis@gnu.org> |
| 396 | ||
| 397 | * i386.h: Insert hyphens into selected VIA PadLock extensions. | |
| 398 | Add xcrypt-ctr. Provide aliases without hyphens. | |
| 399 | ||
| faa7ef87 L |
400 | 2005-04-13 H.J. Lu <hongjiu.lu@intel.com> |
| 401 | ||
| a63027e5 L |
402 | Moved from ../ChangeLog |
| 403 | ||
| faa7ef87 L |
404 | 2005-04-12 Paul Brook <paul@codesourcery.com> |
| 405 | * m88k.h: Rename psr macros to avoid conflicts. | |
| 406 | ||
| 407 | 2005-03-12 Zack Weinberg <zack@codesourcery.com> | |
| 408 | * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. | |
| 409 | Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, | |
| 410 | and ARM_ARCH_V6ZKT2. | |
| 411 | ||
| 412 | 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> | |
| 413 | * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. | |
| 414 | Remove redundant instruction types. | |
| 415 | (struct argument): X_op - new field. | |
| 416 | (struct cst4_entry): Remove. | |
| 417 | (no_op_insn): Declare. | |
| 418 | ||
| 419 | 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> | |
| 420 | * crx.h (enum argtype): Rename types, remove unused types. | |
| 421 | ||
| 422 | 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> | |
| 423 | * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. | |
| 424 | (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. | |
| 425 | (enum operand_type): Rearrange operands, edit comments. | |
| 426 | replace us<N> with ui<N> for unsigned immediate. | |
| 427 | replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped | |
| 428 | displacements (respectively). | |
| 429 | replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. | |
| 430 | (instruction type): Add NO_TYPE_INS. | |
| 431 | (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. | |
| 432 | (operand_entry): New field - 'flags'. | |
| 433 | (operand flags): New. | |
| 434 | ||
| 435 | 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> | |
| 436 | * crx.h (operand_type): Remove redundant types i3, i4, | |
| 437 | i5, i8, i12. | |
| 438 | Add new unsigned immediate types us3, us4, us5, us16. | |
| 439 | ||
| bc4bd9ab MK |
440 | 2005-04-12 Mark Kettenis <kettenis@gnu.org> |
| 441 | ||
| 442 | * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and | |
| 443 | adjust them accordingly. | |
| 444 | ||
| 373ff435 JB |
445 | 2005-04-01 Jan Beulich <jbeulich@novell.com> |
| 446 | ||
| 447 | * i386.h (i386_optab): Add rdtscp. | |
| 448 | ||
| 4cc91dba L |
449 | 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> |
| 450 | ||
| 451 | * i386.h (i386_optab): Don't allow the `l' suffix for moving | |
| 418a8fca AS |
452 | between memory and segment register. Allow movq for moving between |
| 453 | general-purpose register and segment register. | |
| 4cc91dba | 454 | |
| 9ae09ff9 JB |
455 | 2005-02-09 Jan Beulich <jbeulich@novell.com> |
| 456 | ||
| 457 | PR gas/707 | |
| 458 | * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and | |
| 459 | FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and | |
| 460 | fnstsw. | |
| 461 | ||
| 638e7a64 NS |
462 | 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> |
| 463 | ||
| 464 | * m68k.h (m68008, m68ec030, m68882): Remove. | |
| 465 | (m68k_mask): New. | |
| 466 | (cpu_m68k, cpu_cf): New. | |
| 467 | (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, | |
| 468 | mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. | |
| 469 | ||
| 90219bd0 AO |
470 | 2005-01-25 Alexandre Oliva <aoliva@redhat.com> |
| 471 | ||
| 472 | 2004-11-10 Alexandre Oliva <aoliva@redhat.com> | |
| 473 | * cgen.h (enum cgen_parse_operand_type): Add | |
| 474 | CGEN_PARSE_OPERAND_SYMBOLIC. | |
| 475 | ||
| 239cb185 FF |
476 | 2005-01-21 Fred Fish <fnf@specifixinc.com> |
| 477 | ||
| 478 | * mips.h: Change INSN_ALIAS to INSN2_ALIAS. | |
| 479 | Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. | |
| 480 | Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. | |
| 481 | ||
| dc9a9f39 FF |
482 | 2005-01-19 Fred Fish <fnf@specifixinc.com> |
| 483 | ||
| 484 | * mips.h (struct mips_opcode): Add new pinfo2 member. | |
| 485 | (INSN_ALIAS): New define for opcode table entries that are | |
| 486 | specific instances of another entry, such as 'move' for an 'or' | |
| 487 | with a zero operand. | |
| 488 | (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. | |
| 489 | (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. | |
| 490 | ||
| 98e7aba8 ILT |
491 | 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> |
| 492 | ||
| 493 | * mips.h (CPU_RM9000): Define. | |
| 494 | (OPCODE_IS_MEMBER): Handle CPU_RM9000. | |
| 495 | ||
| 37edbb65 JB |
496 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
| 497 | ||
| 498 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves | |
| 499 | to/from test registers are illegal in 64-bit mode. Add missing | |
| 500 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix | |
| 501 | (previously one had to explicitly encode a rex64 prefix). Re-enable | |
| 502 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings | |
| 503 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. | |
| 504 | ||
| 505 | 2004-11-23 Jan Beulich <jbeulich@novell.com> | |
| 5c6af06e JB |
506 | |
| 507 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are | |
| 508 | available only with SSE2. Change the MMX additions introduced by SSE | |
| 509 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A | |
| 510 | instructions by their now designated identifier (since combining i686 | |
| 511 | and 3DNow! does not really imply 3DNow!A). | |
| 512 | ||
| f5c7edf4 AM |
513 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
| 514 | ||
| 515 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, | |
| 516 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. | |
| 517 | ||
| 7499d566 NC |
518 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
| 519 | Vineet Sharma <vineets@noida.hcltech.com> | |
| 520 | ||
| 521 | * maxq.h: New file: Disassembly information for the maxq port. | |
| 522 | ||
| bcb9eebe L |
523 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
| 524 | ||
| 525 | * i386.h (i386_optab): Put back "movzb". | |
| 526 | ||
| 94bb3d38 HPN |
527 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
| 528 | ||
| 529 | * cris.h (enum cris_insn_version_usage): Tweak formatting and | |
| 530 | comments. Remove member cris_ver_sim. Add members | |
| 531 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, | |
| 532 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. | |
| 533 | (struct cris_support_reg, struct cris_cond15): New types. | |
| 534 | (cris_conds15): Declare. | |
| 535 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) | |
| 536 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) | |
| 537 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. | |
| 538 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. | |
| 539 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and | |
| 540 | SIZE_FIELD_UNSIGNED. | |
| 541 | ||
| 37edbb65 | 542 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
| 9306ca4a JB |
543 | |
| 544 | * i386.h (sldx_Suf): Remove. | |
| 545 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. | |
| 546 | (q_FP): Define, implying no REX64. | |
| 547 | (x_FP, sl_FP): Imply FloatMF. | |
| 548 | (i386_optab): Split reg and mem forms of moving from segment registers | |
| 549 | so that the memory forms can ignore the 16-/32-bit operand size | |
| 550 | distinction. Adjust a few others for Intel mode. Remove *FP uses from | |
| 551 | all non-floating-point instructions. Unite 32- and 64-bit forms of | |
| 552 | movsx, movzx, and movd. Adjust floating point operations for the above | |
| 553 | changes to the *FP macros. Add DefaultSize to floating point control | |
| 554 | insns operating on larger memory ranges. Remove left over comments | |
| 555 | hinting at certain insns being Intel-syntax ones where the ones | |
| 556 | actually meant are already gone. | |
| 557 | ||
| 48c9f030 NC |
558 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 559 | ||
| 560 | * crx.h: Add COPS_REG_INS - Coprocessor Special register | |
| 561 | instruction type. | |
| 562 | ||
| 0dd132b6 NC |
563 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
| 564 | ||
| 565 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. | |
| 566 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. | |
| 567 | ||
| 23794b24 MM |
568 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
| 569 | ||
| 570 | * avr.h: Add support for | |
| 571 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. | |
| 572 | ||
| 2a309db0 AM |
573 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
| 574 | ||
| 575 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. | |
| 576 | ||
| b18c562e NC |
577 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
| 578 | ||
| 579 | * msp430.h (msp430_opc): Add new instructions. | |
| 580 | (msp430_rcodes): Declare new instructions. | |
| 581 | (msp430_hcodes): Likewise.. | |
| 582 | ||
| 45d313cd NC |
583 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
| 584 | ||
| 585 | PR/301 | |
| 586 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX | |
| 587 | processors. | |
| 588 | ||
| 30d1c836 ML |
589 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
| 590 | ||
| 591 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. | |
| 592 | ||
| 9a45f1c2 L |
593 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
| 594 | ||
| 595 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. | |
| 596 | ||
| 543613e9 NC |
597 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
| 598 | ||
| 599 | * i386.h: Adjust instruction descriptions to better match the | |
| 600 | specification. | |
| 601 | ||
| b781e558 RE |
602 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
| 603 | ||
| 604 | * arm.h: Remove all old content. Replace with architecture defines | |
| 605 | from gas/config/tc-arm.c. | |
| 606 | ||
| 8577e690 AS |
607 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
| 608 | ||
| 609 | * m68k.h: Fix comment. | |
| 610 | ||
| 1fe1f39c NC |
611 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 612 | ||
| 613 | * crx.h: New file. | |
| 614 | ||
| 1d9f512f AM |
615 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
| 616 | ||
| 617 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. | |
| 618 | ||
| be8c092b NC |
619 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
| 620 | ||
| 621 | * m68k.h: Add 'size' to m68k_opcode. | |
| 622 | ||
| 6b6e92f4 NC |
623 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
| 624 | ||
| 625 | * m68k.h: Switch from ColdFire chip name to core variant. | |
| 626 | ||
| 627 | 2004-04-22 Peter Barada <peter@the-baradas.com> | |
| fd99574b NC |
628 | |
| 629 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand | |
| 630 | descriptions for new EMAC cases. | |
| 631 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly | |
| 632 | handle Motorola MAC syntax. | |
| 633 | Allow disassembly of ColdFire V4e object files. | |
| 634 | ||
| fdd12ef3 AM |
635 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
| 636 | ||
| 637 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. | |
| 638 | ||
| 3922a64c L |
639 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
| 640 | ||
| 641 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. | |
| 642 | ||
| 1f45d988 ML |
643 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 644 | ||
| 645 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. | |
| 646 | ||
| 0f10071e ML |
647 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 648 | ||
| 649 | * i386.h (i386_optab): Added xstore/xcrypt insns. | |
| 650 | ||
| 3255318a NC |
651 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 652 | ||
| 653 | * h8300.h (32bit ldc/stc): Add relaxing support. | |
| 654 | ||
| ca9a79a1 | 655 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
| fdd12ef3 | 656 | |
| ca9a79a1 NC |
657 | * h8300.h (BITOP): Pass MEMRELAX flag. |
| 658 | ||
| 875a0b14 NC |
659 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 660 | ||
| 661 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 | |
| 662 | except for the H8S. | |
| 252b5132 | 663 | |
| c9e214e5 | 664 | For older changes see ChangeLog-9103 |
| 252b5132 RH |
665 | \f |
| 666 | Local Variables: | |
| c9e214e5 AM |
667 | mode: change-log |
| 668 | left-margin: 8 | |
| 669 | fill-column: 74 | |
| 252b5132 RH |
670 | version-control: never |
| 671 | End: |