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[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
36f4aab1
YQ		 12015-10-02 Yao Qi <yao.qi@linaro.org>
2
3 * aarch64.h (aarch64_decode_insn): Declare it.
4
7ecc513a
DV		 52015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
6
7 * s390.h (S390_INSTR_FLAG_HTM): New flag.
8 (S390_INSTR_FLAG_VX): New flag.
9 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
10
b6518b38
NC		 112015-09-23 Nick Clifton <nickc@redhat.com>
12
13 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
14 shifting.
15
f04265ec
NC		 162015-09-22 Nick Clifton <nickc@redhat.com>
17
18 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
19
7bdf96ef
NC		 202015-09-09 Daniel Santos <daniel.santos@pobox.com>
21
22 * visium.h (gen_reg_table): Make static.
23 (fp_reg_table): Likewise.
24 (cc_table): Likewise.
25
f33026a9
MW		 262015-07-20 Matthew Wahab <matthew.wahab@arm.com>
27
28 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
29 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
30 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
31 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
32
ef5a96d5
AM		 332015-07-03 Alan Modra <amodra@gmail.com>
34
35 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
36
c8c8175b
SL		 372015-07-01 Sandra Loosemore <sandra@codesourcery.com>
38 Cesar Philippidis <cesar@codesourcery.com>
39
40 * nios2.h (enum iw_format_type): Add R2 formats.
41 (enum overflow_type): Add signed_immed12_overflow and
42 enumeration_overflow for R2.
43 (struct nios2_opcode): Document new argument letters for R2.
44 (REG_3BIT, REG_LDWM, REG_POP): Define.
45 (includes): Include nios2r2.h.
46 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
47 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
48 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
49 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
50 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
51 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
52 Declare.
53 * nios2r2.h: New file.
54
11a0cf2e
PB		 552015-06-19 Peter Bergner <bergner@vnet.ibm.com>
56
57 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
58 (ppc_optional_operand_value): New inline function.
59
88f0ea34
MW		 602015-06-04 Matthew Wahab <matthew.wahab@arm.com>
61
62 * aarch64.h (AARCH64_V8_1): New.
63
a5932920
MW		 642015-06-03 Matthew Wahab <matthew.wahab@arm.com>
65
66 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
67 (ARM_ARCH_V8_1A): New.
68 (ARM_ARCH_V8_1A_FP): New.
69 (ARM_ARCH_V8_1A_SIMD): New.
70 (ARM_ARCH_V8_1A_CRYPTOV1): New.
71 (ARM_FEATURE_CORE): New.
72
ddfded2f
MW		 732015-06-02 Matthew Wahab <matthew.wahab@arm.com>
74
75 * arm.h (ARM_EXT2_PAN): New.
76 (ARM_FEATURE_CORE_HIGH): New.
77
1af1dd51
MW		 782015-06-02 Matthew Wahab <matthew.wahab@arm.com>
79
80 * arm.h (ARM_FEATURE_ALL): New.
81
9e1f0fa7
MW		 822015-06-02 Matthew Wahab <matthew.wahab@arm.com>
83
84 * aarch64.h (AARCH64_FEATURE_RDMA): New.
85
290806fd
MW		 862015-06-02 Matthew Wahab <matthew.wahab@arm.com>
87
88 * aarch64.h (AARCH64_FEATURE_LOR): New.
89
f21cce2c
MW		 902015-06-01 Matthew Wahab <matthew.wahab@arm.com>
91
92 * aarch64.h (AARCH64_FEATURE_PAN): New.
93 (aarch64_sys_reg_supported_p): Declare.
94 (aarch64_pstatefield_supported_p): Declare.
95
0952813b
DD		 962015-04-30 DJ Delorie <dj@redhat.com>
97
98 * rl78.h (RL78_Dis_Isa): New.
99 (rl78_decode_opcode): Add ISA parameter.
100
823d2571
TG		 1012015-03-24 Terry Guo <terry.guo@arm.com>
102
103 * arm.h (arm_feature_set): Extended to provide more available bits.
104 (ARM_ANY): Updated to follow above new definition.
105 (ARM_CPU_HAS_FEATURE): Likewise.
106 (ARM_CPU_IS_ANY): Likewise.
107 (ARM_MERGE_FEATURE_SETS): Likewise.
108 (ARM_CLEAR_FEATURE): Likewise.
109 (ARM_FEATURE): Likewise.
110 (ARM_FEATURE_COPY): New macro.
111 (ARM_FEATURE_EQUAL): Likewise.
112 (ARM_FEATURE_ZERO): Likewise.
113 (ARM_FEATURE_CORE_EQUAL): Likewise.
114 (ARM_FEATURE_LOW): Likewise.
115 (ARM_FEATURE_CORE_LOW): Likewise.
116 (ARM_FEATURE_CORE_COPROC): Likewise.
117
f63c1776
PA		 1182015-02-19 Pedro Alves <palves@redhat.com>
119
120 * cgen.h [__cplusplus]: Wrap in extern "C".
121 * msp430-decode.h [__cplusplus]: Likewise.
122 * nios2.h [__cplusplus]: Likewise.
123 * rl78.h [__cplusplus]: Likewise.
124 * rx.h [__cplusplus]: Likewise.
125 * tilegx.h [__cplusplus]: Likewise.
126
3f8107ab
AM		 1272015-01-28 James Bowman <james.bowman@ftdichip.com>
128
129 * ft32.h: New file.
130
1e2e8c52
AK		 1312015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
132
133 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
134
b90efa5b
AM		 1352015-01-01 Alan Modra <amodra@gmail.com>
136
137 Update year range in copyright notice of all files.
138
bffb6004
AG		 1392014-12-27 Anthony Green <green@moxielogic.com>
140
141 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
142 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
143
1945cfa5
EB		 1442014-12-06 Eric Botcazou <ebotcazou@adacore.com>
145
146 * visium.h: New file.
147
d306ce58
SL		 1482014-11-28 Sandra Loosemore <sandra@codesourcery.com>
149
150 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
151 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
152 (NIOS2_INSN_OPTARG): Renumber.
153
b4714c7c
SL		 1542014-11-06 Sandra Loosemore <sandra@codesourcery.com>
155
156 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
157 declaration. Fix obsolete comment.
158
96ba4233
SL		 1592014-10-23 Sandra Loosemore <sandra@codesourcery.com>
160
161 * nios2.h (enum iw_format_type): New.
162 (struct nios2_opcode): Update comments. Add size and format fields.
163 (NIOS2_INSN_OPTARG): New.
164 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
165 (struct nios2_reg): Add regtype field.
166 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
167 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
168 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
169 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
170 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
171 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
172 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
173 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
174 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
175 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
176 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
177 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
178 (OP_MASK_OP, OP_SH_OP): Delete.
179 (OP_MASK_IOP, OP_SH_IOP): Delete.
180 (OP_MASK_IRD, OP_SH_IRD): Delete.
181 (OP_MASK_IRT, OP_SH_IRT): Delete.
182 (OP_MASK_IRS, OP_SH_IRS): Delete.
183 (OP_MASK_ROP, OP_SH_ROP): Delete.
184 (OP_MASK_RRD, OP_SH_RRD): Delete.
185 (OP_MASK_RRT, OP_SH_RRT): Delete.
186 (OP_MASK_RRS, OP_SH_RRS): Delete.
187 (OP_MASK_JOP, OP_SH_JOP): Delete.
188 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
189 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
190 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
191 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
192 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
193 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
194 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
195 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
196 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
197 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
198 (OP_MASK_<insn>, OP_MASK): Delete.
199 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
200 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
201 Include nios2r1.h to define new instruction opcode constants
202 and accessors.
203 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
204 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
205 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
206 (NUMOPCODES, NUMREGISTERS): Delete.
207 * nios2r1.h: New file.
208
0b6be415
JM		 2092014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
210
211 * sparc.h (HWCAP2_VIS3B): Documentation improved.
212
3d68f91c
JM		 2132014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
214
215 * sparc.h (sparc_opcode): new field `hwcaps2'.
216 (HWCAP2_FJATHPLUS): New define.
217 (HWCAP2_VIS3B): Likewise.
218 (HWCAP2_ADP): Likewise.
219 (HWCAP2_SPARC5): Likewise.
220 (HWCAP2_MWAIT): Likewise.
221 (HWCAP2_XMPMUL): Likewise.
222 (HWCAP2_XMONT): Likewise.
223 (HWCAP2_NSEC): Likewise.
224 (HWCAP2_FJATHHPC): Likewise.
225 (HWCAP2_FJDES): Likewise.
226 (HWCAP2_FJAES): Likewise.
227 Document the new operand kind `{', corresponding to the mcdper
228 ancillary state register.
229 Document the new operand kind }, which represents frsd floating
230 point registers (double precision) which must be the same than
231 frs1 in its containing instruction.
232
40c7a7cb
KLC		 2332014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
234
72f4393d 235 * nds32.h: Add new opcode declaration.
40c7a7cb 236
7361da2c
AB		 2372014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
238 Matthew Fortune <matthew.fortune@imgtec.com>
239
240 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
241 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
242 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
243 +I, +O, +R, +:, +\, +", +;
244 (mips_check_prev_operand): New struct.
245 (INSN2_FORBIDDEN_SLOT): New define.
246 (INSN_ISA32R6): New define.
247 (INSN_ISA64R6): New define.
248 (INSN_UPTO32R6): New define.
249 (INSN_UPTO64R6): New define.
250 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
251 (ISA_MIPS32R6): New define.
252 (ISA_MIPS64R6): New define.
253 (CPU_MIPS32R6): New define.
254 (CPU_MIPS64R6): New define.
255 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
256
ee804238
JW		 2572014-09-03 Jiong Wang <jiong.wang@arm.com>
258
259 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
260 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
261 (aarch64_insn_class): Add lse_atomic.
262 (F_LSE_SZ): New field added.
263 (opcode_has_special_coder): Recognize F_LSE_SZ.
264
5575639b
MR		 2652014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
266
267 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
268 over to `+J'.
269
43885403
MF		 2702014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
271
272 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
273 (INSN_LOAD_COPROC): New define.
274 (INSN_COPROC_MOVE_DELAY): Rename to...
275 (INSN_COPROC_MOVE): New define.
276
f36e8886 2772014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 278 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
279 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
280 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 281
282 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
283 (AVR_ISA_2xxxa): Define ISA without LPM.
284 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
285 Add doc for contraint used in 16 bit lds/sts.
286 Adjust ISA group for icall, ijmp, pop and push.
287 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
288
00b32ff2
NC		 2892014-05-19 Nick Clifton <nickc@redhat.com>
290
291 * msp430.h (struct msp430_operand_s): Add vshift field.
292
ae52f483
AB		 2932014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
294
295 * mips.h (INSN_ISA_MASK): Updated.
296 (INSN_ISA32R3): New define.
297 (INSN_ISA32R5): New define.
298 (INSN_ISA64R3): New define.
299 (INSN_ISA64R5): New define.
300 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
301 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
302 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
303 mips64r5.
304 (INSN_UPTO32R3): New define.
305 (INSN_UPTO32R5): New define.
306 (INSN_UPTO64R3): New define.
307 (INSN_UPTO64R5): New define.
308 (ISA_MIPS32R3): New define.
309 (ISA_MIPS32R5): New define.
310 (ISA_MIPS64R3): New define.
311 (ISA_MIPS64R5): New define.
312 (CPU_MIPS32R3): New define.
313 (CPU_MIPS32R5): New define.
314 (CPU_MIPS64R3): New define.
315 (CPU_MIPS64R5): New define.
316
3efe9ec5
RS		 3172014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
318
319 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
320
73589c9d
CS		 3212014-04-22 Christian Svensson <blue@cmd.nu>
322
323 * or32.h: Delete.
324
4b95cf5c
AM		 3252014-03-05 Alan Modra <amodra@gmail.com>
326
327 Update copyright years.
328
e269fea7
AB		 3292013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
330
331 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
332 microMIPS.
333
35c08157
KLC		 3342013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
335 Wei-Cheng Wang <cole945@gmail.com>
336
337 * nds32.h: New file for Andes NDS32.
338
594d8fa8
MF		 3392013-12-07 Mike Frysinger <vapier@gentoo.org>
340
341 * bfin.h: Remove +x file mode.
342
87b8eed7
YZ		 3432013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
344
345 * aarch64.h (aarch64_pstatefields): Change element type to
346 aarch64_sys_reg.
347
c9fb6e58
YZ		 3482013-11-18 Renlin Li <Renlin.Li@arm.com>
349
350 * arm.h (ARM_AEXT_V7VE): New define.
351 (ARM_ARCH_V7VE): New define.
352 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
353
a203d9b7
YZ		 3542013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
355
356 Revert
357
358 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
359
360 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
361 (aarch64_sys_reg_writeonly_p): Ditto.
362
75468c93
YZ		 3632013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
364
365 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
366 (aarch64_sys_reg_writeonly_p): Ditto.
367
49eec193
YZ		 3682013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
369
370 * aarch64.h (aarch64_sys_reg): New typedef.
371 (aarch64_sys_regs): Change to define with the new type.
372 (aarch64_sys_reg_deprecated_p): Declare.
373
68a64283
YZ		 3742013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
375
376 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
377 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
378
387a82f1
CF		 3792013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
380
381 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
382 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
383 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
384 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
385 For MIPS, update extension character sequences after +.
386 (ASE_MSA): New define.
387 (ASE_MSA64): New define.
388 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
389 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
390 For microMIPS, update extension character sequences after +.
391
9aff4b7a
NC		 3922013-08-23 Yuri Chornoivan <yurchor@ukr.net>
393
394 PR binutils/15834
395 * i960.h: Fix typos.
396
e423441d
RS		 3972013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
398
399 * mips.h: Remove references to "+I" and imm2_expr.
400
5e0dc5ba
RS		 4012013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * mips.h (M_DEXT, M_DINS): Delete.
404
0f35dbc4
RS		 4052013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
406
407 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
408 (mips_optional_operand_p): New function.
409
14daeee3
RS		 4102013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
411 Richard Sandiford <rdsandiford@googlemail.com>
412
413 * mips.h: Document new VU0 operand characters.
414 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
415 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
416 (OP_REG_R5900_ACC): New mips_reg_operand_types.
417 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
418 (mips_vu0_channel_mask): Declare.
419
3ccad066
RS		 4202013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
421
422 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
423 (mips_int_operand_min, mips_int_operand_max): New functions.
424 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
425
fc76e730
RS		 4262013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
427
428 * mips.h (mips_decode_reg_operand): New function.
429 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
430 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
431 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
432 New macros.
433 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
434 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
435 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
436 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
437 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
438 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
439 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
440 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
441 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
442 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
443 macros to cover the gaps.
444 (INSN2_MOD_SP): Replace with...
445 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
446 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
447 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
448 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
449 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
450 Delete.
451
26545944
RS		 4522013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
453
454 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
455 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
456 (MIPS16_INSN_COND_BRANCH): Delete.
457
7e8b059b
L		 4582013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
459 Kirill Yukhin <kirill.yukhin@intel.com>
460 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
461
462 * i386.h (BND_PREFIX_OPCODE): New.
463
c3c07478
RS		 4642013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
465
466 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
467 OP_SAVE_RESTORE_LIST.
468 (decode_mips16_operand): Declare.
469
ab902481
RS		 4702013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
471
472 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
473 (mips_operand, mips_int_operand, mips_mapped_int_operand)
474 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
475 (mips_pcrel_operand): New structures.
476 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
477 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
478 (decode_mips_operand, decode_micromips_operand): Declare.
479
cc537e56
RS		 4802013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
481
482 * mips.h: Document MIPS16 "I" opcode.
483
f2ae14a1
RS		 4842013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
485
486 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
487 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
488 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
489 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
490 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
491 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
492 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
493 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
494 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
495 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
496 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
497 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
498 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
499 Rename to...
500 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
501 (M_USD_AB): ...these.
502
5c324c16
RS		 5032013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
504
505 * mips.h: Remove documentation of "[" and "]". Update documentation
506 of "k" and the MDMX formats.
507
23e69e47
RS		 5082013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
509
510 * mips.h: Update documentation of "+s" and "+S".
511
27c5c572
RS		 5122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
513
514 * mips.h: Document "+i".
515
e76ff5ab
RS		 5162013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
517
518 * mips.h: Remove "mi" documentation. Update "mh" documentation.
519 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
520 Delete.
521 (INSN2_WRITE_GPR_MHI): Rename to...
522 (INSN2_WRITE_GPR_MH): ...this.
523
fa7616a4
RS		 5242013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
525
526 * mips.h: Remove documentation of "+D" and "+T".
527
18870af7
RS		 5282013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
529
530 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
531 Use "source" rather than "destination" for microMIPS "G".
532
833794fc
MR		 5332013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
534
535 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
536 values.
537
c3678916
RS		 5382013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
539
540 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
541
7f3c4072
CM		 5422013-06-17 Catherine Moore <clm@codesourcery.com>
543 Maciej W. Rozycki <macro@codesourcery.com>
544 Chao-Ying Fu <fu@mips.com>
545
546 * mips.h (OP_SH_EVAOFFSET): Define.
547 (OP_MASK_EVAOFFSET): Define.
548 (INSN_ASE_MASK): Delete.
549 (ASE_EVA): Define.
550 (M_CACHEE_AB, M_CACHEE_OB): New.
551 (M_LBE_OB, M_LBE_AB): New.
552 (M_LBUE_OB, M_LBUE_AB): New.
553 (M_LHE_OB, M_LHE_AB): New.
554 (M_LHUE_OB, M_LHUE_AB): New.
555 (M_LLE_AB, M_LLE_OB): New.
556 (M_LWE_OB, M_LWE_AB): New.
557 (M_LWLE_AB, M_LWLE_OB): New.
558 (M_LWRE_AB, M_LWRE_OB): New.
559 (M_PREFE_AB, M_PREFE_OB): New.
560 (M_SCE_AB, M_SCE_OB): New.
561 (M_SBE_OB, M_SBE_AB): New.
562 (M_SHE_OB, M_SHE_AB): New.
563 (M_SWE_OB, M_SWE_AB): New.
564 (M_SWLE_AB, M_SWLE_OB): New.
565 (M_SWRE_AB, M_SWRE_OB): New.
566 (MICROMIPSOP_SH_EVAOFFSET): Define.
567 (MICROMIPSOP_MASK_EVAOFFSET): Define.
568
0c8fe7cf
SL		 5692013-06-12 Sandra Loosemore <sandra@codesourcery.com>
570
571 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
572
c77c0862
RS		 5732013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
574
575 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
576
b015e599
AP		 5772013-05-09 Andrew Pinski <apinski@cavium.com>
578
579 * mips.h (OP_MASK_CODE10): Correct definition.
580 (OP_SH_CODE10): Likewise.
581 Add a comment that "+J" is used now for OP_*CODE10.
582 (INSN_ASE_MASK): Update.
583 (INSN_VIRT): New macro.
584 (INSN_VIRT64): New macro
585
13761a11
NC		 5862013-05-02 Nick Clifton <nickc@redhat.com>
587
588 * msp430.h: Add patterns for MSP430X instructions.
589
0afd1215
DM		 5902013-04-06 David S. Miller <davem@davemloft.net>
591
592 * sparc.h (F_PREFERRED): Define.
593 (F_PREF_ALIAS): Define.
594
41702d50
NC		 5952013-04-03 Nick Clifton <nickc@redhat.com>
596
597 * v850.h (V850_INVERSE_PCREL): Define.
598
e21e1a51
NC		 5992013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
600
601 PR binutils/15068
602 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
603
51dcdd4d
NC		 6042013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
605
606 PR binutils/15068
607 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
608 Add 16-bit opcodes.
609 * tic6xc-opcode-table.h: Add 16-bit insns.
610 * tic6x.h: Add support for 16-bit insns.
611
81f5558e
NC		 6122013-03-21 Michael Schewe <michael.schewe@gmx.net>
613
614 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
615 and mov.b/w/l Rs,@(d:32,ERd).
616
165546ad
NC		 6172013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
618
619 PR gas/15082
620 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
621 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
622 tic6x_operand_xregpair operand coding type.
623 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
624 opcode field, usu ORXREGD1324 for the src2 operand and remove the
625 TIC6X_FLAG_NO_CROSS.
626
795b8e6b
NC		 6272013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
628
629 PR gas/15095
630 * tic6x.h (enum tic6x_coding_method): Add
631 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
632 separately the msb and lsb of a register pair. This is needed to
633 encode the opcodes in the same way as TI assembler does.
634 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
635 and rsqrdp opcodes to use the new field coding types.
636
dd5181d5
KT		 6372013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
638
639 * arm.h (CRC_EXT_ARMV8): New constant.
640 (ARCH_CRC_ARMV8): New macro.
641
e60bb1dd
YZ		 6422013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
643
644 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
645
36591ba1 6462013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 647 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 648
649 Based on patches from Altera Corporation.
650
651 * nios2.h: New file.
652
e30181a5
YZ		 6532013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
654
655 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
656
0c9573f4
NC		 6572013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
658
659 PR gas/15069
660 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
661
981dc7f1
NC		 6622013-01-24 Nick Clifton <nickc@redhat.com>
663
664 * v850.h: Add e3v5 support.
665
f5555712
YZ		 6662013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
667
668 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
669
5817ffd1
PB		 6702013-01-10 Peter Bergner <bergner@vnet.ibm.com>
671
672 * ppc.h (PPC_OPCODE_POWER8): New define.
673 (PPC_OPCODE_HTM): Likewise.
674
a3c62988
NC		 6752013-01-10 Will Newton <will.newton@imgtec.com>
676
677 * metag.h: New file.
678
73335eae
NC		 6792013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
680
681 * cr16.h (make_instruction): Rename to cr16_make_instruction.
682 (match_opcode): Rename to cr16_match_opcode.
683
e407c74b
NC		 6842013-01-04 Juergen Urban <JuergenUrban@gmx.de>
685
686 * mips.h: Add support for r5900 instructions including lq and sq.
687
bab4becb
NC		 6882013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
689
690 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
691 (make_instruction,match_opcode): Added function prototypes.
692 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
693
776fc418
AM		 6942012-11-23 Alan Modra <amodra@gmail.com>
695
696 * ppc.h (ppc_parse_cpu): Update prototype.
697
f05682d4
DA		 6982012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
699
700 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
701 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
702
cfc72779
AK		 7032012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
704
705 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
706
b3e14eda
L		 7072012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
708
709 * ia64.h (ia64_opnd): Add new operand types.
710
2c63854f
DM		 7112012-08-21 David S. Miller <davem@davemloft.net>
712
713 * sparc.h (F3F4): New macro.
714
a06ea964 7152012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 716 Laurent Desnogues <laurent.desnogues@arm.com>
717 Jim MacArthur <jim.macarthur@arm.com>
718 Marcus Shawcroft <marcus.shawcroft@arm.com>
719 Nigel Stephens <nigel.stephens@arm.com>
720 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
721 Richard Earnshaw <rearnsha@arm.com>
722 Sofiane Naci <sofiane.naci@arm.com>
723 Tejas Belagod <tejas.belagod@arm.com>
724 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 725
726 * aarch64.h: New file.
727
35d0a169 7282012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 729 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 730
731 * mips.h (mips_opcode): Add the exclusions field.
732 (OPCODE_IS_MEMBER): Remove macro.
733 (cpu_is_member): New inline function.
734 (opcode_is_member): Likewise.
735
03f66e8a 7362012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 737 Catherine Moore <clm@codesourcery.com>
738 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 739
740 * mips.h: Document microMIPS DSP ASE usage.
741 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
742 microMIPS DSP ASE support.
743 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
744 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
745 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
746 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
747 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
748 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
749 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
750
9d7b4c23
MR		 7512012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
752
753 * mips.h: Fix a typo in description.
754
76e879f8
NC		 7552012-06-07 Georg-Johann Lay <avr@gjlay.de>
756
757 * avr.h: (AVR_ISA_XCH): New define.
758 (AVR_ISA_XMEGA): Use it.
759 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
760
6927f982
NC		 7612012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
762
763 * m68hc11.h: Add XGate definitions.
764 (struct m68hc11_opcode): Add xg_mask field.
765
b9c361e0
JL		 7662012-05-14 Catherine Moore <clm@codesourcery.com>
767 Maciej W. Rozycki <macro@codesourcery.com>
768 Rhonda Wittels <rhonda@codesourcery.com>
769
6927f982 770 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 771 (PPC_OP_SA): New macro.
772 (PPC_OP_SE_VLE): New macro.
773 (PPC_OP): Use a variable shift amount.
774 (powerpc_operand): Update comments.
775 (PPC_OPSHIFT_INV): New macro.
776 (PPC_OPERAND_CR): Replace with...
777 (PPC_OPERAND_CR_BIT): ...this and
778 (PPC_OPERAND_CR_REG): ...this.
779
780
f6c1a2d5
NC		 7812012-05-03 Sean Keys <skeys@ipdatasys.com>
782
783 * xgate.h: Header file for XGATE assembler.
784
ec668d69
DM		 7852012-04-27 David S. Miller <davem@davemloft.net>
786
6cda1326
DM		 787 * sparc.h: Document new arg code' )' for crypto RS3
788 immediates.
789
ec668d69
DM		 790 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
791 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
792 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
793 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
794 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
795 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
796 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
797 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
798 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
799 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
800 HWCAP_CBCOND, HWCAP_CRC32): New defines.
801
aea77599
AM		 8022012-03-10 Edmar Wienskoski <edmar@freescale.com>
803
804 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
805
1f42f8b3
AM		 8062012-02-27 Alan Modra <amodra@gmail.com>
807
808 * crx.h (cst4_map): Update declaration.
809
6f7be959
WL		 8102012-02-25 Walter Lee <walt@tilera.com>
811
812 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
813 TILEGX_OPC_LD_TLS.
814 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
815 TILEPRO_OPC_LW_TLS_SN.
816
42164a71
L		 8172012-02-08 H.J. Lu <hongjiu.lu@intel.com>
818
819 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
820 (XRELEASE_PREFIX_OPCODE): Likewise.
821
432233b3 8222011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 823 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 824
825 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
826 (INSN_OCTEON2): New macro.
827 (CPU_OCTEON2): New macro.
828 (OPCODE_IS_MEMBER): Add Octeon2.
829
dd6a37e7
AP		 8302011-11-29 Andrew Pinski <apinski@cavium.com>
831
832 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
833 (INSN_OCTEONP): New macro.
834 (CPU_OCTEONP): New macro.
835 (OPCODE_IS_MEMBER): Add Octeon+.
836 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
837
99c513f6
DD		 8382011-11-01 DJ Delorie <dj@redhat.com>
839
840 * rl78.h: New file.
841
26f85d7a
MR		 8422011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
843
844 * mips.h: Fix a typo in description.
845
9e8c70f9
DM		 8462011-09-21 David S. Miller <davem@davemloft.net>
847
848 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
849 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
850 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
851 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
852
dec0624d 8532011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 854 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 855
856 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
857 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
858 (INSN_ASE_MASK): Add the MCU bit.
859 (INSN_MCU): New macro.
860 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
861 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
862
2b0c8b40
MR		 8632011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
864
865 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
866 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
867 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
868 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
869 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
870 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
871 (INSN2_READ_GPR_MMN): Likewise.
872 (INSN2_READ_FPR_D): Change the bit used.
873 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
874 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
875 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
876 (INSN2_COND_BRANCH): Likewise.
877 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
878 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
879 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
880 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
881 (INSN2_MOD_GPR_MN): Likewise.
882
ea783ef3
DM		 8832011-08-05 David S. Miller <davem@davemloft.net>
884
885 * sparc.h: Document new format codes '4', '5', and '('.
886 (OPF_LOW4, RS3): New macros.
887
7c176fa8
MR		 8882011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
889
890 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
891 order of flags documented.
892
2309ddf2
MR		 8932011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
894
895 * mips.h: Clarify the description of microMIPS instruction
896 manipulation macros.
897 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
898
df58fc94 8992011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 900 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 901
902 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
903 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
904 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
905 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
906 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
907 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
908 (OP_MASK_RS3, OP_SH_RS3): Likewise.
909 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
910 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
911 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
912 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
913 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
914 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
915 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
916 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
917 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
918 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
919 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
920 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
921 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
922 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
923 (INSN_WRITE_GPR_S): New macro.
924 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
925 (INSN2_READ_FPR_D): Likewise.
926 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
927 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
928 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
929 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
930 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
931 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
932 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
933 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
934 (CPU_MICROMIPS): New macro.
935 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
936 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
937 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
938 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
939 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
940 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
941 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
942 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
943 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
944 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
945 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
946 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
947 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
948 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
949 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
950 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
951 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
952 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
953 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
954 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
955 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
956 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
957 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
958 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
959 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
960 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
961 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
962 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
963 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
964 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
965 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
966 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
967 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
968 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
969 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
970 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
971 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
972 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
973 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
974 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
975 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
976 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
977 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
978 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
979 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
980 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
981 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
982 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
983 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
984 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
985 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
986 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
987 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
988 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
989 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
990 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
991 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
992 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
993 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
994 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
995 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
996 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
997 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
998 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
999 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1000 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1001 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1002 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1003 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1004 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1005 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1006 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1007 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1008 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1009 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1010 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1011 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1012 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1013 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1014 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1015 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1016 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1017 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1018 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1019 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1020 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1021 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1022 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1023 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1024 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1025 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1026 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1027 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1028 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1029 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1030 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1031 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1032 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1033 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1034 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1035 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1036 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1037 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1038 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1039 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1040 (micromips_opcodes): New declaration.
1041 (bfd_micromips_num_opcodes): Likewise.
1042
bcd530a7
RS		 10432011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1044
1045 * mips.h (INSN_TRAP): Rename to...
1046 (INSN_NO_DELAY_SLOT): ... this.
1047 (INSN_SYNC): Remove macro.
1048
2dad5a91
EW		 10492011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1050
1051 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1052 a duplicate of AVR_ISA_SPM.
1053
5d73b1f1
NC		 10542011-07-01 Nick Clifton <nickc@redhat.com>
1055
1056 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1057
ef26d60e
MF		 10582011-06-18 Robin Getz <robin.getz@analog.com>
1059
1060 * bfin.h (is_macmod_signed): New func
1061
8fb8dca7
MF		 10622011-06-18 Mike Frysinger <vapier@gentoo.org>
1063
1064 * bfin.h (is_macmod_pmove): Add missing space before func args.
1065 (is_macmod_hmove): Likewise.
1066
aa137e4d
NC		 10672011-06-13 Walter Lee <walt@tilera.com>
1068
1069 * tilegx.h: New file.
1070 * tilepro.h: New file.
1071
3b2f0793
PB		 10722011-05-31 Paul Brook <paul@codesourcery.com>
1073
aa137e4d
NC		 1074 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1075
10762011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1077
1078 * s390.h: Replace S390_OPERAND_REG_EVEN with
1079 S390_OPERAND_REG_PAIR.
1080
10812011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1082
1083 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1084
ac7f631b
NC		 10852011-04-18 Julian Brown <julian@codesourcery.com>
1086
1087 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1088
84701018
NC		 10892011-04-11 Dan McDonald <dan@wellkeeper.com>
1090
1091 PR gas/12296
1092 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1093
8cc66334
EW		 10942011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1095
1096 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1097 New instruction set flags.
1098 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1099
3eebd5eb
MR		 11002011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1101
1102 * mips.h (M_PREF_AB): New enum value.
1103
26bb3ddd
MF		 11042011-02-12 Mike Frysinger <vapier@gentoo.org>
1105
89c0d58c
MR		 1106 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1107 M_IU): Define.
1108 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1109
dd76fcb8
MF		 11102011-02-11 Mike Frysinger <vapier@gentoo.org>
1111
1112 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1113
98d23bef
BS		 11142011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1115
1116 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1117 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1118
3c853d93
DA		 11192010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1120
1121 PR gas/11395
1122 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1123 "bb" entries.
1124
79676006
DA		 11252010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1126
1127 PR gas/11395
1128 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1129
1bec78e9
RS		 11302010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1131
1132 * mips.h: Update commentary after last commit.
1133
98675402
RS		 11342010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1135
1136 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1137 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1138 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1139
aa137e4d
NC		 11402010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1141
1142 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1143
435b94a4
RS		 11442010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1145
1146 * mips.h: Fix previous commit.
1147
d051516a
NC		 11482010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1149
1150 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1151 (INSN_LOONGSON_3A): Clear bit 31.
1152
251665fc
MGD		 11532010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1154
1155 PR gas/12198
1156 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1157 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1158 (ARM_ARCH_V6M_ONLY): New define.
1159
fd503541
NC		 11602010-11-11 Mingming Sun <mingm.sun@gmail.com>
1161
1162 * mips.h (INSN_LOONGSON_3A): Defined.
1163 (CPU_LOONGSON_3A): Defined.
1164 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1165
4469d2be
AM		 11662010-10-09 Matt Rice <ratmice@gmail.com>
1167
1168 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1169 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1170
90ec0d68
MGD		 11712010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1172
1173 * arm.h (ARM_EXT_VIRT): New define.
1174 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1175 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1176 Extensions.
1177
eea54501 11782010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1179
eea54501
MGD		 1180 * arm.h (ARM_AEXT_ADIV): New define.
1181 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1182
b2a5fbdc
MGD		 11832010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1184
1185 * arm.h (ARM_EXT_OS): New define.
1186 (ARM_AEXT_V6SM): Likewise.
1187 (ARM_ARCH_V6SM): Likewise.
1188
60e5ef9f
MGD		 11892010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1190
1191 * arm.h (ARM_EXT_MP): Add.
1192 (ARM_ARCH_V7A_MP): Likewise.
1193
73a63ccf
MF		 11942010-09-22 Mike Frysinger <vapier@gentoo.org>
1195
1196 * bfin.h: Declare pseudoChr structs/defines.
1197
ee99860a
MF		 11982010-09-21 Mike Frysinger <vapier@gentoo.org>
1199
1200 * bfin.h: Strip trailing whitespace.
1201
f9c7014e
DD		 12022010-07-29 DJ Delorie <dj@redhat.com>
1203
1204 * rx.h (RX_Operand_Type): Add TwoReg.
1205 (RX_Opcode_ID): Remove ediv and ediv2.
1206
93378652
DD		 12072010-07-27 DJ Delorie <dj@redhat.com>
1208
1209 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1210
1cd986c5
NC		 12112010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1212 Ina Pandit <ina.pandit@kpitcummins.com>
1213
1214 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1215 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1216 PROCESSOR_V850E2_ALL.
1217 Remove PROCESSOR_V850EA support.
1218 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1219 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1220 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1221 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1222 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1223 V850_OPERAND_PERCENT.
1224 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1225 V850_NOT_R0.
1226 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1227 and V850E_PUSH_POP
1228
9a2c7088
MR		 12292010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1230
1231 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1232 (MIPS16_INSN_BRANCH): Rename to...
1233 (MIPS16_INSN_COND_BRANCH): ... this.
1234
bdc70b4a
AM		 12352010-07-03 Alan Modra <amodra@gmail.com>
1236
1237 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1238 Renumber other PPC_OPCODE defines.
1239
f2bae120
AM		 12402010-07-03 Alan Modra <amodra@gmail.com>
1241
1242 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1243
360cfc9c
AM		 12442010-06-29 Alan Modra <amodra@gmail.com>
1245
1246 * maxq.h: Delete file.
1247
e01d869a
AM		 12482010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1249
1250 * ppc.h (PPC_OPCODE_E500): Define.
1251
f79e2745
CM		 12522010-05-26 Catherine Moore <clm@codesourcery.com>
1253
1254 * opcode/mips.h (INSN_MIPS16): Remove.
1255
2462afa1
JM		 12562010-04-21 Joseph Myers <joseph@codesourcery.com>
1257
1258 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1259
e4e42b45
NC		 12602010-04-15 Nick Clifton <nickc@redhat.com>
1261
1262 * alpha.h: Update copyright notice to use GPLv3.
1263 * arc.h: Likewise.
1264 * arm.h: Likewise.
1265 * avr.h: Likewise.
1266 * bfin.h: Likewise.
1267 * cgen.h: Likewise.
1268 * convex.h: Likewise.
1269 * cr16.h: Likewise.
1270 * cris.h: Likewise.
1271 * crx.h: Likewise.
1272 * d10v.h: Likewise.
1273 * d30v.h: Likewise.
1274 * dlx.h: Likewise.
1275 * h8300.h: Likewise.
1276 * hppa.h: Likewise.
1277 * i370.h: Likewise.
1278 * i386.h: Likewise.
1279 * i860.h: Likewise.
1280 * i960.h: Likewise.
1281 * ia64.h: Likewise.
1282 * m68hc11.h: Likewise.
1283 * m68k.h: Likewise.
1284 * m88k.h: Likewise.
1285 * maxq.h: Likewise.
1286 * mips.h: Likewise.
1287 * mmix.h: Likewise.
1288 * mn10200.h: Likewise.
1289 * mn10300.h: Likewise.
1290 * msp430.h: Likewise.
1291 * np1.h: Likewise.
1292 * ns32k.h: Likewise.
1293 * or32.h: Likewise.
1294 * pdp11.h: Likewise.
1295 * pj.h: Likewise.
1296 * pn.h: Likewise.
1297 * ppc.h: Likewise.
1298 * pyr.h: Likewise.
1299 * rx.h: Likewise.
1300 * s390.h: Likewise.
1301 * score-datadep.h: Likewise.
1302 * score-inst.h: Likewise.
1303 * sparc.h: Likewise.
1304 * spu-insns.h: Likewise.
1305 * spu.h: Likewise.
1306 * tic30.h: Likewise.
1307 * tic4x.h: Likewise.
1308 * tic54x.h: Likewise.
1309 * tic80.h: Likewise.
1310 * v850.h: Likewise.
1311 * vax.h: Likewise.
1312
40b36596
JM		 13132010-03-25 Joseph Myers <joseph@codesourcery.com>
1314
1315 * tic6x-control-registers.h, tic6x-insn-formats.h,
1316 tic6x-opcode-table.h, tic6x.h: New.
1317
c67a084a
NC		 13182010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1319
1320 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1321
466ef64f
AM		 13222010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1323
1324 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1325
1319d143
L		 13262010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1327
1328 * ia64.h (ia64_find_opcode): Remove argument name.
1329 (ia64_find_next_opcode): Likewise.
1330 (ia64_dis_opcode): Likewise.
1331 (ia64_free_opcode): Likewise.
1332 (ia64_find_dependency): Likewise.
1333
1fbb9298
DE		 13342009-11-22 Doug Evans <dje@sebabeach.org>
1335
1336 * cgen.h: Include bfd_stdint.h.
1337 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1338
ada65aa3
PB		 13392009-11-18 Paul Brook <paul@codesourcery.com>
1340
1341 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1342
9e3c6df6
PB		 13432009-11-17 Paul Brook <paul@codesourcery.com>
1344 Daniel Jacobowitz <dan@codesourcery.com>
1345
1346 * arm.h (ARM_EXT_V6_DSP): Define.
1347 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1348 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1349
0d734b5d
DD		 13502009-11-04 DJ Delorie <dj@redhat.com>
1351
1352 * rx.h (rx_decode_opcode) (mvtipl): Add.
1353 (mvtcp, mvfcp, opecp): Remove.
1354
62f3b8c8
PB		 13552009-11-02 Paul Brook <paul@codesourcery.com>
1356
1357 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1358 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1359 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1360 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1361 FPU_ARCH_NEON_VFP_V4): Define.
1362
ac1e9eca
DE		 13632009-10-23 Doug Evans <dje@sebabeach.org>
1364
1365 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1366 * cgen.h: Update. Improve multi-inclusion macro name.
1367
9fe54b1c
PB		 13682009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1369
1370 * ppc.h (PPC_OPCODE_476): Define.
1371
634b50f2
PB		 13722009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1373
1374 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1375
c7927a3c
NC		 13762009-09-29 DJ Delorie <dj@redhat.com>
1377
1378 * rx.h: New file.
1379
b961e85b
AM		 13802009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1381
1382 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1383
e0d602ec
BE		 13842009-09-21 Ben Elliston <bje@au.ibm.com>
1385
1386 * ppc.h (PPC_OPCODE_PPCA2): New.
1387
96d56e9f
NC		 13882009-09-05 Martin Thuresson <martin@mtme.org>
1389
1390 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1391
d3ce72d0
NC		 13922009-08-29 Martin Thuresson <martin@mtme.org>
1393
1394 * tic30.h (template): Rename type template to
1395 insn_template. Updated code to use new name.
1396 * tic54x.h (template): Rename type template to
1397 insn_template.
1398
824b28db
NH		 13992009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1400
1401 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1402
f865a31d
AG		 14032009-06-11 Anthony Green <green@moxielogic.com>
1404
1405 * moxie.h (MOXIE_F3_PCREL): Define.
1406 (moxie_form3_opc_info): Grow.
1407
0e7c7f11
AG		 14082009-06-06 Anthony Green <green@moxielogic.com>
1409
1410 * moxie.h (MOXIE_F1_M): Define.
1411
20135e4c
NC		 14122009-04-15 Anthony Green <green@moxielogic.com>
1413
1414 * moxie.h: Created.
1415
bcb012d3
DD		 14162009-04-06 DJ Delorie <dj@redhat.com>
1417
1418 * h8300.h: Add relaxation attributes to MOVA opcodes.
1419
69fe9ce5
AM		 14202009-03-10 Alan Modra <amodra@bigpond.net.au>
1421
1422 * ppc.h (ppc_parse_cpu): Declare.
1423
c3b7224a
NC		 14242009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1425
1426 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1427 and _IMM11 for mbitclr and mbitset.
1428 * score-datadep.h: Update dependency information.
1429
066be9f7
PB		 14302009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1431
1432 * ppc.h (PPC_OPCODE_POWER7): New.
1433
fedc618e
DE		 14342009-02-06 Doug Evans <dje@google.com>
1435
1436 * i386.h: Add comment regarding sse* insns and prefixes.
1437
52b6b6b9
JM		 14382009-02-03 Sandip Matte <sandip@rmicorp.com>
1439
1440 * mips.h (INSN_XLR): Define.
1441 (INSN_CHIP_MASK): Update.
1442 (CPU_XLR): Define.
1443 (OPCODE_IS_MEMBER): Update.
1444 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1445
35669430
DE		 14462009-01-28 Doug Evans <dje@google.com>
1447
1448 * opcode/i386.h: Add multiple inclusion protection.
1449 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1450 (EDI_REG_NUM): New macros.
1451 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1452 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1453 (REX_PREFIX_P): New macro.
35669430 1454
1cb0a767
PB		 14552009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1456
1457 * ppc.h (struct powerpc_opcode): New field "deprecated".
1458 (PPC_OPCODE_NOPOWER4): Delete.
1459
3aa3176b
TS		 14602008-11-28 Joshua Kinard <kumba@gentoo.org>
1461
1462 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1463 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1464
8e79c3df
CM		 14652008-11-18 Catherine Moore <clm@codesourcery.com>
1466
1467 * arm.h (FPU_NEON_FP16): New.
1468 (FPU_ARCH_NEON_FP16): New.
1469
de9a3e51
CF		 14702008-11-06 Chao-ying Fu <fu@mips.com>
1471
1472 * mips.h: Doucument '1' for 5-bit sync type.
1473
1ca35711
L		 14742008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1475
1476 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1477 IA64_RS_CR.
1478
9b4e5766
PB		 14792008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1480
1481 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1482
081ba1b3
AM		 14832008-07-30 Michael J. Eager <eager@eagercon.com>
1484
1485 * ppc.h (PPC_OPCODE_405): Define.
1486 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1487
fa452fa6
PB		 14882008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1489
1490 * ppc.h (ppc_cpu_t): New typedef.
1491 (struct powerpc_opcode <flags>): Use it.
1492 (struct powerpc_operand <insert, extract>): Likewise.
1493 (struct powerpc_macro <flags>): Likewise.
1494
bb35fb24
NC		 14952008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1496
1497 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1498 Update comment before MIPS16 field descriptors to mention MIPS16.
1499 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1500 BBIT.
1501 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1502 New bit masks and shift counts for cins and exts.
1503
dd3cbb7e
NC		 1504 * mips.h: Document new field descriptors +Q.
1505 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1506
d0799671
AN		 15072008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1508
9aff4b7a 1509 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1510 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1511
19a6653c
AM		 15122008-04-14 Edmar Wienskoski <edmar@freescale.com>
1513
1514 * ppc.h: (PPC_OPCODE_E500MC): New.
1515
c0f3af97
L		 15162008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1517
1518 * i386.h (MAX_OPERANDS): Set to 5.
1519 (MAX_MNEM_SIZE): Changed to 20.
1520
e210c36b
NC		 15212008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1522
1523 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1524
b1cc4aeb
PB		 15252008-03-09 Paul Brook <paul@codesourcery.com>
1526
1527 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1528
7e806470
PB		 15292008-03-04 Paul Brook <paul@codesourcery.com>
1530
1531 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1532 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1533 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1534
7b2185f9 15352008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1536 Nick Clifton <nickc@redhat.com>
1537
1538 PR 3134
1539 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1540 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1541 set.
af7329f0 1542
796d5313
NC		 15432008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1544
1545 * cr16.h (cr16_num_optab): Declared.
1546
d669d37f
NC		 15472008-02-14 Hakan Ardo <hakan@debian.org>
1548
1549 PR gas/2626
1550 * avr.h (AVR_ISA_2xxe): Define.
1551
e6429699
AN		 15522008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1553
1554 * mips.h: Update copyright.
1555 (INSN_CHIP_MASK): New macro.
1556 (INSN_OCTEON): New macro.
1557 (CPU_OCTEON): New macro.
1558 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1559
e210c36b
NC		 15602008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1561
1562 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1563
15642008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1565
1566 * avr.h (AVR_ISA_USB162): Add new opcode set.
1567 (AVR_ISA_AVR3): Likewise.
1568
350cc38d
MS		 15692007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1570
1571 * mips.h (INSN_LOONGSON_2E): New.
1572 (INSN_LOONGSON_2F): New.
1573 (CPU_LOONGSON_2E): New.
1574 (CPU_LOONGSON_2F): New.
1575 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1576
56950294
MS		 15772007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1578
1579 * mips.h (INSN_ISA*): Redefine certain values as an
1580 enumeration. Update comments.
1581 (mips_isa_table): New.
1582 (ISA_MIPS*): Redefine to match enumeration.
1583 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1584 values.
1585
c3d65c1c
BE		 15862007-08-08 Ben Elliston <bje@au.ibm.com>
1587
1588 * ppc.h (PPC_OPCODE_PPCPS): New.
1589
0fdaa005
L		 15902007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1591
1592 * m68k.h: Document j K & E.
1593
15942007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1595
1596 * cr16.h: New file for CR16 target.
1597
3896c469
AM		 15982007-05-02 Alan Modra <amodra@bigpond.net.au>
1599
1600 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1601
9a2e615a
NS		 16022007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1603
1604 * m68k.h (mcfisa_c): New.
1605 (mcfusp, mcf_mask): Adjust.
1606
b84bf58a
AM		 16072007-04-20 Alan Modra <amodra@bigpond.net.au>
1608
1609 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1610 (num_powerpc_operands): Declare.
1611 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1612 (PPC_OPERAND_PLUS1): Define.
1613
831480e9 16142007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1615
1616 * i386.h (REX_MODE64): Renamed to ...
1617 (REX_W): This.
1618 (REX_EXTX): Renamed to ...
1619 (REX_R): This.
1620 (REX_EXTY): Renamed to ...
1621 (REX_X): This.
1622 (REX_EXTZ): Renamed to ...
1623 (REX_B): This.
1624
0b1cf022
L		 16252007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1626
1627 * i386.h: Add entries from config/tc-i386.h and move tables
1628 to opcodes/i386-opc.h.
1629
d796c0ad
L		 16302007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1631
1632 * i386.h (FloatDR): Removed.
1633 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1634
30ac7323
AM		 16352007-03-01 Alan Modra <amodra@bigpond.net.au>
1636
1637 * spu-insns.h: Add soma double-float insns.
1638
8b082fb1 16392007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1640 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1641
1642 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1643 (INSN_DSPR2): Add flag for DSP R2 instructions.
1644 (M_BALIGN): New macro.
1645
4eed87de
AM		 16462007-02-14 Alan Modra <amodra@bigpond.net.au>
1647
1648 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1649 and Seg3ShortFrom with Shortform.
1650
fda592e8
L		 16512007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1652
1653 PR gas/4027
1654 * i386.h (i386_optab): Put the real "test" before the pseudo
1655 one.
1656
3bdcfdf4
KH		 16572007-01-08 Kazu Hirata <kazu@codesourcery.com>
1658
1659 * m68k.h (m68010up): OR fido_a.
1660
9840d27e
KH		 16612006-12-25 Kazu Hirata <kazu@codesourcery.com>
1662
1663 * m68k.h (fido_a): New.
1664
c629cdac
KH		 16652006-12-24 Kazu Hirata <kazu@codesourcery.com>
1666
1667 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1668 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1669 values.
1670
b7d9ef37
L		 16712006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1672
1673 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1674
b138abaa
NC		 16752006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1676
1677 * score-inst.h (enum score_insn_type): Add Insn_internal.
1678
e9f53129
AM		 16792006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1680 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1681 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1682 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1683 Alan Modra <amodra@bigpond.net.au>
1684
1685 * spu-insns.h: New file.
1686 * spu.h: New file.
1687
ede602d7
AM		 16882006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1689
1690 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1691
7918206c
MM		 16922006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1693
e4e42b45 1694 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1695 in amdfam10 architecture.
1696
ef05d495
L		 16972006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1698
1699 * i386.h: Replace CpuMNI with CpuSSSE3.
1700
2d447fca 17012006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1702 Joseph Myers <joseph@codesourcery.com>
1703 Ian Lance Taylor <ian@wasabisystems.com>
1704 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1705
1706 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1707
1c0d3aa6
NC		 17082006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1709
1710 * score-datadep.h: New file.
1711 * score-inst.h: New file.
1712
c2f0420e
L		 17132006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1714
1715 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1716 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1717 movdq2q and movq2dq.
1718
050dfa73
MM		 17192006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1720 Michael Meissner <michael.meissner@amd.com>
1721
1722 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1723
15965411
L		 17242006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1725
1726 * i386.h (i386_optab): Add "nop" with memory reference.
1727
46e883c5
L		 17282006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1729
1730 * i386.h (i386_optab): Update comment for 64bit NOP.
1731
9622b051
AM		 17322006-06-06 Ben Elliston <bje@au.ibm.com>
1733 Anton Blanchard <anton@samba.org>
1734
1735 * ppc.h (PPC_OPCODE_POWER6): Define.
1736 Adjust whitespace.
1737
a9e24354
TS		 17382006-06-05 Thiemo Seufer <ths@mips.com>
1739
e4e42b45 1740 * mips.h: Improve description of MT flags.
a9e24354 1741
a596001e
RS		 17422006-05-25 Richard Sandiford <richard@codesourcery.com>
1743
1744 * m68k.h (mcf_mask): Define.
1745
d43b4baf 17462006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1747 David Ung <davidu@mips.com>
d43b4baf
TS		 1748
1749 * mips.h (enum): Add macro M_CACHE_AB.
1750
39a7806d 17512006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1752 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1753 David Ung <davidu@mips.com>
1754
1755 * mips.h: Add INSN_SMARTMIPS define.
1756
9bcd4f99 17572006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1758 David Ung <davidu@mips.com>
9bcd4f99
TS		 1759
1760 * mips.h: Defines udi bits and masks. Add description of
1761 characters which may appear in the args field of udi
1762 instructions.
1763
ef0ee844
TS		 17642006-04-26 Thiemo Seufer <ths@networkno.de>
1765
1766 * mips.h: Improve comments describing the bitfield instruction
1767 fields.
1768
f7675147
L		 17692006-04-26 Julian Brown <julian@codesourcery.com>
1770
1771 * arm.h (FPU_VFP_EXT_V3): Define constant.
1772 (FPU_NEON_EXT_V1): Likewise.
1773 (FPU_VFP_HARD): Update.
1774 (FPU_VFP_V3): Define macro.
1775 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1776
ef0ee844 17772006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1778
1779 * avr.h (AVR_ISA_PWMx): New.
1780
2da12c60
NS		 17812006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1782
1783 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1784 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1785 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1786 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1787 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1788
0715c387
PB		 17892006-03-10 Paul Brook <paul@codesourcery.com>
1790
1791 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1792
34bdd094
DA		 17932006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1794
1795 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1796 first. Correct mask of bb "B" opcode.
1797
331d2d0d
L		 17982006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1799
1800 * i386.h (i386_optab): Support Intel Merom New Instructions.
1801
62b3e311
PB		 18022006-02-24 Paul Brook <paul@codesourcery.com>
1803
1804 * arm.h: Add V7 feature bits.
1805
59cf82fe
L		 18062006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1807
1808 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1809
e74cfd16
PB		 18102006-01-31 Paul Brook <paul@codesourcery.com>
1811 Richard Earnshaw <rearnsha@arm.com>
1812
1813 * arm.h: Use ARM_CPU_FEATURE.
1814 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1815 (arm_feature_set): Change to a structure.
1816 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1817 ARM_FEATURE): New macros.
1818
5b3f8a92
HPN		 18192005-12-07 Hans-Peter Nilsson <hp@axis.com>
1820
1821 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1822 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1823 (ADD_PC_INCR_OPCODE): Don't define.
1824
cb712a9e
L		 18252005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1826
1827 PR gas/1874
1828 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1829
0499d65b
TS		 18302005-11-14 David Ung <davidu@mips.com>
1831
1832 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1833 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1834 save/restore encoding of the args field.
1835
ea5ca089
DB		 18362005-10-28 Dave Brolley <brolley@redhat.com>
1837
1838 Contribute the following changes:
1839 2005-02-16 Dave Brolley <brolley@redhat.com>
1840
1841 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1842 cgen_isa_mask_* to cgen_bitset_*.
1843 * cgen.h: Likewise.
1844
16175d96
DB		 1845 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1846
1847 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1848 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1849 (CGEN_CPU_TABLE): Make isas a ponter.
1850
1851 2003-09-29 Dave Brolley <brolley@redhat.com>
1852
1853 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1854 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1855 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1856
1857 2002-12-13 Dave Brolley <brolley@redhat.com>
1858
1859 * cgen.h (symcat.h): #include it.
1860 (cgen-bitset.h): #include it.
1861 (CGEN_ATTR_VALUE_TYPE): Now a union.
1862 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1863 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1864 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1865 * cgen-bitset.h: New file.
1866
3c9b82ba
NC		 18672005-09-30 Catherine Moore <clm@cm00re.com>
1868
1869 * bfin.h: New file.
1870
6a2375c6
JB		 18712005-10-24 Jan Beulich <jbeulich@novell.com>
1872
1873 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1874 indirect operands.
1875
c06a12f8
DA		 18762005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1877
1878 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1879 Add FLAG_STRICT to pa10 ftest opcode.
1880
4d443107
DA		 18812005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1882
1883 * hppa.h (pa_opcodes): Remove lha entries.
1884
f0a3b40f
DA		 18852005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1886
1887 * hppa.h (FLAG_STRICT): Revise comment.
1888 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1889 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1890 entries for "fdc".
1891
e210c36b
NC		 18922005-09-30 Catherine Moore <clm@cm00re.com>
1893
1894 * bfin.h: New file.
1895
1b7e1362
DA		 18962005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1897
1898 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1899
089b39de
CF		 19002005-09-06 Chao-ying Fu <fu@mips.com>
1901
1902 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1903 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1904 define.
1905 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1906 (INSN_ASE_MASK): Update to include INSN_MT.
1907 (INSN_MT): New define for MT ASE.
1908
93c34b9b
CF		 19092005-08-25 Chao-ying Fu <fu@mips.com>
1910
1911 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1912 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1913 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1914 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1915 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1916 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1917 instructions.
1918 (INSN_DSP): New define for DSP ASE.
1919
848cf006
AM		 19202005-08-18 Alan Modra <amodra@bigpond.net.au>
1921
1922 * a29k.h: Delete.
1923
36ae0db3
DJ		 19242005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1925
1926 * ppc.h (PPC_OPCODE_E300): Define.
1927
8c929562
MS		 19282005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1929
1930 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1931
f7b8cccc
DA		 19322005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1933
1934 PR gas/336
1935 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1936 and pitlb.
1937
8b5328ac
JB		 19382005-07-27 Jan Beulich <jbeulich@novell.com>
1939
1940 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1941 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1942 Add movq-s as 64-bit variants of movd-s.
1943
f417d200
DA		 19442005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1945
18b3bdfc
DA		 1946 * hppa.h: Fix punctuation in comment.
1947
f417d200
DA		 1948 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1949 implicit space-register addressing. Set space-register bits on opcodes
1950 using implicit space-register addressing. Add various missing pa20
1951 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1952 space-register addressing. Use "fE" instead of "fe" in various
1953 fstw opcodes.
1954
9a145ce6
JB		 19552005-07-18 Jan Beulich <jbeulich@novell.com>
1956
1957 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1958
90700ea2
L		 19592007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1960
1961 * i386.h (i386_optab): Support Intel VMX Instructions.
1962
48f130a8
DA		 19632005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1964
1965 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1966
30123838
JB		 19672005-07-05 Jan Beulich <jbeulich@novell.com>
1968
1969 * i386.h (i386_optab): Add new insns.
1970
47b0e7ad
NC		 19712005-07-01 Nick Clifton <nickc@redhat.com>
1972
1973 * sparc.h: Add typedefs to structure declarations.
1974
b300c311
L		 19752005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1976
1977 PR 1013
1978 * i386.h (i386_optab): Update comments for 64bit addressing on
1979 mov. Allow 64bit addressing for mov and movq.
1980
2db495be
DA		 19812005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1982
1983 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1984 respectively, in various floating-point load and store patterns.
1985
caa05036
DA		 19862005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1987
1988 * hppa.h (FLAG_STRICT): Correct comment.
1989 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1990 PA 2.0 mneumonics when equivalent. Entries with cache control
1991 completers now require PA 1.1. Adjust whitespace.
1992
f4411256
AM		 19932005-05-19 Anton Blanchard <anton@samba.org>
1994
1995 * ppc.h (PPC_OPCODE_POWER5): Define.
1996
e172dbf8
NC		 19972005-05-10 Nick Clifton <nickc@redhat.com>
1998
1999 * Update the address and phone number of the FSF organization in
2000 the GPL notices in the following files:
2001 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2002 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2003 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2004 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2005 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2006 tic54x.h, tic80.h, v850.h, vax.h
2007
e44823cf
JB		 20082005-05-09 Jan Beulich <jbeulich@novell.com>
2009
2010 * i386.h (i386_optab): Add ht and hnt.
2011
791fe849
MK		 20122005-04-18 Mark Kettenis <kettenis@gnu.org>
2013
2014 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2015 Add xcrypt-ctr. Provide aliases without hyphens.
2016
faa7ef87
L		 20172005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2018
a63027e5
L		 2019 Moved from ../ChangeLog
2020
faa7ef87
L		 2021 2005-04-12 Paul Brook <paul@codesourcery.com>
2022 * m88k.h: Rename psr macros to avoid conflicts.
2023
2024 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2025 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2026 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2027 and ARM_ARCH_V6ZKT2.
2028
2029 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2030 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2031 Remove redundant instruction types.
2032 (struct argument): X_op - new field.
2033 (struct cst4_entry): Remove.
2034 (no_op_insn): Declare.
2035
2036 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2037 * crx.h (enum argtype): Rename types, remove unused types.
2038
2039 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2040 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2041 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2042 (enum operand_type): Rearrange operands, edit comments.
2043 replace us<N> with ui<N> for unsigned immediate.
2044 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2045 displacements (respectively).
2046 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2047 (instruction type): Add NO_TYPE_INS.
2048 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2049 (operand_entry): New field - 'flags'.
2050 (operand flags): New.
2051
2052 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2053 * crx.h (operand_type): Remove redundant types i3, i4,
2054 i5, i8, i12.
2055 Add new unsigned immediate types us3, us4, us5, us16.
2056
bc4bd9ab
MK		 20572005-04-12 Mark Kettenis <kettenis@gnu.org>
2058
2059 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2060 adjust them accordingly.
2061
373ff435
JB		 20622005-04-01 Jan Beulich <jbeulich@novell.com>
2063
2064 * i386.h (i386_optab): Add rdtscp.
2065
4cc91dba
L		 20662005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2067
2068 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2069 between memory and segment register. Allow movq for moving between
2070 general-purpose register and segment register.
4cc91dba 2071
9ae09ff9
JB		 20722005-02-09 Jan Beulich <jbeulich@novell.com>
2073
2074 PR gas/707
2075 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2076 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2077 fnstsw.
2078
638e7a64
NS		 20792006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2080
2081 * m68k.h (m68008, m68ec030, m68882): Remove.
2082 (m68k_mask): New.
2083 (cpu_m68k, cpu_cf): New.
2084 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2085 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2086
90219bd0
AO		 20872005-01-25 Alexandre Oliva <aoliva@redhat.com>
2088
2089 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2090 * cgen.h (enum cgen_parse_operand_type): Add
2091 CGEN_PARSE_OPERAND_SYMBOLIC.
2092
239cb185
FF		 20932005-01-21 Fred Fish <fnf@specifixinc.com>
2094
2095 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2096 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2097 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2098
dc9a9f39
FF		 20992005-01-19 Fred Fish <fnf@specifixinc.com>
2100
2101 * mips.h (struct mips_opcode): Add new pinfo2 member.
2102 (INSN_ALIAS): New define for opcode table entries that are
2103 specific instances of another entry, such as 'move' for an 'or'
2104 with a zero operand.
2105 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2106 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2107
98e7aba8
ILT		 21082004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2109
2110 * mips.h (CPU_RM9000): Define.
2111 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2112
37edbb65
JB		 21132004-11-25 Jan Beulich <jbeulich@novell.com>
2114
2115 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2116 to/from test registers are illegal in 64-bit mode. Add missing
2117 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2118 (previously one had to explicitly encode a rex64 prefix). Re-enable
2119 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2120 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2121
21222004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2123
2124 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2125 available only with SSE2. Change the MMX additions introduced by SSE
2126 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2127 instructions by their now designated identifier (since combining i686
2128 and 3DNow! does not really imply 3DNow!A).
2129
f5c7edf4
AM		 21302004-11-19 Alan Modra <amodra@bigpond.net.au>
2131
2132 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2133 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2134
7499d566
NC		 21352004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2136 Vineet Sharma <vineets@noida.hcltech.com>
2137
2138 * maxq.h: New file: Disassembly information for the maxq port.
2139
bcb9eebe
L		 21402004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2141
2142 * i386.h (i386_optab): Put back "movzb".
2143
94bb3d38
HPN		 21442004-11-04 Hans-Peter Nilsson <hp@axis.com>
2145
2146 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2147 comments. Remove member cris_ver_sim. Add members
2148 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2149 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2150 (struct cris_support_reg, struct cris_cond15): New types.
2151 (cris_conds15): Declare.
2152 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2153 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2154 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2155 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2156 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2157 SIZE_FIELD_UNSIGNED.
2158
37edbb65 21592004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2160
2161 * i386.h (sldx_Suf): Remove.
2162 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2163 (q_FP): Define, implying no REX64.
2164 (x_FP, sl_FP): Imply FloatMF.
2165 (i386_optab): Split reg and mem forms of moving from segment registers
2166 so that the memory forms can ignore the 16-/32-bit operand size
2167 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2168 all non-floating-point instructions. Unite 32- and 64-bit forms of
2169 movsx, movzx, and movd. Adjust floating point operations for the above
2170 changes to the *FP macros. Add DefaultSize to floating point control
2171 insns operating on larger memory ranges. Remove left over comments
2172 hinting at certain insns being Intel-syntax ones where the ones
2173 actually meant are already gone.
2174
48c9f030
NC		 21752004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2176
2177 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2178 instruction type.
2179
0dd132b6
NC		 21802004-09-30 Paul Brook <paul@codesourcery.com>
2181
2182 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2183 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2184
23794b24
MM		 21852004-09-11 Theodore A. Roth <troth@openavr.org>
2186
2187 * avr.h: Add support for
2188 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2189
2a309db0
AM		 21902004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2191
2192 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2193
b18c562e
NC		 21942004-08-24 Dmitry Diky <diwil@spec.ru>
2195
2196 * msp430.h (msp430_opc): Add new instructions.
2197 (msp430_rcodes): Declare new instructions.
2198 (msp430_hcodes): Likewise..
2199
45d313cd
NC		 22002004-08-13 Nick Clifton <nickc@redhat.com>
2201
2202 PR/301
2203 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2204 processors.
2205
30d1c836
ML		 22062004-08-30 Michal Ludvig <mludvig@suse.cz>
2207
2208 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2209
9a45f1c2
L		 22102004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2211
2212 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2213
543613e9
NC		 22142004-07-21 Jan Beulich <jbeulich@novell.com>
2215
2216 * i386.h: Adjust instruction descriptions to better match the
2217 specification.
2218
b781e558
RE		 22192004-07-16 Richard Earnshaw <rearnsha@arm.com>
2220
2221 * arm.h: Remove all old content. Replace with architecture defines
2222 from gas/config/tc-arm.c.
2223
8577e690
AS		 22242004-07-09 Andreas Schwab <schwab@suse.de>
2225
2226 * m68k.h: Fix comment.
2227
1fe1f39c
NC		 22282004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2229
2230 * crx.h: New file.
2231
1d9f512f
AM		 22322004-06-24 Alan Modra <amodra@bigpond.net.au>
2233
2234 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2235
be8c092b
NC		 22362004-05-24 Peter Barada <peter@the-baradas.com>
2237
2238 * m68k.h: Add 'size' to m68k_opcode.
2239
6b6e92f4
NC		 22402004-05-05 Peter Barada <peter@the-baradas.com>
2241
2242 * m68k.h: Switch from ColdFire chip name to core variant.
2243
22442004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2245
2246 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2247 descriptions for new EMAC cases.
2248 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2249 handle Motorola MAC syntax.
2250 Allow disassembly of ColdFire V4e object files.
2251
fdd12ef3
AM		 22522004-03-16 Alan Modra <amodra@bigpond.net.au>
2253
2254 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2255
3922a64c
L		 22562004-03-12 Jakub Jelinek <jakub@redhat.com>
2257
2258 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2259
1f45d988
ML		 22602004-03-12 Michal Ludvig <mludvig@suse.cz>
2261
2262 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2263
0f10071e
ML		 22642004-03-12 Michal Ludvig <mludvig@suse.cz>
2265
2266 * i386.h (i386_optab): Added xstore/xcrypt insns.
2267
3255318a
NC		 22682004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2269
2270 * h8300.h (32bit ldc/stc): Add relaxing support.
2271
ca9a79a1 22722004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2273
ca9a79a1
NC		 2274 * h8300.h (BITOP): Pass MEMRELAX flag.
2275
875a0b14
NC		 22762004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2277
2278 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2279 except for the H8S.
252b5132 2280
c9e214e5 2281For older changes see ChangeLog-9103
252b5132 2282\f
b90efa5b 2283Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2284
2285Copying and distribution of this file, with or without modification,
2286are permitted in any medium without royalty provided the copyright
2287notice and this notice are preserved.
2288
252b5132 2289Local Variables:
c9e214e5
AM		 2290mode: change-log
2291left-margin: 8
2292fill-column: 74
252b5132
RH		 2293version-control: never
2294End:
GDB Binutils - Deliverables
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