projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 37edbb65 JB |
1 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
| 2 | ||
| 3 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves | |
| 4 | to/from test registers are illegal in 64-bit mode. Add missing | |
| 5 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix | |
| 6 | (previously one had to explicitly encode a rex64 prefix). Re-enable | |
| 7 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings | |
| 8 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. | |
| 9 | ||
| 10 | 2004-11-23 Jan Beulich <jbeulich@novell.com> | |
| 5c6af06e JB |
11 | |
| 12 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are | |
| 13 | available only with SSE2. Change the MMX additions introduced by SSE | |
| 14 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A | |
| 15 | instructions by their now designated identifier (since combining i686 | |
| 16 | and 3DNow! does not really imply 3DNow!A). | |
| 17 | ||
| f5c7edf4 AM |
18 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
| 19 | ||
| 20 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, | |
| 21 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. | |
| 22 | ||
| 7499d566 NC |
23 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
| 24 | Vineet Sharma <vineets@noida.hcltech.com> | |
| 25 | ||
| 26 | * maxq.h: New file: Disassembly information for the maxq port. | |
| 27 | ||
| bcb9eebe L |
28 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
| 29 | ||
| 30 | * i386.h (i386_optab): Put back "movzb". | |
| 31 | ||
| 94bb3d38 HPN |
32 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
| 33 | ||
| 34 | * cris.h (enum cris_insn_version_usage): Tweak formatting and | |
| 35 | comments. Remove member cris_ver_sim. Add members | |
| 36 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, | |
| 37 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. | |
| 38 | (struct cris_support_reg, struct cris_cond15): New types. | |
| 39 | (cris_conds15): Declare. | |
| 40 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) | |
| 41 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) | |
| 42 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. | |
| 43 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. | |
| 44 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and | |
| 45 | SIZE_FIELD_UNSIGNED. | |
| 46 | ||
| 37edbb65 | 47 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
| 9306ca4a JB |
48 | |
| 49 | * i386.h (sldx_Suf): Remove. | |
| 50 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. | |
| 51 | (q_FP): Define, implying no REX64. | |
| 52 | (x_FP, sl_FP): Imply FloatMF. | |
| 53 | (i386_optab): Split reg and mem forms of moving from segment registers | |
| 54 | so that the memory forms can ignore the 16-/32-bit operand size | |
| 55 | distinction. Adjust a few others for Intel mode. Remove *FP uses from | |
| 56 | all non-floating-point instructions. Unite 32- and 64-bit forms of | |
| 57 | movsx, movzx, and movd. Adjust floating point operations for the above | |
| 58 | changes to the *FP macros. Add DefaultSize to floating point control | |
| 59 | insns operating on larger memory ranges. Remove left over comments | |
| 60 | hinting at certain insns being Intel-syntax ones where the ones | |
| 61 | actually meant are already gone. | |
| 62 | ||
| 48c9f030 NC |
63 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 64 | ||
| 65 | * crx.h: Add COPS_REG_INS - Coprocessor Special register | |
| 66 | instruction type. | |
| 67 | ||
| 0dd132b6 NC |
68 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
| 69 | ||
| 70 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. | |
| 71 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. | |
| 72 | ||
| 23794b24 MM |
73 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
| 74 | ||
| 75 | * avr.h: Add support for | |
| 76 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. | |
| 77 | ||
| 2a309db0 AM |
78 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
| 79 | ||
| 80 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. | |
| 81 | ||
| b18c562e NC |
82 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
| 83 | ||
| 84 | * msp430.h (msp430_opc): Add new instructions. | |
| 85 | (msp430_rcodes): Declare new instructions. | |
| 86 | (msp430_hcodes): Likewise.. | |
| 87 | ||
| 45d313cd NC |
88 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
| 89 | ||
| 90 | PR/301 | |
| 91 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX | |
| 92 | processors. | |
| 93 | ||
| 30d1c836 ML |
94 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
| 95 | ||
| 96 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. | |
| 97 | ||
| 9a45f1c2 L |
98 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
| 99 | ||
| 100 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. | |
| 101 | ||
| 543613e9 NC |
102 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
| 103 | ||
| 104 | * i386.h: Adjust instruction descriptions to better match the | |
| 105 | specification. | |
| 106 | ||
| b781e558 RE |
107 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
| 108 | ||
| 109 | * arm.h: Remove all old content. Replace with architecture defines | |
| 110 | from gas/config/tc-arm.c. | |
| 111 | ||
| 8577e690 AS |
112 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
| 113 | ||
| 114 | * m68k.h: Fix comment. | |
| 115 | ||
| 1fe1f39c NC |
116 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 117 | ||
| 118 | * crx.h: New file. | |
| 119 | ||
| 1d9f512f AM |
120 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
| 121 | ||
| 122 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. | |
| 123 | ||
| be8c092b NC |
124 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
| 125 | ||
| 126 | * m68k.h: Add 'size' to m68k_opcode. | |
| 127 | ||
| 6b6e92f4 NC |
128 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
| 129 | ||
| 130 | * m68k.h: Switch from ColdFire chip name to core variant. | |
| 131 | ||
| 132 | 2004-04-22 Peter Barada <peter@the-baradas.com> | |
| fd99574b NC |
133 | |
| 134 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand | |
| 135 | descriptions for new EMAC cases. | |
| 136 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly | |
| 137 | handle Motorola MAC syntax. | |
| 138 | Allow disassembly of ColdFire V4e object files. | |
| 139 | ||
| fdd12ef3 AM |
140 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
| 141 | ||
| 142 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. | |
| 143 | ||
| 3922a64c L |
144 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
| 145 | ||
| 146 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. | |
| 147 | ||
| 1f45d988 ML |
148 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 149 | ||
| 150 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. | |
| 151 | ||
| 0f10071e ML |
152 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 153 | ||
| 154 | * i386.h (i386_optab): Added xstore/xcrypt insns. | |
| 155 | ||
| 3255318a NC |
156 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 157 | ||
| 158 | * h8300.h (32bit ldc/stc): Add relaxing support. | |
| 159 | ||
| ca9a79a1 | 160 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
| fdd12ef3 | 161 | |
| ca9a79a1 NC |
162 | * h8300.h (BITOP): Pass MEMRELAX flag. |
| 163 | ||
| 875a0b14 NC |
164 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 165 | ||
| 166 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 | |
| 167 | except for the H8S. | |
| 252b5132 | 168 | |
| c9e214e5 | 169 | For older changes see ChangeLog-9103 |
| 252b5132 RH |
170 | \f |
| 171 | Local Variables: | |
| c9e214e5 AM |
172 | mode: change-log |
| 173 | left-margin: 8 | |
| 174 | fill-column: 74 | |
| 252b5132 RH |
175 | version-control: never |
| 176 | End: |