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gold: fix ABI pagesize for aarch64
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
e141d84e
YQ		 12015-10-02 Yao Qi <yao.qi@linaro.org>
2
3 * aarch64.h (aarch64_zero_register_p): Move the declaration
4 to column one.
5
36f4aab1
YQ		 62015-10-02 Yao Qi <yao.qi@linaro.org>
7
8 * aarch64.h (aarch64_decode_insn): Declare it.
9
7ecc513a
DV		 102015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
11
12 * s390.h (S390_INSTR_FLAG_HTM): New flag.
13 (S390_INSTR_FLAG_VX): New flag.
14 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
15
b6518b38
NC		 162015-09-23 Nick Clifton <nickc@redhat.com>
17
18 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
19 shifting.
20
f04265ec
NC		 212015-09-22 Nick Clifton <nickc@redhat.com>
22
23 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
24
7bdf96ef
NC		 252015-09-09 Daniel Santos <daniel.santos@pobox.com>
26
27 * visium.h (gen_reg_table): Make static.
28 (fp_reg_table): Likewise.
29 (cc_table): Likewise.
30
f33026a9
MW		 312015-07-20 Matthew Wahab <matthew.wahab@arm.com>
32
33 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
34 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
35 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
36 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
37
ef5a96d5
AM		 382015-07-03 Alan Modra <amodra@gmail.com>
39
40 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
41
c8c8175b
SL		 422015-07-01 Sandra Loosemore <sandra@codesourcery.com>
43 Cesar Philippidis <cesar@codesourcery.com>
44
45 * nios2.h (enum iw_format_type): Add R2 formats.
46 (enum overflow_type): Add signed_immed12_overflow and
47 enumeration_overflow for R2.
48 (struct nios2_opcode): Document new argument letters for R2.
49 (REG_3BIT, REG_LDWM, REG_POP): Define.
50 (includes): Include nios2r2.h.
51 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
52 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
53 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
54 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
55 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
56 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
57 Declare.
58 * nios2r2.h: New file.
59
11a0cf2e
PB		 602015-06-19 Peter Bergner <bergner@vnet.ibm.com>
61
62 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
63 (ppc_optional_operand_value): New inline function.
64
88f0ea34
MW		 652015-06-04 Matthew Wahab <matthew.wahab@arm.com>
66
67 * aarch64.h (AARCH64_V8_1): New.
68
a5932920
MW		 692015-06-03 Matthew Wahab <matthew.wahab@arm.com>
70
71 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
72 (ARM_ARCH_V8_1A): New.
73 (ARM_ARCH_V8_1A_FP): New.
74 (ARM_ARCH_V8_1A_SIMD): New.
75 (ARM_ARCH_V8_1A_CRYPTOV1): New.
76 (ARM_FEATURE_CORE): New.
77
ddfded2f
MW		 782015-06-02 Matthew Wahab <matthew.wahab@arm.com>
79
80 * arm.h (ARM_EXT2_PAN): New.
81 (ARM_FEATURE_CORE_HIGH): New.
82
1af1dd51
MW		 832015-06-02 Matthew Wahab <matthew.wahab@arm.com>
84
85 * arm.h (ARM_FEATURE_ALL): New.
86
9e1f0fa7
MW		 872015-06-02 Matthew Wahab <matthew.wahab@arm.com>
88
89 * aarch64.h (AARCH64_FEATURE_RDMA): New.
90
290806fd
MW		 912015-06-02 Matthew Wahab <matthew.wahab@arm.com>
92
93 * aarch64.h (AARCH64_FEATURE_LOR): New.
94
f21cce2c
MW		 952015-06-01 Matthew Wahab <matthew.wahab@arm.com>
96
97 * aarch64.h (AARCH64_FEATURE_PAN): New.
98 (aarch64_sys_reg_supported_p): Declare.
99 (aarch64_pstatefield_supported_p): Declare.
100
0952813b
DD		 1012015-04-30 DJ Delorie <dj@redhat.com>
102
103 * rl78.h (RL78_Dis_Isa): New.
104 (rl78_decode_opcode): Add ISA parameter.
105
823d2571
TG		 1062015-03-24 Terry Guo <terry.guo@arm.com>
107
108 * arm.h (arm_feature_set): Extended to provide more available bits.
109 (ARM_ANY): Updated to follow above new definition.
110 (ARM_CPU_HAS_FEATURE): Likewise.
111 (ARM_CPU_IS_ANY): Likewise.
112 (ARM_MERGE_FEATURE_SETS): Likewise.
113 (ARM_CLEAR_FEATURE): Likewise.
114 (ARM_FEATURE): Likewise.
115 (ARM_FEATURE_COPY): New macro.
116 (ARM_FEATURE_EQUAL): Likewise.
117 (ARM_FEATURE_ZERO): Likewise.
118 (ARM_FEATURE_CORE_EQUAL): Likewise.
119 (ARM_FEATURE_LOW): Likewise.
120 (ARM_FEATURE_CORE_LOW): Likewise.
121 (ARM_FEATURE_CORE_COPROC): Likewise.
122
f63c1776
PA		 1232015-02-19 Pedro Alves <palves@redhat.com>
124
125 * cgen.h [__cplusplus]: Wrap in extern "C".
126 * msp430-decode.h [__cplusplus]: Likewise.
127 * nios2.h [__cplusplus]: Likewise.
128 * rl78.h [__cplusplus]: Likewise.
129 * rx.h [__cplusplus]: Likewise.
130 * tilegx.h [__cplusplus]: Likewise.
131
3f8107ab
AM		 1322015-01-28 James Bowman <james.bowman@ftdichip.com>
133
134 * ft32.h: New file.
135
1e2e8c52
AK		 1362015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
137
138 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
139
b90efa5b
AM		 1402015-01-01 Alan Modra <amodra@gmail.com>
141
142 Update year range in copyright notice of all files.
143
bffb6004
AG		 1442014-12-27 Anthony Green <green@moxielogic.com>
145
146 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
147 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
148
1945cfa5
EB		 1492014-12-06 Eric Botcazou <ebotcazou@adacore.com>
150
151 * visium.h: New file.
152
d306ce58
SL		 1532014-11-28 Sandra Loosemore <sandra@codesourcery.com>
154
155 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
156 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
157 (NIOS2_INSN_OPTARG): Renumber.
158
b4714c7c
SL		 1592014-11-06 Sandra Loosemore <sandra@codesourcery.com>
160
161 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
162 declaration. Fix obsolete comment.
163
96ba4233
SL		 1642014-10-23 Sandra Loosemore <sandra@codesourcery.com>
165
166 * nios2.h (enum iw_format_type): New.
167 (struct nios2_opcode): Update comments. Add size and format fields.
168 (NIOS2_INSN_OPTARG): New.
169 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
170 (struct nios2_reg): Add regtype field.
171 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
172 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
173 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
174 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
175 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
176 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
177 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
178 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
179 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
180 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
181 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
182 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
183 (OP_MASK_OP, OP_SH_OP): Delete.
184 (OP_MASK_IOP, OP_SH_IOP): Delete.
185 (OP_MASK_IRD, OP_SH_IRD): Delete.
186 (OP_MASK_IRT, OP_SH_IRT): Delete.
187 (OP_MASK_IRS, OP_SH_IRS): Delete.
188 (OP_MASK_ROP, OP_SH_ROP): Delete.
189 (OP_MASK_RRD, OP_SH_RRD): Delete.
190 (OP_MASK_RRT, OP_SH_RRT): Delete.
191 (OP_MASK_RRS, OP_SH_RRS): Delete.
192 (OP_MASK_JOP, OP_SH_JOP): Delete.
193 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
194 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
195 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
196 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
197 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
198 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
199 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
200 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
201 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
202 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
203 (OP_MASK_<insn>, OP_MASK): Delete.
204 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
205 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
206 Include nios2r1.h to define new instruction opcode constants
207 and accessors.
208 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
209 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
210 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
211 (NUMOPCODES, NUMREGISTERS): Delete.
212 * nios2r1.h: New file.
213
0b6be415
JM		 2142014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
215
216 * sparc.h (HWCAP2_VIS3B): Documentation improved.
217
3d68f91c
JM		 2182014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
219
220 * sparc.h (sparc_opcode): new field `hwcaps2'.
221 (HWCAP2_FJATHPLUS): New define.
222 (HWCAP2_VIS3B): Likewise.
223 (HWCAP2_ADP): Likewise.
224 (HWCAP2_SPARC5): Likewise.
225 (HWCAP2_MWAIT): Likewise.
226 (HWCAP2_XMPMUL): Likewise.
227 (HWCAP2_XMONT): Likewise.
228 (HWCAP2_NSEC): Likewise.
229 (HWCAP2_FJATHHPC): Likewise.
230 (HWCAP2_FJDES): Likewise.
231 (HWCAP2_FJAES): Likewise.
232 Document the new operand kind `{', corresponding to the mcdper
233 ancillary state register.
234 Document the new operand kind }, which represents frsd floating
235 point registers (double precision) which must be the same than
236 frs1 in its containing instruction.
237
40c7a7cb
KLC		 2382014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
239
72f4393d 240 * nds32.h: Add new opcode declaration.
40c7a7cb 241
7361da2c
AB		 2422014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
243 Matthew Fortune <matthew.fortune@imgtec.com>
244
245 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
246 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
247 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
248 +I, +O, +R, +:, +\, +", +;
249 (mips_check_prev_operand): New struct.
250 (INSN2_FORBIDDEN_SLOT): New define.
251 (INSN_ISA32R6): New define.
252 (INSN_ISA64R6): New define.
253 (INSN_UPTO32R6): New define.
254 (INSN_UPTO64R6): New define.
255 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
256 (ISA_MIPS32R6): New define.
257 (ISA_MIPS64R6): New define.
258 (CPU_MIPS32R6): New define.
259 (CPU_MIPS64R6): New define.
260 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
261
ee804238
JW		 2622014-09-03 Jiong Wang <jiong.wang@arm.com>
263
264 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
265 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
266 (aarch64_insn_class): Add lse_atomic.
267 (F_LSE_SZ): New field added.
268 (opcode_has_special_coder): Recognize F_LSE_SZ.
269
5575639b
MR		 2702014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
271
272 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
273 over to `+J'.
274
43885403
MF		 2752014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
276
277 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
278 (INSN_LOAD_COPROC): New define.
279 (INSN_COPROC_MOVE_DELAY): Rename to...
280 (INSN_COPROC_MOVE): New define.
281
f36e8886 2822014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 283 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
284 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
285 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 286
287 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
288 (AVR_ISA_2xxxa): Define ISA without LPM.
289 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
290 Add doc for contraint used in 16 bit lds/sts.
291 Adjust ISA group for icall, ijmp, pop and push.
292 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
293
00b32ff2
NC		 2942014-05-19 Nick Clifton <nickc@redhat.com>
295
296 * msp430.h (struct msp430_operand_s): Add vshift field.
297
ae52f483
AB		 2982014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
299
300 * mips.h (INSN_ISA_MASK): Updated.
301 (INSN_ISA32R3): New define.
302 (INSN_ISA32R5): New define.
303 (INSN_ISA64R3): New define.
304 (INSN_ISA64R5): New define.
305 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
306 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
307 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
308 mips64r5.
309 (INSN_UPTO32R3): New define.
310 (INSN_UPTO32R5): New define.
311 (INSN_UPTO64R3): New define.
312 (INSN_UPTO64R5): New define.
313 (ISA_MIPS32R3): New define.
314 (ISA_MIPS32R5): New define.
315 (ISA_MIPS64R3): New define.
316 (ISA_MIPS64R5): New define.
317 (CPU_MIPS32R3): New define.
318 (CPU_MIPS32R5): New define.
319 (CPU_MIPS64R3): New define.
320 (CPU_MIPS64R5): New define.
321
3efe9ec5
RS		 3222014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
323
324 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
325
73589c9d
CS		 3262014-04-22 Christian Svensson <blue@cmd.nu>
327
328 * or32.h: Delete.
329
4b95cf5c
AM		 3302014-03-05 Alan Modra <amodra@gmail.com>
331
332 Update copyright years.
333
e269fea7
AB		 3342013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
335
336 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
337 microMIPS.
338
35c08157
KLC		 3392013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
340 Wei-Cheng Wang <cole945@gmail.com>
341
342 * nds32.h: New file for Andes NDS32.
343
594d8fa8
MF		 3442013-12-07 Mike Frysinger <vapier@gentoo.org>
345
346 * bfin.h: Remove +x file mode.
347
87b8eed7
YZ		 3482013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
349
350 * aarch64.h (aarch64_pstatefields): Change element type to
351 aarch64_sys_reg.
352
c9fb6e58
YZ		 3532013-11-18 Renlin Li <Renlin.Li@arm.com>
354
355 * arm.h (ARM_AEXT_V7VE): New define.
356 (ARM_ARCH_V7VE): New define.
357 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
358
a203d9b7
YZ		 3592013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
360
361 Revert
362
363 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
364
365 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
366 (aarch64_sys_reg_writeonly_p): Ditto.
367
75468c93
YZ		 3682013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
369
370 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
371 (aarch64_sys_reg_writeonly_p): Ditto.
372
49eec193
YZ		 3732013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
374
375 * aarch64.h (aarch64_sys_reg): New typedef.
376 (aarch64_sys_regs): Change to define with the new type.
377 (aarch64_sys_reg_deprecated_p): Declare.
378
68a64283
YZ		 3792013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
380
381 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
382 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
383
387a82f1
CF		 3842013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
385
386 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
387 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
388 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
389 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
390 For MIPS, update extension character sequences after +.
391 (ASE_MSA): New define.
392 (ASE_MSA64): New define.
393 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
394 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
395 For microMIPS, update extension character sequences after +.
396
9aff4b7a
NC		 3972013-08-23 Yuri Chornoivan <yurchor@ukr.net>
398
399 PR binutils/15834
400 * i960.h: Fix typos.
401
e423441d
RS		 4022013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
403
404 * mips.h: Remove references to "+I" and imm2_expr.
405
5e0dc5ba
RS		 4062013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
407
408 * mips.h (M_DEXT, M_DINS): Delete.
409
0f35dbc4
RS		 4102013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
411
412 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
413 (mips_optional_operand_p): New function.
414
14daeee3
RS		 4152013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
416 Richard Sandiford <rdsandiford@googlemail.com>
417
418 * mips.h: Document new VU0 operand characters.
419 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
420 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
421 (OP_REG_R5900_ACC): New mips_reg_operand_types.
422 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
423 (mips_vu0_channel_mask): Declare.
424
3ccad066
RS		 4252013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
426
427 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
428 (mips_int_operand_min, mips_int_operand_max): New functions.
429 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
430
fc76e730
RS		 4312013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
432
433 * mips.h (mips_decode_reg_operand): New function.
434 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
435 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
436 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
437 New macros.
438 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
439 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
440 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
441 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
442 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
443 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
444 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
445 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
446 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
447 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
448 macros to cover the gaps.
449 (INSN2_MOD_SP): Replace with...
450 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
451 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
452 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
453 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
454 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
455 Delete.
456
26545944
RS		 4572013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
458
459 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
460 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
461 (MIPS16_INSN_COND_BRANCH): Delete.
462
7e8b059b
L		 4632013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
464 Kirill Yukhin <kirill.yukhin@intel.com>
465 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
466
467 * i386.h (BND_PREFIX_OPCODE): New.
468
c3c07478
RS		 4692013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
470
471 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
472 OP_SAVE_RESTORE_LIST.
473 (decode_mips16_operand): Declare.
474
ab902481
RS		 4752013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
476
477 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
478 (mips_operand, mips_int_operand, mips_mapped_int_operand)
479 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
480 (mips_pcrel_operand): New structures.
481 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
482 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
483 (decode_mips_operand, decode_micromips_operand): Declare.
484
cc537e56
RS		 4852013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
486
487 * mips.h: Document MIPS16 "I" opcode.
488
f2ae14a1
RS		 4892013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
490
491 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
492 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
493 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
494 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
495 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
496 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
497 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
498 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
499 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
500 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
501 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
502 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
503 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
504 Rename to...
505 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
506 (M_USD_AB): ...these.
507
5c324c16
RS		 5082013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
509
510 * mips.h: Remove documentation of "[" and "]". Update documentation
511 of "k" and the MDMX formats.
512
23e69e47
RS		 5132013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
514
515 * mips.h: Update documentation of "+s" and "+S".
516
27c5c572
RS		 5172013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
518
519 * mips.h: Document "+i".
520
e76ff5ab
RS		 5212013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
522
523 * mips.h: Remove "mi" documentation. Update "mh" documentation.
524 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
525 Delete.
526 (INSN2_WRITE_GPR_MHI): Rename to...
527 (INSN2_WRITE_GPR_MH): ...this.
528
fa7616a4
RS		 5292013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
530
531 * mips.h: Remove documentation of "+D" and "+T".
532
18870af7
RS		 5332013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
534
535 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
536 Use "source" rather than "destination" for microMIPS "G".
537
833794fc
MR		 5382013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
539
540 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
541 values.
542
c3678916
RS		 5432013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
544
545 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
546
7f3c4072
CM		 5472013-06-17 Catherine Moore <clm@codesourcery.com>
548 Maciej W. Rozycki <macro@codesourcery.com>
549 Chao-Ying Fu <fu@mips.com>
550
551 * mips.h (OP_SH_EVAOFFSET): Define.
552 (OP_MASK_EVAOFFSET): Define.
553 (INSN_ASE_MASK): Delete.
554 (ASE_EVA): Define.
555 (M_CACHEE_AB, M_CACHEE_OB): New.
556 (M_LBE_OB, M_LBE_AB): New.
557 (M_LBUE_OB, M_LBUE_AB): New.
558 (M_LHE_OB, M_LHE_AB): New.
559 (M_LHUE_OB, M_LHUE_AB): New.
560 (M_LLE_AB, M_LLE_OB): New.
561 (M_LWE_OB, M_LWE_AB): New.
562 (M_LWLE_AB, M_LWLE_OB): New.
563 (M_LWRE_AB, M_LWRE_OB): New.
564 (M_PREFE_AB, M_PREFE_OB): New.
565 (M_SCE_AB, M_SCE_OB): New.
566 (M_SBE_OB, M_SBE_AB): New.
567 (M_SHE_OB, M_SHE_AB): New.
568 (M_SWE_OB, M_SWE_AB): New.
569 (M_SWLE_AB, M_SWLE_OB): New.
570 (M_SWRE_AB, M_SWRE_OB): New.
571 (MICROMIPSOP_SH_EVAOFFSET): Define.
572 (MICROMIPSOP_MASK_EVAOFFSET): Define.
573
0c8fe7cf
SL		 5742013-06-12 Sandra Loosemore <sandra@codesourcery.com>
575
576 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
577
c77c0862
RS		 5782013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
579
580 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
581
b015e599
AP		 5822013-05-09 Andrew Pinski <apinski@cavium.com>
583
584 * mips.h (OP_MASK_CODE10): Correct definition.
585 (OP_SH_CODE10): Likewise.
586 Add a comment that "+J" is used now for OP_*CODE10.
587 (INSN_ASE_MASK): Update.
588 (INSN_VIRT): New macro.
589 (INSN_VIRT64): New macro
590
13761a11
NC		 5912013-05-02 Nick Clifton <nickc@redhat.com>
592
593 * msp430.h: Add patterns for MSP430X instructions.
594
0afd1215
DM		 5952013-04-06 David S. Miller <davem@davemloft.net>
596
597 * sparc.h (F_PREFERRED): Define.
598 (F_PREF_ALIAS): Define.
599
41702d50
NC		 6002013-04-03 Nick Clifton <nickc@redhat.com>
601
602 * v850.h (V850_INVERSE_PCREL): Define.
603
e21e1a51
NC		 6042013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
605
606 PR binutils/15068
607 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
608
51dcdd4d
NC		 6092013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
610
611 PR binutils/15068
612 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
613 Add 16-bit opcodes.
614 * tic6xc-opcode-table.h: Add 16-bit insns.
615 * tic6x.h: Add support for 16-bit insns.
616
81f5558e
NC		 6172013-03-21 Michael Schewe <michael.schewe@gmx.net>
618
619 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
620 and mov.b/w/l Rs,@(d:32,ERd).
621
165546ad
NC		 6222013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
623
624 PR gas/15082
625 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
626 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
627 tic6x_operand_xregpair operand coding type.
628 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
629 opcode field, usu ORXREGD1324 for the src2 operand and remove the
630 TIC6X_FLAG_NO_CROSS.
631
795b8e6b
NC		 6322013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
633
634 PR gas/15095
635 * tic6x.h (enum tic6x_coding_method): Add
636 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
637 separately the msb and lsb of a register pair. This is needed to
638 encode the opcodes in the same way as TI assembler does.
639 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
640 and rsqrdp opcodes to use the new field coding types.
641
dd5181d5
KT		 6422013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
643
644 * arm.h (CRC_EXT_ARMV8): New constant.
645 (ARCH_CRC_ARMV8): New macro.
646
e60bb1dd
YZ		 6472013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
648
649 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
650
36591ba1 6512013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 652 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 653
654 Based on patches from Altera Corporation.
655
656 * nios2.h: New file.
657
e30181a5
YZ		 6582013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
659
660 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
661
0c9573f4
NC		 6622013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
663
664 PR gas/15069
665 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
666
981dc7f1
NC		 6672013-01-24 Nick Clifton <nickc@redhat.com>
668
669 * v850.h: Add e3v5 support.
670
f5555712
YZ		 6712013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
672
673 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
674
5817ffd1
PB		 6752013-01-10 Peter Bergner <bergner@vnet.ibm.com>
676
677 * ppc.h (PPC_OPCODE_POWER8): New define.
678 (PPC_OPCODE_HTM): Likewise.
679
a3c62988
NC		 6802013-01-10 Will Newton <will.newton@imgtec.com>
681
682 * metag.h: New file.
683
73335eae
NC		 6842013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
685
686 * cr16.h (make_instruction): Rename to cr16_make_instruction.
687 (match_opcode): Rename to cr16_match_opcode.
688
e407c74b
NC		 6892013-01-04 Juergen Urban <JuergenUrban@gmx.de>
690
691 * mips.h: Add support for r5900 instructions including lq and sq.
692
bab4becb
NC		 6932013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
694
695 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
696 (make_instruction,match_opcode): Added function prototypes.
697 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
698
776fc418
AM		 6992012-11-23 Alan Modra <amodra@gmail.com>
700
701 * ppc.h (ppc_parse_cpu): Update prototype.
702
f05682d4
DA		 7032012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
704
705 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
706 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
707
cfc72779
AK		 7082012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
709
710 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
711
b3e14eda
L		 7122012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
713
714 * ia64.h (ia64_opnd): Add new operand types.
715
2c63854f
DM		 7162012-08-21 David S. Miller <davem@davemloft.net>
717
718 * sparc.h (F3F4): New macro.
719
a06ea964 7202012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 721 Laurent Desnogues <laurent.desnogues@arm.com>
722 Jim MacArthur <jim.macarthur@arm.com>
723 Marcus Shawcroft <marcus.shawcroft@arm.com>
724 Nigel Stephens <nigel.stephens@arm.com>
725 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
726 Richard Earnshaw <rearnsha@arm.com>
727 Sofiane Naci <sofiane.naci@arm.com>
728 Tejas Belagod <tejas.belagod@arm.com>
729 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 730
731 * aarch64.h: New file.
732
35d0a169 7332012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 734 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 735
736 * mips.h (mips_opcode): Add the exclusions field.
737 (OPCODE_IS_MEMBER): Remove macro.
738 (cpu_is_member): New inline function.
739 (opcode_is_member): Likewise.
740
03f66e8a 7412012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 742 Catherine Moore <clm@codesourcery.com>
743 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 744
745 * mips.h: Document microMIPS DSP ASE usage.
746 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
747 microMIPS DSP ASE support.
748 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
749 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
750 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
751 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
752 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
753 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
754 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
755
9d7b4c23
MR		 7562012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
757
758 * mips.h: Fix a typo in description.
759
76e879f8
NC		 7602012-06-07 Georg-Johann Lay <avr@gjlay.de>
761
762 * avr.h: (AVR_ISA_XCH): New define.
763 (AVR_ISA_XMEGA): Use it.
764 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
765
6927f982
NC		 7662012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
767
768 * m68hc11.h: Add XGate definitions.
769 (struct m68hc11_opcode): Add xg_mask field.
770
b9c361e0
JL		 7712012-05-14 Catherine Moore <clm@codesourcery.com>
772 Maciej W. Rozycki <macro@codesourcery.com>
773 Rhonda Wittels <rhonda@codesourcery.com>
774
6927f982 775 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 776 (PPC_OP_SA): New macro.
777 (PPC_OP_SE_VLE): New macro.
778 (PPC_OP): Use a variable shift amount.
779 (powerpc_operand): Update comments.
780 (PPC_OPSHIFT_INV): New macro.
781 (PPC_OPERAND_CR): Replace with...
782 (PPC_OPERAND_CR_BIT): ...this and
783 (PPC_OPERAND_CR_REG): ...this.
784
785
f6c1a2d5
NC		 7862012-05-03 Sean Keys <skeys@ipdatasys.com>
787
788 * xgate.h: Header file for XGATE assembler.
789
ec668d69
DM		 7902012-04-27 David S. Miller <davem@davemloft.net>
791
6cda1326
DM		 792 * sparc.h: Document new arg code' )' for crypto RS3
793 immediates.
794
ec668d69
DM		 795 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
796 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
797 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
798 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
799 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
800 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
801 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
802 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
803 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
804 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
805 HWCAP_CBCOND, HWCAP_CRC32): New defines.
806
aea77599
AM		 8072012-03-10 Edmar Wienskoski <edmar@freescale.com>
808
809 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
810
1f42f8b3
AM		 8112012-02-27 Alan Modra <amodra@gmail.com>
812
813 * crx.h (cst4_map): Update declaration.
814
6f7be959
WL		 8152012-02-25 Walter Lee <walt@tilera.com>
816
817 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
818 TILEGX_OPC_LD_TLS.
819 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
820 TILEPRO_OPC_LW_TLS_SN.
821
42164a71
L		 8222012-02-08 H.J. Lu <hongjiu.lu@intel.com>
823
824 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
825 (XRELEASE_PREFIX_OPCODE): Likewise.
826
432233b3 8272011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 828 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 829
830 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
831 (INSN_OCTEON2): New macro.
832 (CPU_OCTEON2): New macro.
833 (OPCODE_IS_MEMBER): Add Octeon2.
834
dd6a37e7
AP		 8352011-11-29 Andrew Pinski <apinski@cavium.com>
836
837 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
838 (INSN_OCTEONP): New macro.
839 (CPU_OCTEONP): New macro.
840 (OPCODE_IS_MEMBER): Add Octeon+.
841 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
842
99c513f6
DD		 8432011-11-01 DJ Delorie <dj@redhat.com>
844
845 * rl78.h: New file.
846
26f85d7a
MR		 8472011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
848
849 * mips.h: Fix a typo in description.
850
9e8c70f9
DM		 8512011-09-21 David S. Miller <davem@davemloft.net>
852
853 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
854 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
855 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
856 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
857
dec0624d 8582011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 859 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 860
861 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
862 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
863 (INSN_ASE_MASK): Add the MCU bit.
864 (INSN_MCU): New macro.
865 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
866 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
867
2b0c8b40
MR		 8682011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
869
870 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
871 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
872 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
873 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
874 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
875 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
876 (INSN2_READ_GPR_MMN): Likewise.
877 (INSN2_READ_FPR_D): Change the bit used.
878 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
879 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
880 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
881 (INSN2_COND_BRANCH): Likewise.
882 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
883 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
884 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
885 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
886 (INSN2_MOD_GPR_MN): Likewise.
887
ea783ef3
DM		 8882011-08-05 David S. Miller <davem@davemloft.net>
889
890 * sparc.h: Document new format codes '4', '5', and '('.
891 (OPF_LOW4, RS3): New macros.
892
7c176fa8
MR		 8932011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
894
895 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
896 order of flags documented.
897
2309ddf2
MR		 8982011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
899
900 * mips.h: Clarify the description of microMIPS instruction
901 manipulation macros.
902 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
903
df58fc94 9042011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 905 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 906
907 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
908 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
909 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
910 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
911 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
912 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
913 (OP_MASK_RS3, OP_SH_RS3): Likewise.
914 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
915 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
916 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
917 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
918 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
919 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
920 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
921 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
922 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
923 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
924 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
925 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
926 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
927 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
928 (INSN_WRITE_GPR_S): New macro.
929 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
930 (INSN2_READ_FPR_D): Likewise.
931 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
932 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
933 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
934 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
935 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
936 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
937 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
938 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
939 (CPU_MICROMIPS): New macro.
940 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
941 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
942 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
943 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
944 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
945 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
946 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
947 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
948 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
949 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
950 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
951 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
952 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
953 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
954 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
955 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
956 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
957 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
958 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
959 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
960 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
961 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
962 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
963 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
964 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
965 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
966 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
967 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
968 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
969 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
970 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
971 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
972 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
973 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
974 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
975 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
976 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
977 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
978 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
979 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
980 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
981 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
982 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
983 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
984 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
985 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
986 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
987 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
988 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
989 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
990 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
991 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
992 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
993 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
994 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
995 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
996 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
997 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
998 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
999 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1000 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1001 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1002 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1003 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1004 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1005 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1006 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1007 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1008 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1009 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1010 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1011 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1012 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1013 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1014 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1015 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1016 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1017 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1018 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1019 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1020 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1021 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1022 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1023 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1024 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1025 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1026 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1027 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1028 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1029 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1030 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1031 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1032 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1033 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1034 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1035 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1036 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1037 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1038 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1039 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1040 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1041 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1042 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1043 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1044 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1045 (micromips_opcodes): New declaration.
1046 (bfd_micromips_num_opcodes): Likewise.
1047
bcd530a7
RS		 10482011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1049
1050 * mips.h (INSN_TRAP): Rename to...
1051 (INSN_NO_DELAY_SLOT): ... this.
1052 (INSN_SYNC): Remove macro.
1053
2dad5a91
EW		 10542011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1055
1056 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1057 a duplicate of AVR_ISA_SPM.
1058
5d73b1f1
NC		 10592011-07-01 Nick Clifton <nickc@redhat.com>
1060
1061 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1062
ef26d60e
MF		 10632011-06-18 Robin Getz <robin.getz@analog.com>
1064
1065 * bfin.h (is_macmod_signed): New func
1066
8fb8dca7
MF		 10672011-06-18 Mike Frysinger <vapier@gentoo.org>
1068
1069 * bfin.h (is_macmod_pmove): Add missing space before func args.
1070 (is_macmod_hmove): Likewise.
1071
aa137e4d
NC		 10722011-06-13 Walter Lee <walt@tilera.com>
1073
1074 * tilegx.h: New file.
1075 * tilepro.h: New file.
1076
3b2f0793
PB		 10772011-05-31 Paul Brook <paul@codesourcery.com>
1078
aa137e4d
NC		 1079 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1080
10812011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1082
1083 * s390.h: Replace S390_OPERAND_REG_EVEN with
1084 S390_OPERAND_REG_PAIR.
1085
10862011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1087
1088 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1089
ac7f631b
NC		 10902011-04-18 Julian Brown <julian@codesourcery.com>
1091
1092 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1093
84701018
NC		 10942011-04-11 Dan McDonald <dan@wellkeeper.com>
1095
1096 PR gas/12296
1097 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1098
8cc66334
EW		 10992011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1100
1101 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1102 New instruction set flags.
1103 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1104
3eebd5eb
MR		 11052011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1106
1107 * mips.h (M_PREF_AB): New enum value.
1108
26bb3ddd
MF		 11092011-02-12 Mike Frysinger <vapier@gentoo.org>
1110
89c0d58c
MR		 1111 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1112 M_IU): Define.
1113 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1114
dd76fcb8
MF		 11152011-02-11 Mike Frysinger <vapier@gentoo.org>
1116
1117 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1118
98d23bef
BS		 11192011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1120
1121 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1122 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1123
3c853d93
DA		 11242010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1125
1126 PR gas/11395
1127 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1128 "bb" entries.
1129
79676006
DA		 11302010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1131
1132 PR gas/11395
1133 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1134
1bec78e9
RS		 11352010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1136
1137 * mips.h: Update commentary after last commit.
1138
98675402
RS		 11392010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1140
1141 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1142 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1143 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1144
aa137e4d
NC		 11452010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1146
1147 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1148
435b94a4
RS		 11492010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1150
1151 * mips.h: Fix previous commit.
1152
d051516a
NC		 11532010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1154
1155 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1156 (INSN_LOONGSON_3A): Clear bit 31.
1157
251665fc
MGD		 11582010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1159
1160 PR gas/12198
1161 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1162 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1163 (ARM_ARCH_V6M_ONLY): New define.
1164
fd503541
NC		 11652010-11-11 Mingming Sun <mingm.sun@gmail.com>
1166
1167 * mips.h (INSN_LOONGSON_3A): Defined.
1168 (CPU_LOONGSON_3A): Defined.
1169 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1170
4469d2be
AM		 11712010-10-09 Matt Rice <ratmice@gmail.com>
1172
1173 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1174 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1175
90ec0d68
MGD		 11762010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1177
1178 * arm.h (ARM_EXT_VIRT): New define.
1179 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1180 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1181 Extensions.
1182
eea54501 11832010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1184
eea54501
MGD		 1185 * arm.h (ARM_AEXT_ADIV): New define.
1186 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1187
b2a5fbdc
MGD		 11882010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1189
1190 * arm.h (ARM_EXT_OS): New define.
1191 (ARM_AEXT_V6SM): Likewise.
1192 (ARM_ARCH_V6SM): Likewise.
1193
60e5ef9f
MGD		 11942010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1195
1196 * arm.h (ARM_EXT_MP): Add.
1197 (ARM_ARCH_V7A_MP): Likewise.
1198
73a63ccf
MF		 11992010-09-22 Mike Frysinger <vapier@gentoo.org>
1200
1201 * bfin.h: Declare pseudoChr structs/defines.
1202
ee99860a
MF		 12032010-09-21 Mike Frysinger <vapier@gentoo.org>
1204
1205 * bfin.h: Strip trailing whitespace.
1206
f9c7014e
DD		 12072010-07-29 DJ Delorie <dj@redhat.com>
1208
1209 * rx.h (RX_Operand_Type): Add TwoReg.
1210 (RX_Opcode_ID): Remove ediv and ediv2.
1211
93378652
DD		 12122010-07-27 DJ Delorie <dj@redhat.com>
1213
1214 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1215
1cd986c5
NC		 12162010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1217 Ina Pandit <ina.pandit@kpitcummins.com>
1218
1219 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1220 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1221 PROCESSOR_V850E2_ALL.
1222 Remove PROCESSOR_V850EA support.
1223 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1224 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1225 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1226 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1227 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1228 V850_OPERAND_PERCENT.
1229 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1230 V850_NOT_R0.
1231 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1232 and V850E_PUSH_POP
1233
9a2c7088
MR		 12342010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1235
1236 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1237 (MIPS16_INSN_BRANCH): Rename to...
1238 (MIPS16_INSN_COND_BRANCH): ... this.
1239
bdc70b4a
AM		 12402010-07-03 Alan Modra <amodra@gmail.com>
1241
1242 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1243 Renumber other PPC_OPCODE defines.
1244
f2bae120
AM		 12452010-07-03 Alan Modra <amodra@gmail.com>
1246
1247 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1248
360cfc9c
AM		 12492010-06-29 Alan Modra <amodra@gmail.com>
1250
1251 * maxq.h: Delete file.
1252
e01d869a
AM		 12532010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1254
1255 * ppc.h (PPC_OPCODE_E500): Define.
1256
f79e2745
CM		 12572010-05-26 Catherine Moore <clm@codesourcery.com>
1258
1259 * opcode/mips.h (INSN_MIPS16): Remove.
1260
2462afa1
JM		 12612010-04-21 Joseph Myers <joseph@codesourcery.com>
1262
1263 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1264
e4e42b45
NC		 12652010-04-15 Nick Clifton <nickc@redhat.com>
1266
1267 * alpha.h: Update copyright notice to use GPLv3.
1268 * arc.h: Likewise.
1269 * arm.h: Likewise.
1270 * avr.h: Likewise.
1271 * bfin.h: Likewise.
1272 * cgen.h: Likewise.
1273 * convex.h: Likewise.
1274 * cr16.h: Likewise.
1275 * cris.h: Likewise.
1276 * crx.h: Likewise.
1277 * d10v.h: Likewise.
1278 * d30v.h: Likewise.
1279 * dlx.h: Likewise.
1280 * h8300.h: Likewise.
1281 * hppa.h: Likewise.
1282 * i370.h: Likewise.
1283 * i386.h: Likewise.
1284 * i860.h: Likewise.
1285 * i960.h: Likewise.
1286 * ia64.h: Likewise.
1287 * m68hc11.h: Likewise.
1288 * m68k.h: Likewise.
1289 * m88k.h: Likewise.
1290 * maxq.h: Likewise.
1291 * mips.h: Likewise.
1292 * mmix.h: Likewise.
1293 * mn10200.h: Likewise.
1294 * mn10300.h: Likewise.
1295 * msp430.h: Likewise.
1296 * np1.h: Likewise.
1297 * ns32k.h: Likewise.
1298 * or32.h: Likewise.
1299 * pdp11.h: Likewise.
1300 * pj.h: Likewise.
1301 * pn.h: Likewise.
1302 * ppc.h: Likewise.
1303 * pyr.h: Likewise.
1304 * rx.h: Likewise.
1305 * s390.h: Likewise.
1306 * score-datadep.h: Likewise.
1307 * score-inst.h: Likewise.
1308 * sparc.h: Likewise.
1309 * spu-insns.h: Likewise.
1310 * spu.h: Likewise.
1311 * tic30.h: Likewise.
1312 * tic4x.h: Likewise.
1313 * tic54x.h: Likewise.
1314 * tic80.h: Likewise.
1315 * v850.h: Likewise.
1316 * vax.h: Likewise.
1317
40b36596
JM		 13182010-03-25 Joseph Myers <joseph@codesourcery.com>
1319
1320 * tic6x-control-registers.h, tic6x-insn-formats.h,
1321 tic6x-opcode-table.h, tic6x.h: New.
1322
c67a084a
NC		 13232010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1324
1325 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1326
466ef64f
AM		 13272010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1328
1329 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1330
1319d143
L		 13312010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1332
1333 * ia64.h (ia64_find_opcode): Remove argument name.
1334 (ia64_find_next_opcode): Likewise.
1335 (ia64_dis_opcode): Likewise.
1336 (ia64_free_opcode): Likewise.
1337 (ia64_find_dependency): Likewise.
1338
1fbb9298
DE		 13392009-11-22 Doug Evans <dje@sebabeach.org>
1340
1341 * cgen.h: Include bfd_stdint.h.
1342 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1343
ada65aa3
PB		 13442009-11-18 Paul Brook <paul@codesourcery.com>
1345
1346 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1347
9e3c6df6
PB		 13482009-11-17 Paul Brook <paul@codesourcery.com>
1349 Daniel Jacobowitz <dan@codesourcery.com>
1350
1351 * arm.h (ARM_EXT_V6_DSP): Define.
1352 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1353 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1354
0d734b5d
DD		 13552009-11-04 DJ Delorie <dj@redhat.com>
1356
1357 * rx.h (rx_decode_opcode) (mvtipl): Add.
1358 (mvtcp, mvfcp, opecp): Remove.
1359
62f3b8c8
PB		 13602009-11-02 Paul Brook <paul@codesourcery.com>
1361
1362 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1363 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1364 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1365 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1366 FPU_ARCH_NEON_VFP_V4): Define.
1367
ac1e9eca
DE		 13682009-10-23 Doug Evans <dje@sebabeach.org>
1369
1370 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1371 * cgen.h: Update. Improve multi-inclusion macro name.
1372
9fe54b1c
PB		 13732009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1374
1375 * ppc.h (PPC_OPCODE_476): Define.
1376
634b50f2
PB		 13772009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1378
1379 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1380
c7927a3c
NC		 13812009-09-29 DJ Delorie <dj@redhat.com>
1382
1383 * rx.h: New file.
1384
b961e85b
AM		 13852009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1386
1387 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1388
e0d602ec
BE		 13892009-09-21 Ben Elliston <bje@au.ibm.com>
1390
1391 * ppc.h (PPC_OPCODE_PPCA2): New.
1392
96d56e9f
NC		 13932009-09-05 Martin Thuresson <martin@mtme.org>
1394
1395 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1396
d3ce72d0
NC		 13972009-08-29 Martin Thuresson <martin@mtme.org>
1398
1399 * tic30.h (template): Rename type template to
1400 insn_template. Updated code to use new name.
1401 * tic54x.h (template): Rename type template to
1402 insn_template.
1403
824b28db
NH		 14042009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1405
1406 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1407
f865a31d
AG		 14082009-06-11 Anthony Green <green@moxielogic.com>
1409
1410 * moxie.h (MOXIE_F3_PCREL): Define.
1411 (moxie_form3_opc_info): Grow.
1412
0e7c7f11
AG		 14132009-06-06 Anthony Green <green@moxielogic.com>
1414
1415 * moxie.h (MOXIE_F1_M): Define.
1416
20135e4c
NC		 14172009-04-15 Anthony Green <green@moxielogic.com>
1418
1419 * moxie.h: Created.
1420
bcb012d3
DD		 14212009-04-06 DJ Delorie <dj@redhat.com>
1422
1423 * h8300.h: Add relaxation attributes to MOVA opcodes.
1424
69fe9ce5
AM		 14252009-03-10 Alan Modra <amodra@bigpond.net.au>
1426
1427 * ppc.h (ppc_parse_cpu): Declare.
1428
c3b7224a
NC		 14292009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1430
1431 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1432 and _IMM11 for mbitclr and mbitset.
1433 * score-datadep.h: Update dependency information.
1434
066be9f7
PB		 14352009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1436
1437 * ppc.h (PPC_OPCODE_POWER7): New.
1438
fedc618e
DE		 14392009-02-06 Doug Evans <dje@google.com>
1440
1441 * i386.h: Add comment regarding sse* insns and prefixes.
1442
52b6b6b9
JM		 14432009-02-03 Sandip Matte <sandip@rmicorp.com>
1444
1445 * mips.h (INSN_XLR): Define.
1446 (INSN_CHIP_MASK): Update.
1447 (CPU_XLR): Define.
1448 (OPCODE_IS_MEMBER): Update.
1449 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1450
35669430
DE		 14512009-01-28 Doug Evans <dje@google.com>
1452
1453 * opcode/i386.h: Add multiple inclusion protection.
1454 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1455 (EDI_REG_NUM): New macros.
1456 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1457 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1458 (REX_PREFIX_P): New macro.
35669430 1459
1cb0a767
PB		 14602009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1461
1462 * ppc.h (struct powerpc_opcode): New field "deprecated".
1463 (PPC_OPCODE_NOPOWER4): Delete.
1464
3aa3176b
TS		 14652008-11-28 Joshua Kinard <kumba@gentoo.org>
1466
1467 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1468 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1469
8e79c3df
CM		 14702008-11-18 Catherine Moore <clm@codesourcery.com>
1471
1472 * arm.h (FPU_NEON_FP16): New.
1473 (FPU_ARCH_NEON_FP16): New.
1474
de9a3e51
CF		 14752008-11-06 Chao-ying Fu <fu@mips.com>
1476
1477 * mips.h: Doucument '1' for 5-bit sync type.
1478
1ca35711
L		 14792008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1480
1481 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1482 IA64_RS_CR.
1483
9b4e5766
PB		 14842008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1485
1486 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1487
081ba1b3
AM		 14882008-07-30 Michael J. Eager <eager@eagercon.com>
1489
1490 * ppc.h (PPC_OPCODE_405): Define.
1491 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1492
fa452fa6
PB		 14932008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1494
1495 * ppc.h (ppc_cpu_t): New typedef.
1496 (struct powerpc_opcode <flags>): Use it.
1497 (struct powerpc_operand <insert, extract>): Likewise.
1498 (struct powerpc_macro <flags>): Likewise.
1499
bb35fb24
NC		 15002008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1501
1502 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1503 Update comment before MIPS16 field descriptors to mention MIPS16.
1504 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1505 BBIT.
1506 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1507 New bit masks and shift counts for cins and exts.
1508
dd3cbb7e
NC		 1509 * mips.h: Document new field descriptors +Q.
1510 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1511
d0799671
AN		 15122008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1513
9aff4b7a 1514 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1515 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1516
19a6653c
AM		 15172008-04-14 Edmar Wienskoski <edmar@freescale.com>
1518
1519 * ppc.h: (PPC_OPCODE_E500MC): New.
1520
c0f3af97
L		 15212008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1522
1523 * i386.h (MAX_OPERANDS): Set to 5.
1524 (MAX_MNEM_SIZE): Changed to 20.
1525
e210c36b
NC		 15262008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1527
1528 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1529
b1cc4aeb
PB		 15302008-03-09 Paul Brook <paul@codesourcery.com>
1531
1532 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1533
7e806470
PB		 15342008-03-04 Paul Brook <paul@codesourcery.com>
1535
1536 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1537 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1538 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1539
7b2185f9 15402008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1541 Nick Clifton <nickc@redhat.com>
1542
1543 PR 3134
1544 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1545 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1546 set.
af7329f0 1547
796d5313
NC		 15482008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1549
1550 * cr16.h (cr16_num_optab): Declared.
1551
d669d37f
NC		 15522008-02-14 Hakan Ardo <hakan@debian.org>
1553
1554 PR gas/2626
1555 * avr.h (AVR_ISA_2xxe): Define.
1556
e6429699
AN		 15572008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1558
1559 * mips.h: Update copyright.
1560 (INSN_CHIP_MASK): New macro.
1561 (INSN_OCTEON): New macro.
1562 (CPU_OCTEON): New macro.
1563 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1564
e210c36b
NC		 15652008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1566
1567 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1568
15692008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1570
1571 * avr.h (AVR_ISA_USB162): Add new opcode set.
1572 (AVR_ISA_AVR3): Likewise.
1573
350cc38d
MS		 15742007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1575
1576 * mips.h (INSN_LOONGSON_2E): New.
1577 (INSN_LOONGSON_2F): New.
1578 (CPU_LOONGSON_2E): New.
1579 (CPU_LOONGSON_2F): New.
1580 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1581
56950294
MS		 15822007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1583
1584 * mips.h (INSN_ISA*): Redefine certain values as an
1585 enumeration. Update comments.
1586 (mips_isa_table): New.
1587 (ISA_MIPS*): Redefine to match enumeration.
1588 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1589 values.
1590
c3d65c1c
BE		 15912007-08-08 Ben Elliston <bje@au.ibm.com>
1592
1593 * ppc.h (PPC_OPCODE_PPCPS): New.
1594
0fdaa005
L		 15952007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1596
1597 * m68k.h: Document j K & E.
1598
15992007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1600
1601 * cr16.h: New file for CR16 target.
1602
3896c469
AM		 16032007-05-02 Alan Modra <amodra@bigpond.net.au>
1604
1605 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1606
9a2e615a
NS		 16072007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1608
1609 * m68k.h (mcfisa_c): New.
1610 (mcfusp, mcf_mask): Adjust.
1611
b84bf58a
AM		 16122007-04-20 Alan Modra <amodra@bigpond.net.au>
1613
1614 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1615 (num_powerpc_operands): Declare.
1616 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1617 (PPC_OPERAND_PLUS1): Define.
1618
831480e9 16192007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1620
1621 * i386.h (REX_MODE64): Renamed to ...
1622 (REX_W): This.
1623 (REX_EXTX): Renamed to ...
1624 (REX_R): This.
1625 (REX_EXTY): Renamed to ...
1626 (REX_X): This.
1627 (REX_EXTZ): Renamed to ...
1628 (REX_B): This.
1629
0b1cf022
L		 16302007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1631
1632 * i386.h: Add entries from config/tc-i386.h and move tables
1633 to opcodes/i386-opc.h.
1634
d796c0ad
L		 16352007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1636
1637 * i386.h (FloatDR): Removed.
1638 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1639
30ac7323
AM		 16402007-03-01 Alan Modra <amodra@bigpond.net.au>
1641
1642 * spu-insns.h: Add soma double-float insns.
1643
8b082fb1 16442007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1645 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1646
1647 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1648 (INSN_DSPR2): Add flag for DSP R2 instructions.
1649 (M_BALIGN): New macro.
1650
4eed87de
AM		 16512007-02-14 Alan Modra <amodra@bigpond.net.au>
1652
1653 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1654 and Seg3ShortFrom with Shortform.
1655
fda592e8
L		 16562007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1657
1658 PR gas/4027
1659 * i386.h (i386_optab): Put the real "test" before the pseudo
1660 one.
1661
3bdcfdf4
KH		 16622007-01-08 Kazu Hirata <kazu@codesourcery.com>
1663
1664 * m68k.h (m68010up): OR fido_a.
1665
9840d27e
KH		 16662006-12-25 Kazu Hirata <kazu@codesourcery.com>
1667
1668 * m68k.h (fido_a): New.
1669
c629cdac
KH		 16702006-12-24 Kazu Hirata <kazu@codesourcery.com>
1671
1672 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1673 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1674 values.
1675
b7d9ef37
L		 16762006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1677
1678 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1679
b138abaa
NC		 16802006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1681
1682 * score-inst.h (enum score_insn_type): Add Insn_internal.
1683
e9f53129
AM		 16842006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1685 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1686 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1687 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1688 Alan Modra <amodra@bigpond.net.au>
1689
1690 * spu-insns.h: New file.
1691 * spu.h: New file.
1692
ede602d7
AM		 16932006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1694
1695 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1696
7918206c
MM		 16972006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1698
e4e42b45 1699 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1700 in amdfam10 architecture.
1701
ef05d495
L		 17022006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1703
1704 * i386.h: Replace CpuMNI with CpuSSSE3.
1705
2d447fca 17062006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1707 Joseph Myers <joseph@codesourcery.com>
1708 Ian Lance Taylor <ian@wasabisystems.com>
1709 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1710
1711 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1712
1c0d3aa6
NC		 17132006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1714
1715 * score-datadep.h: New file.
1716 * score-inst.h: New file.
1717
c2f0420e
L		 17182006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1719
1720 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1721 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1722 movdq2q and movq2dq.
1723
050dfa73
MM		 17242006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1725 Michael Meissner <michael.meissner@amd.com>
1726
1727 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1728
15965411
L		 17292006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1730
1731 * i386.h (i386_optab): Add "nop" with memory reference.
1732
46e883c5
L		 17332006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1734
1735 * i386.h (i386_optab): Update comment for 64bit NOP.
1736
9622b051
AM		 17372006-06-06 Ben Elliston <bje@au.ibm.com>
1738 Anton Blanchard <anton@samba.org>
1739
1740 * ppc.h (PPC_OPCODE_POWER6): Define.
1741 Adjust whitespace.
1742
a9e24354
TS		 17432006-06-05 Thiemo Seufer <ths@mips.com>
1744
e4e42b45 1745 * mips.h: Improve description of MT flags.
a9e24354 1746
a596001e
RS		 17472006-05-25 Richard Sandiford <richard@codesourcery.com>
1748
1749 * m68k.h (mcf_mask): Define.
1750
d43b4baf 17512006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1752 David Ung <davidu@mips.com>
d43b4baf
TS		 1753
1754 * mips.h (enum): Add macro M_CACHE_AB.
1755
39a7806d 17562006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1757 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1758 David Ung <davidu@mips.com>
1759
1760 * mips.h: Add INSN_SMARTMIPS define.
1761
9bcd4f99 17622006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1763 David Ung <davidu@mips.com>
9bcd4f99
TS		 1764
1765 * mips.h: Defines udi bits and masks. Add description of
1766 characters which may appear in the args field of udi
1767 instructions.
1768
ef0ee844
TS		 17692006-04-26 Thiemo Seufer <ths@networkno.de>
1770
1771 * mips.h: Improve comments describing the bitfield instruction
1772 fields.
1773
f7675147
L		 17742006-04-26 Julian Brown <julian@codesourcery.com>
1775
1776 * arm.h (FPU_VFP_EXT_V3): Define constant.
1777 (FPU_NEON_EXT_V1): Likewise.
1778 (FPU_VFP_HARD): Update.
1779 (FPU_VFP_V3): Define macro.
1780 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1781
ef0ee844 17822006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1783
1784 * avr.h (AVR_ISA_PWMx): New.
1785
2da12c60
NS		 17862006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1787
1788 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1789 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1790 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1791 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1792 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1793
0715c387
PB		 17942006-03-10 Paul Brook <paul@codesourcery.com>
1795
1796 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1797
34bdd094
DA		 17982006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1799
1800 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1801 first. Correct mask of bb "B" opcode.
1802
331d2d0d
L		 18032006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1804
1805 * i386.h (i386_optab): Support Intel Merom New Instructions.
1806
62b3e311
PB		 18072006-02-24 Paul Brook <paul@codesourcery.com>
1808
1809 * arm.h: Add V7 feature bits.
1810
59cf82fe
L		 18112006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1812
1813 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1814
e74cfd16
PB		 18152006-01-31 Paul Brook <paul@codesourcery.com>
1816 Richard Earnshaw <rearnsha@arm.com>
1817
1818 * arm.h: Use ARM_CPU_FEATURE.
1819 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1820 (arm_feature_set): Change to a structure.
1821 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1822 ARM_FEATURE): New macros.
1823
5b3f8a92
HPN		 18242005-12-07 Hans-Peter Nilsson <hp@axis.com>
1825
1826 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1827 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1828 (ADD_PC_INCR_OPCODE): Don't define.
1829
cb712a9e
L		 18302005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1831
1832 PR gas/1874
1833 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1834
0499d65b
TS		 18352005-11-14 David Ung <davidu@mips.com>
1836
1837 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1838 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1839 save/restore encoding of the args field.
1840
ea5ca089
DB		 18412005-10-28 Dave Brolley <brolley@redhat.com>
1842
1843 Contribute the following changes:
1844 2005-02-16 Dave Brolley <brolley@redhat.com>
1845
1846 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1847 cgen_isa_mask_* to cgen_bitset_*.
1848 * cgen.h: Likewise.
1849
16175d96
DB		 1850 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1851
1852 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1853 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1854 (CGEN_CPU_TABLE): Make isas a ponter.
1855
1856 2003-09-29 Dave Brolley <brolley@redhat.com>
1857
1858 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1859 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1860 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1861
1862 2002-12-13 Dave Brolley <brolley@redhat.com>
1863
1864 * cgen.h (symcat.h): #include it.
1865 (cgen-bitset.h): #include it.
1866 (CGEN_ATTR_VALUE_TYPE): Now a union.
1867 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1868 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1869 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1870 * cgen-bitset.h: New file.
1871
3c9b82ba
NC		 18722005-09-30 Catherine Moore <clm@cm00re.com>
1873
1874 * bfin.h: New file.
1875
6a2375c6
JB		 18762005-10-24 Jan Beulich <jbeulich@novell.com>
1877
1878 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1879 indirect operands.
1880
c06a12f8
DA		 18812005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1882
1883 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1884 Add FLAG_STRICT to pa10 ftest opcode.
1885
4d443107
DA		 18862005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1887
1888 * hppa.h (pa_opcodes): Remove lha entries.
1889
f0a3b40f
DA		 18902005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1891
1892 * hppa.h (FLAG_STRICT): Revise comment.
1893 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1894 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1895 entries for "fdc".
1896
e210c36b
NC		 18972005-09-30 Catherine Moore <clm@cm00re.com>
1898
1899 * bfin.h: New file.
1900
1b7e1362
DA		 19012005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1902
1903 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1904
089b39de
CF		 19052005-09-06 Chao-ying Fu <fu@mips.com>
1906
1907 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1908 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1909 define.
1910 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1911 (INSN_ASE_MASK): Update to include INSN_MT.
1912 (INSN_MT): New define for MT ASE.
1913
93c34b9b
CF		 19142005-08-25 Chao-ying Fu <fu@mips.com>
1915
1916 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1917 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1918 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1919 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1920 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1921 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1922 instructions.
1923 (INSN_DSP): New define for DSP ASE.
1924
848cf006
AM		 19252005-08-18 Alan Modra <amodra@bigpond.net.au>
1926
1927 * a29k.h: Delete.
1928
36ae0db3
DJ		 19292005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1930
1931 * ppc.h (PPC_OPCODE_E300): Define.
1932
8c929562
MS		 19332005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1934
1935 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1936
f7b8cccc
DA		 19372005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1938
1939 PR gas/336
1940 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1941 and pitlb.
1942
8b5328ac
JB		 19432005-07-27 Jan Beulich <jbeulich@novell.com>
1944
1945 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1946 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1947 Add movq-s as 64-bit variants of movd-s.
1948
f417d200
DA		 19492005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1950
18b3bdfc
DA		 1951 * hppa.h: Fix punctuation in comment.
1952
f417d200
DA		 1953 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1954 implicit space-register addressing. Set space-register bits on opcodes
1955 using implicit space-register addressing. Add various missing pa20
1956 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1957 space-register addressing. Use "fE" instead of "fe" in various
1958 fstw opcodes.
1959
9a145ce6
JB		 19602005-07-18 Jan Beulich <jbeulich@novell.com>
1961
1962 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1963
90700ea2
L		 19642007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1965
1966 * i386.h (i386_optab): Support Intel VMX Instructions.
1967
48f130a8
DA		 19682005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1969
1970 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1971
30123838
JB		 19722005-07-05 Jan Beulich <jbeulich@novell.com>
1973
1974 * i386.h (i386_optab): Add new insns.
1975
47b0e7ad
NC		 19762005-07-01 Nick Clifton <nickc@redhat.com>
1977
1978 * sparc.h: Add typedefs to structure declarations.
1979
b300c311
L		 19802005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1981
1982 PR 1013
1983 * i386.h (i386_optab): Update comments for 64bit addressing on
1984 mov. Allow 64bit addressing for mov and movq.
1985
2db495be
DA		 19862005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1987
1988 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1989 respectively, in various floating-point load and store patterns.
1990
caa05036
DA		 19912005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1992
1993 * hppa.h (FLAG_STRICT): Correct comment.
1994 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1995 PA 2.0 mneumonics when equivalent. Entries with cache control
1996 completers now require PA 1.1. Adjust whitespace.
1997
f4411256
AM		 19982005-05-19 Anton Blanchard <anton@samba.org>
1999
2000 * ppc.h (PPC_OPCODE_POWER5): Define.
2001
e172dbf8
NC		 20022005-05-10 Nick Clifton <nickc@redhat.com>
2003
2004 * Update the address and phone number of the FSF organization in
2005 the GPL notices in the following files:
2006 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2007 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2008 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2009 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2010 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2011 tic54x.h, tic80.h, v850.h, vax.h
2012
e44823cf
JB		 20132005-05-09 Jan Beulich <jbeulich@novell.com>
2014
2015 * i386.h (i386_optab): Add ht and hnt.
2016
791fe849
MK		 20172005-04-18 Mark Kettenis <kettenis@gnu.org>
2018
2019 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2020 Add xcrypt-ctr. Provide aliases without hyphens.
2021
faa7ef87
L		 20222005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2023
a63027e5
L		 2024 Moved from ../ChangeLog
2025
faa7ef87
L		 2026 2005-04-12 Paul Brook <paul@codesourcery.com>
2027 * m88k.h: Rename psr macros to avoid conflicts.
2028
2029 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2030 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2031 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2032 and ARM_ARCH_V6ZKT2.
2033
2034 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2035 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2036 Remove redundant instruction types.
2037 (struct argument): X_op - new field.
2038 (struct cst4_entry): Remove.
2039 (no_op_insn): Declare.
2040
2041 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2042 * crx.h (enum argtype): Rename types, remove unused types.
2043
2044 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2045 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2046 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2047 (enum operand_type): Rearrange operands, edit comments.
2048 replace us<N> with ui<N> for unsigned immediate.
2049 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2050 displacements (respectively).
2051 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2052 (instruction type): Add NO_TYPE_INS.
2053 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2054 (operand_entry): New field - 'flags'.
2055 (operand flags): New.
2056
2057 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2058 * crx.h (operand_type): Remove redundant types i3, i4,
2059 i5, i8, i12.
2060 Add new unsigned immediate types us3, us4, us5, us16.
2061
bc4bd9ab
MK		 20622005-04-12 Mark Kettenis <kettenis@gnu.org>
2063
2064 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2065 adjust them accordingly.
2066
373ff435
JB		 20672005-04-01 Jan Beulich <jbeulich@novell.com>
2068
2069 * i386.h (i386_optab): Add rdtscp.
2070
4cc91dba
L		 20712005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2072
2073 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2074 between memory and segment register. Allow movq for moving between
2075 general-purpose register and segment register.
4cc91dba 2076
9ae09ff9
JB		 20772005-02-09 Jan Beulich <jbeulich@novell.com>
2078
2079 PR gas/707
2080 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2081 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2082 fnstsw.
2083
638e7a64
NS		 20842006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2085
2086 * m68k.h (m68008, m68ec030, m68882): Remove.
2087 (m68k_mask): New.
2088 (cpu_m68k, cpu_cf): New.
2089 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2090 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2091
90219bd0
AO		 20922005-01-25 Alexandre Oliva <aoliva@redhat.com>
2093
2094 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2095 * cgen.h (enum cgen_parse_operand_type): Add
2096 CGEN_PARSE_OPERAND_SYMBOLIC.
2097
239cb185
FF		 20982005-01-21 Fred Fish <fnf@specifixinc.com>
2099
2100 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2101 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2102 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2103
dc9a9f39
FF		 21042005-01-19 Fred Fish <fnf@specifixinc.com>
2105
2106 * mips.h (struct mips_opcode): Add new pinfo2 member.
2107 (INSN_ALIAS): New define for opcode table entries that are
2108 specific instances of another entry, such as 'move' for an 'or'
2109 with a zero operand.
2110 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2111 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2112
98e7aba8
ILT		 21132004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2114
2115 * mips.h (CPU_RM9000): Define.
2116 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2117
37edbb65
JB		 21182004-11-25 Jan Beulich <jbeulich@novell.com>
2119
2120 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2121 to/from test registers are illegal in 64-bit mode. Add missing
2122 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2123 (previously one had to explicitly encode a rex64 prefix). Re-enable
2124 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2125 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2126
21272004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2128
2129 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2130 available only with SSE2. Change the MMX additions introduced by SSE
2131 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2132 instructions by their now designated identifier (since combining i686
2133 and 3DNow! does not really imply 3DNow!A).
2134
f5c7edf4
AM		 21352004-11-19 Alan Modra <amodra@bigpond.net.au>
2136
2137 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2138 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2139
7499d566
NC		 21402004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2141 Vineet Sharma <vineets@noida.hcltech.com>
2142
2143 * maxq.h: New file: Disassembly information for the maxq port.
2144
bcb9eebe
L		 21452004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2146
2147 * i386.h (i386_optab): Put back "movzb".
2148
94bb3d38
HPN		 21492004-11-04 Hans-Peter Nilsson <hp@axis.com>
2150
2151 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2152 comments. Remove member cris_ver_sim. Add members
2153 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2154 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2155 (struct cris_support_reg, struct cris_cond15): New types.
2156 (cris_conds15): Declare.
2157 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2158 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2159 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2160 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2161 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2162 SIZE_FIELD_UNSIGNED.
2163
37edbb65 21642004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2165
2166 * i386.h (sldx_Suf): Remove.
2167 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2168 (q_FP): Define, implying no REX64.
2169 (x_FP, sl_FP): Imply FloatMF.
2170 (i386_optab): Split reg and mem forms of moving from segment registers
2171 so that the memory forms can ignore the 16-/32-bit operand size
2172 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2173 all non-floating-point instructions. Unite 32- and 64-bit forms of
2174 movsx, movzx, and movd. Adjust floating point operations for the above
2175 changes to the *FP macros. Add DefaultSize to floating point control
2176 insns operating on larger memory ranges. Remove left over comments
2177 hinting at certain insns being Intel-syntax ones where the ones
2178 actually meant are already gone.
2179
48c9f030
NC		 21802004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2181
2182 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2183 instruction type.
2184
0dd132b6
NC		 21852004-09-30 Paul Brook <paul@codesourcery.com>
2186
2187 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2188 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2189
23794b24
MM		 21902004-09-11 Theodore A. Roth <troth@openavr.org>
2191
2192 * avr.h: Add support for
2193 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2194
2a309db0
AM		 21952004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2196
2197 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2198
b18c562e
NC		 21992004-08-24 Dmitry Diky <diwil@spec.ru>
2200
2201 * msp430.h (msp430_opc): Add new instructions.
2202 (msp430_rcodes): Declare new instructions.
2203 (msp430_hcodes): Likewise..
2204
45d313cd
NC		 22052004-08-13 Nick Clifton <nickc@redhat.com>
2206
2207 PR/301
2208 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2209 processors.
2210
30d1c836
ML		 22112004-08-30 Michal Ludvig <mludvig@suse.cz>
2212
2213 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2214
9a45f1c2
L		 22152004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2216
2217 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2218
543613e9
NC		 22192004-07-21 Jan Beulich <jbeulich@novell.com>
2220
2221 * i386.h: Adjust instruction descriptions to better match the
2222 specification.
2223
b781e558
RE		 22242004-07-16 Richard Earnshaw <rearnsha@arm.com>
2225
2226 * arm.h: Remove all old content. Replace with architecture defines
2227 from gas/config/tc-arm.c.
2228
8577e690
AS		 22292004-07-09 Andreas Schwab <schwab@suse.de>
2230
2231 * m68k.h: Fix comment.
2232
1fe1f39c
NC		 22332004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2234
2235 * crx.h: New file.
2236
1d9f512f
AM		 22372004-06-24 Alan Modra <amodra@bigpond.net.au>
2238
2239 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2240
be8c092b
NC		 22412004-05-24 Peter Barada <peter@the-baradas.com>
2242
2243 * m68k.h: Add 'size' to m68k_opcode.
2244
6b6e92f4
NC		 22452004-05-05 Peter Barada <peter@the-baradas.com>
2246
2247 * m68k.h: Switch from ColdFire chip name to core variant.
2248
22492004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2250
2251 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2252 descriptions for new EMAC cases.
2253 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2254 handle Motorola MAC syntax.
2255 Allow disassembly of ColdFire V4e object files.
2256
fdd12ef3
AM		 22572004-03-16 Alan Modra <amodra@bigpond.net.au>
2258
2259 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2260
3922a64c
L		 22612004-03-12 Jakub Jelinek <jakub@redhat.com>
2262
2263 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2264
1f45d988
ML		 22652004-03-12 Michal Ludvig <mludvig@suse.cz>
2266
2267 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2268
0f10071e
ML		 22692004-03-12 Michal Ludvig <mludvig@suse.cz>
2270
2271 * i386.h (i386_optab): Added xstore/xcrypt insns.
2272
3255318a
NC		 22732004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2274
2275 * h8300.h (32bit ldc/stc): Add relaxing support.
2276
ca9a79a1 22772004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2278
ca9a79a1
NC		 2279 * h8300.h (BITOP): Pass MEMRELAX flag.
2280
875a0b14
NC		 22812004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2282
2283 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2284 except for the H8S.
252b5132 2285
c9e214e5 2286For older changes see ChangeLog-9103
252b5132 2287\f
b90efa5b 2288Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2289
2290Copying and distribution of this file, with or without modification,
2291are permitted in any medium without royalty provided the copyright
2292notice and this notice are preserved.
2293
252b5132 2294Local Variables:
c9e214e5
AM		 2295mode: change-log
2296left-margin: 8
2297fill-column: 74
252b5132
RH		 2298version-control: never
2299End:
GDB Binutils - Deliverables
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