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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
3ccad066
RS		 12013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
4 (mips_int_operand_min, mips_int_operand_max): New functions.
5 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
6
fc76e730
RS		 72013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
8
9 * mips.h (mips_decode_reg_operand): New function.
10 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
11 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
12 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
13 New macros.
14 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
15 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
16 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
17 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
18 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
19 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
20 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
21 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
22 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
23 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
24 macros to cover the gaps.
25 (INSN2_MOD_SP): Replace with...
26 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
27 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
28 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
29 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
30 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
31 Delete.
32
26545944
RS		 332013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
34
35 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
36 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
37 (MIPS16_INSN_COND_BRANCH): Delete.
38
7e8b059b
L		 392013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
40 Kirill Yukhin <kirill.yukhin@intel.com>
41 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
42
43 * i386.h (BND_PREFIX_OPCODE): New.
44
c3c07478
RS		 452013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
46
47 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
48 OP_SAVE_RESTORE_LIST.
49 (decode_mips16_operand): Declare.
50
ab902481
RS		 512013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
52
53 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
54 (mips_operand, mips_int_operand, mips_mapped_int_operand)
55 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
56 (mips_pcrel_operand): New structures.
57 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
58 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
59 (decode_mips_operand, decode_micromips_operand): Declare.
60
cc537e56
RS		 612013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
62
63 * mips.h: Document MIPS16 "I" opcode.
64
f2ae14a1
RS		 652013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
66
67 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
68 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
69 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
70 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
71 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
72 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
73 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
74 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
75 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
76 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
77 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
78 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
79 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
80 Rename to...
81 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
82 (M_USD_AB): ...these.
83
5c324c16
RS		 842013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
85
86 * mips.h: Remove documentation of "[" and "]". Update documentation
87 of "k" and the MDMX formats.
88
23e69e47
RS		 892013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
90
91 * mips.h: Update documentation of "+s" and "+S".
92
27c5c572
RS		 932013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
94
95 * mips.h: Document "+i".
96
e76ff5ab
RS		 972013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
98
99 * mips.h: Remove "mi" documentation. Update "mh" documentation.
100 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
101 Delete.
102 (INSN2_WRITE_GPR_MHI): Rename to...
103 (INSN2_WRITE_GPR_MH): ...this.
104
fa7616a4
RS		 1052013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
106
107 * mips.h: Remove documentation of "+D" and "+T".
108
18870af7
RS		 1092013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
110
111 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
112 Use "source" rather than "destination" for microMIPS "G".
113
833794fc
MR		 1142013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
115
116 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
117 values.
118
c3678916
RS		 1192013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
120
121 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
122
7f3c4072
CM		 1232013-06-17 Catherine Moore <clm@codesourcery.com>
124 Maciej W. Rozycki <macro@codesourcery.com>
125 Chao-Ying Fu <fu@mips.com>
126
127 * mips.h (OP_SH_EVAOFFSET): Define.
128 (OP_MASK_EVAOFFSET): Define.
129 (INSN_ASE_MASK): Delete.
130 (ASE_EVA): Define.
131 (M_CACHEE_AB, M_CACHEE_OB): New.
132 (M_LBE_OB, M_LBE_AB): New.
133 (M_LBUE_OB, M_LBUE_AB): New.
134 (M_LHE_OB, M_LHE_AB): New.
135 (M_LHUE_OB, M_LHUE_AB): New.
136 (M_LLE_AB, M_LLE_OB): New.
137 (M_LWE_OB, M_LWE_AB): New.
138 (M_LWLE_AB, M_LWLE_OB): New.
139 (M_LWRE_AB, M_LWRE_OB): New.
140 (M_PREFE_AB, M_PREFE_OB): New.
141 (M_SCE_AB, M_SCE_OB): New.
142 (M_SBE_OB, M_SBE_AB): New.
143 (M_SHE_OB, M_SHE_AB): New.
144 (M_SWE_OB, M_SWE_AB): New.
145 (M_SWLE_AB, M_SWLE_OB): New.
146 (M_SWRE_AB, M_SWRE_OB): New.
147 (MICROMIPSOP_SH_EVAOFFSET): Define.
148 (MICROMIPSOP_MASK_EVAOFFSET): Define.
149
0c8fe7cf
SL		 1502013-06-12 Sandra Loosemore <sandra@codesourcery.com>
151
152 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
153
c77c0862
RS		 1542013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
155
156 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
157
b015e599
AP		 1582013-05-09 Andrew Pinski <apinski@cavium.com>
159
160 * mips.h (OP_MASK_CODE10): Correct definition.
161 (OP_SH_CODE10): Likewise.
162 Add a comment that "+J" is used now for OP_*CODE10.
163 (INSN_ASE_MASK): Update.
164 (INSN_VIRT): New macro.
165 (INSN_VIRT64): New macro
166
13761a11
NC		 1672013-05-02 Nick Clifton <nickc@redhat.com>
168
169 * msp430.h: Add patterns for MSP430X instructions.
170
0afd1215
DM		 1712013-04-06 David S. Miller <davem@davemloft.net>
172
173 * sparc.h (F_PREFERRED): Define.
174 (F_PREF_ALIAS): Define.
175
41702d50
NC		 1762013-04-03 Nick Clifton <nickc@redhat.com>
177
178 * v850.h (V850_INVERSE_PCREL): Define.
179
e21e1a51
NC		 1802013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
181
182 PR binutils/15068
183 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
184
51dcdd4d
NC		 1852013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
186
187 PR binutils/15068
188 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
189 Add 16-bit opcodes.
190 * tic6xc-opcode-table.h: Add 16-bit insns.
191 * tic6x.h: Add support for 16-bit insns.
192
81f5558e
NC		 1932013-03-21 Michael Schewe <michael.schewe@gmx.net>
194
195 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
196 and mov.b/w/l Rs,@(d:32,ERd).
197
165546ad
NC		 1982013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
199
200 PR gas/15082
201 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
202 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
203 tic6x_operand_xregpair operand coding type.
204 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
205 opcode field, usu ORXREGD1324 for the src2 operand and remove the
206 TIC6X_FLAG_NO_CROSS.
207
795b8e6b
NC		 2082013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
209
210 PR gas/15095
211 * tic6x.h (enum tic6x_coding_method): Add
212 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
213 separately the msb and lsb of a register pair. This is needed to
214 encode the opcodes in the same way as TI assembler does.
215 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
216 and rsqrdp opcodes to use the new field coding types.
217
dd5181d5
KT		 2182013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
219
220 * arm.h (CRC_EXT_ARMV8): New constant.
221 (ARCH_CRC_ARMV8): New macro.
222
e60bb1dd
YZ		 2232013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
224
225 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
226
36591ba1
SL		 2272013-02-06 Sandra Loosemore <sandra@codesourcery.com>
228 Andrew Jenner <andrew@codesourcery.com>
229
230 Based on patches from Altera Corporation.
231
232 * nios2.h: New file.
233
e30181a5
YZ		 2342013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
235
236 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
237
0c9573f4
NC		 2382013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
239
240 PR gas/15069
241 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
242
981dc7f1
NC		 2432013-01-24 Nick Clifton <nickc@redhat.com>
244
245 * v850.h: Add e3v5 support.
246
f5555712
YZ		 2472013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
248
249 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
250
5817ffd1
PB		 2512013-01-10 Peter Bergner <bergner@vnet.ibm.com>
252
253 * ppc.h (PPC_OPCODE_POWER8): New define.
254 (PPC_OPCODE_HTM): Likewise.
255
a3c62988
NC		 2562013-01-10 Will Newton <will.newton@imgtec.com>
257
258 * metag.h: New file.
259
73335eae
NC		 2602013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
261
262 * cr16.h (make_instruction): Rename to cr16_make_instruction.
263 (match_opcode): Rename to cr16_match_opcode.
264
e407c74b
NC		 2652013-01-04 Juergen Urban <JuergenUrban@gmx.de>
266
267 * mips.h: Add support for r5900 instructions including lq and sq.
268
bab4becb
NC		 2692013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
270
271 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
272 (make_instruction,match_opcode): Added function prototypes.
273 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
274
776fc418
AM		 2752012-11-23 Alan Modra <amodra@gmail.com>
276
277 * ppc.h (ppc_parse_cpu): Update prototype.
278
f05682d4
DA		 2792012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
280
281 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
282 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
283
cfc72779
AK		 2842012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
285
286 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
287
b3e14eda
L		 2882012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
289
290 * ia64.h (ia64_opnd): Add new operand types.
291
2c63854f
DM		 2922012-08-21 David S. Miller <davem@davemloft.net>
293
294 * sparc.h (F3F4): New macro.
295
a06ea964 2962012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 297 Laurent Desnogues <laurent.desnogues@arm.com>
298 Jim MacArthur <jim.macarthur@arm.com>
299 Marcus Shawcroft <marcus.shawcroft@arm.com>
300 Nigel Stephens <nigel.stephens@arm.com>
301 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
302 Richard Earnshaw <rearnsha@arm.com>
303 Sofiane Naci <sofiane.naci@arm.com>
304 Tejas Belagod <tejas.belagod@arm.com>
305 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 306
307 * aarch64.h: New file.
308
35d0a169 3092012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 310 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 311
312 * mips.h (mips_opcode): Add the exclusions field.
313 (OPCODE_IS_MEMBER): Remove macro.
314 (cpu_is_member): New inline function.
315 (opcode_is_member): Likewise.
316
03f66e8a 3172012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 318 Catherine Moore <clm@codesourcery.com>
319 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 320
321 * mips.h: Document microMIPS DSP ASE usage.
322 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
323 microMIPS DSP ASE support.
324 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
325 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
326 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
327 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
328 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
329 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
330 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
331
9d7b4c23
MR		 3322012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
333
334 * mips.h: Fix a typo in description.
335
76e879f8
NC		 3362012-06-07 Georg-Johann Lay <avr@gjlay.de>
337
338 * avr.h: (AVR_ISA_XCH): New define.
339 (AVR_ISA_XMEGA): Use it.
340 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
341
6927f982
NC		 3422012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
343
344 * m68hc11.h: Add XGate definitions.
345 (struct m68hc11_opcode): Add xg_mask field.
346
b9c361e0
JL		 3472012-05-14 Catherine Moore <clm@codesourcery.com>
348 Maciej W. Rozycki <macro@codesourcery.com>
349 Rhonda Wittels <rhonda@codesourcery.com>
350
6927f982 351 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 352 (PPC_OP_SA): New macro.
353 (PPC_OP_SE_VLE): New macro.
354 (PPC_OP): Use a variable shift amount.
355 (powerpc_operand): Update comments.
356 (PPC_OPSHIFT_INV): New macro.
357 (PPC_OPERAND_CR): Replace with...
358 (PPC_OPERAND_CR_BIT): ...this and
359 (PPC_OPERAND_CR_REG): ...this.
360
361
f6c1a2d5
NC		 3622012-05-03 Sean Keys <skeys@ipdatasys.com>
363
364 * xgate.h: Header file for XGATE assembler.
365
ec668d69
DM		 3662012-04-27 David S. Miller <davem@davemloft.net>
367
6cda1326
DM		 368 * sparc.h: Document new arg code' )' for crypto RS3
369 immediates.
370
ec668d69
DM		 371 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
372 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
373 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
374 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
375 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
376 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
377 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
378 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
379 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
380 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
381 HWCAP_CBCOND, HWCAP_CRC32): New defines.
382
aea77599
AM		 3832012-03-10 Edmar Wienskoski <edmar@freescale.com>
384
385 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
386
1f42f8b3
AM		 3872012-02-27 Alan Modra <amodra@gmail.com>
388
389 * crx.h (cst4_map): Update declaration.
390
6f7be959
WL		 3912012-02-25 Walter Lee <walt@tilera.com>
392
393 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
394 TILEGX_OPC_LD_TLS.
395 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
396 TILEPRO_OPC_LW_TLS_SN.
397
42164a71
L		 3982012-02-08 H.J. Lu <hongjiu.lu@intel.com>
399
400 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
401 (XRELEASE_PREFIX_OPCODE): Likewise.
402
432233b3 4032011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 404 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 405
406 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
407 (INSN_OCTEON2): New macro.
408 (CPU_OCTEON2): New macro.
409 (OPCODE_IS_MEMBER): Add Octeon2.
410
dd6a37e7
AP		 4112011-11-29 Andrew Pinski <apinski@cavium.com>
412
413 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
414 (INSN_OCTEONP): New macro.
415 (CPU_OCTEONP): New macro.
416 (OPCODE_IS_MEMBER): Add Octeon+.
417 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
418
99c513f6
DD		 4192011-11-01 DJ Delorie <dj@redhat.com>
420
421 * rl78.h: New file.
422
26f85d7a
MR		 4232011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
424
425 * mips.h: Fix a typo in description.
426
9e8c70f9
DM		 4272011-09-21 David S. Miller <davem@davemloft.net>
428
429 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
430 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
431 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
432 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
433
dec0624d 4342011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 435 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 436
437 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
438 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
439 (INSN_ASE_MASK): Add the MCU bit.
440 (INSN_MCU): New macro.
441 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
442 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
443
2b0c8b40
MR		 4442011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
445
446 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
447 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
448 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
449 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
450 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
451 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
452 (INSN2_READ_GPR_MMN): Likewise.
453 (INSN2_READ_FPR_D): Change the bit used.
454 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
455 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
456 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
457 (INSN2_COND_BRANCH): Likewise.
458 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
459 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
460 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
461 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
462 (INSN2_MOD_GPR_MN): Likewise.
463
ea783ef3
DM		 4642011-08-05 David S. Miller <davem@davemloft.net>
465
466 * sparc.h: Document new format codes '4', '5', and '('.
467 (OPF_LOW4, RS3): New macros.
468
7c176fa8
MR		 4692011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
470
471 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
472 order of flags documented.
473
2309ddf2
MR		 4742011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
475
476 * mips.h: Clarify the description of microMIPS instruction
477 manipulation macros.
478 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
479
df58fc94 4802011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 481 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 482
483 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
484 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
485 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
486 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
487 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
488 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
489 (OP_MASK_RS3, OP_SH_RS3): Likewise.
490 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
491 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
492 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
493 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
494 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
495 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
496 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
497 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
498 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
499 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
500 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
501 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
502 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
503 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
504 (INSN_WRITE_GPR_S): New macro.
505 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
506 (INSN2_READ_FPR_D): Likewise.
507 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
508 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
509 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
510 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
511 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
512 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
513 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
514 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
515 (CPU_MICROMIPS): New macro.
516 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
517 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
518 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
519 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
520 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
521 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
522 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
523 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
524 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
525 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
526 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
527 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
528 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
529 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
530 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
531 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
532 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
533 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
534 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
535 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
536 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
537 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
538 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
539 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
540 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
541 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
542 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
543 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
544 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
545 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
546 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
547 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
548 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
549 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
550 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
551 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
552 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
553 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
554 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
555 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
556 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
557 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
558 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
559 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
560 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
561 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
562 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
563 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
564 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
565 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
566 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
567 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
568 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
569 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
570 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
571 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
572 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
573 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
574 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
575 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
576 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
577 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
578 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
579 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
580 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
581 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
582 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
583 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
584 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
585 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
586 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
587 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
588 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
589 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
590 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
591 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
592 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
593 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
594 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
595 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
596 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
597 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
598 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
599 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
600 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
601 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
602 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
603 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
604 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
605 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
606 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
607 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
608 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
609 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
610 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
611 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
612 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
613 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
614 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
615 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
616 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
617 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
618 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
619 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
620 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
621 (micromips_opcodes): New declaration.
622 (bfd_micromips_num_opcodes): Likewise.
623
bcd530a7
RS		 6242011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
625
626 * mips.h (INSN_TRAP): Rename to...
627 (INSN_NO_DELAY_SLOT): ... this.
628 (INSN_SYNC): Remove macro.
629
2dad5a91
EW		 6302011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
631
632 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
633 a duplicate of AVR_ISA_SPM.
634
5d73b1f1
NC		 6352011-07-01 Nick Clifton <nickc@redhat.com>
636
637 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
638
ef26d60e
MF		 6392011-06-18 Robin Getz <robin.getz@analog.com>
640
641 * bfin.h (is_macmod_signed): New func
642
8fb8dca7
MF		 6432011-06-18 Mike Frysinger <vapier@gentoo.org>
644
645 * bfin.h (is_macmod_pmove): Add missing space before func args.
646 (is_macmod_hmove): Likewise.
647
aa137e4d
NC		 6482011-06-13 Walter Lee <walt@tilera.com>
649
650 * tilegx.h: New file.
651 * tilepro.h: New file.
652
3b2f0793
PB		 6532011-05-31 Paul Brook <paul@codesourcery.com>
654
aa137e4d
NC		 655 * arm.h (ARM_ARCH_V7R_IDIV): Define.
656
6572011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
658
659 * s390.h: Replace S390_OPERAND_REG_EVEN with
660 S390_OPERAND_REG_PAIR.
661
6622011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
663
664 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 665
ac7f631b
NC		 6662011-04-18 Julian Brown <julian@codesourcery.com>
667
668 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
669
84701018
NC		 6702011-04-11 Dan McDonald <dan@wellkeeper.com>
671
672 PR gas/12296
673 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
674
8cc66334
EW		 6752011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
676
677 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
678 New instruction set flags.
679 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
680
3eebd5eb
MR		 6812011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
682
683 * mips.h (M_PREF_AB): New enum value.
684
26bb3ddd
MF		 6852011-02-12 Mike Frysinger <vapier@gentoo.org>
686
89c0d58c
MR		 687 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
688 M_IU): Define.
689 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 690
dd76fcb8
MF		 6912011-02-11 Mike Frysinger <vapier@gentoo.org>
692
693 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
694
98d23bef
BS		 6952011-02-04 Bernd Schmidt <bernds@codesourcery.com>
696
697 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
698 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
699
3c853d93
DA		 7002010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
701
702 PR gas/11395
703 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
704 "bb" entries.
705
79676006
DA		 7062010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
707
708 PR gas/11395
709 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
710
1bec78e9
RS		 7112010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
712
713 * mips.h: Update commentary after last commit.
714
98675402
RS		 7152010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
716
717 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
718 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
719 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
720
aa137e4d
NC		 7212010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
722
723 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
724
435b94a4
RS		 7252010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
726
727 * mips.h: Fix previous commit.
728
d051516a
NC		 7292010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
730
731 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
732 (INSN_LOONGSON_3A): Clear bit 31.
733
251665fc
MGD		 7342010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
735
736 PR gas/12198
737 * arm.h (ARM_AEXT_V6M_ONLY): New define.
738 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
739 (ARM_ARCH_V6M_ONLY): New define.
740
fd503541
NC		 7412010-11-11 Mingming Sun <mingm.sun@gmail.com>
742
743 * mips.h (INSN_LOONGSON_3A): Defined.
744 (CPU_LOONGSON_3A): Defined.
745 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
746
4469d2be
AM		 7472010-10-09 Matt Rice <ratmice@gmail.com>
748
749 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
750 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
751
90ec0d68
MGD		 7522010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
753
754 * arm.h (ARM_EXT_VIRT): New define.
755 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
756 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
757 Extensions.
758
eea54501 7592010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 760
eea54501
MGD		 761 * arm.h (ARM_AEXT_ADIV): New define.
762 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
763
b2a5fbdc
MGD		 7642010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
765
766 * arm.h (ARM_EXT_OS): New define.
767 (ARM_AEXT_V6SM): Likewise.
768 (ARM_ARCH_V6SM): Likewise.
769
60e5ef9f
MGD		 7702010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
771
772 * arm.h (ARM_EXT_MP): Add.
773 (ARM_ARCH_V7A_MP): Likewise.
774
73a63ccf
MF		 7752010-09-22 Mike Frysinger <vapier@gentoo.org>
776
777 * bfin.h: Declare pseudoChr structs/defines.
778
ee99860a
MF		 7792010-09-21 Mike Frysinger <vapier@gentoo.org>
780
781 * bfin.h: Strip trailing whitespace.
782
f9c7014e
DD		 7832010-07-29 DJ Delorie <dj@redhat.com>
784
785 * rx.h (RX_Operand_Type): Add TwoReg.
786 (RX_Opcode_ID): Remove ediv and ediv2.
787
93378652
DD		 7882010-07-27 DJ Delorie <dj@redhat.com>
789
790 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
791
1cd986c5
NC		 7922010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
793 Ina Pandit <ina.pandit@kpitcummins.com>
794
795 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
796 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
797 PROCESSOR_V850E2_ALL.
798 Remove PROCESSOR_V850EA support.
799 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
800 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
801 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
802 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
803 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
804 V850_OPERAND_PERCENT.
805 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
806 V850_NOT_R0.
807 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
808 and V850E_PUSH_POP
809
9a2c7088
MR		 8102010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
811
812 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
813 (MIPS16_INSN_BRANCH): Rename to...
814 (MIPS16_INSN_COND_BRANCH): ... this.
815
bdc70b4a
AM		 8162010-07-03 Alan Modra <amodra@gmail.com>
817
818 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
819 Renumber other PPC_OPCODE defines.
820
f2bae120
AM		 8212010-07-03 Alan Modra <amodra@gmail.com>
822
823 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
824
360cfc9c
AM		 8252010-06-29 Alan Modra <amodra@gmail.com>
826
827 * maxq.h: Delete file.
828
e01d869a
AM		 8292010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
830
831 * ppc.h (PPC_OPCODE_E500): Define.
832
f79e2745
CM		 8332010-05-26 Catherine Moore <clm@codesourcery.com>
834
835 * opcode/mips.h (INSN_MIPS16): Remove.
836
2462afa1
JM		 8372010-04-21 Joseph Myers <joseph@codesourcery.com>
838
839 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
840
e4e42b45
NC		 8412010-04-15 Nick Clifton <nickc@redhat.com>
842
843 * alpha.h: Update copyright notice to use GPLv3.
844 * arc.h: Likewise.
845 * arm.h: Likewise.
846 * avr.h: Likewise.
847 * bfin.h: Likewise.
848 * cgen.h: Likewise.
849 * convex.h: Likewise.
850 * cr16.h: Likewise.
851 * cris.h: Likewise.
852 * crx.h: Likewise.
853 * d10v.h: Likewise.
854 * d30v.h: Likewise.
855 * dlx.h: Likewise.
856 * h8300.h: Likewise.
857 * hppa.h: Likewise.
858 * i370.h: Likewise.
859 * i386.h: Likewise.
860 * i860.h: Likewise.
861 * i960.h: Likewise.
862 * ia64.h: Likewise.
863 * m68hc11.h: Likewise.
864 * m68k.h: Likewise.
865 * m88k.h: Likewise.
866 * maxq.h: Likewise.
867 * mips.h: Likewise.
868 * mmix.h: Likewise.
869 * mn10200.h: Likewise.
870 * mn10300.h: Likewise.
871 * msp430.h: Likewise.
872 * np1.h: Likewise.
873 * ns32k.h: Likewise.
874 * or32.h: Likewise.
875 * pdp11.h: Likewise.
876 * pj.h: Likewise.
877 * pn.h: Likewise.
878 * ppc.h: Likewise.
879 * pyr.h: Likewise.
880 * rx.h: Likewise.
881 * s390.h: Likewise.
882 * score-datadep.h: Likewise.
883 * score-inst.h: Likewise.
884 * sparc.h: Likewise.
885 * spu-insns.h: Likewise.
886 * spu.h: Likewise.
887 * tic30.h: Likewise.
888 * tic4x.h: Likewise.
889 * tic54x.h: Likewise.
890 * tic80.h: Likewise.
891 * v850.h: Likewise.
892 * vax.h: Likewise.
893
40b36596
JM		 8942010-03-25 Joseph Myers <joseph@codesourcery.com>
895
896 * tic6x-control-registers.h, tic6x-insn-formats.h,
897 tic6x-opcode-table.h, tic6x.h: New.
898
c67a084a
NC		 8992010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
900
901 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
902
466ef64f
AM		 9032010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
904
905 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
906
1319d143
L		 9072010-01-14 H.J. Lu <hongjiu.lu@intel.com>
908
909 * ia64.h (ia64_find_opcode): Remove argument name.
910 (ia64_find_next_opcode): Likewise.
911 (ia64_dis_opcode): Likewise.
912 (ia64_free_opcode): Likewise.
913 (ia64_find_dependency): Likewise.
914
1fbb9298
DE		 9152009-11-22 Doug Evans <dje@sebabeach.org>
916
917 * cgen.h: Include bfd_stdint.h.
918 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
919
ada65aa3
PB		 9202009-11-18 Paul Brook <paul@codesourcery.com>
921
922 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
923
9e3c6df6
PB		 9242009-11-17 Paul Brook <paul@codesourcery.com>
925 Daniel Jacobowitz <dan@codesourcery.com>
926
927 * arm.h (ARM_EXT_V6_DSP): Define.
928 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
929 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
930
0d734b5d
DD		 9312009-11-04 DJ Delorie <dj@redhat.com>
932
933 * rx.h (rx_decode_opcode) (mvtipl): Add.
934 (mvtcp, mvfcp, opecp): Remove.
935
62f3b8c8
PB		 9362009-11-02 Paul Brook <paul@codesourcery.com>
937
938 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
939 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
940 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
941 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
942 FPU_ARCH_NEON_VFP_V4): Define.
943
ac1e9eca
DE		 9442009-10-23 Doug Evans <dje@sebabeach.org>
945
946 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
947 * cgen.h: Update. Improve multi-inclusion macro name.
948
9fe54b1c
PB		 9492009-10-02 Peter Bergner <bergner@vnet.ibm.com>
950
951 * ppc.h (PPC_OPCODE_476): Define.
952
634b50f2
PB		 9532009-10-01 Peter Bergner <bergner@vnet.ibm.com>
954
955 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
956
c7927a3c
NC		 9572009-09-29 DJ Delorie <dj@redhat.com>
958
959 * rx.h: New file.
960
b961e85b
AM		 9612009-09-22 Peter Bergner <bergner@vnet.ibm.com>
962
963 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
964
e0d602ec
BE		 9652009-09-21 Ben Elliston <bje@au.ibm.com>
966
967 * ppc.h (PPC_OPCODE_PPCA2): New.
968
96d56e9f
NC		 9692009-09-05 Martin Thuresson <martin@mtme.org>
970
971 * ia64.h (struct ia64_operand): Renamed member class to op_class.
972
d3ce72d0
NC		 9732009-08-29 Martin Thuresson <martin@mtme.org>
974
975 * tic30.h (template): Rename type template to
976 insn_template. Updated code to use new name.
977 * tic54x.h (template): Rename type template to
978 insn_template.
979
824b28db
NH		 9802009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
981
982 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
983
f865a31d
AG		 9842009-06-11 Anthony Green <green@moxielogic.com>
985
986 * moxie.h (MOXIE_F3_PCREL): Define.
987 (moxie_form3_opc_info): Grow.
988
0e7c7f11
AG		 9892009-06-06 Anthony Green <green@moxielogic.com>
990
991 * moxie.h (MOXIE_F1_M): Define.
992
20135e4c
NC		 9932009-04-15 Anthony Green <green@moxielogic.com>
994
995 * moxie.h: Created.
996
bcb012d3
DD		 9972009-04-06 DJ Delorie <dj@redhat.com>
998
999 * h8300.h: Add relaxation attributes to MOVA opcodes.
1000
69fe9ce5
AM		 10012009-03-10 Alan Modra <amodra@bigpond.net.au>
1002
1003 * ppc.h (ppc_parse_cpu): Declare.
1004
c3b7224a
NC		 10052009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1006
1007 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1008 and _IMM11 for mbitclr and mbitset.
1009 * score-datadep.h: Update dependency information.
1010
066be9f7
PB		 10112009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1012
1013 * ppc.h (PPC_OPCODE_POWER7): New.
1014
fedc618e
DE		 10152009-02-06 Doug Evans <dje@google.com>
1016
1017 * i386.h: Add comment regarding sse* insns and prefixes.
1018
52b6b6b9
JM		 10192009-02-03 Sandip Matte <sandip@rmicorp.com>
1020
1021 * mips.h (INSN_XLR): Define.
1022 (INSN_CHIP_MASK): Update.
1023 (CPU_XLR): Define.
1024 (OPCODE_IS_MEMBER): Update.
1025 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1026
35669430
DE		 10272009-01-28 Doug Evans <dje@google.com>
1028
1029 * opcode/i386.h: Add multiple inclusion protection.
1030 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1031 (EDI_REG_NUM): New macros.
1032 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1033 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1034 (REX_PREFIX_P): New macro.
35669430 1035
1cb0a767
PB		 10362009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1037
1038 * ppc.h (struct powerpc_opcode): New field "deprecated".
1039 (PPC_OPCODE_NOPOWER4): Delete.
1040
3aa3176b
TS		 10412008-11-28 Joshua Kinard <kumba@gentoo.org>
1042
1043 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1044 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1045
8e79c3df
CM		 10462008-11-18 Catherine Moore <clm@codesourcery.com>
1047
1048 * arm.h (FPU_NEON_FP16): New.
1049 (FPU_ARCH_NEON_FP16): New.
1050
de9a3e51
CF		 10512008-11-06 Chao-ying Fu <fu@mips.com>
1052
1053 * mips.h: Doucument '1' for 5-bit sync type.
1054
1ca35711
L		 10552008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1056
1057 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1058 IA64_RS_CR.
1059
9b4e5766
PB		 10602008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1061
1062 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1063
081ba1b3
AM		 10642008-07-30 Michael J. Eager <eager@eagercon.com>
1065
1066 * ppc.h (PPC_OPCODE_405): Define.
1067 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1068
fa452fa6
PB		 10692008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1070
1071 * ppc.h (ppc_cpu_t): New typedef.
1072 (struct powerpc_opcode <flags>): Use it.
1073 (struct powerpc_operand <insert, extract>): Likewise.
1074 (struct powerpc_macro <flags>): Likewise.
1075
bb35fb24
NC		 10762008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1077
1078 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1079 Update comment before MIPS16 field descriptors to mention MIPS16.
1080 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1081 BBIT.
1082 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1083 New bit masks and shift counts for cins and exts.
1084
dd3cbb7e
NC		 1085 * mips.h: Document new field descriptors +Q.
1086 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1087
d0799671
AN		 10882008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1089
1090 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1091 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1092
19a6653c
AM		 10932008-04-14 Edmar Wienskoski <edmar@freescale.com>
1094
1095 * ppc.h: (PPC_OPCODE_E500MC): New.
1096
c0f3af97
L		 10972008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1098
1099 * i386.h (MAX_OPERANDS): Set to 5.
1100 (MAX_MNEM_SIZE): Changed to 20.
1101
e210c36b
NC		 11022008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1103
1104 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1105
b1cc4aeb
PB		 11062008-03-09 Paul Brook <paul@codesourcery.com>
1107
1108 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1109
7e806470
PB		 11102008-03-04 Paul Brook <paul@codesourcery.com>
1111
1112 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1113 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1114 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1115
7b2185f9 11162008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1117 Nick Clifton <nickc@redhat.com>
1118
1119 PR 3134
1120 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1121 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1122 set.
af7329f0 1123
796d5313
NC		 11242008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1125
1126 * cr16.h (cr16_num_optab): Declared.
1127
d669d37f
NC		 11282008-02-14 Hakan Ardo <hakan@debian.org>
1129
1130 PR gas/2626
1131 * avr.h (AVR_ISA_2xxe): Define.
1132
e6429699
AN		 11332008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1134
1135 * mips.h: Update copyright.
1136 (INSN_CHIP_MASK): New macro.
1137 (INSN_OCTEON): New macro.
1138 (CPU_OCTEON): New macro.
1139 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1140
e210c36b
NC		 11412008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1142
1143 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1144
11452008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1146
1147 * avr.h (AVR_ISA_USB162): Add new opcode set.
1148 (AVR_ISA_AVR3): Likewise.
1149
350cc38d
MS		 11502007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1151
1152 * mips.h (INSN_LOONGSON_2E): New.
1153 (INSN_LOONGSON_2F): New.
1154 (CPU_LOONGSON_2E): New.
1155 (CPU_LOONGSON_2F): New.
1156 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1157
56950294
MS		 11582007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1159
1160 * mips.h (INSN_ISA*): Redefine certain values as an
1161 enumeration. Update comments.
1162 (mips_isa_table): New.
1163 (ISA_MIPS*): Redefine to match enumeration.
1164 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1165 values.
1166
c3d65c1c
BE		 11672007-08-08 Ben Elliston <bje@au.ibm.com>
1168
1169 * ppc.h (PPC_OPCODE_PPCPS): New.
1170
0fdaa005
L		 11712007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1172
1173 * m68k.h: Document j K & E.
1174
11752007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1176
1177 * cr16.h: New file for CR16 target.
1178
3896c469
AM		 11792007-05-02 Alan Modra <amodra@bigpond.net.au>
1180
1181 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1182
9a2e615a
NS		 11832007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1184
1185 * m68k.h (mcfisa_c): New.
1186 (mcfusp, mcf_mask): Adjust.
1187
b84bf58a
AM		 11882007-04-20 Alan Modra <amodra@bigpond.net.au>
1189
1190 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1191 (num_powerpc_operands): Declare.
1192 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1193 (PPC_OPERAND_PLUS1): Define.
1194
831480e9 11952007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1196
1197 * i386.h (REX_MODE64): Renamed to ...
1198 (REX_W): This.
1199 (REX_EXTX): Renamed to ...
1200 (REX_R): This.
1201 (REX_EXTY): Renamed to ...
1202 (REX_X): This.
1203 (REX_EXTZ): Renamed to ...
1204 (REX_B): This.
1205
0b1cf022
L		 12062007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1207
1208 * i386.h: Add entries from config/tc-i386.h and move tables
1209 to opcodes/i386-opc.h.
1210
d796c0ad
L		 12112007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1212
1213 * i386.h (FloatDR): Removed.
1214 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1215
30ac7323
AM		 12162007-03-01 Alan Modra <amodra@bigpond.net.au>
1217
1218 * spu-insns.h: Add soma double-float insns.
1219
8b082fb1 12202007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1221 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1222
1223 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1224 (INSN_DSPR2): Add flag for DSP R2 instructions.
1225 (M_BALIGN): New macro.
1226
4eed87de
AM		 12272007-02-14 Alan Modra <amodra@bigpond.net.au>
1228
1229 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1230 and Seg3ShortFrom with Shortform.
1231
fda592e8
L		 12322007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1233
1234 PR gas/4027
1235 * i386.h (i386_optab): Put the real "test" before the pseudo
1236 one.
1237
3bdcfdf4
KH		 12382007-01-08 Kazu Hirata <kazu@codesourcery.com>
1239
1240 * m68k.h (m68010up): OR fido_a.
1241
9840d27e
KH		 12422006-12-25 Kazu Hirata <kazu@codesourcery.com>
1243
1244 * m68k.h (fido_a): New.
1245
c629cdac
KH		 12462006-12-24 Kazu Hirata <kazu@codesourcery.com>
1247
1248 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1249 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1250 values.
1251
b7d9ef37
L		 12522006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1253
1254 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1255
b138abaa
NC		 12562006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1257
1258 * score-inst.h (enum score_insn_type): Add Insn_internal.
1259
e9f53129
AM		 12602006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1261 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1262 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1263 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1264 Alan Modra <amodra@bigpond.net.au>
1265
1266 * spu-insns.h: New file.
1267 * spu.h: New file.
1268
ede602d7
AM		 12692006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1270
1271 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1272
7918206c
MM		 12732006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1274
e4e42b45 1275 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1276 in amdfam10 architecture.
1277
ef05d495
L		 12782006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1279
1280 * i386.h: Replace CpuMNI with CpuSSSE3.
1281
2d447fca 12822006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1283 Joseph Myers <joseph@codesourcery.com>
1284 Ian Lance Taylor <ian@wasabisystems.com>
1285 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1286
1287 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1288
1c0d3aa6
NC		 12892006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1290
1291 * score-datadep.h: New file.
1292 * score-inst.h: New file.
1293
c2f0420e
L		 12942006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1295
1296 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1297 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1298 movdq2q and movq2dq.
1299
050dfa73
MM		 13002006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1301 Michael Meissner <michael.meissner@amd.com>
1302
1303 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1304
15965411
L		 13052006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1306
1307 * i386.h (i386_optab): Add "nop" with memory reference.
1308
46e883c5
L		 13092006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1310
1311 * i386.h (i386_optab): Update comment for 64bit NOP.
1312
9622b051
AM		 13132006-06-06 Ben Elliston <bje@au.ibm.com>
1314 Anton Blanchard <anton@samba.org>
1315
1316 * ppc.h (PPC_OPCODE_POWER6): Define.
1317 Adjust whitespace.
1318
a9e24354
TS		 13192006-06-05 Thiemo Seufer <ths@mips.com>
1320
e4e42b45 1321 * mips.h: Improve description of MT flags.
a9e24354 1322
a596001e
RS		 13232006-05-25 Richard Sandiford <richard@codesourcery.com>
1324
1325 * m68k.h (mcf_mask): Define.
1326
d43b4baf 13272006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1328 David Ung <davidu@mips.com>
d43b4baf
TS		 1329
1330 * mips.h (enum): Add macro M_CACHE_AB.
1331
39a7806d 13322006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1333 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1334 David Ung <davidu@mips.com>
1335
1336 * mips.h: Add INSN_SMARTMIPS define.
1337
9bcd4f99 13382006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1339 David Ung <davidu@mips.com>
9bcd4f99
TS		 1340
1341 * mips.h: Defines udi bits and masks. Add description of
1342 characters which may appear in the args field of udi
1343 instructions.
1344
ef0ee844
TS		 13452006-04-26 Thiemo Seufer <ths@networkno.de>
1346
1347 * mips.h: Improve comments describing the bitfield instruction
1348 fields.
1349
f7675147
L		 13502006-04-26 Julian Brown <julian@codesourcery.com>
1351
1352 * arm.h (FPU_VFP_EXT_V3): Define constant.
1353 (FPU_NEON_EXT_V1): Likewise.
1354 (FPU_VFP_HARD): Update.
1355 (FPU_VFP_V3): Define macro.
1356 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1357
ef0ee844 13582006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1359
1360 * avr.h (AVR_ISA_PWMx): New.
1361
2da12c60
NS		 13622006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1363
1364 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1365 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1366 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1367 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1368 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1369
0715c387
PB		 13702006-03-10 Paul Brook <paul@codesourcery.com>
1371
1372 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1373
34bdd094
DA		 13742006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1375
1376 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1377 first. Correct mask of bb "B" opcode.
1378
331d2d0d
L		 13792006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1380
1381 * i386.h (i386_optab): Support Intel Merom New Instructions.
1382
62b3e311
PB		 13832006-02-24 Paul Brook <paul@codesourcery.com>
1384
1385 * arm.h: Add V7 feature bits.
1386
59cf82fe
L		 13872006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1388
1389 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1390
e74cfd16
PB		 13912006-01-31 Paul Brook <paul@codesourcery.com>
1392 Richard Earnshaw <rearnsha@arm.com>
1393
1394 * arm.h: Use ARM_CPU_FEATURE.
1395 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1396 (arm_feature_set): Change to a structure.
1397 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1398 ARM_FEATURE): New macros.
1399
5b3f8a92
HPN		 14002005-12-07 Hans-Peter Nilsson <hp@axis.com>
1401
1402 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1403 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1404 (ADD_PC_INCR_OPCODE): Don't define.
1405
cb712a9e
L		 14062005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1407
1408 PR gas/1874
1409 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1410
0499d65b
TS		 14112005-11-14 David Ung <davidu@mips.com>
1412
1413 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1414 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1415 save/restore encoding of the args field.
1416
ea5ca089
DB		 14172005-10-28 Dave Brolley <brolley@redhat.com>
1418
1419 Contribute the following changes:
1420 2005-02-16 Dave Brolley <brolley@redhat.com>
1421
1422 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1423 cgen_isa_mask_* to cgen_bitset_*.
1424 * cgen.h: Likewise.
1425
16175d96
DB		 1426 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1427
1428 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1429 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1430 (CGEN_CPU_TABLE): Make isas a ponter.
1431
1432 2003-09-29 Dave Brolley <brolley@redhat.com>
1433
1434 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1435 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1436 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1437
1438 2002-12-13 Dave Brolley <brolley@redhat.com>
1439
1440 * cgen.h (symcat.h): #include it.
1441 (cgen-bitset.h): #include it.
1442 (CGEN_ATTR_VALUE_TYPE): Now a union.
1443 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1444 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1445 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1446 * cgen-bitset.h: New file.
1447
3c9b82ba
NC		 14482005-09-30 Catherine Moore <clm@cm00re.com>
1449
1450 * bfin.h: New file.
1451
6a2375c6
JB		 14522005-10-24 Jan Beulich <jbeulich@novell.com>
1453
1454 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1455 indirect operands.
1456
c06a12f8
DA		 14572005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1458
1459 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1460 Add FLAG_STRICT to pa10 ftest opcode.
1461
4d443107
DA		 14622005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1463
1464 * hppa.h (pa_opcodes): Remove lha entries.
1465
f0a3b40f
DA		 14662005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1467
1468 * hppa.h (FLAG_STRICT): Revise comment.
1469 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1470 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1471 entries for "fdc".
1472
e210c36b
NC		 14732005-09-30 Catherine Moore <clm@cm00re.com>
1474
1475 * bfin.h: New file.
1476
1b7e1362
DA		 14772005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1478
1479 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1480
089b39de
CF		 14812005-09-06 Chao-ying Fu <fu@mips.com>
1482
1483 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1484 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1485 define.
1486 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1487 (INSN_ASE_MASK): Update to include INSN_MT.
1488 (INSN_MT): New define for MT ASE.
1489
93c34b9b
CF		 14902005-08-25 Chao-ying Fu <fu@mips.com>
1491
1492 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1493 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1494 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1495 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1496 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1497 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1498 instructions.
1499 (INSN_DSP): New define for DSP ASE.
1500
848cf006
AM		 15012005-08-18 Alan Modra <amodra@bigpond.net.au>
1502
1503 * a29k.h: Delete.
1504
36ae0db3
DJ		 15052005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1506
1507 * ppc.h (PPC_OPCODE_E300): Define.
1508
8c929562
MS		 15092005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1510
1511 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1512
f7b8cccc
DA		 15132005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1514
1515 PR gas/336
1516 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1517 and pitlb.
1518
8b5328ac
JB		 15192005-07-27 Jan Beulich <jbeulich@novell.com>
1520
1521 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1522 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1523 Add movq-s as 64-bit variants of movd-s.
1524
f417d200
DA		 15252005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1526
18b3bdfc
DA		 1527 * hppa.h: Fix punctuation in comment.
1528
f417d200
DA		 1529 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1530 implicit space-register addressing. Set space-register bits on opcodes
1531 using implicit space-register addressing. Add various missing pa20
1532 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1533 space-register addressing. Use "fE" instead of "fe" in various
1534 fstw opcodes.
1535
9a145ce6
JB		 15362005-07-18 Jan Beulich <jbeulich@novell.com>
1537
1538 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1539
90700ea2
L		 15402007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1541
1542 * i386.h (i386_optab): Support Intel VMX Instructions.
1543
48f130a8
DA		 15442005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1545
1546 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1547
30123838
JB		 15482005-07-05 Jan Beulich <jbeulich@novell.com>
1549
1550 * i386.h (i386_optab): Add new insns.
1551
47b0e7ad
NC		 15522005-07-01 Nick Clifton <nickc@redhat.com>
1553
1554 * sparc.h: Add typedefs to structure declarations.
1555
b300c311
L		 15562005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1557
1558 PR 1013
1559 * i386.h (i386_optab): Update comments for 64bit addressing on
1560 mov. Allow 64bit addressing for mov and movq.
1561
2db495be
DA		 15622005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1563
1564 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1565 respectively, in various floating-point load and store patterns.
1566
caa05036
DA		 15672005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1568
1569 * hppa.h (FLAG_STRICT): Correct comment.
1570 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1571 PA 2.0 mneumonics when equivalent. Entries with cache control
1572 completers now require PA 1.1. Adjust whitespace.
1573
f4411256
AM		 15742005-05-19 Anton Blanchard <anton@samba.org>
1575
1576 * ppc.h (PPC_OPCODE_POWER5): Define.
1577
e172dbf8
NC		 15782005-05-10 Nick Clifton <nickc@redhat.com>
1579
1580 * Update the address and phone number of the FSF organization in
1581 the GPL notices in the following files:
1582 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1583 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1584 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1585 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1586 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1587 tic54x.h, tic80.h, v850.h, vax.h
1588
e44823cf
JB		 15892005-05-09 Jan Beulich <jbeulich@novell.com>
1590
1591 * i386.h (i386_optab): Add ht and hnt.
1592
791fe849
MK		 15932005-04-18 Mark Kettenis <kettenis@gnu.org>
1594
1595 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1596 Add xcrypt-ctr. Provide aliases without hyphens.
1597
faa7ef87
L		 15982005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1599
a63027e5
L		 1600 Moved from ../ChangeLog
1601
faa7ef87
L		 1602 2005-04-12 Paul Brook <paul@codesourcery.com>
1603 * m88k.h: Rename psr macros to avoid conflicts.
1604
1605 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1606 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1607 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1608 and ARM_ARCH_V6ZKT2.
1609
1610 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1611 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1612 Remove redundant instruction types.
1613 (struct argument): X_op - new field.
1614 (struct cst4_entry): Remove.
1615 (no_op_insn): Declare.
1616
1617 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1618 * crx.h (enum argtype): Rename types, remove unused types.
1619
1620 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1621 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1622 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1623 (enum operand_type): Rearrange operands, edit comments.
1624 replace us<N> with ui<N> for unsigned immediate.
1625 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1626 displacements (respectively).
1627 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1628 (instruction type): Add NO_TYPE_INS.
1629 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1630 (operand_entry): New field - 'flags'.
1631 (operand flags): New.
1632
1633 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1634 * crx.h (operand_type): Remove redundant types i3, i4,
1635 i5, i8, i12.
1636 Add new unsigned immediate types us3, us4, us5, us16.
1637
bc4bd9ab
MK		 16382005-04-12 Mark Kettenis <kettenis@gnu.org>
1639
1640 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1641 adjust them accordingly.
1642
373ff435
JB		 16432005-04-01 Jan Beulich <jbeulich@novell.com>
1644
1645 * i386.h (i386_optab): Add rdtscp.
1646
4cc91dba
L		 16472005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1648
1649 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1650 between memory and segment register. Allow movq for moving between
1651 general-purpose register and segment register.
4cc91dba 1652
9ae09ff9
JB		 16532005-02-09 Jan Beulich <jbeulich@novell.com>
1654
1655 PR gas/707
1656 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1657 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1658 fnstsw.
1659
638e7a64
NS		 16602006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1661
1662 * m68k.h (m68008, m68ec030, m68882): Remove.
1663 (m68k_mask): New.
1664 (cpu_m68k, cpu_cf): New.
1665 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1666 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1667
90219bd0
AO		 16682005-01-25 Alexandre Oliva <aoliva@redhat.com>
1669
1670 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1671 * cgen.h (enum cgen_parse_operand_type): Add
1672 CGEN_PARSE_OPERAND_SYMBOLIC.
1673
239cb185
FF		 16742005-01-21 Fred Fish <fnf@specifixinc.com>
1675
1676 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1677 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1678 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1679
dc9a9f39
FF		 16802005-01-19 Fred Fish <fnf@specifixinc.com>
1681
1682 * mips.h (struct mips_opcode): Add new pinfo2 member.
1683 (INSN_ALIAS): New define for opcode table entries that are
1684 specific instances of another entry, such as 'move' for an 'or'
1685 with a zero operand.
1686 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1687 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1688
98e7aba8
ILT		 16892004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1690
1691 * mips.h (CPU_RM9000): Define.
1692 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1693
37edbb65
JB		 16942004-11-25 Jan Beulich <jbeulich@novell.com>
1695
1696 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1697 to/from test registers are illegal in 64-bit mode. Add missing
1698 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1699 (previously one had to explicitly encode a rex64 prefix). Re-enable
1700 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1701 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1702
17032004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1704
1705 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1706 available only with SSE2. Change the MMX additions introduced by SSE
1707 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1708 instructions by their now designated identifier (since combining i686
1709 and 3DNow! does not really imply 3DNow!A).
1710
f5c7edf4
AM		 17112004-11-19 Alan Modra <amodra@bigpond.net.au>
1712
1713 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1714 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1715
7499d566
NC		 17162004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1717 Vineet Sharma <vineets@noida.hcltech.com>
1718
1719 * maxq.h: New file: Disassembly information for the maxq port.
1720
bcb9eebe
L		 17212004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1722
1723 * i386.h (i386_optab): Put back "movzb".
1724
94bb3d38
HPN		 17252004-11-04 Hans-Peter Nilsson <hp@axis.com>
1726
1727 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1728 comments. Remove member cris_ver_sim. Add members
1729 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1730 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1731 (struct cris_support_reg, struct cris_cond15): New types.
1732 (cris_conds15): Declare.
1733 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1734 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1735 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1736 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1737 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1738 SIZE_FIELD_UNSIGNED.
1739
37edbb65 17402004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1741
1742 * i386.h (sldx_Suf): Remove.
1743 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1744 (q_FP): Define, implying no REX64.
1745 (x_FP, sl_FP): Imply FloatMF.
1746 (i386_optab): Split reg and mem forms of moving from segment registers
1747 so that the memory forms can ignore the 16-/32-bit operand size
1748 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1749 all non-floating-point instructions. Unite 32- and 64-bit forms of
1750 movsx, movzx, and movd. Adjust floating point operations for the above
1751 changes to the *FP macros. Add DefaultSize to floating point control
1752 insns operating on larger memory ranges. Remove left over comments
1753 hinting at certain insns being Intel-syntax ones where the ones
1754 actually meant are already gone.
1755
48c9f030
NC		 17562004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1757
1758 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1759 instruction type.
1760
0dd132b6
NC		 17612004-09-30 Paul Brook <paul@codesourcery.com>
1762
1763 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1764 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1765
23794b24
MM		 17662004-09-11 Theodore A. Roth <troth@openavr.org>
1767
1768 * avr.h: Add support for
1769 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1770
2a309db0
AM		 17712004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1772
1773 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1774
b18c562e
NC		 17752004-08-24 Dmitry Diky <diwil@spec.ru>
1776
1777 * msp430.h (msp430_opc): Add new instructions.
1778 (msp430_rcodes): Declare new instructions.
1779 (msp430_hcodes): Likewise..
1780
45d313cd
NC		 17812004-08-13 Nick Clifton <nickc@redhat.com>
1782
1783 PR/301
1784 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1785 processors.
1786
30d1c836
ML		 17872004-08-30 Michal Ludvig <mludvig@suse.cz>
1788
1789 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1790
9a45f1c2
L		 17912004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1792
1793 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1794
543613e9
NC		 17952004-07-21 Jan Beulich <jbeulich@novell.com>
1796
1797 * i386.h: Adjust instruction descriptions to better match the
1798 specification.
1799
b781e558
RE		 18002004-07-16 Richard Earnshaw <rearnsha@arm.com>
1801
1802 * arm.h: Remove all old content. Replace with architecture defines
1803 from gas/config/tc-arm.c.
1804
8577e690
AS		 18052004-07-09 Andreas Schwab <schwab@suse.de>
1806
1807 * m68k.h: Fix comment.
1808
1fe1f39c
NC		 18092004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1810
1811 * crx.h: New file.
1812
1d9f512f
AM		 18132004-06-24 Alan Modra <amodra@bigpond.net.au>
1814
1815 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1816
be8c092b
NC		 18172004-05-24 Peter Barada <peter@the-baradas.com>
1818
1819 * m68k.h: Add 'size' to m68k_opcode.
1820
6b6e92f4
NC		 18212004-05-05 Peter Barada <peter@the-baradas.com>
1822
1823 * m68k.h: Switch from ColdFire chip name to core variant.
1824
18252004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1826
1827 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1828 descriptions for new EMAC cases.
1829 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1830 handle Motorola MAC syntax.
1831 Allow disassembly of ColdFire V4e object files.
1832
fdd12ef3
AM		 18332004-03-16 Alan Modra <amodra@bigpond.net.au>
1834
1835 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1836
3922a64c
L		 18372004-03-12 Jakub Jelinek <jakub@redhat.com>
1838
1839 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1840
1f45d988
ML		 18412004-03-12 Michal Ludvig <mludvig@suse.cz>
1842
1843 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1844
0f10071e
ML		 18452004-03-12 Michal Ludvig <mludvig@suse.cz>
1846
1847 * i386.h (i386_optab): Added xstore/xcrypt insns.
1848
3255318a
NC		 18492004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1850
1851 * h8300.h (32bit ldc/stc): Add relaxing support.
1852
ca9a79a1 18532004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1854
ca9a79a1
NC		 1855 * h8300.h (BITOP): Pass MEMRELAX flag.
1856
875a0b14
NC		 18572004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1858
1859 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1860 except for the H8S.
252b5132 1861
c9e214e5 1862For older changes see ChangeLog-9103
252b5132 1863\f
752937aa
NC		 1864Copyright (C) 2004-2012 Free Software Foundation, Inc.
1865
1866Copying and distribution of this file, with or without modification,
1867are permitted in any medium without royalty provided the copyright
1868notice and this notice are preserved.
1869
252b5132 1870Local Variables:
c9e214e5
AM		 1871mode: change-log
1872left-margin: 8
1873fill-column: 74
252b5132
RH		 1874version-control: never
1875End:
GDB Binutils - Deliverables
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